IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
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Hybrid Digital Adaptive Control for Fast Transient
Response in Synchronous Buck DC–DC Converters
Amir Babazadeh, Student Member, IEEE, and Dragan Maksimović, Senior Member, IEEE
Abstract—This paper presents a hybrid digital adaptive (HDA)
control for fast step-load transient responses in synchronous buck
dc–dc converters. The proposed HDA controller results in neartime-optimal step-load transient responses even when the output
voltage is sampled using a relatively low-resolution, narrow-range
window A/D converter. The controller is a combination of a standard constant-frequency pulsewidth-modulated (PWM) control in
the vicinity of steady-state operating point and a bank of switching
surface controllers (SSCs) away from the reference. The switching
surface slope is adaptively selected by a supervisor based on an
inductor current estimate. Furthermore, the controller is capable
of taking into account a maximum inductor current limitation. A
large-signal stability analysis is presented for all possible cases during transients when one of the SSCs is active. Experimental results
demonstrate fast transient responses for a 1.3 V, 10 A synchronous
buck converter over a wide range of step-load transients.
Index Terms—DC–DC switched-mode power converters, digital
control, switching surface control, time-optimal control.
I. INTRODUCTION
ECENT advances in digital control of switched-mode dc–
dc power converters have opened possibilities for practical realizations of more advanced control concepts, such as
hybrid control [1]. Hybrid controllers, which include switching
among multiple controllers depending on control objectives or
operating conditions, have been shown to yield performance
improvements compared to a fixed controller [1]. This paper
presents a hybrid digital adaptive (HDA) controller to improve
transient responses in synchronous buck dc–dc converters. A
block diagram of the HDA controller is shown in Fig. 1(a).
The motivation for and the relationships between the proposed HDA controller and previous works in this area are as
follows. Widely adopted methods for control of switched-mode
dc–dc converters are based on constant-frequency pulsewidthmodulated (PWM) operation, small-signal averaged converter
models [2], [3], and standard linear controllers, such as
proportional–integral–derivative (PID). The advantages include
constant-frequency operation, well-established design methods,
and many years of successful applications in practice. It is also
well known, however, that linear control does not offer the best
R
Manuscript received March 8, 2009; revised June 3, 2009 and August 27,
2009. Current version published December 18, 2009. This paper was presented
in part at the IEEE Power Electronics Specialists Conference, Rhodes, Greece,
June 2008. Recommended for publication by Associate Editor A. Prodic.
A. Babazadeh is with Infineon North America (Primarion, Inc.), Torrance,
CA 90505 USA (e-mail: amir.babazadeh@infineon.com).
D. Maksimović is with the Department of Electrical, Computer, and Energy
Engineering, University of Colorado at Boulder, Boulder, CO 80309-0425 USA
(e-mail: maksimov@colorado.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2009.2033065
Fig. 1. (a) Hybrid digital adaptive controller around a synchronous buck
converter. Experimental prototype parameters are: V g = 7–10 V, L = 1 µH,
C = 300 µF, switching frequency fs = 780 kHz, qA / D = 10 mV, N o s = 32,
V re f = 1.3 V, and Ilo a d = 0–10 A. (b) Waveforms illustrating the ideal timeoptimal response to a step-load transient.
possible performance for switched-mode converters. In particular, nonlinear control methods are needed to approach ideal timeoptimal step-load transient responses. The ideal time-optimal
control (TOC) in the synchronous buck converter, including a
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
single switch action, and the corresponding response are illustrated in Fig. 1(b). The classical approaches for obtaining the
ideal TOC based on Pontryagin’s minimum principle [4] are not
practical in power converters, since: 1) the solution needs the exact dynamics of the system, which is usually not available; 2) the
computations involved may be very complicated; and 3) TOC
is sensitive to operating conditions, parameter tolerances, and
parasitics. For these reasons, alternative approaches leading to
improved dynamic response capabilities have recently gained a
lot of attention. These alternative methods include the charge
balance principle [5]–[9], as well as switching surface control
(SSC) and related approaches [10]–[20].
Digital control techniques based on the charge balance principle employing the quantized output voltage have been presented in [5]–[7]. These controllers can demonstrate near-timeoptimal performances when subject to isolated step-load transients, if voltage A/D converters with relatively high resolution
and relatively wide conversion range are available, and when
the component parasitics [such as the capacitor equivalent series resistance (ESR)] are negligible. However, the performance
is not clear for arbitrary transients, including multiple consecutive transients during timed ON/OFF actions of the controller, or
in the presence of component parasitics.
Another alternative to TOC in dc–dc converters is presented
by SSC approaches. By taking into account the converter state
trajectories in the two possible switched states, a switching surface (SS) can be derived that naturally provides an ON/OFF sequence that results in the fastest, i.e., time-optimal transient response. Various implementations of linear and nonlinear SSCs
employing the output voltage and the inductor (capacitor) current sensing have been addressed in [9]–[20]. A proximate timeoptimal digital control (PTOD) employing a linear SSC during
the transient operations based on the quantized output voltage
and a capacitor current estimate has been proposed in [19].
This method can result in near-time-optimal step-load transient
responses, while improving the potential for robust operation
under arbitrary disturbances, and having a relatively simple,
low gate count realization. This approach can be considered as
an alternative to the constrained time-optimal control method
presented in [21].
This paper extends the PTOD controller presented in [19] in
two directions. First, further improvements in step-load transient responses are realized by an adaptive adjustment of the
linear SS slope based on the inductor and capacitor current
estimates, leading to the HDA controller shown in Fig. 1(a).
The HDA controller leads to dynamic responses even closer to
time-optimum for a wide range of step-load transients, while
preserving the system robustness and simplicity. Furthermore,
a method is proposed to incorporate inductor current limitation,
which is commonly required in practice. Second, in the context
of discrete-time piecewise linear systems, based on [22]–[24],
a stability analysis of the sampled data system is presented
for three possible modes arising in transient operations: 1) the
sliding-mode operation, where the stability on the SS can be
shown using the Lyapunov method; 2) the asymptotic mode,
where quadratic piecewise Lyapunov functions are employed to
verify the stability; and 3) the mixed mode (including both the
sliding mode and the asymptotic mode).
The paper is organized as follows. The architecture of the
HDA controller and its extension to the case that includes inductor current limitation are presented in Section II. The stability
analysis for the transient mode is presented in Section III. Experimental results for a 1.3 V, 10 A synchronous buck converter
are given in Section IV. Section V concludes the paper.
II. HYBRID DIGITAL ADAPTIVE CONTROL
A block diagram of the HDA controller around a synchronous
buck converter is shown in Fig. 1(a). The architecture can be
classified as a hybrid controller, which consists of a supervisor
with the role of selecting a proper controller at a given instant
of time, and a bank of controllers [1]. The bank of controllers
includes a standard constant-frequency PWM controller with a
linear PID compensator operating in the vicinity of the steadystate operating point, and several SSCs adaptively selected and
activated in transients.
The goal of this controller is to return the output voltage
error e = vo −Vref , which is sampled and quantized by an A/D
converter having the least significant bit (LSB) resolution qA/D ,
to regulation in near-minimum time for a wide range of step-load
transients, while incorporating the inductor current limitation.
A. Discrete-Time Large-Signal Model for the SS-Controlled
System
To explain SSC operation and adaptation, consider the statespace model of the synchronous buck converter shown in
Fig. 1(a)
ẋ = A1 x + B1 + D1 ,
c1 = 1
(1)
x ∈ X1 ,
and
ẋ = A2 x + B2 + D2 ,
x ∈ X2 ,
where x = [vo −Vref
ic ]T = [e
c1 = 0
(2)
ic ]T
A1 = A2 =

R
Resr RRL 
Resr R
RL
−
−
1+
 L(Resr + R)
R
C(Resr + R) L(Resr + R) 




RRL
R
RL
1
−
−
1+
−
L(Resr + R)
R
C(Resr + R) L(Resr + R)
Resr
RVg
B1 =
L(Resr + R)
1
0
B2 =
0
(R + RL )Vref
(R + RL )Vref Resr
D1 = D2 = −
=−
B1 .
L(Resr + R)
RVg
1
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BABAZADEH AND MAKSIMOVIĆ: HYBRID DIGITAL ADAPTIVE CONTROL FOR FAST TRANSIENT RESPONSE
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Here, X1 , X2 ⊂ 2 are the partitions of the state plane where the
high-side switch control signal (c1 ) is one and zero, respectively,
Resr is the capacitor equivalent series resistance, R is the load
model, and RL is the total conduction loss series resistance. The
discrete-time HDA controller receives samples of the output
voltage error at the system clock rate
fsam ple = Nos fs = 32fs
(3)
where fs is the PWM switching frequency and Nos = 32 is the
oversampling rate. The discrete-time version of the model (1),
(2) using Tsam ple = 1/fsam ple can be written as
xd [k + 1] = Ad xd [k] + Bd c1 + Dd
where
a11
a12
= eA 1 T s a m p l e
a22
T s a m p l e
bd1
A1 τ
Bd =
e dτ B1
=
bd2
0
T s a m p l e
dd1
Dd =
eA 1 τ dτ D1 .
=
dd2
0
Ad =
(4)
a21
(5)
(6)
(7)
Fig. 2. State-space trajectories for four step-load transients, and optimum
slopes of the corresponding linear switching surface.
TABLE I
OPTIMUM SLOPES OF SWITCHING SURFACES
B. TOC With No Inductor Current Limitation
Suppose that a step-up transient brings the states to a point
xd0 ∈ X1 away from steady state. If the difference (4) is solved
forward (c1 = 1) from this initial point and backward (c1 = 0)
from the steady-state operating point, i.e., origin, the intersection
results in the SS that leads to time-optimal transient response
for this transient. In general, the SS leading to time-optimal
response for arbitrary initial points is nonlinear [15], [16]. As a
simple alternative, this nonlinear surface can be approximated
by a bank of linear SSs as
Si [n] = e[n] + λi .ic [n]
(8)
where λi is the slope of the SS expressed in Ohms (Ω). The slope
λi is selected by the supervisor unit in Fig. 1(a). The optimum
switching surface slope depends on the power-stage parameter
values (L and C), the input voltage Vg , and the amplitude of
the step-load transient. Furthermore, the effects of the capacitor
ESR and the delay in activating an SSC can be significant,
as illustrated in Fig. 2, which shows state-space trajectories
obtained by simulations for four different step-load transients
in the prototype converter.
Upon a transient, the trajectory first jumps to point A due
to the capacitor ESR. The PID controller continues to operate
taking the trajectory to point B. During the activation delay,
between points A and B, the capacitor and the inductor currents remain approximately constant. At point B, the supervisor
detects the transient and activates an SSC. Table I shows the
optimum SS slopes λi for four different step-load transients
corresponding to the state trajectories in Fig. 2.
C. TOC Taking Into Account the Inductor Current Limit
As shown in Fig. 1(b), fast step-up load transient response
has a potential for significant inductor current overshoot, which
Fig. 3. Waveforms illustrating the ideal time-optimal response to a step-load
transient taking into account the inductor current limit.
may cause saturation of the inductor core and current overstress
of the electronic switches, or require oversizing the inductor. It
is therefore of interest to reexamine TOC taking into account
inductor current limitation. The ideal TOC in this case includes
three segments, as shown in Fig. 3. During the first interval
(T1 + T2 ), the high-side switch is ON, the current ramps up, and
the output voltage passes the valley point at time T1 . In the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
inductor current saturation mode or not. The inductor current can
be sensed directly, or estimated based on the duty cycle value
D available in the digital controller, as detailed in [25]–[27].
For simplicity, the estimation approach is applied in the experimental prototype described in this paper. Based on a simplified
steady-state-averaged model of the buck converter, the initial
load current, which is equal to the averaged value of the inductor current, can be found as
Î o,init = k1 (D − D0 )
Fig. 4.
Phase portrait of the SS-controlled system with inductor current limit.
second interval (T3 ), the inductor current remains at the
maximum-allowed level. A control with infinite number of
switches (infinite switching frequency) would theoretically be
required to keep the inductor current exactly at this level. In
other words, the system enters sliding mode in this interval.
In practice, finite sampling frequency, a hysteresis band in the
control loop, and quantization effects lead to finite switching
frequency during T3 .
In the final interval (T4 ), the high-side switch is OFF and the
inductor current ramps down to the final value, while simultaneously the output voltage comes back to regulation.
The SSC approach can be extended to implementation of
TOC while incorporating the inductor current limitation. In the
state-space plane (e, ic ), the current limit can be expressed as
IC ,m ax = IL ,m ax − Io,final
(9)
where Io,final is the final load current and IC ,m ax is the maximum capacitor current corresponding to iL = IL ,m ax . When
the capacitor current hits the limit (9), the controller enters the
saturation mode and picks a nonlinear surface including two
segments. The segment at iC = IC ,m ax will be denoted as the
current-limiting surface, and the segment passing through the
origin will be denoted simply as the saturated switching surface
(λsat ). The trajectory slides along the current-limiting surface
first. The follow-up OFF switch action based on λsat brings the
trajectory to the origin, as shown in Fig. 4.
Implementing the ideal saturation mode requires very high
switching frequency, which is undesirable in practice. To control
the switching frequency in this mode, it is possible to a set a
lower threshold (∆IC ) on the horizontal part of the SS, as shown
in Fig. 4.
The same saturated SS (λsat ) can be employed for all transients with the same IC ,m ax .
D. Inductor Current
As stated before, the supervisor requires a value of the inductor current to determine whether the controller should enter the
(10)
where Î o,init is an estimate of the initial load current, D0 is
the steady-state duty cycle command at zero load, and k1 is approximately equal to Vg /RL , where RL approximately models
conduction losses including the MOSFET ON-resistances and
the inductor winding resistance.
The capacitor current estimate is achieved based on the
method described in [19]. This estimate includes two intervals.
First, an approximate minimum point IC ,m in is found applying
a discrete-time moving average of order k filter to the difference
of the output voltage error samples given by
C
1 − z −k e(z) = Hek (z)e(z)
(11)
îc (z) = −
kTsam ple
where the estimation filter transfer function Hek ej ω T s a m p l e
can be written as
Hek ej ω T s a m p l e =− (jωC) e−j ω k T s a m p l e /2 sinc (ωkTsam ple /2).
(12)
The filter Hek ej ω T s a m p l e shows that (11) approximates
ideal analog differentiation, but with a delay of kTsam ple /2.
In the second interval, a delay compensation and estimation
based on inductor current slopes leads to high-resolution capacitor current estimate. Since the current increment (∆i) during
the delay (kTsam ple /2) is similar for the capacitor and the inductor, an inductor current estimate can be achieved using the
initial load current and also the filter effect (∆i) at T1 , as shown
in Fig. 5.
It should be noted that the inductor current is equal to the
final load current at the time when the capacitor current is equal
to zero, i.e., at the end of interval T2 .
E. Adaptive SS Adjustment
Operation of the supervisor unit in the HDA controller of
Fig. 1(a) can be explained with reference to Fig. 5. The supervisor selects constant-frequency PWM controller with linear PID
in the vicinity of steady state. A transient is recognized when
the quantized output error e exceeds 2qA/D = 20 mV, and the
capacitor current estimate exceeds 2 LSB indicating that the
states (e, ic ) are significantly away from the steady-state operating point (origin). If the errors are below the thresholds, the
constant-frequency PWM control remains active and brings the
output voltage to regulation. Upon transient detection, one SS
from the bank of SSs is selected. As in [19], the PID controller
continues to run at all times, with no modifications required to
facilitate smooth transitions.
The SS adjustment can be performed based on ∆Io , which
gives an approximation of the step-load amplitude at time
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BABAZADEH AND MAKSIMOVIĆ: HYBRID DIGITAL ADAPTIVE CONTROL FOR FAST TRANSIENT RESPONSE
Fig. 6.
Fig. 5.
Capacitor and inductor current estimates for a step-load transient.
interval (T1 + T2 ) as
∆Io = iL (T1 + T2 ) − Iˆo,init .
(13)
Keeping track of iL (t) enables the supervisor to incorporate
the inductor current limitation, as described in Section II-C. In
this case, the saturated switching surface (λsat ) can be adaptively adjusted based on the value of IC ,m ax . However, the dependence on the input voltage is not taken into account, which
is a limitation of the approach presented in this paper.
In the experimental prototype, the selection based on ∆Io is
among eight different slopes, which correspond to 4 step-up load
amplitudes of 25% (2.5 A), 50% (5 A), 75% (7.5 A), or 100%
(10 A) and four corresponding step-down load amplitudes. The
slope closest to the optimal is selected so that near-time-optimal
transient responses can be obtained under all possible step-load
transients.
III. STABILITY ANALYSIS
The objective of the stability analysis is to find the conditions
that guarantee the convergence of the state variables toward a desired steady-state operating point where the output is regulated
by the PID compensator under a fixed duty cycle. Stability analysis for the HDA-controlled buck converter can be studied for
steady state and transient operations separately. In the vicinity
of steady-state operation, the standard stability analysis based
on the converter linear small-signal-averaged model applies [3].
The linear PID compensator is designed for adequate stability
margins. In transient operations, however, the linearized smallsignal model is not valid, and the large-signal discrete-time
model, as described in Section II, should be employed.
In this section, the stability analysis of the HDA-controlled
system, which receives the samples of the output voltage at the
2629
Discrete-time QSM.
system clock rate (32fs ), is presented. A/D quantization effects
are neglected.
In a second-order system, there are theoretically four possible
dynamics in the vicinity of the SS [24]: 1) trajectories approach
the surface from both sides; 2) trajectories approach the surface
from one side and leave from the other side; 3) trajectories
leave the surface from both sides, and finally; 4) trajectories are
tangential to the surface on either side. In the switched-mode
power converter, the relevant cases 1 and 2 result in sliding mode
(SM) and asymptotic mode (AM), respectively.
Whether the SS-controlled buck converter enters the SM, AM,
or both (called mixed-mode (MM) in this paper), depends on the
SS slope λ and the initial condition in the state-space plane. If
the selected SS is optimal for a given transient, the states return
to steady state in minimum time, and the system does not show
SM behavior. However, if the SS is not optimal, the system may
enter SM or MM. Here, we present the stability analysis for the
discrete-time system for all three possible transient modes.
A. System in SM
When the trajectories from both sides approach the SS,
the system enters the SM operation. The principles of SM
in discrete-time systems [28]–[30] are different from the
continuous-time SM in power converters, which have been researched and applied more extensively (e.g., [31]–[33]). In contrast to ideal continuous-time case when the system trajectory
moves along the SS, in discrete-time sliding mode, the trajectory may move around the surface, as shown in Fig. 6, which is
why it is often called quasi-sliding mode (QSM).
The attributes of discrete-time QSM illustrated in Fig. 6 have
been addressed in [28] as follows: 1) starting from any initial
state, the trajectory will move toward the SS and cross it in
finite time; 2) once the trajectory has crossed the SS the first
time, it will cross the surface again in every successive sampling
period, resulting in a zigzag motion around the SS; and 3) the
size of each successive zigzagging step is nonincreasing and the
trajectory stays within a band around the SS.
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Fig. 7.
Regions of existence of sliding mode in the state plane obtained (a) by (16) and (17) and (b) by (18) and (19).
For analyzing the system’s behavior regarding the SM on the
switching surface S[k], consider a Lyapunov function V (S) [29]
V (S) = |S[k]| .
(14)
Based on the Lyapunov second theorem, the condition for
existence of sliding motion and convergent switching is obtained
by
∆V = |S[k + 1]| − |S[k]| < 0.
(15)
Taking into account all possible cases, one can derive the
following equivalent conditions:
S[k] > 0, S[k + 1] > 0 ⇒ ∆V = S[k + 1] − S[k] < 0
S[k] < 0, S[k + 1] < 0 ⇒ ∆V = −(S[k + 1] − S[k]) < 0
⇒ (S[k + 1] − S[k])sgn(S[k]) < 0 (16)
where sgn() denotes the sign function, and also
S[k] < 0, S[k + 1] > 0 ⇒ ∆V = S[k + 1] + S[k] < 0
S[k] > 0, S[k + 1] < 0 ⇒ ∆V = −(S[k + 1] + S[k]) < 0
⇒ (S[k + 1] + S[k])sgn(S[k]) ≥ 0. (17)
In a switched-mode power converter, the trajectory cannot
move tangentially to the SS and so it must cross the surface in
finite time. Therefore, conditions (16) and (17) are the necessary and sufficient conditions for QSM. Inequality (16) denotes
the necessary conditions for QSM existence and implies that
the system should be moving in the direction of the sliding surface, while it does not guarantee that the size of zigzagging
step is nonincreasing. Inequality (17), however, implies that the
trajectory around the SS stays in a specified band.
Conditions (16) and (17) can be illustrated graphically by
defining
Z1 = [1
λ](xd [k + 1] − xd [k]) > 0,
S<0
(18)
Z2 = [1
λ](xd [k + 1] − xd [k]) < 0,
S>0
(19)
where Z1 and Z2 are the surfaces representing condition (16)
and
P1 = [1
λ](xd [k + 1] + xd [k]) < 0,
S<0
(20)
P2 = [1
λ](xd [k + 1] + xd [k]) > 0,
S>0
(21)
where P1 and P2 are the surfaces representing condition (17).
Consider a typical positive value of the SS slope λ. Fig. 7(a)
shows that the regions located in Z1 < 0 and Z2 > 0 do not
satisfy the necessary condition (16), so they cannot be attracting
SM regions. This is, however, not sufficient to say that the area
between Z1 > 0 and Z2 < 0 is an attracting SM. In addition,
(20) and (21) must be satisfied. Fig. 7(b) illustrates the surfaces
P1 and P2 and shows a band where (20) and (21) are not satisfied.
It should be noted that P2 and the SS have an intersection at
Z2 = 0, and that P1 and the SS have an intersection at Z1 = 0.
In conclusion, Fig. 7 verifies that the region between Z1 = 0
and Z2 = 0 satisfies the conditions for QSM operation. Since the
band illustrating (17) is very close to the surface, and therefore,
the zigzagging steps are very small, one can proceed to study
the QSM dynamics based on the idea of equivalent control
[28]–[30]. Details are given in Appendix A, where it is shown
that the SS-controlled synchronous buck converter in discretetime SM is stable if
λ > −Resr .
(22)
The aforesaid inequality shows that the system admits some
negative values of λ, if Resr = 0.
B. System in AM
The system is in AM when the trajectories approach the SS
from one side and leave it from the other side. For example, the
trajectories in Fig. 2, where the SS slope results in time-optimal
responses, illustrate operation in AM. The goal of stability in
this mode is to show that all trajectories tend toward a small
region around the origin, assuming (22) is satisfied.
For performing a stability analysis in this case, one can study
the SS-controlled buck converters in the context of discretetime piecewise linear systems, as a class of nonlinear discrete
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BABAZADEH AND MAKSIMOVIĆ: HYBRID DIGITAL ADAPTIVE CONTROL FOR FAST TRANSIENT RESPONSE
Fig. 8.
Phase plane of the system: (a) trajectory with limit cycling, and (b) with stable equilibrium point.
Fig. 9.
Phase plane including inductor current and output voltage illustrating limit cycle (left) and stable equilibrium point (right).
systems. In the switching systems, such as the SS-controlled
buck converter, the common Lyapunov method usually does not
admit any solutions. Stability analysis is, instead, based on a
quadratic piecewise Lyapunov function (QPWLF) [22], [23].
Appendix B presents a method for constructing the QPWLF,
assuming condition (22) is satisfied. This function is guaranteed
to be decreasing in both partitions of the state plane and in
transitions across the SS. This, according to a result presented in
[22] and [23], implies that the trajectory approaches the steadystate operating point exponentially (asymptotically), i.e., the
output voltage comes back to regulation in finite time when a
transient occurs.
C. System in MM
In the MM, the system trajectories include both SM and AM.
This is a common situation in the HDA-controlled buck con-
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verter, since the limited number of SS slopes implies that the
ideal time-optimal response is achieved only for several specific
load transients. In all other cases, the responses may include
both SM and AM modes. It can be shown that the system is stable in MM if 1) the conditions for stability in SM are satisfied
and 2) if the QPWLF [33, Appendix B] is decreasing in both
partitions.
D. Example
In the experimental prototype, the measured value of Resr ≈
1.4 mΩ. Figs. 8(a) and (b) illustrates the phase portrait of the
system obtained by simulation for λ = −1.5 mΩ [violating condition (22)], and λ = −1.1 mΩ [satisfying condition (22)],
respectively.
Fig. 8(a) shows that the origin is unstable and that there is a
limit cycle in the system, while Fig. 8(b) verifies the existence
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
Fig. 10. Waveforms illustrating limit cycle (left) and stable equilibrium point (right). The waveforms shown are, top-to-bottom: ac-coupled output voltage vo
(100 mV/div), inductor current iL (5 A/div), switch-node voltage v s (20 V/div), and a load control signal.
of a stable attracting SM. Fig. 9 shows experimental results of
the phase portrait including the inductor current and the output
voltage for the same two values of the SS slopes, as in Fig. 8.
Finally, Fig. 10 shows 0–10 A step-load transients for the two
considered SS slope values. The experimental results are consistent with the stability analysis and simulation results.
TABLE II
OPTIMUM SCALING FACTORS FOR STEP-UP TRANSIENTS, V g = 7 V
IV. EXPERIMENTAL RESULTS
1) Step-Up Load Transient: In step-up transients, the SS
with slope λ is selected for the 5–10 A transient. The scaling
factors γ i in the HDA controller are listed in Table II, closely
corresponding to the ideal values shown in Table I. In this case,
the input voltage is Vg = 7 V.
Fig. 11 compares dynamic responses of the standard PID and
the HDA controllers for the 5–10 A transient. In this case, the
PTOD controller and the HDA controller are the same. For the
PID controller, the A/D conversion range is just wide enough to
avoid saturation and to enable relatively fast transient response.
With the HDA controller, a narrower-range window A/D is sufficient to achieve an improved response, at the expense of a
higher A/D sampling rate.
Fig. 12 compares dynamic responses of the PTOD controller
and the HDA controller for three different step-load transients.
The HDA controller achieves responses closer to time-optimal
in all cases.
Selection of the optimum switching surface slopes depends
on the input voltage Vg . As an illustration, Table III shows
the optimum slope scaling factors for four step-up transients
under a different input voltage (Vg = 10 V). Fig. 13 shows the
corresponding experimental waveforms for four different stepup load transients.
In the experiments shown in Fig. 13, the new set of scaling
factors according to Table III were manually loaded to the controller to account for the different input voltages. To remove this
limitation, different banks of scaling factors could be selected
by the supervisor based on input voltage sensing, or based on
the steady-state duty cycle command, which is available in the
digital controller.
2) Step-Down Load Transients: In step-down transients, the
switching surface slope for the PTOD controller is adjusted for
10–5 A transient. The scaling factors for the SS slopes used in
In this section, experimental results for the HDA-controlled
buck converter of Fig. 1 are shown, without and with inductor
current limitation. The experimental prototype parameters are:
Vg = 7–10 V, L = 1 µH, C = 300 µF, fs = 780 kHz, qA/D =
10 mV, Resr = 1.4 mΩ, RL = 10 mΩ, sampling frequency is
32fs = 25 MHz(Nos = 32), Vref = 1.3 V, and Iload = 0–10 A.
A. Transient Responses With No Inductor Current Limitation
In the experimental prototype with the parameters shown in
Fig. 1(a), the digital controller can be programmed to operate as:
1) a standard constant-frequency PWM with PID only, which
is designed for 100 kHz of bandwidth and 60◦ of phase margin
using an A/D having a conversion range of CA/D = ±55 mV
and the LSB resolution of qA/D = 10 mV; 2) a PTOD controller
with a single linear switching surface having a fixed slope λi = λ
adjusted for a specific load transient (e.g., 5–10 A) [19]; and
3) the hybrid digital adaptive controller with several linear SSCs
having adaptively adjusted slope λi = γi λ, where γi is a five-bit
binary register with three fractional (γi is between 0 and 3.875
with steps of 0.125). The value of λ in this experiment is the
same as in [19]
λ≈
Nos Tsam ple
≈ 4.2 mΩ.
C
(23)
In the experimental evaluations, the A/D converter used in the
PTOD and the HDA controllers has an even narrower conversion
range CA/D = ±35 mV around the reference compared to the
standard PID controller (CA/D = ±55 mV). However, it should
be noted that the PTOD or HDA controllers sample the output
voltage at a much higher rate (32fs ), and thus, require a faster
A/D converter compared to the standard PID controller.
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BABAZADEH AND MAKSIMOVIĆ: HYBRID DIGITAL ADAPTIVE CONTROL FOR FAST TRANSIENT RESPONSE
2633
Fig. 11. Experimental step-up load transient waveforms for the standard constant-frequency PWM with PID using an A/D with the conversion range C A / D =
±55 mV (left), and PTOD and HDA controllers with the linear switching surface adjusted for near-time-optimal response (right). An A/D with a narrower
conversion range (C A / D = ±35 mV) is used in the PTOD and the HDA controller. The input voltage is V g = 7 V. The waveforms shown are, top-to-bottom:
ac-coupled output voltage vo (100 mV/div), inductor current iL (5 A/div), switch-mode voltage v s (20 V/div), and a load control signal.
Fig. 12. Experimental step-up load transient waveforms for the HDA controller with four adaptively selected SSC slopes (left), and (b) proximate time-optimal
controller with a single linear SSC (right). The transients are 0–10 A, 2.5–10 A, and 7.5–10 A from top to bottom. The input voltage is V g = 7 V.
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2634
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
Fig. 13.
Experimental waveforms for 0–10 A (top left), 2.5–10 A (top right), 5–10 A (bottom left), 7.5–10 A (bottom right) step-load transients for V g = 10 V.
TABLE III
OPTIMUM SCALING FACTORS FOR STEP-UP TRANSIENTS, V g = 10 V
TABLE IV
OPTIMUM SCALING FACTORS FOR STEP-DOWN TRANSIENTS, V g = 7 V
the HDA controller are listed in Table IV, for the input voltage
Vg = 7 V.
Fig. 14 shows experimental results for the PTOD controller
and the HDA adjusted for 10–5 A transient.
Fig. 15 compares dynamic responses of the PTOD controller
and the HDA controller for other step-load transients. The
hybrid controller achieves responses closer to time-optimal in
all cases. It should be noted that the step-down responses are not
as good as step-up responses. This is to be expected given that
Vref = 1.3 V is much smaller than Vg − Vref . The near-timeoptimal responses are limited by the power-stage parameters,
and could be improved further by reducing L, by increasing
C, by turning OFF the synchronous rectifier, or by employing
auxiliary switches [34]–[36].
Fig. 14. Experimental step-down (10–5 A) load transient waveforms for the
PTOD and the HDA controllers with the linear switching surface adjusted for
near-time-optimal response. The input voltage is V g = 7 V.
B. Transient Responses With Inductor Current Limitation
In this section, the experimental results taking into account
inductor current limitation are shown in Fig. 16. In both cases,
the current limit is set at IL ,m ax = 14 A, while different values for ∆IC show how the current-limited near-time-optimal
responses can be achieved in two or three switching actions,
respectively.
While the results in Fig. 16 illustrate the feasibility of incorporating an inductor current limitation in the HDA controller,
the inductor current estimation described in Section II-C results
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BABAZADEH AND MAKSIMOVIĆ: HYBRID DIGITAL ADAPTIVE CONTROL FOR FAST TRANSIENT RESPONSE
2635
Fig. 15. Experimental step-down load transient waveforms for the HDA controller with four adaptively selected slopes of linear SSC (left), and (b) proximate
time-optimal controller with a single linear SSC (right). The transients are 10–2.5 A and 10–7.5 A from top to bottom. The input voltage is V g = 7 V.
Fig. 16. Experimental waveforms with the HDA controller for a 2.5–10 A step-load transient with IL , m a x = 14 A, ∆IC = 3 A (left) and ∆IC = 2 A (right).
The input voltage is V g = 7 V.
in several practical limitations including errors in IL ,m ax due to
estimation errors, and dependences on the input voltage, which
are not accounted for by the estimator. These limitations could
be removed by incorporating inductor current sensing instead
of the estimator.
V. CONCLUSION
The paper has presented an HDA controller that includes a
standard constant-frequency PWM operation in the vicinity of
steady state, and a bank of linear switching surface controllers
operating in transients, with slopes adaptively selected based on
capacitor and inductor current estimates. As a result, the HDA
controller is capable of achieving near-time-optimal responses
for a wide range of step-load transients, for a given fixed input
voltage. Feasibility of extending the HDA controller to achieve
near-time-optimal performance over a range of input voltages is
also discussed. Furthermore, the controller includes an option
to set a limitation for the maximum-allowed inductor current.
A stability analysis using piecewise-quadratic Lyapunov
functions and discrete-time sliding-mode approach was presented to show that the HDA-controlled converter is stable under all operating conditions and arbitrary disturbances. Experimental results with a 1.3 V, 10 A synchronous buck converter
demonstrated near-time-optimal responses for a wide range of
step-load transients using a voltage A/D converter with a relatively low-resolution and a limited conversion range.
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2636
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
APPENDIX
A. Derivation of SM Dynamics and Stability Condition (22)
Assume the system trajectories stay on the SS
S[k + i] = 0,
for some i > 1
(24)
so the equivalent control in the system (4) is obtained by
c1eq = −(ΛBd )−1 Λ(Ad xd [k] + Dd )
(25)
where Λ = [1 λ] and Λ.Bd = 0 is a scalar. The system’s dynamics on the SS using the equivalent control is
xd [k + 1] = ΩAd xd [k] + ΩDd
(26)
where
Ω = (I − Bd (ΛBd )−1 Λ)
−λbd1
λbd2
1
=
.
bd1 + λbd2 −bd2
bd1
Fig. 17.
It is important to note that matrix Ω is not full rank since
det(Ω) = 0. This is because in SM, the system motion is constrained to be on the SS. A further simplification of (26) results
in
λα(λ) λβ(λ)
λη(λ)
xd [k + 1] =
xd [k] +
(27)
−α(λ) −β(λ)
−η(λ)
Contour lines of the quadratic piecewise-Lyapunov function V (xd ).
By replacing (30) and (31) into (29) and applying linearripple approximations, one can find the following approximate
stability criterion:
λ>−
Resr
2
1 + ac22 Tsam ple /2 + ac22 ac21 Tsam
ple /4
(32)
which yields (22)
where
α(λ) =
λ > −Resr , as Tsam ple → 0.
bd2 a12 − bd1 a22
bd2 a11 − bd1 a21
, β(λ) =
bd1 + λbd2
bd1 + λbd2
B. Stability Analysis in AM
and
bd2 dd1 − bd1 dd2
.
bd1 + λbd2
It can easily be shown that η(λ) = 0. The reduced order
dynamics of the system in SM can finally be written as
η(λ) =
e[k + 1] = (λα(λ) − β(λ)e[k]
(28)
leading to stable dynamics on the SS if the pole of the system
(28) is located inside the unit circle
|λα(λ) − β(λ)| < 1 ⇒ λm in < λ < λm ax .
Now, redefine matrices
Resr ac21
A = A1 = A2 =
ac21
(29)
Resr
ac12
bc .
, B1 =
ac22
1
The discrete equivalent model using zero-order hold as
Tsam ple → 0 is given by
Ad = eA T s a m p l e ≈ I + ATsam ple
ac12 Tsam ple
1 + Resr ac21 Tsam ple
=
(30)
ac21 Tsam ple
1 + ac22 Tsam ple
T s a m p l e
2
ATsam
ple
Aτ
Bd1 =
e dτ B1 ≈ I · Tsam ple +
B1
2
0
Resr + ac21 Tsam ple /2
≈
(31)
Tsam ple bc .
1 + ac22 Tsam ple /2
The QPWLF for the switched-mode power converter described by (4) can be written as [22], [23]
T
Φi qi
xd
T
V (xd ) = x̄d Φ̄i x̄d = xd 1
T
1
qi ri
= xTd Φi xd + 2qiT xd + ri ,
xd ∈ Xi − XP ,
i = 1, 2
(33)
where Φi and qi are 2 × 2 and 2 × 1 matrices, ri is a scalar, and
the SS divides the state plane into two partitions Xi . Here, XP
is a small region around the origin where the PID compensator
takes over after the transient. Without loss of generality, one can
assign an arbitrary stable system for this region.
Stability of the system (4) in AM can be examined based
on a result [23, Theorem 3.1], which states that the system is
exponentially (asymptotically) stable if the QPWLF (33) is decreasing along all trajectories of (4) in each of the two partitions,
and also across the SS. An immediate result of the aforesaid theorem is that the trajectory hits the boundaries of XP in finite time,
so the PID will be activated after an arbitrary transient. Fig. 17
shows the contour lines (i.e., level curves) of V (xd ), which are
families of ellipsoids in each of the two partitions. Also shown
are the switching surface (S = 0 line) having a positive slope
λ > 0 and XP .
A method for constructing a QPWLF that satisfies the stability
conditions for a trajectory cycle is discussed next. Each cycle
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BABAZADEH AND MAKSIMOVIĆ: HYBRID DIGITAL ADAPTIVE CONTROL FOR FAST TRANSIENT RESPONSE
includes a trajectory that starts from one partition (partition
1 in step-up transients) and ends in the same partition in just
two switching actions. If the high-side switch in system (4)
is ON (c1 = 1), there is a stable equilibrium point at (Xeq1 =
R
− Vref , 0), so a Lyapunov function V1 (xd ) = (xd −
Vg R +R
L
Xeq1 )T Φ1 (xd − Xeq1 ) can be obtained by solving
ATd1 Φ1 Ad1 − Φ1 < 0.
(34)
It is clear that the corresponding Lyapunov function V1 (xd )
is decreasing along all trajectories in partition 1. Similarly, for
(c1 = 0), the system has an equilibrium point at (−Vref , 0),
and one can easily find V2 (xd ). Again, the Lyapunov function is
decreasing along all trajectories in partition 2. Note that, without
loss of generality, the Lyapunov functions V1 (xd ) and V2 (xd )
are scaled so that their values are the same on each point on the
SS.
To satisfy the stability condition for a cycle, it remains to find
the conditions such that the QPWLF is decreasing in transitions
from the secondary partition to first one. The discussion can
proceed based on the value of the switching surface slope λ. For
simplicity, assume first that Resr = 0, so that the ellipsoids’ axes
are located on ic = 0, and consider a positive SS slope λ ≥ 0.
Due to the ellipsoidal shape of the functions, one can observe
that a transition from partition 2 across the SS in the fourth
quadrant (e > 0 and ic < 0) will end up at a lower contour line
in partition 1. On the other hand, the Lyapunov functions are
scaled to be equal in transition from partition 1 to 2 in the second
quadrant (e < 0 and ic > 0).Therefore the QPWLF V (xd ) is not
increasing in transitions across the SS, and consequently, the
cycle is shrinking toward the origin for λ ≥ 0 similar to what is
shown in the Fig. 17.
Consider next λ < 0: in this case, a transition from partition 2
to partition 1 in the third quadrant (e < 0 and ic < 0) will end up
at a higher contour line in partition 1. The stability conditions
are not met, and the system may end up limit cycling around the
origin. An example of this behavior is shown in Section III-D.
If Resr > 0, then the ellipsoids’ axes deviate slightly from
(ic = 0) and point toward positive currents. As a result, following the aforesaid discussion, the system remains stable for small
negative λ, which can be shown to be approximately −Resr , as
in (22). This analysis can be repeated several times, till the
trajectory enters Xp .
In the experimental prototype, there are four positive SS
slopes that correspond to the 10, 7.5, 5, and 2.5 A step-up
load transients, respectively and another four slopes for the
corresponding step-down load transient. Based on the earlier
discussion, asymptotic stability is verified for each of the SS
slopes.
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Dragan Maksimovic (M’89–SM’04) received the
B.S. and M.S. degrees in electrical engineering from
the University of Belgrade, Belgrade, Serbia, in 1984
and 1986, respectively, and the Ph.D. degree from
the California Institute of Technology, Pasadena, in
1989.
From 1989 to 1992, he was with the University
of Belgrade, Serbia. Since 1992, he has been with
the Department of Electrical, Computer, and Energy
Engineering, University of Colorado, Boulder, where
he is currently a Professor, and the Director of the
Colorado Power Electronics Center. His current research interests include digital control techniques and mixed-signal IC design for power electronics.
Prof. Maksimovic is currently an Associate Editor for the IEEE
TRANSACTIONS ON POWER ELECTRONICS. He was the recipient of the 1997
National Science Foundation CAREER Award, the Power Electronics Society
Transactions Prize Paper Award in 1997 and 2008, the Bruce Holland Excellence in Teaching Award in 2004, and the University of Colorado Inventor of
the Year Award in 2006.
Amir Babazadeh (S’03) received the B.S. degree
in electrical engineering from Amirkabir University
of Technology (Tehran Polytechnic), Tehran, Iran, in
2000, the M.S. degree in electrical engineering from
Sharif University of Technology, Tehran, in 2002, and
the Ph.D. degree from the University of Colorado,
Boulder, in 2009.
From 2003 to 2006, he was engaged in research
under a Central Research Supporting Organization
for Young Researchers (ZF) Scholarship at the University of Bremen, Germany, and since 2009, he has
been with Infineon North America (Primarion Inc.), Torrance, CA, where he is
a Senior Systems Engineer. His current research interests include digital techniques in dc–dc power converters, modeling and simulation of switched-mode
dc–dc power converters, optimal control, and piecewise-linear systems.
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