Issues of CMOS Scaling —
On and Off the Roadmap
Presented at Petaflops II
Kang
KangL.
L.Wang
Wang
University
UniversityofofCalifornia,
California,Los
LosAngeles
Angeles
Device
DeviceResearch
ResearchLaboratory
Laboratory
Los
LosAngeles,
Angeles,CA
CA90095
90095
Phone:(310)825-1609
Phone:(310)825-1609Fax:(310)206-4685
Fax:(310)206-4685
EEmail:wang@ee.ucla.edu
mail:wang@ee.ucla.edu
Work in part supported by SRC, NSF and DARPA
1
The Si Story:
Scaled
-down Devices —Scaled
-up performance
Scaled-down
Scaled-up
Trend of Si MOSFET gate length in both the research and production levels for DRAM. (Ref.
NTRS, 1997, Iwai, et al Microelectronic Engineering 28, 147, 1995). Inset shows the SIA NTRS
of CMOS Technology.
2
Overview
SIA Roadmap (Manufacturing)
0.3 µm
1996
180 nm
100 nm 70 nm
2000
CMOS
CMOS
2005
Primary
Drivers
50 nm
2009
2011
• Cost
• Functionality/Density
• Low power
• Performance
Off
Off the
the Roadmap
Roadmap
••Si-based
Si-basednanostructures
nanostructures
••Quantum
Quantumeffects
effectsin
inMOS
MOS
••Integration
Integrationmethods
methods
••Functionality
Functionalityand
anddensity
density
••New
Newarchitectures
architectures
3
Current Status and the Roadmap
TiSi 2
Planar CMOS
P olySi
P oly Si G ate
Di ele ctr ic
❑
Device feature size of 10-20 nm
demonstrated
Good electrostatic characteristics
demonstrated (gain >1~10)
Cgd
n+
Lg
Source
n+
D rain
1.0
Vg=0->2V, step=0.25V
0.8
CMOS will continue to be on the
map for the next 10 years.
Id(mA/um)
❑
0.6
0.4
0.2
0.0
0.0
0.5
1.0
Vd
1.5
2.0
4
System Perspectives —
Ops
—Ops
❑
Transit time
❑
Switch time (NAND)
ts = 2τ (Cout/Cg) -32 τ
fs = Ft /10
For 10 nm device,
Ft = 1.6 THz
Clock frequency, Fclock
=Ft / 100
Total transistor ops
= Density N x Fclock
Max ops = N x Ft
❑
❑
25
(Ops/sec)/sq cm
❑
τ = Lg / v , or Ft = 1 / 2πτ
•Dispersion of the clock
•Substrate loss
•RC
10
24
10
23
10
22
10
21
10
20
10
19
10
18
10
17
10
16
10
15
10
14
10
13
10
12
10
11
10
10
10
9
10
8
10
10
Transistor Ops at ft
Transistor Ops at fclk
System Ops (ITRS)
clock frequency fclk (ITRS)
100
500
Feature Size (nm)
5
Power Consumption
❑
❑
Small
Small static
static power
power consumption
consumption
Power
Power consumption
consumption
== ffss*C
*V dd22
*Cout
out*Vdd
Power (W/sq cm)
❑
❑
10
3
10
2
10
1
10
0
10
•Subthreshold current
ITRS
Switching
Tunneling
Off Current
-1
10
-2
10
-3
10
Gate
Drain
100
Feature Size (nm)
6
Opportunities and challenges
Driver: SIA Roadmap
Banner
❑
Increase functional
throughput
▲
❑
Density
▲
❑
Interconnect
Low power/ high drive
▲
▲
❑
Functional clusters
VT and its control
VDD
Performance
▲
Gm , Ft, etc.
7
Off and Beyond SIA Roadmap
—
Roadmap—
Paradigm Shifts
❑
Device Science
3-D devices
Use quantum mechanics to
improve the integration
problem
▲
❑
Technology
❑
Patterning
ISX -- Technology
▲
▲
New Architectures
▲
▲
▲
❑
Nanometer-scale structures and
effects
❑
Minimal global interconnects
High degrees of functional
concurrency
Topological invariance
▲
Atomic/molecular scale
fluctuations
Inherently Self-adjusted,
adaptive Inherently selfassembled approach (ISX)
Other alternate approaches
New computation physics
▲
▲
What and how ?
Migration from Si ??
8
Issues on Scaled Mainstream Technology:
CMOS
Size
EB
❑
❑ Devices:
Good device :DIBL Gdd < Gmm
— Low power
Vdd
dd
Non-scalable
Non-scalable subthreshold:
subthreshold:
Subthreshold
Subthreshold leakage
leakage and
and standby
standby
power-~ 0.2~0.5 V
power-- V
Vdd
dd ~ 0.2~0.5 V
Oxide
Oxide tunneling:10-15
tunneling:10-15 A
A
Doping
Doping fluctuation
fluctuation
Hot
Hot carrier
carrier reliability
reliability
▲
▲no
no major
major problems
problems for
for low
low voltage
voltage
S
Lg
D
Given EB=0. 5 eV, WKB
tunneling gives 2.6 nm
Voltage
Subthreshold behavior
Io=exp (Vg’/kT)(1-exp (qVd/kT)),
and 4kT gives
Vdd ~ 0.2 ~0.5 V
9
SiGe CMOS Transistors — To improve Gm
SiO2
❑
❑
❑
❑
❑
❑
❑
❑
Use
Use SiGe
SiGe to
to improve
improve µ
Superlattice
Superlattice FET
FET to
to reduce
reduce alloy
alloy
scattering
scattering
Convenience
Convenience for
for CMOS
CMOS
integration
integration
Pure
Pure Ge/Si
Ge/Si thin
thin layers
layers
Poly-Si
Oxide
p+
undoped Si layer
n+
undoped-Si layer
SOI or n or p-type Si
Substrate
Expanded view of active layer
Ge
70Å Si cap layer
Undoped Short period
Si/Ge Superlattice
Si
Ec
Ef
Ev
H. Sakaki, Solid State Communications, 92, 119 (1994);
K.L. Wang, S.G. Thomas, and M.O. Tanner, "SiGe Band
Engineering for MOS,CMOS, and Quantum Effect
Devices," J. of Materials Research-Chapman &Hall,
Materials in Elec., 6, 311-324, 1995 U.K.
SimGen
Relaxed SiGe
SiO2
10
VERTICAL MOSFET
Structure
Advantages
Advantages
Higher
Higher density
density (4X
(4X or
or
greater)
greater)
Shorter
Shorter L
L (70
(70 -- 50
50 %)
%) ~~ 10
10
nm
nm
Accurate
Accurate L
L control
control
Compatible
Compatible with
with today’s
today’s
technology
technology
Freedom
Freedom in
in channel
channel
engineering
engineering
Local
Local buried
buried interconnects
interconnects
3D
3D Integration
Integration by
by stacking
stacking
Large
Large conductance
conductance
11
Device Characteristics
50 nm thick a-Si cap
edge of hole dug
with FIB
240 nm thick SiO2
300 nm thick poly-Si
Subthreshold Current
nano silicon structure
1.E-03
1.E-04
Drain Current
1.E-05
1.E-06
1.E-07
Vd = 0.5 V
Vd = 2 V
1.E-08
1.E-09
1.E-10
1.E-11
-0.8
-0.3
0.2
Gate Bias (V)
12
Improved Design
Self
-aligned Surrounding Gate Vertical MOS
Self-aligned
■
■
■
■
■
■
■
■
Low gate source
Capacitance
High gm
m
High speed
Smaller size
Poly Gate Pad
Drain (Al)
Source (Al)
n+
PECVD SiO2
LOCOS
G
n+
n+
G
As implantation n+
p- Si+ Substrate
13
Potential Tera
-scale Integration
Tera-scale
HIGH
HIGH DENSITY
DENSITY
Superimposed
Superimposed Source/Drain
Source/Drain
electrodes
electrodes
Three
Three parallel
parallel interconnection
interconnection
layers
layers
LAYOUTS
LAYOUTS OF
OF TWO
TWO INPUT
INPUT NAND
NAND GATE
GATE
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
SOI
SOI CMOS:
CMOS: 156
156 λλ22
==SOI
SOI VCMOS:
VCMOS: 42
42 λλ22,, about
about 1:4
1:4
Assuming
Assuming λλ==== 30
30 nm
nm and
and A
A == 80
80 cm
cm22
12 / chip
Device
Device density
density ~~ 10
1012
/ chip
3-D
3-D integration
integration
14
SRAM Using a Bistable Tunneling Element
Reduce SRAM From Six CMOS to One Pillar
with Three Elements
❑
SRAM Macro with Vertical
MOS and Bistable Diode
Word Line
VDD
I
state II
VOH
VOL
Bit Line
VIH
p-Si
VOUT
A
VSS
GeSi
B
state I
V
n-Si
VBIT (pulse)
p-Si for Vertical MOS Channel
VIL
Poly Gate
n-Si epilayer for Vertical MOS Source
Si Substrate
Bit
line
VDD
Time
R LOAD
Vertical MOS
VOUT
Diode Bi-stable
Word line
GND
High Speed
Low Power
High density
15
Integration of Quantum Well Bistable Diode
with CMOS (Si)
undoped
Si 100Å
n
Si
50Å
n
Si
1000Å
undoped Si 50Å
undoped Si 400Å
■
■
■
■
■
■
■
■
Reduce
Reducedevice
devicecount
count
Nanometer
Nanometerscale
scale
Fully
FullySiSi
High
Highconductance
conductanceon
on
state
and
high
state and high
resistance
resistanceoff
offstate
state
undoped Si 100Å
Ionized Acceptors
Ionized Donors
p
Si
2000Å
p
Si(100)
Sub
MT235F
16
Memory and Logic Macros
Logic
Logic Macros
Macros
❑
❑ Integration
Integration with
with Bipolar
Bipolar
transistors
transistors
Full
Full adder,
adder, XNOR,
XNOR, etc.
etc.
❑
❑ How
How to
to take
take advantages
advantages of
of
quantum
quantum devices
devices with
with CMOS?
CMOS?
Logic
Logic Macros
Macros
❑
❑ Reduced
Reduced cell
cell area
area
❑
❑ Reduced
Reduced Power
Power
Ref. A. C. Seabaugh, et al., IEDM 1993, 419-422.
17
Interconnect Issues
Cu
Cu and
and Low
Low K
K aa factor
factor of
of 66
improvement
improvement
Global
Global Interconnects
Interconnects (signal
(signal fidelity)
fidelity)
❑
❑ Electrical
Electrical interconnects
interconnects
❑
❑
Fat
Fat multilayer
multilayer wires
wires
Increase
Increase height:
height: vertical
vertical
integration
integration and
and geometry:
geometry: to
to
minimize
minimize the
the interference
interference
New
New directions
directions
Integrated
Integrated approach
approach
Incorporating
Incorporating quantum
quantum devices
devices to
to
increase
increase functionality
functionality and
and
reduce
reduce the
the contacts
contacts and
and
interconnects
interconnects
Optical
Optical &Wireless
&Wireless interconnects
interconnects
CONNECTION PROBABILITY
Delay : ( Rw )( 0.4 ⋅ CL ⋅ L + CT )
Interconnect Probability
0.08
Local Interconnect
0.06
0.04
Global Interconnect
0.02
0
0
0.2
0.4
0.6
0.8
1.0
WIRE LENGTH/CHIP DIAGONAL LENGTH
Global Interconnect
Local Interconnect
18
33-D
-D Integration and Architectures
❑
❑
❑
❑
Multilayer
Multilayer in-situ
in-situ integration
integration
Ex-situ
Ex-situ integration:
integration:
Optical
Optical and
and wireless
wireless
MCM
MCM and
and alike
alike
Wireless
Wireless interconnects
interconnects
▲
▲ Microwave
Microwave strip
strip lines,
lines,
Cellular
Cellular
Optical
Optical interconnects
interconnects
▲
▲ Light
Light source:
source: Polymer,
Polymer, SiSibased
based
Vert. diamond vias
CVD Diamond Film
Low Standby
Power Logics
and Memories
❑
❑
SiO2
Si
Mixed-signal Circuits
(RF Wireless etc.)
Radiation
V
D D
Vertical stack illustrating many layers
vertically. The bottom one is for mixed
mode devices and the top ones are for
DSP circuits and memories.
17
17
18
03 V
S S
02
In-situ
Ex-situ
19
Optical Interconnect — Chip --to-Chip
to-Chip
On-chip
On-chip components
components
❑
❑ Waveguides
Waveguides
❑
❑ Detectors
Detectors
❑
❑ Sources
Sources
❑
❑ Modulators
Modulators
Off-chip
Off-chip components
components
❑
❑ Sources
Sources
OE components
OE components
ULSI chip
Fiber In
Fiber
Out
Carrier
Challenge: Source and efficiency
20
ISX Fabrication of Nanodevices
1996
0.3 µm
❑
❑
Alternate Approach
Self-assembly: quantum dots
Molecular and atomic
manipulation or engineering
Facet
Facet growth,
growth, selective
selective growth,
growth, and
and
vicinal
vicinal surface
surface
2000
180 nm
Optical Lithography
2006
100 nm
2009
Deep or EUV
70 nm
Self-assembly
❑
❑
Technology issues:
Size variations
Registration (ISX)
2012
50 nm
1nm
Atomic plane and
Molecular sizes
21
Arranged Array on a Strained Pattern
Processing (ISX)
• Self-registration
• nonlinear behaviors in the process
Kamins, et al. (HP)
Molecular Engineering?
22
Nanoelectronics Architecures
Requirements: R. Bate; J. Barker and others
❑❑
❑❑
❑❑
❑❑
❑❑
❑❑
Power
Powerdissipation:
dissipation:Short
Short
interconnect,
interconnect,concurrent
concurrent
architecture
architecture
Local
Localinterconnections
interconnections
Minimal
Minimaldevice
devicefan-outs
fan-outs
Local
Localfunctions
functionsbased
basedon
on
Distributed
Distributeddevice
deviceproperties
properties
Fault
Faultmanagement
managementininall
alllevels
levelsof
of
functionality
functionality
Self
Selfassembly
assemblyand
andself
selfrepairing
repairing
logic's
logic's(ISX)
(ISX)
❑❑
❑❑
❑❑
❑❑
❑❑
Systolic
Systolicarrays
arraysand
and
Hypermesh
Hypermesh
Highly
Highlyparallel
parallel
Cellular
CellularAutomata
Automata
Highly
Highlyparallel
parallel
State
Statemachine
machine
Adaptive
Adaptive
Neural
Neuralnetwork
network
Collective
Collectivecomputations
computations
Other
Othercomputational
computational
methods:
methods:e.g.,
e.g.,Quantum
Quantum
computation
computation
R.T.Bate, SPIE 729, 26 in Quantum well and superlattice physics, (1987)
23
Computational/Memory Array Incorporating
Quantum Devices
RTD or Zener diode
24
Quantum Computer
Quantum entanglement of states
α
Classical Bit
+β
Quantum parallel
Processing
0 or 1 or α 0 + β 1
0 or 1
000
001
011
100
100
101
110
111
Quantum Bit
T
T(000)_
T(001)
T(011)
T(100)_
T(100)
T(101)
T(110)
T(111)
25
Quantum Computation
Radical speed-up of the following tasks
❑
❑
Factorization of big numbers [D. Deutsch, P. Shor]
— polynomial time solution
Searching of databases [Grover] — solution in
O(N)1/2 steps as compared to O(N) steps
26
Summary
SIA Roadmap (Manufacturing)
0.3 µm
1996
180 nm
2000
100 nm 70 nm
2006
2008
50 nm
10 nm
2010
2016
• Increasing Integration scale
(density and)
SIA
SIAITRS
ITRS • Increasing functional throughput
(speed)
• Low power
CMOS
CMOS
New
Paradigms
•• Device
Device Science
Science —
— Integrated
Integrated Quantum
Quantum
effects
effects in
in MOS
MOS
ISX
•• Process
Process in
in Si-based
Si-based nanostructures
nanostructures
•• New
New architectures
architectures and
and new
new computation
computation
methods
methods
27