QUEEN'S UNIVERSITY AT KINGSTON
\QECE
ELECTRICAL &COMPUTER ENGINEERING
ELEC451
Digital Integrated Circuit
Engineering
Course Notes
Fall 2009
© S.J. Simmons 2005-2009
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Introduction
1
MOS Transistors
4
MOS Current versus Voltage Characteristics
9
CMOS Processing
11
The CMOS N-Well Process
17
Other Process Issues
23
Design Rules
26
The CMOS Inverter
30
CMOS Logic Implementation
34
Efficient CMOS Logic Layout
37
Muliplexer-Based Logic Implementation
39
Alternative Logic Implementations
43
CMOS Dynamic Behaviour
47
Sloped Signals and CMOS Dynamic Behaviour
49
Switched-R Delay Modelling
52
CMOS Power Dissipation
54
CMOS Transistor Parasitic Capacitances
57
Characterizing Logic Gate Delays
60
Buffering to Reduce Total Propagation Delay
64
Latches and Flip-Flops for Clocked Systems
66
Dynamic Logic
70
Clocked Systems Concepts
74
Static vs. Dynamic Clocked Systems
77
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Clock Overlap Issues
81
Interconnect Delay Contributions
84
Clock Distribution
87
Chip Input/Output Circuits and Connections
90
Memory Arrays
95
Static RAM (SRAM)
100
Dynamic RAM (DRAM)
104
Erasable Progra.mmable ROM
108
Programmable Logic
113
Process Technology Scaling Issues
120
Low Power Methods
124
Design/Implementation Alternatives
131
Design Flow
138
The Present, and Future Trends
146
AfterWord
150
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Introduction
In ELEC451 we will look at the engineering of digital integrated circuits from the bottom up.
We begin the course by examining the physical process by which CMOS transistors are
fabricated on a silicon wafer, and end the course with the design processes used to design multi­
million-transistor chips.
By the end of the course, you should have an appreciation for and basic understanding of:
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The scale of modern day digital integrated circuits.
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The speed at which the circuits operate, and how to model their switching behaviour.
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The different circuit styles that can be employed, and their relative advantages and
disadvantages.
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The dominant role played by circuit pa.rasitics in circuit/chip performance.
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How weak on-chip signals are interfaced to drive circuit board lines in the external world.
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How ongoing technological advances affect circuit speed, density, and power consumption.
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The design and characteristics of different volatile and non-volatile memory types.
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The design of programmable logic arrays.
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The different chip implementation styles available to the designer.
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The design flow from circuit concept to final chip implementation.
The Semiconductor Industry Association (an affiliation of interested companies and
organizations) periodically issues a "technology roadmap" that makes predictions about where
integrated circuit engineering is headed. Figure 1 and Table 1 on page 2 illustrate trends in
process feature size, number of transistors per chip, and microprocessor chip clock rate. Note
how regular periodic shrinks in feature sizes have been allowing an exponential rate of increase
in the number of transistors per chip, and in the achievable clock speeds, without power
consumption exploding (and this trend is predicted to continue in the near future). We will see
later in the course why these gains have been possible.
Page 3 is a die photomicrograph of a Pentium™ II processor (courtesy Intel Corporation). This
photo illustrates the enormous level of circuit integration that was possible even several years
ago, and gives a useful encapsulation of what we wish to study in ELEC451. We will explore the
processes and design considerations that go into the creation of such a device, and the limits on
its performance.
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DEEP-SUBMICRON DESIGN
2001
0.15
IV
·2003
0.13" .
1.2-1.5
1.2-1.5
40M
76M
1.7G
4.2.9G
385
430
1,500
2,100
1,400
1,600
110
130
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Pentium™
3