4
IC TECHNOLOGY AND PACKAGING TRENDS
MARKET OVERVIEW
In 1970 bipolar ICs represented almost two-thirds of the total IC market (Figure 4-1). In 1995,
however, bipolar ICs accounted for only about 12 percent of the IC dollar volume shipped.
Marketshare
(Percent)
Process
Technology
Characteristics
1970 1980 1994
1995
(EST)
2000
(FCST)
MOS:
31
5
—
—
—
Obsolete
2
37
1
<1
<1
CMOS
Mainstream technology, extensive research
has solved inherent difficulties (e. g., latch-up,
slow operation)
2
10
78
79
90
BiCMOS
Offers both MOS and bipolar advantages.
High cost/complexity limits applications.
—
—
5
8
3
ECL
Fastest silicon-based process, competing
with GaAs. Becoming obsolete.
3
3
1
<1
<1
TTL
Slow, obsolete
29
8
<1
<1
—
S/LS TTL
Mainstream bipolar logic, under pressure
from MOS ASICs
7
13
2
1
<1
LINEAR
Mainstream analog technology, some
competition from CMOS, especially in
A/D converters and amplifiers, and GaAs
26
24
12
10
6
Cost competitive with ECL. Will be used
especially for analog applications in the future.
—
—
<1
<1
<1
PMOS
Slow, obsolete
NMOS/HMOS
Bipolar:
GaAs:
Source: ICE, "Status 1996"
11218S
Figure 4-1. Marketshare Overview of Process Technology
As shown, five of the nine technologies listed in Figure 4-1 were either obsolete in 1995 or will be
by 2000. These technologies include PMOS, NMOS, ECL, TTL, and S/LS TTL. Systems houses
would be wise to stay clear of designing-in ICs that use any of these five technologies, especially
if the system is intended to have a long lifetime.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-1
IC Technology and Packaging Trends
No technology of the past has dominated the IC marketplace like CMOS does now. ICE estimates
that ICs produced using CMOS will represent 90 percent of the total merchant market IC dollar
volume in 2000 (Figure 4-2).
Other 3%
Bipolar 7%
Bipolar
12%
Other
9%
1995
$128.5B
CMOS 79%
2000
$331.9B
CMOS 90%
Source: ICE, "Status 1996"
20282A
Figure 4-2. CMOS, Dominant IC Process Technology
It is interesting to note the small marketshare ECL-based ICs have held over the past twenty-four
years. It seems that in the past, and into the future, although ECL ICs are the fastest silicon-based
devices available, the high power dissipation and high cost of ECL circuitry will relegate it to only
a niche process technology. ECL IC sales are forecast to represent less than one-half of one percent
of the dollar volume sold in 2000.
From 1995 to 2000 ICE forecasts that BiCMOS ICs will show an –5 percent CAGR ($10.7B to $8.4B).
Moreover, BiCMOS ICs will represent only three percent of the total IC market and will still be
considered a high-performance niche technology.
Figure 4-3 shows the major IC process technologies and their positions on the bell-shaped lifecycle curve. ECL technology is now approaching the “obsolete stage.” CMOS technology has been
in the “maturity” stage since the mid-1980’s. Moreover, ICE expects that CMOS will still be in the
maturity stage well into the twenty-first century. As of 1995, there was no new technology that
showed the potential to dethrone CMOS as the mainstream IC process in the foreseeable future.
Cost effectiveness, steadily increasing performance, and consistently high levels of investment in
research and development by the IC manufacturers will keep CMOS the mainstream technology
throughout the 1990’s and beyond.
Figure 4-4 shows the IC process technology marketshare trends from 1982 through 2000. This
illustrates very clearly how CMOS technology has become the dominant process at the expense of
NMOS and bipolar digital. CMOS ASICs and standard logic will continue to replace TTL, and
CMOS DRAMs and microprocessor products have replaced NMOS DRAMs and most MPU
4-2
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
devices. Considering the enormous expense of a fab facility and the increasing complexity of the
IC technology, non-CMOS processes have become a luxury that most IC producers cannot afford.
CMOS
BIPOLAR
ANALOG
S/LS TTL
GaAs
ECL
BiCMOS
Diamond
HMOS
SiGe
TTL
PMOS
NMOS
Introduction
Growth
Maturity
Saturation
Decline
Source: ICE, "Status 1996"
Obsolete
16809G
Figure 4-3. Process Technology Lifecycle (1995)
($)
<1%
<1%
100
4%
ECL
90
19%
<1%
<1% GaAs
AND OTHER
BIPOLAR
4%
TTL AND
OTHER
12%
BIPOLAR
ANALOG
20%
2% 1%
10%
12%
80
70
<1% <1% ECL
TTL
6%
<1%
<1%
PERCENT
22%
60
<1%
PMOS
2%
50
24%
79%
78%
40
MOS
90%
NMOS
41%
30
20
39%
BiCMOS
CMOS
10
12%
8%
5%
0
1982
$10.2B
Source: ICE, "Status 1996"
1994
$90.3B
1987
$29.0B
1995
$128.5B
YEAR
3%
2000
$331.9B
12070R
Figure 4-4. 1982-2000 IC Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-3
IC Technology and Packaging Trends
Figures 4-5 and 4-6 show the MOS market as expressed in dollars. The popularity of CMOS compared to NMOS, PMOS, and BiCMOS is very evident here. ICE forecasts that BiCMOS and CMOS
will represent almost 100 percent of the total MOS market in 2000. CMOS became the technology
of choice for MOS memory as density reached and surpassed 1M. All 1M and denser DRAMs are
produced using CMOS technology and ICE believes that nearly all of the VLSI and ULSI memory devices of the future will be CMOS or BiCMOS.
100
4%
PMOS
90
1 % <1%
<1%
<1%
80
39%
NMOS
PERCENT
70
60
74%
89%
50
97%
93%
40
30
60%
20
10
BiCMOS
CMOS
22%
10%
6%
0
1982
$5.5B
1987
$18.4B
1994
$76.6B
1995
$112.5B
3%
2000
$307.3B
Year
Source: ICE, "Status 1996"
12072R
Figure 4-5. 1982-2000 MOS Technology Trends
Bipolar technology market trends are shown in Figure 4-7. The “ECL” and “TTL and Other” segments of the bipolar market are forecast to decrease in magnitude as well as in percent of the total.
CMOS ASICs and standard logic are replacing many of the TTL devices. Figure 4-8 shows the continued decline in the TTL logic segment that is forecast to occur throughout the 1990’s. Overall,
although the bipolar segment is rapidly shrinking in marketshare (from 12 percent in 1995 to only
about six percent in 2000), the total bipolar dollar volume is forecast to display a six percent CAGR
from 1987 to 2000.
4-4
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Technology
1987 - 2000
CAGR
(Percent)
7,350
1,100
880
320
–21
11,050
70,885
100,905
298,530
29
—
4,605
10,700
8,425
18,400
76,560
112,485
307,275
BiCMOS
Total
2000
($M)
(FCST)
1994
($M)
NMOS and PMOS
CMOS
1995
($M)
(EST)
1987
($M)
11 *
24
*CAGR from 1994-2000
Source: ICE, "Status 1996"
16811J
Figure 4-6. MOS Technology Market Trends (1987-2000)
100
10%
ECL
7%
12%
6%
2% 4%
90
15%
13%
80
70
42%
TTL AND
OTHER
32%
Percent
60
50
78%
40
30
ANALOG
48%
81%
94%
56%
20
10
0
1982
$4.6B
2000
$22.8B
1994
$13.3B
1987
$10.6B
1995
$15.5B
Year
Source: ICE, "Status 1996"
12073R
Figure 4-7. 1982-2000 Bipolar Technology Trends
The reader should be cautioned against putting too much emphasis on the 1995 16 percent
increase in the bipolar IC market. The very strong yen was responsible for a good deal of the 1995
total bipolar analog market increase. Even the strong overall IC demand will not give a reprieve
to the declining TTL and other bipolar logic market in the future (Figure 4-9).
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-5
IC Technology and Packaging Trends
1987
($M)
Technology
1994
($M)
1995
($M)
(EST)
2000
($M)
(FCST)
1987 – 2000
CAGR
(Percent)
ECL
1,265
860
965
480
–7
TTL and Other
3,400
2,065
1,988
996
–9
Bipolar Analog
5,935
10,390
12,520
21,315
10
10,600
13,315
15,473
22,791
6
Total
Source: ICE, "Status 1996"
16812J
Figure 4-8. Bipolar Technology Market Trends (1987-2000)
1994
1995
(EST)
General Purpose
1,100
1,085
550
Special Purpose
435
450
340
–5
Gate Array/Std. Cell
295
270
55
–27
Product
MPU/MCU/MPR
FPL
Memory
Total
2000
(FCST)
1995 - 2000
CAGR
–13
20
8
1
–34
155
120
40
–20
60
55
10
–29
2,065
1,988
996
–13
Source: ICE, "Status 1996"
18881D
Figure 4-9. TTL/Other Bipolar Logic Market
CMOS
CMOS technology continues to be much more popular than other technologies due to the following key reasons.
• Experience/inertia
• Low power density.
• Relatively good noise immunity and soft error protection.
• Low threshold bias sensitivity.
• Design simplicity and relatively easy layout, especially for ASICs.
• Capability for lower power analog and digital circuitry on the same chip.
Because of these advantages, CMOS is expected to continue to be the technology of choice for the
VLSI and ULSI products of the future. Just as NMOS replaced the slower and more power-hungry PMOS technology in the 1970’s, CMOS supplanted NMOS in the 1980’s. The speed and power
characteristics of CMOS are the major contributors to its increase in marketshare. In fact, CMOS
will approach bipolar speeds as lithography techniques improve, gate oxides become thinner, and
smaller feature sizes become manufacturable.
4-6
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
CMOS technology continues to advance and evolve to meet the majority of IC performance
demands. Figure 4-10 shows the historical trends in CMOS technology.
1977
1980
1983
1986
1989
1992
Gate Length (µm)
3
2
1.5
1.1
0.9
0.6
Channel Length (µm)(Leff)
2
1.5
1.2
0.9
0.6
0.4
Gate Oxide (Å)
700
400
250
250
200
150
Junction Depth (µm)
0.6
0.4
0.3
0.25
0.2
0.15
5
5
5
5
5
5
NMOS Idsat @ Vg = 5V (mA/µm)
0.1
0.14
0.23
0.27
0.36
0.56
PMOS Idsat @ Vg = 5V (mA/µm)
—
0.06
0.11
0.14
0.19
0.27
800
350
250
200
160
VCC (V)
Gate Delay @ FO = 1 (ps)
Source: UC Berkeley/Semiconductor International/ICE, "Status 1996"
90
19211A
Figure 4-10. Historical Trends in MOSFET Scaling
As feature sizes shrink below 0.5µm and gate oxides thin to less than 100Å (Figure 4-11), a 5V
power supply is not practical. Therefore, these devices are being designed for 3.3V power supplies
(or lower) or are designed for 5V with the signal being converted to a lower voltage internally. In
the late 1990’s and early 2000’s, it is expected that ICs with operating voltages of 2V and less will
be required (Figure 4-12).
Figure 4-13 shows the Semiconductor Industry Association’s National Technology Roadmap for
Semiconductors, released in 1994. Because the devices described will most likely be CMOS, it can
also be considered a 15-year roadmap for CMOS processing technology.
While 0.1µm CMOS technology is not expected to be in widespread use before the year 2000,
many of the large IC producers with advanced research labs are already releasing data on such
devices. Figure 4-14 shows Fujitsu’s preliminary 0.1µm CMOS process parameters.
Figure 4-15 shows performance results from AT&T, Fujitsu, and IBM for their ≤0.25µm CMOS
devices. As shown, power supply voltage levels experimented with range from 0.5V to 3.0V. One
of the drawbacks to moving to lower voltage levels is the difficulty in improving performance at
the same rate as was accomplished using 5V. As shown in Figure 4-16, low-voltage technology
performance is expected to double every four generations as opposed to every two generations
when using 5V. Figure 4-17 looks at some of the driving factors affecting the move to low-voltage
device technology.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-7
IC Technology and Packaging Trends
160
140
Published Data
Trend Line
Gate Oxide Thickness (Å)
120
100
80
60
40
20
0
0
0.1
0.2
0.3
Gate Length (µm)
0.4
0.5
Source: Intel/ICE, "Status 1996"
0.6
20284
Figure 4-11. Gate Oxide Thickness Trend
6
5
Operating Voltage (V)
Published Data
Trend Line
4
3
2
1
0
0
0.1
0.2
0.3
Gate Length (µm)
0.4
Source: Intel/ICE, "Status 1996"
0.5
0.6
20285
Figure 4-12. Operating Voltage Trend
4-8
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Driver
Year of first DRAM shipment
Minimum feature (µm)
1995
0.35
1998
0.25
2001
0.18
2004
0.13
2007
0.10
2010
0.07
Memory
Bits/chip (DRAM/flash)
Cost/bit @ volume (millicents)
64M
0.017
256M
0.007
1G
0.003
4G
0.001
16G
0.0005
64G
0.0002
4M
2M
1
7M
6M
0.5
13M
20M
0.2
25M
50M
0.1
50M
2100M
0.05
90M
300M
0.02
2M
0.3
4M
0.1
7M
0.05
12M
0.03
25M
0.02
40M
0.01
Number of Chip I/Os
Chip to package (pads) high perf.
900
1350
2000
2600
3600
4800
L,A
Number of package pins/balls
Microprocessor/controller
ASIC (high performance)
Package cost (cents/pin)
512
750
1.4
512
1100
1.3
512
1700
1.1
512
2200
1.0
800
3000
0.9
1024
4000
0.8
A
Chip frequency (MHz)
On-chip clock, cost-performance
On-chip clock, high-performance
Chip-to-board speed, high performance
150
300
150
200
450
200
300
600
250
400
800
300
500
1000
375
625
1100
475
Chip size (mm2)
DRAM
Microprocessor
ASIC
190
250
450
280
300
660
420
360
750
640
430
900
960
520
1100
1400
620
1400
Maximum number wiring levels (logic)
On-chip
4–5
5
5–6
6
6–7
7–8
µP
Defect density (d/cm2)
0.75
0.45
0.35
0.25
0.2
0.15
D
Minimum mask count
Cycle time days (theoretical)
18
9
20
10
20
10
22
11
22
11
24
12
L
L
Maximum substrate diameter (mm)
Bulk or epitaxial or SOI† wafer
200
200
300
300
400
400
D
Power supply voltage (V)
Desktop
Battery
3.3
2.5
1.5
0.9
1.2
0.9
0.9
0.9
µP
A
Maximum power
High performance with heatsink (W)
Logic without heatsink (W/cm2)
Battery
80
5
2.5
100
7
2.5
120
10
3.0
140
10
3.5
160
10
4.0
180
10
4.5
µP
A
L
3.3
16–32
25
1.7
16–32
40
1.3
16–32
50
0.7
8–16
70
0.5
4–8
90
0.4
4
90+
L
L
L
Logic (High volume: Microprocessor)
Logic transistors/cm2 (packed)
Bits/cm2 (cache SRAM)
Cost transistor @ volume (millicents)
D
L(µP)
L(A)
Logic (Low volume: ASIC)
Transistors/cm2 (auto layout)
Nonrecurring engineering
cost/transistor (millicents)
Design and test
Volume tester cost/pin ($K)
Number of test vectors (µP/M)
% IC function with BIST/DFT#
† silicon-on-insulator
1.8
2.5
1.8–2.5 0.9–1.8
µP
L
A=ASIC D=DRAM
L=Logic µP=Microprocessor
* built-in self test
# design for testability
Source: Solid State Technology/ICE, "Status 1996"
20286A
Figure 4-13. The 15-Year SIA Roadmap
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-9
IC Technology and Packaging Trends
Parameter
NMOS
PMOS
10Ωcm p-type (100)
10Ωcm p-type (100)
Twin Well
Twin Well
350nm LOCOS
350nm LOCOS
B+ 40keV 7 x 1012
As+ 180keV 5 x 1012
Gate Oxide
3.9nm (800°C)
3.9nm (800°C)
Gate Stack
Poly-Si 160nm + SiO2 50nm
Poly-Si 160nm + SiO2 50nm
As+ 10keV 4 x 1013
BF2+ 5keV 1 x 1014
SiN 60nm
SiN 60nm
As+ 30keV 3.2 x 1015
BF2+ 20keV 5 x 1015
850°C, 5 minutes
850°C, 5 minutes
Starting Material
Well
Isolation
Channel Implant
Shallow Junction Implant
Spacer
Deep Junction Implant
Anneal
Source: Fujitsu/IEDM/ICE, "Status 1996"
19214
45
100
80
0.25µm
60
0.20µm
40
Unloaded 51-stage CMOS inverter
Delay Time (ps/gate)
Delay (ps)
Figure 4-14. Process Parameters of 0.1µm CMOS
0.15µm
20
0.10µm
40
Lg = 0.15µm
35
30
Lg = 0.1µm
Lg = 0.075µm
25
20
15
10
1.0
1.5
2.0
2.5
1.5
2.0
2.5
3.0
Supply Voltage (V)
Supply Voltage (V)
Unloaded gate delay as a function
of power supply voltage and gate length
CMOS inverter gate delay versus
power supply voltage
Source: AT&T/ICE, "Status 1996"
3.5
Source: Fujitsu/ICE, "Status 1996"
Gate Delay/Stage (ps)
200
100
80
60
Leff (n/p)
(0.25µm CMOS)
0.14/0.12µm
0.12/0.10µm
0.12/0.10µm (simulation)
40
20
300K
10
0.5
1.0
1.5
2.0
Supply Voltage (V)
2.5
Measured (points) and simulated (dashed)
CMOS-inverter delay versus supply voltage
Source: IBM/ICE, "Status 1996"
19215
Figure 4-15. IEDM ≤0.25µ CMOS Performance Results
4-10
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
350
315
280
245
1.0
0.9
0.8
0.7
210
Speed Doubles Every
2 Generations
0.5
175
0.4
140
105
0.3
3.3V
2.2V
1.5V
5V
0.2
(Low Power)
70
Unloaded Inverter Delay (ps)
Gate Delay (Arbitrary Units)
0.6
3.3V
Speed Doubles Every
4 Generations
(High Speed)
2.2V
0.1
2µm
1µm
0.5µm
0.25µm
35
0.13µm
Technology Generation
Source: ISSCC94/UC Berkeley/ICE, "Status 1996"
19499
Figure 4-16. Low-Power Speed Lag
Primary Feature
Feature Driver
Continued requirements for
higher integration density
Products
DRAMs
Pros and Cons
Slowest Voltage versus Time
evolution
SRAMs
Device
Physics
Not a driver for revolutionary
device technology changes
Integration density drives scaling
Scaling drives device physics
Not a good test bed for nondevice power reduction
techniques
Device physics limit operating
voltage, resulting in lower power
High
Performance
Portable
Products
High integration density circuits
operating at maximum
performance bump against
package power constraint
MPUs
DSPs
Basic cell performance may
start to diminish; power limited
performance not compensated
by scaling
ASICs
Increased performance will
require non-device and nonscaling solutions: systems
circuits, . . . .
Reduced power achieved by
lower operating voltage or
design modifications
Full custom
Battery life as key operator
MCUs
Fastest Voltage versus Time driver
May compromise integration
density
DSPs
Non-traditional technology driver
Frequency
Control
Drives revolutionary device
technologies: GaAs, modified
CMOS, mixed technologies
May not require peak
performance (frequency,
delays, MIPS,. . . .)
Some specialized products
RF/An./Dig
Lacks industry infrastructure and
volume support base
Source: Motorola/ICE, "Status 1996"
20287
Figure 4-17. Voltage Reduction Drivers
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-11
IC Technology and Packaging Trends
As the composition of most digital systems changes from TTL to CMOS, the use of the 5V power
supply may no longer be an asset, but a liability. Since power consumption is proportional to the
square of the supply voltage, lowering the voltage from 5V to 3.3V can reduce the power as much
as 70 percent. This means less heat has to be removed from the package.
CMOS is the current technology of choice in all but the fastest systems. CMOS can be designed to
operate from very high voltage supplies down to the 0.7V found in watches. Each end of this
range has its own problems. If the supply voltage were very high, the power consumption would
be very high but the ICs would not be susceptible to noise voltage and incorrect states. At the
other extreme, the opposite is true.
As has been touched upon, CMOS’ primary attribute is the ability to operate at low-power and
low-voltage levels. These characteristics have become especially important in the emerging 3.3V
portable, laptop, notebook, etc., PC markets (Figure 4-18). With the continuing trend toward finer
IC feature sizes and compact portable systems, the increased availability of low-voltage CMOS
ICs helped pure 2.7V-3.3V systems proliferate beginning in the early 1990’s. It is estimated that
most of the 2000 IC market will be served by ≤3.3V ICs (up from about 12 percent in 1995).*
Power (W) at 5V
Notebook Computer
System Components
Typical 5V
Power
(W)
Power at
3.3V Logic
(W)
Expected
3.3V Power
(W)
Logic
Other
Functions
CPU Plus Core Logic
2.20
0.00
2.20
0.95
0.95
System Memory
0.50
0.00
0.50
0.22
0.22
Display Controller Subsystem
1.50
0.00
1.50
0.65
0.65
LCD Panel Plus Backlight
0.30
3.20
3.50
0.13
3.33
Hard-Disk Drive*
0.20
0.30
0.50
0.09
0.39
Miscellaneous Circuits
0.50
0.00
0.50
0.21
0.21
DC/DC Conversion
0.00
1.70
1.70
0.00
1.20
Total System Power
10.40
6.95
*Hard-disk drive power estimates reflect a mix of active and idle time.
Source: Cirrus Logic/Electronic Products/ICE, "Status 1996"
19217
Figure 4-18. 3.3V Logic Power Savings in a Typical Notebook Computer
The demand for low-voltage ICs came on so fast that it caught most IC producers by surprise.
Many companies initially tried to satisfy this surging demand by offering screened 5V parts that
would also operate at lower voltages. However, this “derating” oftentimes caused problems in the
system under certain operating conditions. Thus, almost all IC producers have aggressively introduced fully characterized devices that are specifically designed for low-voltage operation.
* In 1995 about 10 percent of 4M DRAMs, 25 percent of 16M DRAMs, and 90 percent of the 64M DRAMs used a 3.3V power
supply.
4-12
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
In the transition period from 5V to low-voltage systems, system designers will be using both 5V
and low-voltage ICs on the same printed circuit board (Figure 4-19). Targeting such systems,
AT&T offers a standard cell library that allows the user to mix and match 5V and 3V cells on the
same chip. Other companies that are helping bridge the 5V to low-voltage gap with “mixed-voltage” ICs include Oki, TI, Toshiba, Atmel, and NCR.
100
90
Percentage of Design Starts
80
70
5V
60
50
3V
40
30
20
5/3V
10
2.xV
0
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
Year
Source: VLSI Technology/ICE, "Status 1996"
19179A
Figure 4-19. Transition from 5V to 3V Systems
ECL
Inherently, ECL devices are very uniform, stable, and generate low noise. Also, ECL requires only
a 1V swing in 3-4ns compared with a typical TTL chip that requires a 5V swing in the same timeframe.
Even though the tradeoffs of ECL’s high speed versus CMOS’ low cost and low power are well
known, there is a trend that is beginning to blur those distinctions — convergence. Many new
high-end, high-performance systems are mixing ECL or TTL with CMOS to optimize the designs
for both high speed and low cost (e.g., BiCMOS).
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-13
IC Technology and Packaging Trends
The ECL IC market was about $965 million in 1995 and is made up of ASIC, standard and special
purpose logic, and memory devices (Figure 4-20). ASICs held 55 percent of the total ECL market
in 1995 and that is expected to decrease to 48 percent in 2000. Logic devices held 29 percent of the
ECL market in 1995 with 41 percent forecast for 2000. As is shown in Figure 4-20, the 2000 ECL
IC market is forecast to be about half of what it was in 1995.
Product
1991
($M)
1991
percent
of total
1994
($M)
1994
percent
of total
1995
(EST)
($M)
1995
percent
of total
2000
(FCST)
($M)
2000
percent
of total
Memory
305
19
150
17
150
16
55
11
Total Logic*
280
18
275
32
285
29
195
41
ASIC
965
63
435
51
530
55
230
48
Total
1,550
100
860
100
965
100
480
100
*Includes General and Special Purpose Logic.
Source: ICE, "Status 1996"
18110F
Figure 4-20. ECL IC Market Forecast
One of the reasons for the forecasted steep decline in the ECL market is the use of GaAs, BiCMOS,
and even CMOS technologies in what were the bastions of ECL ICs—mainframes and supercomputers. For example, in Fujitsu’s minisupercomputers (VPP300 and VX), Fujitsu is using only
CMOS ICs. These minisupercomputers are air-cooled and use vector parallel processing to
achieve up to 35.2Gflops performance. Moreover, in mid-1993 Fujitsu announced it was suspending future development of ECL gate arrays. A Fujitsu spokesman was quoted as saying that ECL
designs are disappearing very rapidly in the marketplace.
The movement to using other technologies besides ECL for high-speed systems is especially devastating to the large military ECL IC market. The lackluster military IC market coupled with the
increasing use of CMOS, GaAs, and BiCMOS ICs will heavily contribute to the declining ECL IC
industry in the mid-to-late 1990’s.
It now appears unlikely that future improvements in ECL technology will come from the purely
merchant IC vendors. This is due in some part to the relatively small ECL IC market (less than one
percent of the total 1995 merchant IC market) and the low volume of research money being spent
on ECL technology by the open-market vendors.
The major ECL IC manufacturers are shown in Figure 4-21. These producers accounted for about
98 percent of the merchant ECL IC market in 1995.
The Japanese companies have traditionally had the largest ECL IC marketshare primarily because
of their emphasis on mainframe computers. It is interesting to note that at the 1995 ISSCC conference there was only one paper (given on “low-power” ECL by Toshiba) delivered (out of 123 total)
4-14
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
that dealt with strictly ECL technology. Typically, if ECL technology was described in a paper it
was usually coupled with CMOS circuitry in a BiCMOS process. As has been discussed, the trend
of replacing ECL circuitry in most new systems with CMOS, BiCMOS, and GaAs technologies is
well on its way.
1995 Sales
($M, EST)
Marketshare
(Percent)
Major Emphasis
Fujitsu
270
28
ASICs, SRAMs
Motorola
225
23
ASICs, Logic
Hitachi
185
19
ASICs, SRAMs
NEC
ASICs, SRAMs
Company
140
15
AMCC
40
4
ASICs
Synergy
30
3
SRAMs, Logic
Siemens
25
3
ASICs
GEC Plessey
20
2
Logic
National
10
1
ASICs
20
2
—
965
100
—
Others
Total
Source: ICE, "Status 1996"
17130H
Figure 4-21. 1995 Major ECL IC Suppliers
BiCMOS
Because BiCMOS offers advantages over both bipolar digital and CMOS, it will eventually replace
a small portion of the high-end market held by pure ECL and CMOS ICs. Some BiCMOS devices
now produced include: MPUs (e.g., the Pentium), smart-power ICs, bus drivers, analog-to-digital
converters, track/hold amplifiers, disk-drive controllers, memory controllers, SRAMs, PLDs, gate
arrays, and standard cells.
BiCMOS technology has been considered a high-speed replacement for pure CMOS because it
offers a performance edge by implementing both CMOS and bipolar transistors on the same chip.
Through the selective use of CMOS and bipolar circuitry, high-performance paths can be created
with ECL (bipolar) while lower-performance, high-density paths can be created with CMOS gates.
BiCMOS architecture that consists of a small percentage of bipolar transistors is called CMOSbased. For this architecture, non-critical paths (the majority of the chip) consist of CMOS gates,
while bipolar transistors are used mainly for driving long metal lines and as output buffers (critical paths). This is the most common type of BiCMOS technology.
ECL-based BiCMOS architectures consist of predominantly ECL technology with CMOS transistors available for the implementation of large storage elements. The resulting IC offers excellent
performance and density with a high level of programmability.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-15
IC Technology and Packaging Trends
Figure 4-22 provides a list of advantages BiCMOS technology offers over bipolar digital and
CMOS technologies. The main disadvantage of BiCMOS is the cost penalty created by the complicated process of building both bipolar and MOS transistors into a single device.* It is because
of this increased complexity that Intel has stated it intends to move the Pentium MPU from a 20mask BiCMOS process to a 16-mask pure CMOS technology.
DISADVANTAGES
ADVANTAGES
• High drive capability with large loads
• Designers lack experience and awareness
–Ability to optimize critical path
• Design tools and macro library are needed
–Improved skew
• Cost penalty
• High input impedance
• Process complexity
• Improved performance by a factor of 2 or 3
• Difficult to achieve performance advantage
using low-voltage sub-0.5 µ processes
• High CMOS-equivalent density
• Low power dissipation
• Mixed ECL, TTL, and CMOS interfaces
• Mixed analog-digital capability
• Improved noise margin and noise immunity
• Broad product base
• Ease of optimal product design
• Worthy replacement for TTL gate arrays
• Extends CMOS process lifetime
Source: National Semiconductor/ICE, "Status 1996"
17839A
Figure 4-22. BiCMOS Pros and Cons
Since many of the current BiCMOS processes lose their performance advantage when using less
than a 5.0V power supply, the BiCMOS manufacturers are faced with a dilemma as power supply
voltages for high-density, sub-0.5µm devices move to 3.3V. Toshiba’s 0.5µm 500K-gate array
addresses this problem with an innovative cell and circuit design called BipnMOS. Although the
device operates at 3.3V, the bipolar circuitry is not inhibited and the BipnMOS process offers a significant performance advantage over a pure CMOS array.
Because of the decreased performance in many current sub-5V BiCMOS technologies, the future
of BiCMOS in the systems of the late-1990’s depends on the ability to economically produce specialized BiCMOS processes. Toshiba’s BipnMOS process described above is one example of a specialized complementary BiCMOS process. Motorola also has specialized BiCMOS processes that
target ASIC, very high-speed, and low-voltage applications. The supply voltage sub-0.5µm
BiCMOS triangle will especially challenge the BiCMOS producers in the mid- to late-1990’s.
* In 3Q95 NEC introduced its QB-8 0.35µm BiCMOS ASIC technology. This process eliminates the typically used epitaxial layer for the bipolar devices in an attempt to “simplify” the inherently complex BiCMOS technology.
4-16
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
At the 1995 ISSCC, AT&T discussed its BiCMOS technology targeting high-performance analog
applications (e.g., communications systems) in three papers (Figure 4-23). As shown in Figure 424, besides the Pentium-dominated microcomponent area, the analog segment is a strong market
for BiCMOS ICs.
AT&T – BiCMOS optical preamplifier
AT&T – BiCMOS sample-and-hold amplifier
Intel – 0.6µ BiCMOS processor with dynamic execution
AT&T – BiCMOS frequency synthesizer
IBM – SCI link in 0.8µ BiCMOS
Source: ICE, "Status 1996"
20292
Figure 4-23. Sampling of 1995 ISSCC BiCMOS Papers
Standard
Logic
2%
Gate Arrays
4%
Standard
Cell
2%
Other
<1%
SRAMs
5%
Analog
11%
Microcomponents
75%
1995
$10,700M
Microcomponents
6%
Other
3%
Standard Cell
9%
Standard
Logic
10%
2000
$8,425M
Gate
Arrays
12%
Source: ICE, "Status 1996"
Analog
37%
SRAMs
23%
13643N
Figure 4-24. Worldwide BiCMOS Market Forecast
BiCMOS has also become popular for very high-speed SRAMs (Figure 4-25). The access times of
some BiCMOS SRAMs are half those of most CMOS SRAMs of the same density, and ECL SRAMs
can’t match BiCMOS densities. At the leading edge, NEC introduced a 3ns access time BiCMOS
1M SRAM in 1995.
As shown in Figure 4-26, the BiCMOS market was led by microcomponent (i.e., Pentium) products in 1995. The total BiCMOS IC market is forecast to decline at a 5 percent CAGR from 19952000, and only represent three percent of the total IC market in 2000. This decline is due to the
expectation that Intel will move its advanced MPU products from BiCMOS to CMOS in the late
1990’s.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-17
IC Technology and Packaging Trends
Density
Access Time
(ns)
Technology
Cypress
256K
6, 8, 10
BiCMOS
Hitachi
256K
1M
6, 7, 8, 9, 10, 12
10, 12
BiCMOS
BiCMOS
IDT
256K
512K
7, 8, 10
9, 10
BiCMOS
BiCMOS
Micron
256K
1M
10, 12
9, 10
CMOS
CMOS
Mitsubishi
256K
8, 10, 12
BiCMOS
Motorola
256K
512K
1M
4M
6, 7, 8, 10
7, 9
5, 6, 7, 9, 10
10
BiCMOS
BiCMOS
BiCMOS
BiCMOS
NEC
256K
1M
6, 7, 8
3, 8, 9, 10, 12
BiCMOS
BiCMOS
Paradigm
256K
512K
9, 10, 12
9, 10, 12
CMOS
CMOS
Samsung
256K
1M
4M
6, 7, 8, 9, 10
8, 9, 10
10
BiCMOS
BiCMOS
BiCMOS
1M
10, 12
CMOS
256K
1M
10, 12
10, 12
BiCMOS
BiCMOS
Company
Sony
Toshiba
Source: ICE, "Status 1996"
19124B
Figure 4-25. Sampling of High-Density Ultra Fast (≤12ns) SRAM Suppliers
The total value of the BiCMOS market is now highly dependent upon the technology Intel uses to
produce the Pentium and Pentium Pro (P6) MPUs. As of 3Q95, all of Intel’s Pentiums were manufactured using BiCMOS. Assuming Intel shipped about 28 million Pentiums in 1995 at an ASP of
$283, the market for BiCMOS Pentiums alone in 1995 was about $7.9 billion (almost four times
larger than the total 1993 BiCMOS IC market)!
Intel has stated, however, that in the long-run it intends to move both the Pentium and Pentium
Pro devices to pure CMOS technology. The conversion to a pure CMOS process is expected begin
in 1996 as Intel moves the Pentium Pro and Pentium devices to its 0.35µm process. It should be
noted that the timing and completeness of this conversion will have a tremendous impact on the
total BiCMOS market figures in the late 1990’s!
4-18
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
1994
Product
$M
1995 (EST)
Percent of
Product
Category
$M
2000 (FCST)
Percent of
Product
Category
$M
Percent of
Product
Category
SRAMs
375
10
550
9
1,900
13
Gate Arrays
365
7
460
8
975
9
Microcomponents
2,500
11
8,000
24
500*
<1
Analog
1,000
7
1,225
7
3,150
9
Standard Logic
175
2
225
2
850
4
Standard Cell
150
4
190
4
750
6
Other
40
<1
50
<1
300
<1
Total
4,605
5
10,700
8
8,425
3
*Assumes some versions of Pentium continue to be produced in
BiCMOS and that Pentium Pro and P7 Intel families are not BiCMOS.
Source: ICE, "Status 1996"
16820J
Figure 4-26. Worldwide BiCMOS Marketshare
The complexity of the BiCMOS process, especially for low-voltage devices, continues to challenge
the IC producer. Some IC manufacturers have been less sure about the future of BiCMOS as feature sizes shrink to less than 0.5µm. In general, it appears that besides the mid-1990’s Pentium use
of BiCMOS, only the very high performance segment (5-14 percent) of a particular product category will require the use of the typically costly and complex BiCMOS technology. Moreover, as IC
producers attempt to limit the number of processes they can fully (i.e., economically) support,
BiCMOS will be a “luxury” that many suppliers will not be able to justify.
GaAs
As GaAs device manufacturers convert to 100mm wafers* and continue to shrink device features
to as small as 0.4µm, GaAs ICs have become more competitive with silicon. Inexpensive GaAs
MMIC device use in portable communications applications surged in 1995. The total GaAs market is forecast to have a 1995-2000 CAGR of 25 percent (analog 30 percent, digital 17 percent) and
grow to about $1.8 billion in 2000 (Figure 4-27).
Although GaAs IC sales are expected to show excellent growth from 1995 to 2000, the portion of
the market represented by development contracts is expected to decline significantly beginning in
1995. Most of the GaAs development funding today is from the Advanced Research Projects
Agency’s (ARPA) MIMIC program. However, this program ended in 1994. In late 1994 ARPA
announced its intent to fund the MAFET (Microwave Analog Front-End Technology) program.
* Some leading GaAs producers will attempt to move to 150mm wafers by 1997.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-19
IC Technology and Packaging Trends
Thus, it appears that some funding will be available in the mid-1990’s but will be difficult to sustain into the late 1990’s. There are numerous military GaAs IC producers pursuing the merchant
GaAs market because of the overall declining military business and funding.
2,000
Analog IC Sales
1,820
1,800
Digital IC Sales
Development Funding (e.g. MIMIC)
1600,
1,430
Millions of Dollars
1,400
1,200
1,120
1,500
1,000
905
1,170
800
730
400
520
390
330
140
200
900
590
600
180
240
310
400
120 55
135 60 150
70
100
95
120
110
100
90
1991
1992
1993
1994
0
*Includes development funding.
675
520
435
1995
1996
60 170
1997
20
200
20 240 20 300
1998
1999
2000
Year
Source: ICE, "Status 1996"
17134F
Figure 4-27. Worldwide GaAs IC Merchant Market* Forecast
The booming market for communications equipment has led to the long-awaited commercial success of GaAs IC technology. Some of the most attractive market areas are cellular phones (Figure
4-28), digital personal communications systems, local networks, satellites, broad-band tuners,
automotive sensors, and sophisticated space systems. High-speed computing and fiber-optic
applications may offer substantial volumes for high-performance GaAs devices as well.
If the GaAs IC market is ever destined to break the $1.0 billion barrier it will be because of a surge
in the RF/MMIC analog GaAs marketplace. While there is still considerable concern over whether
there will be significant demand for digital GaAs ICs used in computer systems, high-volume use
of analog GaAs ICs in 2GHz and higher performance wireless communications is almost guaranteed. Analog GaAs ICs have even done fairly well at penetrating 800MHz-type applications.
4-20
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
1994
1995
1996
22
53
79
95
106
115
122
DECT
49
795
2,665
7,280
9,566
10,746
11,271
CT2(+)
158
161
221
782
1,426
2,341
3,529
PHS
91
376
1,984
5,360
8,335
10,102
10,564
Total
319
1,385
4,948
13,515
19,433
23,303
25,487
ISM Band
Source: ICE, "Status 1996"
1997
1998
1999
2000
20283
Figure 4-28. Worldwide Digital Cordless Telephone Shipments ($M)
It has been a rough start for GaAs-based computers. Although Convex Computer Corp. began
shipping the first GaAs supercomputers in 1991, the supercomputer market began slumping in
early 1992 and has yet to recover. Vitesse, the major supplier of GaAs ICs to Convex, also felt the
effects of the supercomputer slowdown.
The much anticipated GaAs-based Cray Computer, Inc. computer, initially due to ship in late 1991
to Lawrence Livermore Labs, could not be delivered and Lawrence Livermore Labs subsequently
canceled its order.
The canceled order from Lawrence Livermore Labs started Cray Computer on its rocky road
(Figure 4-29). After Lawrence Livermore Labs withdrew its order, Cray Computer announced it
would try to offer four- and eight-processor systems instead of the 16-processor machine that was
initially planned.
Figure 4-30 shows how the GaAs IC market breaks down by end use. In 1995, the military/aerospace segment held only 22 percent of the market (down from over 50 percent in 1990). ICE estimates that military/aerospace will represent only 10 percent of the market in 2000. Much of the
limited mainframe computer GaAs IC needs will be served by internal IC production from divisions of companies like Fujitsu, NEC, and Hitachi. With the Chapter 11 filing by Cray Computer,
the outlook for mass production of GaAs-based computers has turned decidedly gloomy.
Figure 4-31 shows the top ten GaAs IC sales leaders for 1994 and 1995. Fujitsu had taken over the
top ranking from TriQuint in 1993 as it ramped up its dedicated GaAs fab (Yamanashi, Japan). As
shown, analog GaAs ICs represented about three-fourths of the total merchant GaAs IC market in
1995.
Figure 4-32 shows a number of significant announcements made during 1995 for GaAs ICs. With
large companies such as Fujitsu, Motorola, NEC, etc., greatly increasing GaAs IC technology
emphasis, the GaAs IC market has only recently become a market that can be taken seriously.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-21
IC Technology and Packaging Trends
October, 1983
Cray 3 supercomputer project is launched at Cray Research.
Production is set for 1988.
May, 1989
Cray 3 project is set to be spun off into a separate company.
The new Cray Computer Corp. is led by Cray Research
founder Seymour Cray. Already a year late, Cray 3 hits more
snags, with production now planned for winter, 1990.
April, 1990
Schedule slips again; Cray 3 now due in winter, 1991.
June, 1991
New stock issue raises $61 million. Shares initially traded at
$12.50.
December, 1991
Tired of delays, Lawrence Livermore national lab, Cray
Computer's only customer, cancels its order.
April/May, 1992
CEO Neil Davenport resigns. Bereft of customers, reclusive
Seymour Cray announces plans for four- and eight-processor
systems (instead of sixteen) and says that Cray Computer will
seek a partner. Stock trades around $4 a share.
May, 1993
An unidentified group of overseas investors and founder
Seymour Cray put an estimated $33 million into the company.
The funding allowed the company to operate through June of
1994.
June, 1994
Received a $17.5 million line of credit. The funding is
expected to allow Cray Computer to complete its GaAs-based
Cray-4 mainframe prototypes.
March, 1995
After spending $300 million and not selling a single machine,
Cray Computer filed for Chapter 11 bankruptcy protection due
to cash flow problems.
September, 1995
Cray Computer sold its fabrication equipment and fab facility
(Colorado Springs, CO) to M/A-COM as part of a larger effort
to liquidate its assets.
Source: Business Week/ICE, "Status 1996"
17833E
Figure 4-29. Cray Computer’s Saga
Military/
Aerospace
10%
Military/
Aerospace
22%
Computer
14%
Other 9%
1995
$535M
Telecom
55%
Telecom
72%
Other 6%
Computer
12%
2000
$1,800M
*Not including development funding.
Source: ICE, "Status 1996"
13329L
Figure 4-30. Total GaAs IC Market* by End Use
4-22
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
1995 Sales ($M, EST)
1994 Sales ($M)
1995
Rank
Company
Analog
Digital
Total
Analog
Digital
Total
1
Fujitsu
45
38
83
56
36
92
2
Anadigics
35
—
35
53
—
53
3
TriQuint
10
20
30
19
28
47
4
Thomson-CSF
36
—
36
44
—
44
5
Vitesse
—
28
28
2
36
38
6
TI
25
4
29
30
5
35
7
Philips
25
—
25
32
—
32
8
Oki
22
4
26
27
4
31
9
27
Rockwell
19
5
24
22
5
10
NEC
18
—
18
25
—
25
—
Others**
75
21
96
90
21
111
310
120
430
400
135
535
Total
* Not including development funding.
** Others include Raytheon, Mitsubishi, Matsushita, Siemens, etc.
Source: ICE, "Status 1996"
18111F
Figure 4-31. Top Ten 1994 and 1995 GaAs IC Sales* Leaders
• Burr Brown cancelled its plans to enter the merchant GaAs IC business in 1995.
• In 1Q95 Westinghouse (Baltimore, MD) announced that it had doubled the space of
its GaAs fab to 10,000 sq. ft. The facility will support ARPA’s MAFET program as
well as offer commercial foundry services.
• NEC announced that it would double its GaAs capacity at its Kansai wafer fab in
FY95 in part by moving from 3-inch to 100mm wafers.
• Seymour Cray's GaAs supercomputer company Cray Computer filed Chapter 11 in
1Q95 and sold its fab to M/A-Com in 3Q95.
• Vitesse, traditionally a digital GaAs IC producer, announced its first analog devices
(amplifiers) in 2Q95. The devices are a result of a cooperative agreement with IBM.
• Oki announced a wide-range of 3V GaAs ICs targeting cellular, voice and data
communications applications.
• Fujitsu, Oki, and Mitsubishi all announced big capacity increases for analog GaAs
IC devices for FY95.
• It was reported in 2Q95 that Philips was negotiating to buy a stake in TriQuint.
• Anadigics planned to spend $12 million of its first public offering in 1995 to convert
its fab facility from 3-inch to 100mm wafers.
• Vitesse announced its GLX™ family of 0.5µm GaAs gate arrays in 4Q95. The
devices offer up to 250K total gates (60-70 percent usable) with volume pricing at
about 0.10¢ per gate. Production is expected to begin in 2Q96.
• The second space shuttle experiment to grow GaAs wafers in space took place in
September of 1995.
• Motorola is experimenting with a single-transistor SRAM cell using multiplequantum-well GaAs structures.
Source: ICE, "Status 1996"
19225C
Figure 4-32. Sampling of 1995 GaAs IC Announcements
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-23
IC Technology and Packaging Trends
SiGe DEVICES
As semiconductor manufacturers struggle to put more transistors on each chip and increase circuit speed, the physical and electrical limitations of silicon wafers become a major concern. As a
result, alternative materials are being considered.
For years, it was thought that gallium arsenide would become the new wafer material of choice.
It now appears as though GaAs will never be considered more than a niche technology. Even
though the GaAs IC market is forecast to have a 1995-2000 CAGR of 25 percent, it will still represent only a very small percentage of the total IC market.
In 1991, IBM announced it was dropping its gallium-arsenide efforts in favor of silicon-germanium (SiGe) technology. Today, IBM is unquestionably the leader in SiGe research and development.
Research at IBM and other laboratories around the world is seeing promising performance advantages with SiGe. In 1995 IBM worked with Hughes Research Laboratories to co-develop SiGe ICs.
The concept behind SiGe is to add (through the doping process) the benefit of germanium’s high
carrier mobility* to a silicon wafer. The electron mobility in silicon germanium is nearly twice that
of silicon only. High mobility benefits both bipolar and field effect transistor (FET) devices.
Shown in Figure 4-33 is a cross section of IBM’s high-performance FET designed using its new
0.25µm BiCMOS SiGe process.
Gate
Source
Drain
SiO2
N+ Si
SiGe (30%)
Silicon
Silicon-Germanium (SiGe)
Silicon Channel
Two Degree
Electron Gas
Silicon-Germanium Graded Buffer
Source: IBM Corp./ICE, "Status 1996"
18736
Figure 4-33. IBM’s High-Performance SiGe FET
* Electron mobility of germanium is 3900cm2/Vs versus 1500 for silicon. Hole mobility for germanium is 1900 versus 450
for silicon.
4-24
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
In 4Q93 it was announced that Analog Devices and IBM were joining together to develop SiGe ICs
targeting the wireless communications market. These SiGe devices are set to challenge GaAs at
frequencies at or above 1GHz! However, 1995 SiGe IC sales of Analog Devices were minimal.
In July of 1995, Telefunken Semiconductors announced it would begin sampling a SiGe analog RF IC
in late 1995 with production due sometime in early 1996. The device contains 30 transistors, is produced using 1.0µm feature sizes, and has a die size of two square millimeters. The device will compete with GaAs ICs since it is targeting 1.8GHz mobile telecom applications as a power amplifier.
SiGe will not only be competing with GaAs but also with BiCMOS and even bipolar technologies
in the wireless communications market. The technology that gains the greatest marketshare will
be the one that can “economically” meet the performance requirements of the growing number of
high-performance applications*. The market is still taking a wait-and-see approach to SiGe since
parts have only now begun sampling.
IC MACROTRENDS
Integration Density Trends
Integration levels have grown continually since the invention of the IC. The MOS integration levels have increased an average of 35 to 50 percent per year for the past 24 years (Figure 4-34). As
shown, MOS memory ULSI ICs are expected to contain over 256 million transistors by 1998 and
ICs with 1 billion transistors per chip forecasted by the year 2000.
Considering that NEC announced its 64M DRAM devices in March 1993, and Samsung
announced it had produced a fully functional 256M DRAM in 3Q94, it currently appears the
DRAM IC density trend line will be intact through at least the late-1990’s. Intel’s Pentium MPU
(3.1 million transistors) fell slightly short of the MPU/Logic trend line in 1993, and the Pentium
Pro CPU only also fell short in 1995 at 5.5 million transistors. It should be noted that Intel split
the Pentium Pro MPU and its SRAM cache memory (16 million transistors) into separate dice that
are packaged in a multichip module. This may be the first indication of a trend to use multiple
dice to produce advanced processor functions.
Die Size Trends
As the number of transistors per die has escalated, average die sizes have also been increasing.
Figure 4-35 shows that the die area of leading-edge ICs has increased about 13 percent per year.
The trend toward larger die sizes, at least for memory, is forecast to continue at this rate into at
least the late-1990’s.
* Telefunken states that the SiGe wafer processing cost is about 30 percent greater than for silicon wafers.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-25
IC Technology and Packaging Trends
1G
1G
256M
Pentium Pro
MPU and Cache
Memory Chip
100M
64M
P8?
Number of Transistors per Chip
16M
P7?
10M
Pentium
Pentium Pro
MPU Only
4M
IBM
Gate
Array
80486
1M
1M
256K
100K
80386
LSI Logic
Gate Array
68020
80286
64K
68000
8086
16K
10K
4K
8085
8080
1K
= Microprocessor/Logic
4004
= Memory (DRAM)
1K
70 72
74
76
78
80
82
84
86
88
90
92
94
96
98
00
Year
Memory increase = 1.5/year
MPU increase = 1.35/year
Source: ICE, "Status 1996"
11745P
Figure 4-34. IC Density Trends
To illustrate how risky it is to continue to extrapolate current trends far into the future, a look at
the die sizes of leading-edge DRAMs introduced at the ISSCC (International Solid-State Circuits
Conference) proves interesting.
The die sizes of the 256M DRAM described at the 1994 and 1995 ISSCCs ranged from 472K sq. mils
to 638K sq. mils (Figure 4-36). As shown, the NEC 1G DRAM if square (most DRAMs are rectangular) would be about 1.2 inches on a side!
Extrapolating out to 2003 ISSCC announcements, a 6.58M sq. mil 256G DRAM, if square, would
be 2.6 inches on a side. Given the typical 2:1 aspect ratio of the DRAM die, the 2003 DRAM die
size would be about 3.6 inches by 1.8 inches.
4-26
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
2,000
P8?
P7?
Pentium Pro
MPU and Cache
1,000
1G
800
IBM
Gate Array
600
Pentium
Pro
MPU
R4000
256M Only
64M
80486
P54C
400
Chip Area (Thousands of sq mils)
Pentium
200
80386
68020
4M
80286
68000
100
16M
1M
80
256K
60
8086
Z80
40
16K
64K
8080
4K
20
= Microprocessor
= Memory
10
70 72
74
76
78
80
82
84 86
Year
88
90
92
94
96
98
00
Memory increase = 1.13/year
MPU increase = 1.13/year
Source: Intel/ICE, "Status 1996"
11746M
Figure 4-35. IC Die Size Trends
Company
Density
Chip Size
Feature
Cell
Size (µm) Size (µm2) (K sq. mils)
Access
Time (ns)
Organization
Conference
Hyundai
256M
0.3
—
561
36
32M x 8
ISSCC '95
Matsushita
256M
0.25
0.72
638
—
16M x 16
ISSCC '94
Mitsubishi*
256M
0.25
0.72
472
34
32M x 8
ISSCC '94
Oki**
256M
0.25
0.72
530
—
32M x 8
ISSCC '94
Hitachi
1G
0.16
0.29
1,108
33
64M x 16
ISSCC'95
NEC
1G
0.25
0.54
1,451
—
—
ISSCC '95
* Produced using KrF excimer laser lithography.
** Packaged in a 64-pin 600 mil TSOP, produced using e-beam lithography.
Source: ICE, "Status 1996"
20289
Figure 4-36. ISSCC Advanced DRAMs
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-27
IC Technology and Packaging Trends
As shown, this die size begins to approach what we would now call wafer-scale integration. What
wafer size would be needed for such a huge die to be practical––10”, 12”, or larger? What level of
redundancy would be needed to keep yields above zero? What about defect density levels?
By 2003 the IC industry may be forced into some type of three-dimensional (stacking one or more
transistors on top of each other) technology in an attempt to keep die size manageable. However,
three-dimensional technology will come with its own set of constraints and problems that one
cannot even fully imagine at this time.
Other economic factors also come
into play as a result of increasing die
sizes. For example, about 150 “1983described” 256K DRAMs were able
to fit on a 100mm (4”) wafer (the
most popular wafer size at that
time). However, only about 68
“1994-described” 256M DRAMs
could fit on an 200mm (8”) wafer
today. Using the extrapolated 2003
256G DRAM chip size, only about
12 would fit on a 300mm (12”) wafer
(Figure 4-37)!
Source: ICE, "Status 1996"
19501
Figure 4-37. Twelve 3.6”x1.8” “2003 256G DRAMs”
Fit on a 12” Wafer
While it is difficult enough to imagine a 3.6”x1.8” die, it is even more
difficult to imagine the economic
practicalities of producing such a
die. As was mentioned earlier,
Intel’s division of the Pentium Pro
into an MPU die and cache memory die
may signify the ultimate response to
concerns over huge die sizes.
Wafer Size Trends
The usual IC industry response to ever larger dice has been to increase wafer size. Just as 200mm
wafers are now becoming the standard for high-volume advanced IC production, there has been
an increased interest in preparing for what currently appears to be the next standard wafer size—
300mm (i.e., 12-in. wafers).
4-28
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
There exist a few fundamentally sound reasons why the IC industry has settled on the 300mm
diameter and not another size for wafer processing. A move to 250mm wafers does not yield a
significant enough increase in area to justify the much higher equipment investment (Figure 4-38).
Also, relatively few cost benefits result from increases to wafer sizes of 350mm (14 inch) or 400mm
(16 inch), because the 350mm/400mm processing equipment will require significantly higher
development costs than for 300mm.
4" → 5"
56
Wafer Diameter Transition
4" → 6"
125
5" → 8"
156
6" → 8"
78
8" → 10"
56
10" → 12"
44
8" → 12"
125
0
50
100
150
200
Percent Increase
Source: EMR/ICE, "Status 1996"
18603
Figure 4-38. Wafer Area Increases (Percent)
Currently, SEMI plans to have the first draft of its 300mm wafer specification standards available
in July of 1996*. Moreover, U.S. industry leaders are attempting to have Japanese companies join
Sematech and the SIA in a joint 300mm wafer task force to help develop the infrastructure (e.g.,
fab equipment) to handle these large wafers.
Once standards are in place and equipment is readied, there are additional issues that must be
remedied if 300mm wafer processing is to become a reality. A few of the many wafer processing
questions or concerns that must be addressed include:
• What chemical quantities for processing and cleaning will be needed for 300mm wafers?
• Ensuring uniformity of deposition and etch.
• Ensuring the integrity of wafer flatness across a huge diameter.
* Cassette-sized lots of 13 and 25 wafers and a wafer thickness standard of 775 microns have already been proposed.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-29
IC Technology and Packaging Trends
• Will there be only single-wafer implantation processes?
• Reduction or elimination of test wafer usage in the coming years.
• 300mm wafers will require a far lower furnace operating temperature (900°C) versus
200mm wafers (1200°C).
• Ergonomic issues such as cassette-sized lots of 25, 13, or fewer wafers.
Wafer cost is another barrier that stands in the way of moving to 300mm wafer production. In
mid-1995, the approximate price of a 300mm wafer was $1000. In the 1999-2000 timeframe, when
300mm wafer usage is expected to be in higher volume, wafer costs are estimated to be in the
range of $450.
Standards, equipment development, and costs—Figure 4-39 shows Sematech’s estimates of these
and other factors relative to 200mm wafers that are significant considerations in the transition to
300mm wafers.
200mm 300mm 350mm 400mm
Total Throughput*
1.00
0.60
0.50
0.40
Tool Cost
1.00
1.50
1.75
2.00
Tool Size
1.00
1.25
1.35
1.50
Wafer Cost
$100
$450
$700
$1,100
*Area-based lithography, ion implant, metrology and test.
Source: Sematech/ICE, "Status 1996"
19770
Figure 4-39. Considerations in Transitioning to Larger Wafers (Relative to 200mm)
Two of the most aggressive companies wanting to implement 300mm wafers early are Motorola
and Samsung. Both companies would like to have fully functional high-volume 300mm fabs in
place by late 1997 or early 1998.
As shown in Figure 4-40, a 1998 300mm fab startup would be at least 12 years before the forecasted peak market for 300mm wafer usage. Moreover, the 1.7 million 300mm wafers expected to be
used in the year 2000 (Figure 4-41) could be processed by just seven fabs having a capacity of 5000
wafers per week each.
Although the IC industry is only beginning down its path toward 12-inch wafers, a consortium to
develop 16-inch (400mm) was put together in 4Q95. Early consortium members included
Mitsubishi Materials, Sumitomo Sitix, SEH, MEMC, and Wacker Siltronic. The consortium hoped
to get Japan’s MITI to fund up to half of the proposed $150 million budget.
4-30
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
15
14
Wafer Size (inches)
13
12
First Wafers in R & D
11
10
9
8
7
Year of Market Peak
6
5
4
3
1984
1991
1994
1997
1986
2003
2010
2015
1998
Source: VLSI Research Inc./ICE, "Status 1996"
20290
Figure 4-40. Wafer-Size History and Forecast
2,000
Wafers (Thousands)
1,500
1,000
1,700
500
700
0
100
1997
200
1998
1999
2000
Source: VLSI Research Inc./ICE, "Status 1996"
20291
Figure 4-41. Estimated 300mm Wafer Production
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-31
IC Technology and Packaging Trends
Feature Size Trends
Figure 4-42 shows how the feature sizes for a “tight production resolution” device have decreased
from about 3µm in 1980 to about 0.35µm in 1994. This represents about a 15 percent decrease
every year. This trend is expected to continue and feature sizes are forecast to be about 0.15µm by
2000 for tight production resolution. It is interesting to note that in 2000, 0.7µm feature sizes will
be considered mundane.
10
Loos
e Pro
Tigh
t Pro
duct
HMOS II
(2.0µ)
1
ion R
on R
esolu
tion 256K DRAM
(1.6µ)
WE 32100
32-Bit MPU
(1.5µ)
HMOS IV
(1.0µ)
1992 Forecasted Commercial
Limit For Optical Lithography (0.15µ)
(2.0µ)
1M DRAM
(1.2µ)
(1.0µ)
4M DRAM
(0.8µ)
16M DRAM
(0.5µ)
4M DRAM
(0.8µ)
Toshiba
(0.25µ)
IBM
(0.25µ)
Gate Array
(X-Ray)
(0.7µ)
64M DRAM
(0.35µ)
16M DRAM
(0.5µ)
Bell Labs
(0.14µ)
0.1
tion
esolu
1990 Forecasted Commercial
Limit For Optical Lithography (0.35µ)
Microns
ducti
Dev
64M DRAM
(0.35µ)
elop
256M
DRAM
(0.2µ)
men
t
256M
DRAM
(0.2µ)
1G DRAM
(0.15µ)
Toshiba
(0.1µ)
MIT (0.06µ)
X-Ray
1G
DRAM
(0.15µ)
4G
DRAM
(0.08µ)
= Laboratory Reasearch
Toshiba
(0.04µ)
0.01
80
81
82
Source: ICE, "Status 1996"
83
84
85
86
87
88
Year
89
90
91
92
93
94
95
96
97
98
00
10981M
Figure 4-42. IC Feature Size Trends
Figure 4-43 shows some of the 1995 announcements regarding state-of-the-art feature sizes. With
the year 2000 still being five years away, it appears 0.1µm lithography will be a production reality by then.
Figure 4-42 also shows the forecasted performance limits of the most popular types of lithography
equipment. Due to its “relative” low costs and technical advancements (e.g., phase-shift photomasks), optical lithography is now forecast to have a much longer life than originally thought
(maybe to 0.15µm). It now appears that optical techniques will be the mainstream of IC lithography for the rest of this century (Figure 4-44).
4-32
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
AT&T
Unveiled a 0.25µm (0.18Leff) CMOS process targeted at wireless
communications. A 60GHz cut-off frequency (ft) is achieved at
2.5V. The process can produce devices that operate at less than
1V.
AT&T
Bell Labs
Developed a 0.075µm Leff NMOS transistor using a laser plasma
source for x-ray lithography. Tungsten deposited on a
polysilicon membrane was used to create the masks.
Sandia
Developed an "extreme ultraviolet" lithography tool to produce
0.1µm feature sizes. Instead of optical lenses, Sandia used
mirrors with special coatings having a surface precision of one
atom.
Toshiba
Fabricated an MOS transistor with a gate length of 0.09µm and a
gate oxide of only 15Å.
Hitachi
Developed a CMOS circuit with a 0.09µm feature size using
e-beam lithography.
NEC
Developed a CMOS circuit with a 0.07µm feature size using
e-beam lithography.
Matsushita
Developed a CMOS circuit with a 0.05µm gate length. The device
had a propogation delay of 13.1 ps.
Source: ICE, "Status 1996"
20293A
Figure 4-43. 1995 Leading-Edge Feature Size Announcements
16Mb
ARI - annular-ring illumination
OAI - off-axis illumination
PSM - phase-shift masking
s - shrink DRAM version
I-line
I-line + ARI
DRAM
16Mb-s
I-line + OAI
Deep-UV
Deep-UV + OAI or PSM
64Mb
I-line + OAI or PSM
Deep-UV + ARI or OAI
64Mb-s
256Mb
256Mb-s
0.15
I-line + PSM
Deep-UV + OAI or PSM
Deep-UV + PSM
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Minimum Lithography Resolution (µm)
Source: Canon/ICE, "Status 1996"
18625
Figure 4-44. Advanced Optical Lithography Scenarios
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-33
IC Technology and Packaging Trends
Summary
Gorden Moore, chairman of Intel, believes that the 256M DRAM may actually cost more on a
price-per-bit basis than a 16M DRAM. The ultimate question now, Moore believes, is not the physical limitations of the future ICs but whether the industry can afford to make them.
In general, there are basically two schools of thought concerning turn-of-the-century advanced
ICs. The first is that the post-2000 devices will happen as planned and will be economical as well.
The reasoning behind this view lies in historical precedent. In other words, since the 1990’s-type
ICs appeared “impossible” in the early 1980’s, and yet were created with the assistance of significant technological advances, the “impossible” appearing post-2000 devices will follow this same
path to fruition.
The second school of thought is that it is not realistic to keep extrapolating historical trends to
infinity. At some point, physical or economic limits present themselves.
ICE’s view is more in line with the second school of thought ideology. While ICE does not expect
the technological advances in the IC industry to stop, the pace of the advances (e.g., density, feature size, etc.) should slow. Associated with, and sometimes causing this slowdown, will be the
questionable economic feasibility of many of the new technologies.
IC PACKAGING TRENDS
Market Overview
IC packaging is receiving a great deal more attention now than in the past. This is partly due to
the increasing percentage of the total system performance picture that IC packaging represents. As
system producers soon discover, an IC package can be as much or more a performance limiting
factor as the IC die itself.
Another reason for the heightening interest in packaging is the rising cost of housing the IC die.
ICE forecasts that IC packaging costs will continue to rise significantly throughout the 1990’s since
more and more of the newer IC devices now require high-lead-count (i.e., expensive) packages.
Figures 4-45 and 4-46 show the sizes of the markets for the major package types. The SOP-type
package had the greatest share of the 1995 IC market as surface mount (SM) technology continued
to make inroads. In fact, 1994 was the first year ever that surface mount ICs outshipped throughhole IC units. It is expected that by 2000, SM devices will have about nine times the marketshare
of through-hole devices. BGA, SOP, Plastic PGA, and “other” packages are anticipated to show
the strongest growth through 2000. The dominant package types—plastic DIPs, SOPs, and
PQFPs—are forecast to make up about 85 percent of the IC unit market in 2000.
4-34
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
1995 (EST)
1994
2000 (FCST)
1994-2000
CAGR
(%)
Percent
Of Total
1995/1994
Percent
Change
15,575
32
–1
7,700
10
–13
545
1
9
200
<1
–18
<1
40
<1
–11
20
<1
–13
<1
105
<1
40
180
<1
11
60
<1
85
<1
42
200
<1
19
15
<1
25
<1
67
600
<1
89
SOP*
17,000
41
21,725
44
28
43,000
59
15
PLCC
2,200
5
2,300
5
5
2,500
3
2
PQFP
4,300
10
6,100
12
42
12,000
16
14
Other**
1,600
4
2,500
5
56
7,000
10
23
41,600
100
49,000
100
18
73,400
100
8
$90,305
–
$128,493
–
–
$331,866
–
–
–
WW IC ASP
$2.17
–
$2.62
–
*Includes UTSOPs, QSOPs, TSOPs, and SOJs.
**Includes TAB-on-board, COB, flatpacks, metal cans, LLCC, LDCC, etc.
$4.52
–
–
Package
Type
Units
(M)
Percent
Of Total
15,805
38
500
1
Sidebraze DIP
45
Ceramic PGA
75
Plastic PGA
BGA
Plastic DIP
CERDIP
Total
WW IC Market
Units
(M)
Units
(M)
Percent
Of Total
Source: ICE, "Status 1996"
14737M
Figure 4-45. Worldwide Merchant IC Package Marketshare
Other
1%
Plastic DIP
10%
Through Hole
11%
Through
Hole
34%
Plastic
DIP
32%
1995
49.0B
SOP
44%
Surface
Mount
66%
2000
73.4B
Other
30%
SOP
59%
Surface Mount
89%
Other
2%
Other
22%
Source: ICE, "Status 1996"
16827J
Figure 4-46. IC Package Marketshare (Units)
As shown in Figure 4-47 most of the packaging operations for IC devices are still located in the
Asia-Pacific region. The attractiveness of this region of the world for IC assembly is due to low
labor costs as well as the existing experienced and sophisticated packaging infrastructure. ICE
forecasts that this situation will be little changed in the year 2000.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-35
IC Technology and Packaging Trends
ROW 2%
Europe
5%
North
America 8%
49.0B
Units
Japan 28%
Asia Pacific
57%
Source: Emissarius, Ltd./ICE, "Status 1996"
20312A
Figure 4-47. 1995 Final IC Packaging by Location
As surface mount (SM) packages become more available and SM assembly capabilities continue
to improve, SM technology is becoming more accepted. The primary advantage of SM packaging
is the improved performance and savings in space that it affords. Not only are the packages smaller but they can also be placed on both sides of the printed circuit board (PCB). This savings in
space can reduce board cost by as much as 60 percent, while offering improved performance. For
these reasons the SM market is expected to continue to grow rapidly over the next five years.
Figure 4-48 shows the 1995 and 2000 IC markets segmented by product type and surface mount
unit volume. As shown, in 1995 the MOS memory segment had a very high penetration rate for
surface mount (93%). However, the largest unit volume segments of analog and MOS logic were
60 percent surface mount in 1995.
Market ($B)
Product
1995
(EST)
2000
(FCST)
ASP ($)
Unit Volume (B)
1995
(EST)
2000
(FCST)
1995
(EST)
2000
(FCST)
Percent
Surface
Surface Mount Mount Units (B)
1995
2000
(EST) (FCST)
1995
(EST)
2000
(FCST)
2.95
1.48
0.62
0.50
4.73
2.95
55
75
2.60
2.21
Analog
17.39
36.13
0.81
0.99
21.41
36.47
60
85
12.85
31.04
Microcomponent
33.21
82.78
7.34
10.71
4.52
7.73
80
96
3.62
7.42
MOS Logic
21.72
48.60
1.79
2.68
12.10
18.15
60
90
7.26
16.34
Memory
53.22
162.88
8.53
20.11
6.24
8.10
93
99
5.80
8.02
128.49
331.87
2.62
4.52
49.00
73.40
66
89
32.13
65.02
Digital Bipolar
Total
CAGR 1995-2000
21%
12%
8%
—
Source: ICE, "Status 1996"
15%
20313A
Figure 4-48. 2000 Surface Mount IC Unit Forecast
4-36
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
As shown in Figure 4-49, the analog segment will contribute over half of the annual increase in
total IC and surface mount unit volume shipments through the year 2000. Since most analog components are low-density devices, the surface mount trend in this segment is primarily directed at
SOP package types. Overall, analog and memory products will represent the majority of SOP
usage in the year 2000.
1995/2000
Unit Volume
Change (B)
Contribution
To Total
Increase
(Percent)
1995/2000
Surface Mount
Unit Volume
Change (B)
Contribution
To Total
Increase
(Percent)
15.06
62
18.19
55
MOS Logic
6.05
25
9.08
28
Microcomponent
3.21
13
3.80
12
Memory
1.86
8
2.22
7
Bipolar Digital
–1.78
–8
–0.39
–2
1995/2000
Net Annual
Increase
24.40
—
32.89
—
Product
Analog
Source: ICE, "Status 1996"
20314A
Figure 4-49. Analog and MOS Logic Products Drive Surface Mount Volume
As I/O counts have increased, the industry has gravitated toward fine-pitch lead technology
(FPT). The Institute for Interconnection and Packaging Electronic Circuits (IPC) defines FPT as
those devices that have lead pitches ranging from 0.1mm to 0.5mm (4mils to 20mils). Below
0.1mm, the term “ultrafine” pitch has been unofficially put forth.
With fine-pitch technology (FPT), the leads’ susceptibility to damage is high. Fine-pitch leads cannot be touched before being placed on a board or substrate. In most cases the packaged device
must be placed and held in position until soldering of the leads is completed.
Lead coplanarity and integrity are critical. This is why carriers are frequently being used to hold
the outer leads of the packages until immediately before attachment. The carriers also provide easily accessible test contacts so that chips can be fully tested before board assembly. The delicate
nature of fine- or ultrafine-pitched packages has many designers considering the ball grid array
(BGA) option for their packages. BGAs are discussed later in this section.
Memory devices packaged in thin small-outline packages (TSOPs) are gaining in popularity. They
are finding applications in palmtop and notebook computers and memory cards. Manufacturers
of non-portable computers are also looking at the TSOP; it will most likely become the primary
memory package for the 16M DRAM. Toshiba expects that almost 50 percent of its 16M DRAMs
will be packaged in TSOPs in 1996.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
4-37
IC Technology and Packaging Trends
Fujitsu developed what it calls UTSOP (Ultra-Thin SOP) package types for memory. The UTSOPI version has a body thickness of 0.65mm and a PCB mounted height of 0.7mm. UTSOP-II versions
have a 0.45mm body thickness and a 0.5mm PCB mounted height.
IBM, in keeping with a trend to push much of its proprietary technology into the mainstream, is
divulging more information about its flip-chip packaging methodology. IBM’s flip chips—officially, C4 chips for controlled-collapse chip connection—have small solder bumps arranged in an
array pattern over the surface of an IC. The packaging permits higher I/O densities, less weight,
a lower profile, and shorter lead lengths. IBM announced in 1995 that flip-chip reliability can be
enhanced substantially by placing encapsulants around the IC to reduce stress (Figure 4-50). IBM
engineers also found encapsulants improved the reliability of TSOPs.
Encapsulant
Solder Bumps
IC
Substrate
Source: IBM/ICE, "Status 1996"
18633
Figure 4-50. IBM Improves Flip-Chip Reliability with Encapsulants
The total IC packaging market by material type is shown in Figure 4-51. Because of the move to
plastic-packaged flash memory and away from ceramic-packaged EPROMs, as well as the military implementing plastic IC packages in many of the less-harsh system environments*, ceramic
IC packages are expected to decrease one point in marketshare between 1995 and 2000. Plastic
package marketshare will decrease to 90 percent of the market and metal/other packages (which
would include bare dice for MCMs) will grow five points.
Plastic
≈94%
Plastic
≈90%
1995
49.0B
2000
73.4B
Other*
≈4%
Ceramic
≈1%
Ceramic
≈2%
Other*
≈9%
*Includes TAB-on-board, COB, flatpacks, metal cans, bare dice for MCMs, etc.
Source: ICE, "Status 1996"
12061Q
Figure 4-51. Worldwide Merchant IC Package Marketshare by Material (Units)
* In 1994 AMI began offering plastic-packaged ASIC devices that exceeded MIL-STD-883 reliability standards. AMI plastic-packaged parts cost 25 percent less than similar ceramic-packaged devices.
4-38
INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Overall, the IC package market as
expressed in units is projected to
display a CAGR of only eight percent from 1995 to 2000 (Figure 4-52).
The annual IC unit growth rates
have steadily trended downward
since the mid-1980’s.
Time
Period
CAGR
(%)
1981 – 1986
18
1987 – 1994
12
1995 – 2000
8
Source: ICE, "Status 1996"
17797F
Figure 4-52. IC Unit Volume CAGRs
The IC product mix change (i.e.,
away from SSI/MSI digital bipolar
ICs) has helped cause this unit shipment rate decline. Moreover, the density/complexity of
advanced 32-bit/64-bit MPUs and ASICs has risen dramatically, and many applications can now
use one IC where previously hundreds of IC units were required. This trend is expected to continue into the late 1990’s and will have a significant impact on the IC packaging material suppliers.
As was previously mentioned, the increasing density and complexity of ICs is helping to slow unit
volume growth rates. However, these high-density devices are also pushing the state-of-the-art in
pin count. If current trends continue, IC packages with pin counts of greater than 1,000 will be in
production well before the year 2000 (Figure 4-53). IBM’s 1.3M usable-gate array, introduced in
1993, is available in pin counts of more than 900!
1,000
ASICs
MPUs
Memory
Number of Pins
Rate of Increase:
100
3 times in
7 years
1.5 times
in 7 years
2.5 times
in 7 years
10
1960
1970
1980
Year
Source: MITI/EMR/ICE, "Status 1996"
1993
2000
17801B
Figure 4-53. Pin Count Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
Multichip Modules (MCMs)
Multichip Module (MCM) technology is becoming more and more important to the continued
growth of the electronics industry*. MCMs will be a strong factor in all electronics applications
based on ICE’s analysis (Figure 4-54). An MCM has multiple ICs packaged on an insulating substrate that interconnects the ICs and provides external connections. This definition of an MCM is
similar to the classical definition of a hybrid microcircuit. MCMs could be considered as a portion
of hybrid microelectronics. The term MCM will rapidly replace the term hybrid to define any
assembly of multiple ICs.
Application
Company
Mainframe
Product
Description
IBM
ES/9000
MLC MCM-C
Unisys
A16/A19
Multicavity ceramic PGA
Siemens
7500
MCM-L with flip-TAB
IBM
AS/400
MLC with flip-chip
NCR
3500
Laminate with TAB
Control Data
4680
nCHIP's thin-film process
Tadpole Tech.
SPARCbook
nCHIP's thin-film process
Silicon Graph.
Iris
4-chip ceramic PGA
IBM
RS/6000
MLC with flip chip
Austek Micro.
486 upgrade
MMS's thin-film on aluminum
IBM
9095
Four-chip ceramic MCM
AT&T
Many
PolyHIC thin-film process
PMC
SONET
Thin-film on silicon
NEC
SONET
2-sided glass ceramic
Communication
Matsushita
Pager
Laminated MCM
Automotive
Mercedes
Mercedes
4-chip 2-sided LTCC from MPA
Military
Rockwell
DSP
Thin-film on silicon
Hughes
Processor
Thin-film on alumina (HDMI)
Honeywell
Processor
Cofired ceramic MCM
Consumer
Matsushita
VCR
MCM-D for CCD driver ICs
Medical
Medtronics
Defibrillator
MLC
Mid-range Computer
Workstation
Personal Computer
Telecom
Source: TechSearch International, Inc./IBM/ICE, "Staus 1996"
19484
Figure 4-54. Examples of MCM Applications
MCMs are vital in all electronics markets because they can provide improved system performance
and smaller size and weight and reduce overall costs. ICE considers MCMs to represent the next
major change in IC packaging. The conversion to MCMs will proceed slowly and steadily like the
conversion from through-hole mount to surface mount initially proceeded, not overnight as some
forecasters have predicted. The MCM market will build on the currently established hybrid
microcircuits market.
*Additional information regarding MCMs can be found in ICE’s “MCMs, Technology and Applications” publication.
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INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
MCMs are currently viewed as complex hybrid microcircuits with virtually all of the components
mounted to the substrate being semiconductors, not passive components. Figure 4-55a shows an example of a relatively low-density hybrid circuit and Figure 4-55b shows three MCMs as currently defined.
(a.)
(b.)
Photos courtesy of Natel Engineering Co., Inc and CTS
Source: ICE, “Status 1996”
19477
Figure 4-55. Examples of Hybrid Circuit (a.) and MCMs (b.)
A major segment of MCMs are liquid crystal displays (LCDs). These displays are built on glass
substrates and contain millions of interconnects and transistors deposited on the glass. The driver ICs are now being mounted to these substrates using a specialized assembly technique
referred to as chip-on-glass (COG). LCDs are some of the most sophisticated MCMs currently in
production. Additionally, LCD manufacturing technology shows great promise for reducing the
cost of manufacturing other MCM substrates.
MCM Substrates
MCM substrates are grouped into three major categories — MCM-C, MCM-D, and MCM-L. These
designations refer to the substrate and the method of substrate manufacturing. The chart in Figure
4-56 shows the characteristics of each of these three major substrate types. As shown in Figure 4-57,
there can be a dramatic difference in the cost of the various MCM substrate technologies.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
Characteristics
MCM-C
MCM-D
MCM-L
Pitch per layer
10 mils (254 µm)
1 mil (25 µm)
8 mils (200 µm)
No. of Layers
>60
5
5-25
Alumina
Silicon
FR-4
Aluminum Nitride
Alumina
Polyimide
Beryllium Oxide
Glass
Power Dissipation
High
Medium
Low
Cost
Medium
High
Low
Speed Performance
Medium
High
Low
Density
Materials
Source: ICE, "Status 1996"
19129
Figure 4-56. MCM Substrate Comparison
MCM Type
Materials
Cost Ratio
MCM-L
Various organic laminates
1.0
MCM-L/D
Laminates with deposited polyimide/metal
1.3–1.5
MCM-C
Low-temperature co-fired ceramic (LTCC)
1.5–2.0
MCM-C/D
LTCC and polyimide/metal deposition
2.0–3.0
MCM-D
Silicon and glass substrates
4.0–6.0
19486
Source: Consultar/ICE, "Status 1996"
Figure 4-57. Projected MCM Substrate Cost Ratios
Ceramic
MCM-C substrates are cofired (C) ceramic-based multilayer substrates. The metalization layers
are deposited and defined by screen printing. This technology was used by IBM to produce the
thermal conduction module (TCM), which was the first MCM produced in large volume.
Deposition
MCM-D substrates used deposited (D) metal and insulating layers to form circuits. These layers
can be deposited on a variety of substrates, including silicon. The technology utilized was initially
based on semiconductor wafer fabrication techniques but has now evolved to also use technology from LCDs and Tape Automated Bonding (TAB) processes. In all cases the metalization
process is subtractive. A layer of metal is deposited, defined by photoresist and then etched to
define the required pattern. MCM-D technology yields the highest individual-layer wiring density. MCM-D technology also results in the best high-speed performance. Both of these advantages come with the highest cost.
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INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Laminated
MCM-L substrates are laminated (L) using techniques from Printed Wiring Board (PWB) and TAB
manufacturing. This technology offers low cost but cannot provide extremely high-performance
circuits because of the physical properties of the materials used for insulating layers.
Combinations
The MCM industry is already combining substrate technologies to optimize the technical solutions. In particular, combinations of an MCM-C substrate containing ground and power connections with an MCM-D substrate providing the signal layers has proven viable. ICE expects this
trend to continue with the best features of each substrate style used as the application requires
(Figure 4-58). Eventually the three current categories of substrates may require modifications as
various combinations prove to be more useful.
Application
Substrate Type
Notebook/Portable PDA
MCM-L, MCM-L/D — initially COB
then flip chip
Cellular Phones/Pagers
MCM-L, MCM-L/D — rapidly going to
flip-chip assembly
Camcorders/Games
MCM-L, COB — evaluating flip chip
Military
MCM-C, MCM-C/D — still need hermetic
packaging, chip-and-wire assembly
Medical
MCM-C for implantable products,
MCM-L for instruments
Telecommunications
MCM-D and MCM-L/D for performance
— flip chip will be dominant
High-Performance Computing
Platforms
MCM-D and MCM-L/D — silicon
substrates heavily used
Automotive
MCM-L — flip chip, well established
for MCM-C, will be used with MCM-L,
some MCM-C under hood
Smart Cards
MCM-L, strong user of TAB, will
migrate to flip chip
Displays
MCM-D with glass substrate, TAB and
direct chip-on-glass with TAB for
flip chip
Source: Consultar/ICE, "Status 1996"
19476
Figure 4-58. MCM Applications by Substrate Type
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
The Chip As A Package
A major breakthrough in MCMs is thinking about the IC chip itself as the first level package. The
concept is illustrated in Figure 4-59. This concept is driven by the difference between the size of
the single-chip IC package and the size of the chip itself. Not only is the space savings critical
(Figure 4-60) in many applications but electrical performance is enhanced by placing chips closer
together in a single module.
This “chip as a package” idea has been utilized previously in some single-chip products using the
chip-on-board (COB) technology. An IC chip is mounted to a PC board, wirebonded, and covered
with a layer of protective plastic (glob top). These products were and are used heavily in consumer products like video games and watches. MCM takes this concept further and places multiple chips on a substrate. In many cases the MCM will be able to replace an existing printed circuit assembly using surface mounted individual IC packages. This replacement market will be
driven by the usual market forces of cost, performance, and size.
Source: Rockwell
Source: ICE, “Status 1996”
16204
Figure 4-59. Conventional Board and Equivalent MCM
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INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Bare die 400 sq. mils
Flip-chip (8% larger)
Wirebond (39% larger)
Flip TAB (69% larger)
Conventional TAB (69% – 164% larger)
196-lead quad flat pack (1,880% larger)
Source: nChip/ICE, "Status 1996"
19148
Figure 4-60. Packaging Penalties
A big concern in the MCM marketplace has always been the known-good-die issue. Texas
Instruments and MicroModule Systems (MMS) have teamed to offer their solution to the knowngood-die issue. The companies have developed a temporary package (DieMate) that allows manufacturers to test bare dice with area pads used in flip-chip technology. MMS will supply the thinfilm packages that are custom made for a given chip type. The carrier (Figure 4-61) will have contacts and an interconnect pattern laid on it so that the chip for which it is made can be placed on
it upside down, with its bonding pads matching up to contacts in the carrier. The chip is held to
the carrier with pressure during burn-in and testing, and is then released and removed, with an
operator knowing whether the die is good or bad. Other companies, including AT&T, Chip
Supply, IBM, Micron, and Motorola, have developed methods of testing known good die as well.
TI estimates the overall cost of using the DieMate system at between 25-50 cents per chip in high
volumes.
The MCM Market
As shown in Figure 4-62, laminate-based MCMs accounted for the majority of MCMs sold in 1995.
By the year 2000, MCM-Ls will still make up 55 percent of the multichip module market, but there
will be a significant movement to MCM-Ds as pricing becomes more competitive for these parts.
Solutions to better managing known good bare-die issues cannot come soon enough. Several IC
manufacturers are expanding further into MCMs and welcome any help they can get to make
their job easier.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
Force Delivery
Mechanism
Die
Lid
Die Edge
Registration
Feature
Carrier
Interconnect
Compliant Material
Socket
Source: Semiconductor International/MMS/ICE, "Status 1996"
19228
Figure 4-61. Temporary Carrier for Die-Level Burn-In
MCM-C
5%
MCM-C
10%
MCM-D
25%
1995
$530M
MCM-L
65%
MCM-D
40%
2000
$2,200M
MCM-L
55%
*Not including components.
Source: ICE, "Status 1996"
18526E
Figure 4-62. MCM Market Projections*
Figure 4-63 shows ICE’s forecast for the MCM marketplace. The figures in Figure 4-63 do not
include the cost of the dice in the MCM. New standards, CAD tools, consortiums, and an increasing supply of tested known-good bare dice should help spur a 33 percent CAGR for the MCM
market through the end of the decade. Figure 4-64 shows that nChip shipped twice as many MCM
units in 1Q95 as it did in all of 1994. Figure 4-65 shows an MCM forecast from Toshiba that
includes the value of the IC dice in the MCM. The $30 billion MCM forecast figure in the year 2000
would represent about nine percent of the expected $331 billion total IC market at that time.
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INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
2,500
Millions of Dollars
2,000
1,500
1,000
500
0
1991
1992
1993
1994
1995* 1996
Year
1997
1998
1999
2000
*About 75% of market was captive
Source: ICE, "Status 1996"
18636B
Number of MCM Units Shipped
Figure 4-63. MCM Market Forecast
1991
1992
1993
1994
1Q95
Year
Source: Advanced Packaging/ICE, "Status 1996"
20430
Figure 4-64. nChip MCM Shipments by Year
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
35
Other
Total MCM
30
Worldwide MCM Sales
Industrial
Telecommunications
25
Consumer
Computer
20
15
10
5
0
1992
1993
1994
1995
1996
Year
1997
1998
1999
Source: Toshiba/EMR/ICE, "Status 1996"
2000
19231
Figure 4-65. Worldwide MCM Forecast (Fully Populated Value)
Ball Grid Arrays (BGAs)
One of the most talked about surface mount packages is the ball grid array (BGA), shown in Figure
4-66. In the packaging industry, it is currently the hottest thing going. A BGA package, rather than
using pins for leads, mounts to a board using solder balls located on the underside of the package.
Molding Compound
Gold Wirebond
Epoxy
Die Attach
IC Die
Gold-plated
Die Attach
BT Resin Glass Epoxy
Solder
Ball
Plated-Through
Hole
Substrate: BT resin glass epoxy
Die Attach: Silver-filled epoxy
Wire: Gold
Cover: Custom molding compound
Copper Foil Pads
& Interconnect
Solder
Mask
Source: Motorola/ICE, "Status 1996"
18510
Figure 4-66. OMPAC Ball Grid Array from Motorola
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INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Proponents of this package say it provides benefits such as small size, good yields, excellent electrical performance, and low profiles—features that have been demanded by systems designers. By
spreading the contacts over the bottom of the packaged device, the size of the package is reduced
compared to quad flat packs. No longer are there many small leads jutting out from all edges of
the package. The package has prodded some engineers to state that within five years, there will not
be much high leadcount fine pitch in use—everyone will be using these new arrays (Figure 4-67).
1.8
Ball-Grid Array (BGA)
1.6
Pitch (mm)
1.4
1.2
Technological jump
from QFP to BGA
Quad Flat Pack (QFP)
1.0
Technological
limit for QFP
fine pitch
0.8
Limit of what can
be done "simply"
0.6
Limit range of what can be
reasonably accomplished in
light of cost considerations
0.4
0.2
0
100
200
300
400
500
600
700
800
900
I/Os
Source: IBL-Löttechnik/ICE, "Status 1996"
20315
Figure 4-67. Fine Pitch, High I/Os Push Packaging to Ball-Grid Arrays
One of the biggest concerns of using a BGA are the solder balls, which also happens to be one of
the big advantages of the package. While the configuration makes the dimensions smaller, many
of the solder joints are hidden beneath the package, making visual inspection impossible (x-ray
inspection is required). Another concern is the high costs associated with BGAs. Even with
increased volumes, BGAs will more than likely command a greater price than QFPs since BGAs
have a circuit board that holds the chip and fans out the leads. And, though the printed circuit
board area may be small, circuit boards that can handle BGAs may well require more layers. From
an area standpoint, BGAs take less space, but routing traces to them tend to use more PCB layers.
This can serve to increase the cost of the subsystem. Moreover, repairability is also difficult with
current BGA packages.
At present, there has been more discussion about using the new package than actually incorporating it into products. Motorola and Compaq are currently the two largest users of BGA packages. It is estimated that these two firms alone used about 15 million BGA-packaged ICs in 1995.
Motorola uses the BGA package in its pagers and cellular phone products and is offering the BGA
as a packaging option on some of its standard products (e.g., SRAMs).
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
Until further experience can be gained, BGA packaging will be looked upon cautiously. However,
most people involved agree that the proliferation of BGAs is just around the corner and it should
not be too long before BGAs are embraced as a competitive alternative to high pin-count QFPs. A
list of some 1995 BGA announcements is given in Figure 4-68.
•Kyocera is expected to begin producing 1,144-ball BGAs on a 35mm x 35mm
ceramic substrate beginning in 3Q95. To reduce thermal coefficient of expansion
stress with such a large substrate, Kyocera surrounds the base of the solder balls
with Al 2O3 (See Figure 4-69).
• VLSI Technology began offering its high-end ASICs in tape ball grid array (TBGA)
packages in 1Q95. VLSI paid a one-time license fee to IBM for use of the TBGA
technology.
•Micron Substrate Corp. (Tempe, AZ) used its patented via/plane process to develop
low-cost ceramic BGA packages. The package is said to cost about two cents per
ball compared with the typical five to six cents per ball.
•Motorola introduced a 313-lead staggered ball BGA (to allow easier routing) package
in 1Q95.
•Motorola began selling SRAM modules using 357-ball BGAs in 3Q95.
•LSI Logic intends to ship 2.5 million ASICs in plastic BGAs in 1995.
•IBM Microelectronics began offering 313-700 I/O plastic BGA packages to the
open market in 1Q95. Previously IBM had concentrated on ceramic BGA packages.
•Amkor and Tessera Inc. signed an agreement in which Amkor will make an equity
investment in Tessera and will directly supply the market with Tessera developed
BGAs.
•Amkor plans to construct the first non-captive BGA packaging facility in the U.S. in
1996. Amkor Anam's Seoul assembly facility is targeting BGA capacity of 2.8 million
units per month by the end of 1995.
• Sheldahl Inc. and TI formed a partnership to develop a variety of BGA packages
using Sheldahl's "ViaGrid" microsubstrate technology.
• 3M began marketing microflex material for BGA packages. 3M has an alliance with
Tessera Inc.
• Shinko Electric Industries began production of µBGA packaging in 4Q95. Initial
capacity was 100K units per month. Shinko licensed the technology from Tessera
Inc.
• Olin Interconnect Technologies is developing a metal BGA package using an
anodized-aluminum substrate with a thin-film circuit layer. The package will dissipate
from 5 to 7W without heat sinking.
• Chip Scale Inc. and Motorola unveiled a licensing agreement that allows Motorola to
develop chip scale packages of under 100 leads using Chip Scale's Micro SMT
technology.
Source: ICE, "Status 1996"
20316A
Figure 4-68. Sampling of 1995 BGA Announcements
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INTEGRATED CIRCUIT ENGINEERING CORPORATION
IC Technology and Packaging Trends
Alumina Ceramic
Low-temp solder pad
Hi-temp
solder ball
Source: Kyocera/EMR/ICE, "Status 1996"
20317
Figure 4-69. Kyocera’s “Buried Ball” Technology
The Hitachi/Tessera µBGA package (Figure 4-70) and the Mitsubishi device shown in Figure 4-71
are examples of the new so-called chip-scale packages (CSP). The CSP has only a thin layer of
plastic resin coating the chip, which makes the completed package only slightly larger than the die
itself (less than 20 percent larger). The solder bump pitches of the Mitsubishi CSP package are
1mm or 0.8mm (about 40 and 32 mils, respectively).The company believes that memory ICs are a
potentially big user of CSP.
Protective
Coating
HG72G/E Gate/Embedded Array Chip
Compliant Layer
Interconnect
Bump Array
– 672 Bumps
– Gold Plated
Flex Circuit
Printed Circuit Board
The bump array, which is mounted on a compliant layer to reduce
the mechanical stress of the solder joint and accommodate surface
irregularities on the printed circuit board, uses gold plated bumps
for reliability.
Source: Hitachi/ICE, "Status 1996"
19505
Figure 4-70. Diagram of a µBGA Package
INTEGRATED CIRCUIT ENGINEERING CORPORATION
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IC Technology and Packaging Trends
External
Electrode
Bump
Resin
Electrode
Wiring
Pad
Conductor
Pattern
IC
Source: EE Times/ICE, "Status 1996"
19506
Figure 4-71. Mitsubishi’s Chip-Scale Package (CSP)
It is interesting to note that most early CSP development work was accomplished by Japanese
companies. However, as was mentioned in Figure 4-68, ChipScale Inc., Motorola, and Tessera Inc.
are three North American companies that plan to be at the forefront of commercializing CSP IC
packaging.
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INTEGRATED CIRCUIT ENGINEERING CORPORATION