Heat dissipation, or the "thermal barrier, " is a problem that
circuit designers have faced for years. The answer in the
1980's may be CMOS.
w
L
'
,
CkN 41 C
Special Feature:
CMOS LSI - The Computer Component
Process of the 80's
Donald L. Wollesen
American Microsystems, Inc.
LSI-large-scale integration (or, as some prefer to
call it, large-scale insanity)-is a present-day fact of
life. In addition, we have invented the term VLSI:
"V" for very. Single microprocessor chips have been
designed and products produced which contain in excess of 35,000 transistors, a transistor count which
few entire systems could boast of a scant 10 years ago
(even counting the IC transistors).
Although many circuit design and process improvements have been made in the 70's, most of the
progress has been made in a fine-line photolithography. These improvements have been largely
evolutionary refinements in photoaligner machine
design, optics, photoresist, and mask making. Looking to the future, I can see no indication that progress
will cease. The cost of the basic production photolithographic tool of the semiconductor art-the mask
aligner-has increased from about $12,000 ten years
ago to about $240,000 today-a 35 percent per year
price increase, compounded yearly. A state-of-the-art
wafer stepper is over $500,000. The payoff has been
reflected in memory density increasing by a factor of
4 every four years. Table 1 gives an approximate
timetable of what happened in the 70's and what will
Table 1.
MOS Dynamic RAMs.
INITIAL INTRODUCTION
PER BIT PARITY WITH
PRIOR GENERATION
MATURITY
February 1980
1K
1970
4K
1974
16K
1978
64K
1981
1972
1976
1980
1984
1974
1978
1982
1986
-
probably happen in the early 80's for MOS N-channel
dynamic RAMs. What this data shows is a bitdensity improvement of about 41 percent per
year-compounded. Static MOS RAMs have trailed
dynamic RAM density by three to four years. MOS
ROMs have led dynamic RAMs by three to fouryears
in bit density.
Most semiconductor industry seers will maintain
that we expect to continue on the same growth curve
for most if not all of the 1980's. Whereas this will
most likely be true for memories, there is some
serious question if logic and linear-based designs will
require the density and its attendant massive capital
investment. For these types of products (such as
toys, calculators, watches, microprocessor machine
control devices, etc.), economics may show that the
VLSI capital investment cost will not justify the cost
reduction benefit to the component.
"Microecology"
Another factor is coming to rear its ugly head: excessive power dissipation in LSI, and more so in
VLSI. Bipolar LSI chips have always run hot and
have been able to do so simply because bipolar transistors' switching time does not degrade appreciably
as junction temperature rises (at least over accepted
operating junction temperature ranges). MOS transistor gain (and hence speed) will drop by a factor of 2
over a junction temperature increase of 1000C to
1250C. For example, a MOS circuit will be about
twice as fast at room temperature as it is at 125 °Cambient. Although MOS devices tend to self current
limit at high temperatures and avoid the "self
destruct" potential of bipolars, the reduction in
0018-9162180/0200-0059$00.75 1 1980 IEEE
59
operating speed is normally unacceptable to most
computer component users.
Bipolar IC designers have been up against the
"thermal barrier" for years. A 16-pin DIP is good for
about 1-watt dissipation, 40-pin DIPs about 2 watts
dissipation, and special heat-sinked packages about 4
watts dissipation. (See Table 2.) For MOS circuitry
where operating speed is not a concern, MOS circuits
can be run at thermal dissipations about the same as
bipolar chips. High-performance MOS ICs normally
are limited to about half this power dissipation. Heatsinked IC packages have not been used by any commodity MOS IC device.
There are quite a few MOS LSIs in 5- and 6-micron
NMOS technology which are presently limited by
package power dissipation constraints. Power
dissipation has been and is a major impediment to
bipolar IC designers-and now NMOS LSI circuit
designers are facing the same problem. Circuit
designers have been aware of this barrier for years
and have used circuit innovations such as dynamic
circuitry and edge-triggered circuitry plus lots of
clocks to keep power dissipation within reasonable
limits. For pure N-channel designs, about all of the
power conservation tricks have already been pulled.
The day of reckoning is upon N Channel: the thermal
barrier has arrived.
The 1980's will require semiconductors to do more
functions on a given die, and demands for higher performance will not abate. The, fundamental power
dissipation constraint of low-cost high-volume
semiconductor component packages is not expected
to change much. What this calls for is a process which
is not up against a thermal barrier. CMOS is probably
the best choice. The nice thing about it is, for a given
patterned gate linewidth, CMOS is about twice as
fast as N-channel. That's nice. CMOS will be the
leader in microecology.
reduction in power dissipation compared with other
technologies (I2L comes close, but "no cigar").
As complementary MOS circuits grew in density
and silicon gate technology emerged in the early
1970's, the first generation of LSI CMOS was born.
CMOS LSI was initially used for watch and calculator chips, and to this day the battle in those applications between the simpler metal-gate process and the
denser (though more expensive) silicon-gate technology yields no clear winner.
But today's memories and microprocessors demand far greater speed than watches and calculators,
and for these uses silicon gate CMOS is clearly the
victor. Products at the density level of 4K static
RAMs, which also demand high speed, mandate an
entirely new approach in process technology and
device structures. Moreover, the burgeoning
Figure 1. Basic CMOS two-input gate.
Some CMOS history
One might ask why CMOS has not been a highvolume commodity process in the past. Well, it has
been in a sense; its uses were unique. It was used
where nothing else would do-in ultra-low-power applications such as watches and calculators. The
watch batteries in a CMOS LCD display calculator
(without ever being recharged) will often outlast much
larger NiCads in an LED PMOS calculator even with
many, many recharges. CMOS results in a massive
Table 2.
Power dissipation constraints.
16-PIN DIP
40-PIN DIP HEAT-SINKED
IC PACKAGE
2 WATT
4 WATT
BIPOLAR [Cs
1 WATT
LOW-PERFORMANCE MOS ICs
1 WATT
2 WATT
NOT USED
HIGH-PERFORMANCE MOS ICs
0.5 WATT
1 WATT
NOT USED
Figure 2. Basic NMOS depletion load two-input gate.
COMPUTER
analog/digital LSI that mixes linear circuits with
logic makes new demands in terms of performance
and density.
A closer look at speed-power product
The inherent performance of any IC relates to two
primary factors: the fundamental transistor device
speed and the fundamental basic gate circuit used.
There is little evidence in commercial ICs that
CMOS is in fact any faster than NMOS. There is a
reason for this, however. Due to competitive pressures, NMOS development has been pushed very
hard by memory technology demands. CMOS has not
been. Several manufacturers have 4-micron and
smaller N-channel processes in production. In
CMOS, quite a few people have 6-micron CMOS in
production, but hardly anyone has 5-micron CMOS in
production.
Because of this phenomenon, N-channel technology has enough lead time where there are few CMOS
circuits which are as fast as their N-channel counterparts. If one chooses to compare basic gate speed using identical design rules, the CMOS gate will switch
in less than half the time of an N-channel gate.
The basic gate
Figure 3. CMOS gate transient behavior: (a) voltage; (b) current.
Figures 1 and 2 show the circuit of a basic two-input
gate-one in CMOS, the other in N-channel. The
CMOS gate has the nice feature of both active pullup
and active pulldown. It only draws power in a transient condition. In a static data state, it draws
negligible power-only junction and subthreshold
leakage current. We can call this a "demand" type of
logic gate in that it only draws power on demand of a
transient excursion.
The NMOS gate uses an active pulldown but a
passive pullup. If both inputs are low and the output
is high, it draws no power. If the output is in a low
state, it draws 100 pA (or whatever it is designed to
draw) no matter what. Transient currents are,
relatively speaking, negligible. This is a "loss load"
type of gate.
Looking at Figures 3 and 4, which show idealized
voltage and current transient waveforms, one notices
several things:
(1) CMOS voltage rise and fall times are comparable, NMOS fall time is fast, rise time is
(relatively) slow;
(2) (rise plus fall) - 2 of the CMOS gate is about
twice as fast as the N-channel gate;
(3) the CMOS gate output voltage settles essentially at each voltage rail, with good voltage
margin from V., and Voh the N-channel gate settles at the Vdd rail and has good static V0h
margin but does not settle close to the ground
rail and does not have good V., margin;
(4) process control of depletion load current is not
as good as one would like, hence the rise time
Figure 4. NMOS gate transient behavior: (a) voltage; (b) current.
February 1980
61
varies a lot (a factor of 2 is common), and
dynamic Voh margin may be poor if the circuit
designer is pushing for high speed in the basic
gate;
(5) at maximum NMOS gate toggle rate, the
CMOS gate will draw two to four times more
current than the NMOS gate;
(6) with an IC in the standby mode, the NMOS circuit will statistically have half of its gates "on"
and will draw orders of magnitude more power
than the CMOS IC.
To be fair about the comparison, NMOS circuit
designers do use active pullup techniques to improve
gate speed without the expense of additional DC
power. But then, these techniques do consume more
chip area and, in most cases, it simply is not static
logic any longer.
10-,
Speed-power product on the basic gate
10-2
a-
Lu
ccC8 i o-!
V)
LU
0-
0o-
1o-I
1U-°
SWITCHING SPEED(S)
1u
lo-9
Figure 5. This comparison of switching energies (based on performance of a single 5-sm gate) shows bulk CMOS equal in speed to
CMOS on sapphire. The former's junction capacitance is offset by the
latter's losses in majority-carrier mobility. (Courtesy Electronics.)
Table 3.
Current requirements of 16-K bytes of random
access memory (mA).
TECHNOLOGY
CMOS
STANDBY
24
Each
Chip Chips
0.005 0.12
840
35
3
72
N-CHANNEL
N-CHANNEL
(with power-down)
Note: All memory elements are 4K by 1-bit static RAMs.
62
In reviewing Figures 1-4, one can see some things
which aren't so obvious:
(1) that the power supply may be varied as much as
5:1 (e.g., from 2.5V to 12.5V) for the CMOS gate
whereas the NMOS gate (in an IC environment)
may only tolerate a 2:1 change in power supply
voltage and in high-speed circuits often much
less;
(2) that CMOS is not a "ratioed" logic (an advantage), whereas NMOS is a "ratioed" logic (e.g.,
in order to increase the speed of the gate of the
ratio of "on" resistance of the depletion pullup
to the enhancement, pulldown must be reduced-but if carried too far it will eliminate Vol
margin and render the gate inoperable);
(3) as technology brings finer-line geometries, the
control of the NMOS gate "ratio" will get
worse and worse, whereas CMOS will be relatively less affected by process variances (and
hence is expected to yield better).
ACTIVE
8
Each
Chip Chips
40
5
360
45
280
35
TOTAL
40
1,200
350
Figure 5 compares several technologies in switching speed versus power consumption. It is, however,
based on the performance of a single input inverting
gate; every gate in the system would have to be toggling at maximum rate for an extrapolation of gatelevel performance to system-level performance. But
it at least gives an idea of relative performance.
CMOS does tend to slow down as a function of the
number of gate inputs: for a single gate switching
speed of 2.5 nanoseconds, a four-input gate would
switch in about 10 ns-but with only a slight penalty
in power dissipation.
The data is based on 5 Mm technologies operated at
5V. It is worth noting that, from the standpoint of
speed, 5 Wm bulk silicon matches 5 Mm CMOS on sapphire. The reason is that although bulk CMOS exhibits far greater junction capacitance, CMOS on
sapphire is limited in its majority carrier mobility,
which holds it to a lower gain constant for a given
device. Still, CMOS on sapphire retains a substantial
advantage in gate power. However, it may not yield
any advantage at a system level, because its standby
leakage current is much higher. Also, it is a very expensive technology. CMOS and CMOS on sapphire
are the only technologies that dissipate power only on
logic transitions.
Integrated injection logic is a constant "loss-load"
technology, unlike CMOS: high speed is traded off
against low power by the designer. 12L has a broad
speed-power band, but it follows the entire speedpower curve only if its bias current is changed from
standby to active, something that is not usually done
in small systems.
The inherent standby attribute of static CMOS
technology is one of its greatest strengths from a
system standpoint. Consider an 8-bit microprocessor
with 16K bytes of RAM. Because the microprocessor
can perform only one address operation at a time,
COMPUTER
nArI 1rli U11rLAY aby I tM DESIGN NOTE 2.
16,383 bytes of memory do nothing but remember
while 1 byte is being accessed. Moreover, in most
cases any peripheral interfacing circuits will also be
having to wait until memory is being accessed.
Current comparison
Table 3 compares the current required for CMOS
N-channel (2114 type) and N-channel power-down
memories, based on the assumption that the 16K
bytes of memory are made up of 32 4K by 1-bit static
RAMs. At any given time, eight chips are active and
24 are inactive. The memory system's total current,
which is the sum of the standby and active currents,
is 30 times greater with N-channel than with CMOS
RAMs. Even power-down N-channel RAMs, which
are not often used in microprocessor systems because
the cost or the increased system complexity is rarely
worth the trouble, draw almost nine times as much
current as CMOS.
CMOS is the only logic form that operates in an
automatic power-down mode. Even if 12L static
RAMs were available commercially, they would at
best compete with edge-triggered N-channel RAMs
and would probably have similar operating current;
only the standby currents would be less with NMOS.
Lest one scoff at this comparison, within two years
there should be 16K CMOS static RAMs available for
use in systems. One could, in fact, package these
devices in a leadless package, test them, and then
solder eight of them to a 28-pin DIP and have, in fact,
a quasi "hybrid" form of this 16K-byte RAM on one
IC package. Assuming one would want to use a 5-volt
power supply for this static RAM, let's take the
system current from the total column in Table 3 and
compute power dissipation:
the CMOS RAM-200 mW
the NMOS RAM-6 watts
the NMOS power-down RAM-2 watts
For one 28-pin DIP, 200 mW for CMOS is a piece of
cake. For NMOS, it just is not practical. Now, the
concept of "microecology" is put in perspective. It
will take the component density of the 80's to drive
this point home. As a result, the use of CMOS technology in more and more applications as time goes by
will be mandated.
CMOS-why isn't it here today?
A common question comes up: If CMOS is so great,
why hasn't it been more popular? The answer is simple: the computer industry has not been willing to pay
for it; CMOS has been an expensive process, and the
extra performance didn't warrant the price premium.
N-channel devices have traditionally used smaller
geometries than CMOS, a fact which results in
greater density and resulting lower cost per function.
Since there is no fundamental reason why CMOS cannot be built with fine-line geometries, CMOS is in the
process of catching up in this area.
February 1980
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The CMOS wafer cost historically has been substantially higher than N-channel, and the CMOS die
area consumed for an equivalent function has been
substantially greater than N-channel. Between the
two, finished die cost was much greater. However,
nothing ever sta,ys the same in the semiconductor
business.
Semiconductor memory-CMOS and NMOS
As memories get larger, the area penalty wril get less
and less.
Although this article is not addressing linear circuits, AMI has developed a general-purpose op amp
in both NMOS and CMOS. The CMOS op armp performs much better and only uses 45 percent 6f the
NMOS cell area.
Figure 6 graphically shows what has been happening over the years when comparing CMOS and
NMOS. In the 1980's, CMOS will become costcompetitive overall with NMOS wafer cost.
There is a basic trend in the semiconductor memory
business: memory core has increased by a factor of 4
every four years. The peripheral memory control, ad- Wafer cost
dress, and decoder circuitry only doubles every four
CMOS wafers have, historically, cost more than
years (peripheral circUit area increase is equal to the
square root of the memory core area increase). Al- NMOS wafers. That, too is changing. Wafer costing
though this appears innocuous, it is very important is pretty sensitive data to any semiconductor
for future trends in CMOS vs NMOS die area.
In the past, CMOS logic area was about double that
of N-channel. Contemporary 5-micron CMOS process
Table 4.
improvements have improved this to a factor of
CMOS 4K static RAM: design rules Impact.
about 1.5. The peripheral circuitry is, essentially,
logic.
BITS CELL SIZE MEMORY AREA
PROCESS
(sq. mils)
(sq. mils)
The core of the memory need not be any different.
68,400
16.7
4K
Here are some examples:
CMOS, 6p Rules
41,000
10.8
4K
CMOS, 5j Rules
23,700
5.8
4K
4y Rules
ROM. It is hard to conceive of a ROM cell with CMOS,
12,288
3.0
4K
Rules
Load,
4j1
CMOS
Poly
the
same
feature
size,
for
So
one
transistor.
than
more
NMOS and CMOS memory areas are equal.
Static RAM. Historically, the CMOS RAM has
used four N-channel and two P-channel transistors in
the core cell. However, if one uses the most dense
static RAM cell, the "poly load" cell, in a CMOS
RAM. The "poly load" cell can use load resistors at
1-10 G-ohm range, which is perfectly compatible with
CMOS goals. If one uses this strategy, NMOS and
CMOS cell sizes are equal. And, with CMOS, you get
a bonus: CMOS is relatively immune to alpha particles. NMOS isn't!
Table 4 shows the progress CMOS is making in
static RAM cell sizes.
DIE SIZE
(mils)
262 x 262
235 x 235
189 x 189
140 x 140
Table 5.
4K static RAM area comparison.
NMOS
(mil2)
CORE AREA (poly load)
PERIPHERAL CIRCUITS
OVERHEAD AREA
(bonding pads, etc.)
TOTAL AREA
11,200
5,700
5,600
VAREA
150 mil
22,500
X DENSITY
PENALTY
1.0
CMOS
(mil2)
1.04
11,200
7,410
5,840
1.08
24,336
1.3
156 mil
Dynamic RAMs. No one has done a CMOS DRAM.
But if one wanted to, the single capacitor transistor
cell would be the same area in CMOS as it would be in
N-channel.
PROMs. Programmable ROM cells in CMOS are
the same size as they are in NMOS. In essence,
memory core area in NMOS and CMOS are the same;
there is no advantage either way.
Table 5 shows the impact of comparing the implementation of a 4K poly load static RAM in NMOS
and CMOS. The die area density penalty is only 8 percent by going to CMOS. This is a drastic improvement of the 100 percent aerea penalty paid by using
the classic six-transistot CMOS memory cell. Die
cost is proportional to'- die area)2. For this comparison, the relative die cost has gone from four times
NMOS to 1.6 times NMOS by changing from the use
of a CMOS core cell to the same core cell as N-channel.
February 1980
Figure 6. CMOS vs NMOS-1973 through 1981.
65
manufacturer, so I will address it in relative terms. If
you count masking layers in any MOS process, you
can get a reasonable compatison of relative *afer
cost (see Table 6.) So, let's look at the history of tihask
count. Silicon gate CMOS has been at 8-10 levels ever
since it was invented. NMOS started out as a relatively simple five-mask, low-performance (by today's
standards) process. In order to keep improving speed
and still stay within package power-dissipation
limits, masks have been added to such an extent that
the highest performance 5-micron NMOS process has
the same number of mask layers as AMI's 5-micron
CMOS process. So, wafer cost is converging too.
Figure 7 shows the comparative cost trends for the
past and near future.
From a die area viewpoint, from a process complexity viewpoint, and from a circuit yield viewpoint,
CMOS has been an expensive medium blit it is getting cheaper: NMOS has been an inexpensive process
media but it is-getting more costly. The relative costs
per function have been converging and probably will
be essentially the same within four years.
Now, if you include speed into the system cost
equation, faster cycle times make the system utility
factor higher. Lower power requirements reduce
power supply and component cooling cost overhead.
So, even if there is a nominal cost premium for a
CMOS computer component, total system costs can
be reduced.
Power consumption cost
The cost of a kilowatt hour is also substantial. At
$0.06/kW-hr, if a 1-kW system is left on 24 hours a
day (as many are), one year's usage (8736 hours/year)
results in an operating cost of $427 for electric power.
Assuming thai a CMOS system would run at 10 percent of this power, then electric power cost savings
(per kW of N-channel system) is $393 per kW-year.
CMOS process flexibility
Pew LSI protesses are flexible in application. LSI
densities will encourage the use of more different
types of circuitry on one die. CMOS is the only
technology capable of creating all of the following circuits and attributes simultaneously on one die:
nlhrITAI
I IMrAD
RAM
OP AMPS
ROM
LOGIC
PROGRAMMABLE ROM
INTERFACE DRIVERS
AUTOMATIC POWER-DOWN
COMPARATOHS
VOLTAGE REtRENCES
D/A AND A/D CONVERTERS
AUDIO FILTERS
PROGRAMMABLE POWER-DOWN
Why pick CMOS for new designs?
Table 6.
Process complexity trends: silicon gate.
YEAR
1973
1975
1977
1979
1981
LINE WIDTH
7.5 MICRONS
6 MICRONS
5 MICRONS
4 MICRONS
3 MICRONg
PMOS
5-7 MASKS
6-8 MASKS
-
-
NMOS
5-7 MASKS
6-8 MASKS
7-9 MASKS
8-10 MASKS
8-11 MASKS
CMOS
8-9 MASKS
8-9 MASKS
8-10 MASKS
7-16 6ASKS
7-12 MASKS
As we enter the next decade, the demand for continued product improvements will not cease. Here are
a few reasons in favor of converting new designs into
CMOS LSI:
(1) CMOS is the fastest MOS process format.
(2) High-performance N-channel wafer costs are
converging on CMOS wafer costs: cost crossover expected by 1981,
(3) CMOS layout density is approaching N-channel
(a) CMOS area = 1.3 N-channel area for complex digital circuits.
(b) CMOS area = 1.0 N-channel area for memory cells.
(4) CMOS is not affected by thermal dissipation
limits of popular IC packages. N-channel and
bipolar technologies are thermal dissipation
limited.
(5) CMOS is the lowest copt linear process.
(6) On-chip filters cannot be done in bipolar; they
can be done in CMOS.
Custom circuit desighs
Figure 7. Cost trends.
66
Many computer manufacturers utilize custom
MOS ICs in their products to gain performance advantages and lower system costs. These custom circuits may be designed by the computer manufacturer
COMPUTER
or by a semiconductor vendor. Normally, design span
Each application will have its own optimumn protime is of the essence, in order to stay technologically cess and logic format. Metal gate P-channel will recompetitive.
main a cost-effective medium for low-density circuit
These electrical circuit designs are normally applications. Silicon gate N-channel will continue as a
simulated by a CAD program. This entails semicon- mainstream process where high density and interductor device modeling in order to get accurate mediate speeds and substantial power dissipation are
results. N-channel designs use both enhancement acceptable. Bipolar will also continue as a mnainstream
transistors and depletion transistors. CMOS uses process where power dissipation is not an issue, high
only enhancement transistors. Depletion transistor density is not an issue, but raw speed is primary.
models are normally not as accurate as enhancement CMOS will emerge as a lower-power, high-density,
models. Depletion transistor process control is not as intermediate-speed LSI and VLSI process. U
good as that for enhancement transistors. Reducing
transistor geometries aggravates both the model accuracy and the process control.
What all this means is that, for LSI and VLSI,
Donald L. Wollesen is department
CMOS models better than NMOS. This, in turn,
manager of R&D CMOS Device Develmeans that the chance of "first silicon" working and
opment and Design Technology R&D
meeting specifications will favor the CMOS circuit.
at American Microsystems, Inc. He
And as time goes by, and geometries get smaller, the
received his BSEE from Cal Poly in
1963 and an MBA from the University
scales will tip even more in favor of the CMOS circuit
of Santa Clara in 1976. A holder of four
performing to the CAD circuit simulation program.
US patents, Wollesen has worked in the
The end result is that the design cost will be higher
semiconductor industry since 1963 and
for N-channel than it will for CMOS. Also, IC design
has designed numerous bipolar, JFET,
engineers are a scarce resource, which is better util- and MOS devices as well as digital, linear, audio, and RF cirized on a new design than on a redesign.
cuits.
l
WORKSHOP ON
INTERCONNECTION
NETW\ORKS
for parallel and
distributed processing
April 21-22, 1980
Purdue University,W. Lafayette, IN
SPONSORED BYACM SIGARCH AND IEEE
COMPUTER SOCIETY TCCA,TCCC,TCDP
\g
IN COOPERATION WITH PURDUE UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING
11.e .,,
,r _ '
February 1980
To obtain registration information and
details, contact the workshop chairman.
program
WORKSHOP CHAIRMAN:
Howard Jay Siegel
Purdue University
School of Electrical Engineering
West Lafayette, IN
4?907
PROGRAM COMMITTEE:
Kenneth E. Batcher, Goodyear Aerospace
Tse-yun Feng, Wayne State Univ.
Duncan Lawrie, Univ. of Illinois - Urbana
G. Jack Lipovski, Univ. of Texas - Austin
Gerald M. Masson, Johns Hopkins Univ.
S. Diane Smith, Univ. of Wisconsin - Madison
Harold S. Stone, Univ. of Massachusetts - Amherst
Kenneth J. Thurber, Sperry Univac
Charles R. Vick, BMDATC
67