Instructor : Saraju P. Mohanty, Ph. D.
NOTE : The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality.
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Advanced Topics in VLSI Systems

• Power and Energy
• Dynamic Power
• Static Power
• Low Power Design
Advanced Topics in VLSI Systems
2

Advanced Topics in VLSI Systems
3

Power Dissipation Trend
100000
10000
1000
1.5KW
500W
Pentium® proc
18KW
5KW
100
10
1
8008
4004
8085
8080
286
8086
386
486
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
Advanced Topics in VLSI Systems
4

Power Density
IV
Advanced Topics in VLSI Systems
5

Power Dissipation
Static Dissipation Dynamic Dissipation
Sub-threshold current
Gate Leakage
Reverse-biased diode Leakage
Contention current
Capacitive Switching
Gate Leakage
Short circuit
Advanced Topics in VLSI Systems
Source: Weste and Harris 2005
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I
3
I
5
I
6
I
1
I
2
: reverse bias pn junction (both ON & OFF)
: subthreshold leakage (OFF )
I
4
: Gate Leakage current (both ON & OFF)
: gate current due to hot carrier injection (both ON & OFF)
: gate induced drain leakage (OFF)
: channel punch through current (OFF)
Source Drain
N +
I
2
I
6
P-Substrate
I
5
Advanced Topics in VLSI Systems
I
1
N +
Source: Roy 2003
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10 2
10 0
Dynamic
300
250
200
102 Trajectory,
With High-K
150
100
104
50
106
Chronological (Year) 
0
1990 1995 2000 2005 2010 2015 2020
Chronological (Year) 
Source: Hansen Thesis 2004
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Advanced Topics in VLSI Systems

Advanced Topics in VLSI Systems
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Power Dissipation in CMOS : Dynamic
Capacitance Switching Current : This flows to charge and discharge capacitance loads during logic changes.
Short-Circuit Current : This is the current due to the
DC path between the supply and ground during output transition.
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Advanced Topics in VLSI Systems

Power Dissipation in CMOS : Static
• Subthrehold Current: Sub-threshold current that arises from the inversion charges that exists at the gate voltages below the threshold voltage.
• Tunneling Current: There is a finite probability for carrier being pass through the gate oxide. This results in tunneling current thorough the gate oxide.
• Reverse-biased Diode Leakage: Reverse bias current in the parasitic diodes.
• Contention Current in Ratioed Circuits: Ratioed circuits burn power in fight between ON transistors
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Advanced Topics in VLSI Systems

Power Dissipation in CMOS : Dynamic
A general CMOS transistor circuit
•Dynamic power is required to charge and discharge capacitances load when transistors switch.
•One cycle involves a rising and falling output.
•On rising output, charge
Q = CLVDD is required.
•On falling output, charge is dumped to GND.
Advanced Topics in VLSI Systems
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Power Dissipation in CMOS : Dynamic
Note:
1. the difference between the two is the loss
2. Energy doesn’t depend on frequency
Advanced Topics in VLSI Systems
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Power Dissipation in CMOS : Dynamic
For N c clock cycles energy loss :
E
Nc
= C
L
V dd
2 n(N c
) n(N c
) : is the number of 0->1 transitions in N c
clock cycles
Note: Power depends on frequency
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• When transistors switch, both NMOS and PMOS networks may be momentarily ON at once.
• Leads to a blip of “short circuit” current.
• < 10% of dynamic power if rise/fall times are comparable for input and output.
Advanced Topics in VLSI Systems
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• In OFF state, undesired leakage current flow.
• It contributes to power dissipation of idle circuits.
• If v
V th t
is the thermal voltage and I
0
is the current at
then the subthreshold current is :
( ) v t
• Drain-Induced-Barrier-Lowering (DIBL) an prominent effect for short channel transistors also impacts subthreshold conduction by lowering V th
• It increases as the V th
decreases or V gs
• It increases as the temperature increases.
.
increases.
Advanced Topics in VLSI Systems
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Junction Leakage
• The pn junctions between diffusion, substrate and well are all junction diodes.
• These are revered biased as substrate is connected to GND and well connected to V dd
.
• However, reversed biased diode also conduct small amount of current.
Advanced Topics in VLSI Systems
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Static Power : Junction Leakage
• The reverse-biased junction current is expressed as follows: (D is not for drain, S is not for source)
• I
S
I
D
= I
S
[ exp (V
D
/ v
T
) – 1 ]
depends on the doping level, the area, and perimeter of the diffusion region.
• V
D
is the diode voltage e.g. V sb
or V db
.
Advanced Topics in VLSI Systems
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I gs
I gcs
I
I
I gd gcd gb
BSIM4 Model
•There is a finite probability for carrier being pass through the gate oxide.
•This results in tunneling current thorough the gate oxide.
•The effect is predominate for lower oxide thickness.
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Advanced Topics in VLSI Systems

• The gate oxide leakage current can be expressed as follows [Kim2003, Chandrakasan2001] (K and
α are experimentally derived factors).
I gate
=K W gate
(V dd
/T gate
) 2 exp (– α T gate
/V dd
)
• Options for reduction of gate leakage power :
– Decreasing of supply voltage V
– Increasing gate SiO
2 dd
(will play its role)
thickness T gate
(opposed to the technology trend !!)
– Decreasing gate width W gate
(only linearly dependent)
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Advanced Topics in VLSI Systems

Advanced Topics in VLSI Systems
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Packaging costs
Chip and system cooling costs
Power supply rail
Power affects
Noise and reliability
Environmental
Battery life
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• Average Power
• Total Energy
• Energy-Delay-Product (EDP)
• Power-Delay-Product (PDP)
• Power-Square-Delay-Product (PSDP)
• Peak Power
• Transient Power
• Cycle Difference Power
• Peak Power Differential
• Cycle-to-Cycle Power Gradient (Fluctuation)
• and many more ……
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Advanced Topics in VLSI Systems

• To maintain supply voltage levels
• To increase reliability
• To use smaller heat sinks
• To make packaging cheaper
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• To increase battery life time
• To enhance noise margin
• To reduce energy costs
• To reduce use of natural resources
• To increase system reliability
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• To reduce power supply noise
• To reduce cross-talk and electromagnetic noise
• To increase battery efficiency
• To increase reliability
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 Using the lowest possible supply voltage.
 Using the smallest geometry, highest frequency devices, but operating them at lowest possible frequency.
 Using parallelism and pipelining to lower required frequency of operation.
 Power management by disconnecting the power source when the system is idle.
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Advanced Topics in VLSI Systems

 Reduce Supply Voltage (V performance degradation dd
): delay increases;
 Reduce Clock Frequency (f): only power saving no energy
 Reduce Switching Activity (N or E(sw)): no switching no power loss !!! Not in fully under designers control. Switching activity depends on the logic function. Temporal/and spatial correlations difficult to handle.
 Reduce Physical Capacitance: done by reducing device size reduces the current drive of the transistor making the circuit slow
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Advanced Topics in VLSI Systems

How Much is Saved ?? Varying V dd
/ f
Voltage (V dd
) Frequency (f) Power (P d
) Energy (E d
)
V dd f max
P d
E d
V dd
/ 2 f max
* P d
/ 4 E d
/ 4
V dd
/ 2 f max
/ 2 P d
/ 8 E d
/ 4
V dd f max
/ 2 P d
/ 2 E d
* Note : f max
Vs f
Advanced Topics in VLSI Systems
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• Reduce static power:
– Selectively use ratioed circuits.
– Selectively use low V th
– Leakage reduction:
devices.
Stacked devices, body bias, low temperature.
Advanced Topics in VLSI Systems
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