Vol. 35, No. 5
Journal of Semiconductors
May 2014
FDTD based transition time dependent crosstalk analysis for coupled
RLC interconnects
Devendra Kumar Sharma1; Ž , Brajesh Kumar Kaushik2 , and R. K. Sharma3
1 Department
of ECE, Meerut Institute of Engineering and Technology, Meerut, India
of Electronics & Computer Engineering, Indian Institute of Technology, Roorkee, India
3 Department of ECE, National Institute of Technology, Kurukshetra, Haryana, India
2 Department
Abstract: The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line &
coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime
importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs.
The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have
mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects,
two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique
is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps
in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results,
SPICE simulations are run and results are compared. A good agreement of the computed results has been observed
with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the
performance parameters using the proposed method.
Key words: FDTD; transition time; crosstalk noise; delay; coupled interconnects
DOI: 10.1088/1674-4926/35/5/055001
EEACC: 2570
1. Introduction
In current technology, complex geometry of on-chip wires
introduces parasitics which are line parasitics (R; L; C / and
coupling parasitics (M; CC /Œ1 . These parasitics are the primary
source of crosstalk noise and delay, which affect signal integrity. Crosstalk is the coupling of energy from one line to
another line through coupling parasitics. The near and far end
crosstalk noise on the victim line can be determined by taking the sum of the victim line currents. The characteristic of
crosstalk noise is dependent on the termination of the victim
lineŒ2 . A crosstalk induced glitch can cause false switching,
thereby creating logic errors. The crosstalk induced delay occurs when the interconnect lines are switching simultaneously.
The induced delay can cause chip failure more than crosstalk
induced glitch.
The performance parameters are strongly dependent on
per unit wire and inter wire parasitics, signal transition time,
switching patterns, clock skew and driver/load characteristics.
The factors affecting crosstalk noise and delay have been analyzed by the researchers in different aspects. The sources of
noise in interconnect and their effects on the performance of
an integrated circuit have been presented in Ref. [3]. Agarwal et al.Œ4 have reported on a crosstalk noise analysis in coupled lines in order to investigate the effects of physical design
changes. Kaushik et al.Œ5 have analyzed the effect of line resistance and driver width on the crosstalk in on-chip interconnects. The effects of coupling parasitics on delay and clock
skew have been reported in Ref. [6]. The analysis of the effect
of rise time needs much concern, because it is an important
parameter in high speed electronics that affects crosstalk noise
and delay. The signal transition time or rise time or edge rate
is a strong function of interconnect parasiticsŒ7 .
The effect of signal transition time on crosstalk noise, delay and power dissipation has been analyzed in Refs. [8–10].
The effect of coupling parasitics on signal transition time has
been reported in Ref. [11]. Usually authors have analyzed the
effect of transition time on performance parameters by taking it as equal for the inputs to interconnect lines. The effect
of unequal transition time on crosstalk has been reported in
Ref. [11]. The study of unequal transition time is important because it is quite common to have mismatching in the rise time
of input signals propagating through different length wires.
Mostly, the researches have analyzed SPICE results to
show the effect of signal rise time on performance parametersŒ8 11 . Recently, the computational techniques are being
used by researchers for analyzing interconnectsŒ12 14 . There
are various numerical techniques available for the purpose,
however, the FDTD method is popular because it is flexible,
versatile and simple. This method is a direct time domain approach with no transformations. In this paper, FDTD based
analysis is presented to show the impact of input transition time
on crosstalk noise and delay in lossy coupled interconnects.
The analysis is carried out for the cases of equal and unequal
rise time of inputs. The dependency of functional and dynamic
crosstalk on rise time is analyzed using an FDTD approach. To
validate the proposed model, the FDTD results are compared
with those of the SPICE results.
† Corresponding author. Email: d_k_s1970@yahoo.co.in
Received 30 September 2013
© 2014 Chinese Institute of Electronics
055001-1
J. Semicond. 2014, 35(5)
Devendra Kumar Sharma et al.
G
C
C
1 D
t
2
L
R
1 D
C
t
2
1
;
1
;
C
G
2 D
;
t
2
L
R
2 D
C
:
t
2
(5)
The discretized voltage (Vij / and current (Iij / are represented as
Vij D V ..i 1/z; jt / ;
1
j
i
Ii D I
z; jt :
2
Fig. 1. Coupled interconnect lines.
2. FDTD algorithm for coupled interconnects
In this section, the FDTD algorithm is presented to carry
the analysis of transition time effect on the performance parameter. For this, two uniformly distributed R; L; C lines coupled inductively and capacitively are considered, as shown in
Fig. 1. The R; L; C distributed model equivalent to a transmission line is taken into consideration because it is more effective
in the current scenarioŒ15; 16 .
The coupled lines partial differential equations (PDEs) in
space and time are described asŒ17
@V .z; t /
@
C L I.z; t/ C RI.z; t/ D 0;
@z
@t
(1)
@
@
I.z; t / C C V .z; t/ C GV .z; t/ D 0;
@z
@t
(2)
where V .z; t / and I.z; t/ are 2 1 matrices of instantaneous
voltage and current respectively at point z along the line. The
R; L; C; G are 2 2 parasitic matrices per unit length of the
interconnect.
From Eqs. (1) and (2), the voltages and currents are computed using the FDTD technique, wherein the derivatives are
approximated by central difference because it is more accurate than either backward or forward difference. To apply the
FDTD technique, each interconnect line under consideration
is discretized into Nz sections each of length z, called a spatial cell. The total solution time is discretized into Nt segments,
each of duration t , called a temporal cell. In order to ensure
stability in the FDTD solution, the N zC1 voltage points (V1 ,
, VN zC1 / are interlaced one half cell apart with Nz current
points (I1 , , IN z /, both in space and time similar to Ref. [18].
Approximating the derivatives of Eqs. (1) and (2) using the
central difference method and after simplification, the recursive equations of voltage and current are obtained as
(6)
(7)
Assuming that the CMOS driver is replaced by a resistive
driver of value RD to drive each interconnect line in coupled
structure and let source voltage Vs be a 2 1 source matrix.
Now, applying the boundary condition at the source (z D
0), the recursive equation of V1 is obtained as
V1nC1 D A1 A2 V1n C A1 A3 .Vsn C VsnC1 /
A3 D
1
; A1 D .U C A3 /
RD z
1
2A1 A3 RD I1nC1=2 ;
(8)
; A2 D Œ1 2
A3 : (9)
Now consider that each interconnect line is terminated by
a capacitive load of value CL . Applying the boundary condition
at the load point (z D l/, the recursive equation of load voltage
is obtained as
ILn
nC1=2
n
D
V
B
C
B
I
VNnC1
;
(10)
2
N zC1 1
zC1
Nz
2
B1 D .1 CL C 1 2 zt /.1 CL C Uzt /
B2 D 21 t .1 CL C zt /
1
:
1
;
(11)
The voltage and current at discrete points on the line are
numerically computed using recursive equations (3) and (4).
Equations (8)–(11) are the recursive relations at source end and
load end respectively. The stability of the FDTD technique is
determined by the Courant condition, which states that the time
step (t ) must not be greater than the propagation time over
each cellŒ17 . The FDTD algorithm discussed in this section is
implemented using MATLAB.
3. Transition time effects: FDTD results and validation
To analyze the effects of equal and unequal transition time
of inputs on dynamic and functional crosstalk, two distributed
R; L; C lines coupled inductively and capacitively are consid
ered. The length of interconnect line is 4 mm. The interconnect
1
nC1=2
IknC1
VknC1 D 1 2 Vkn C
I
;
2
6
k
6
N
z;
wires under consideration are 2 m wide, 0.68 m thick and
1
k
z
separated
by 0.24 mŒ9 . The interconnect parasitics are ex(3)
tracted using the RaphaelŒ4 extraction tool. The values of par
1
nC3=2
nC1=2
nC1
nC1
V
Ik
D 1 2 Ik
C
VkC1 ; 1 6 k 6 N z: asitics per meter length of the interconnect are C D 190 pF,
z k
(4)
CC D 64 pF, L D 1.722 H and M D 1.4 H. Each input
Here, n; k are integers and 1 , 2 , 1 , 2 represent the 2 2
is a ramp signal with a nominal transition time of 20 ps. Each
matrices whose values are given as
CMOS driver is replaced by an equivalent resistance of 50 .
055001-2
J. Semicond. 2014, 35(5)
Devendra Kumar Sharma et al.
Fig. 2. Delay affected by equal rise time for in-phase switching of
inputs.
The far end of each line is terminated with a capacitive load of
30 fF.
To analyze the effects using the proposed algorithm,
FDTD computations are carried out to determine peak crosstalk
noise and delay. First, the delay is computed for simultaneously
switching interconnects as a function of equal and unequal
rise time because for dynamically switching lines, crosstalk
induced delay is the parameter of interest. Second, the peak
crosstalk noise is computed as a function of rise time at the far
end of the static victim line. For FDTD computations, the recursive equations obtained in Section 2 are solved in a boot
strapping fashion. The solution starts with initially relaxed
lines having zero voltage and current. The voltage and current
are solved using Eqs. (3)–(5) by iterating k for a fixed time and
then iterating time. For analysis, 20 spatial discretizations are
taken for the length under consideration. The time step (t ) is
obtained as 0.66 ps with the line velocity of 3 108 m/s. To
validate the computed results, SPICE simulations are run and
results are compared with those of FDTD results.
Fig. 3. Delay affected by equal rise time for out-of-phase switching of
inputs.
Fig. 4. Effect of unequal rise time on delay for in-phase switching of
inputs.
current flowing in the line increases, which leads to a decrease
in propagation delay.
3.1. Effect of equal rise time
To analyze the effect of equal rise time on dynamic
crosstalk, the rise time of the input signals is varied from 20 to
120 ps in steps of 10 ps. The delay is computed through the
FDTD approach for in-phase and out-of-phase switching of inputs and compared with those of SPICE delay, as shown in
Figs. 2 and 3. The following are the observations:
(1) For in-phase switching of inputs (Fig. 2), the propagation delay increases with decreasing rise time. This is due to
the fact that for in-phase switching, the effective inductance of
the line is increased by mutual inductance. The induced current in the victim line is in the opposite direction to that of the
original current flowing in the victim line. The inductive effect
becomes more prominent with reducing rise time. This leads
to an increase in the induced current that causes the net current
to decrease. So, the propagation delay increases with reducing
rise time.
(2) For out-of-phase switching of inputs as shown in Fig. 3,
the propagation delay decreases with reducing rise time. For
this case, the current induced in the line is in the same direction
as that of the original current of the line. Therefore, the net
3.2. Effect of unequal rise time
The effect of an unequal rise time on the propagation delay for simultaneously switching inputs is analyzed using the
FDTD approach. For analysis, the difference in transition time
of the input signals, i.e. tr D tr1 – tr2 is varied from 0 to 60
ps, by varying tr1 and keeping tr2 fixed at nominal value under consideration. Here, tr1 and tr2 are the rise time of input
ramp signals at the two interconnect lines respectively. To obtain the effect of an unequal rise time, FDTD computations are
carried out. The computed results are compared with those of
the SPICE simulated results, as shown in Figs. 4 and 5.
From Fig. 4, it is observed that for in-phase switching of
inputs, the propagation delay decreases with an increase in the
transition time difference .tr /. This is due to the fact that with
increasing tr , the inductive effect becomes less prominent.
Also, for in-phase switching of inputs, the induced current is
in the opposite direction of the original current. Therefore, the
propagation delay decreases with increasing tr . For opposite
phase switching of inputs (Fig. 5), it is observed that the propagation delay decreases with increasing difference in rise time
055001-3
J. Semicond. 2014, 35(5)
Devendra Kumar Sharma et al.
Rise time
(ps)
20
30
40
50
60
70
80
90
100
110
120
Fig. 5. Effect of unequal rise time on delay for out-of-phase switching
of inputs.
Table 1. % Error in peak crosstalk noise.
FDTD noise
SPICE noise
% Error
(V)
(V)
0.4015
0.4084
1:72
0.3963
0.4018
1:39
0.3870
0.3869
0.0258
0.3789
0.3811
0:581
0.3734
0.3726
0.214
0.3674
0.3674
0.0
0.3621
0.3619
0.0552
0.3579
0.3569
0.279
0.3540
0.3532
0.226
0.3504
0.3494
0.285
0.3473
0.3463
0.291
rise time, an average error of 3.13% in delay is observed.
4. Conclusion
This paper addresses the impact of equal and unequal
transition time on delay for dynamic inputs using the FDTD
method. Furthermore, the FDTD based peak crosstalk noise is
also analyzed at the far end of the static victim line. To investigate the effects using the proposed method, discretizations are
carried out in time and space both. The recursive equations of
voltage and current are derived and computations are carried
out. For validation, the FDTD results are compared with conventional SPICE simulated results. The comparisons show that
the FDTD method captures the propagation delay and crosstalk
noise quite accurately. An average error of less than 3.2% is observed for the proposed method based on FDTD as compared
to SPICE results. The proposed method is useful for computing
the delay and crosstalk noise in on-chip interconnects, even in
the case of mismatched transition time of inputs.
Fig. 6. Effect of rise time on peak crosstalk noise.
.tr /. For an unequal transition time of inputs, the observations will be different at the two lines. However, for an equal
transition time, the observations at the lines will be the same.
3.3. Effect of rise time on functional crosstalk
The effect of rise time on the functional crosstalk noise
is analyzed by taking the victim line as static low. The peak
crosstalk noise is computed using the FDTD technique, as
shown in Fig. 6. For computation, the input-rise time is varied from 20 to 120 ps. From Fig. 6, it is observed that the peak
crosstalk noise increases with the decreasing rise time of the
input. This is due to the fact that at a low value of the rise time,
the inductive effect becomes strong, so, the voltage peak increases.
From the results discussed previously, it is observed that
the proposed method estimates the delay and crosstalk noise in
close agreement with SPICE results. The percentage error for
FDTD computed peak crosstalk noise with respect to SPICE
noise is provided in Table 1. From Table 1, the FDTD method
results in an average error of 0.21% as compared to SPICE.
Furthermore, as compared to SPICE, the proposed FDTD approach results in an average error of 2.02% in delay in case of
an equal rise time of the inputs. However, in case of an unequal
References
[1] Rabaey J M. Digital integrated circuits: a design perspective.
Prentice-Hall, Englewood Cliffs, N.J., 1996
[2] Bakoglu H B. Circuits, interconnections and packaging for VLSI.
Reading, MA: Addison-Wesley, 1990
[3] Elgamel M A, Bayoumi M A. Interconnect noise analysis and
optimization in deep submicron technology. IEEE Circuits Syst
Mag, 2003, Fourth Quarter: 6
[4] Agarwal K, Sylvester D, Blaauw D. Modeling and analysis
of crosstalk noise is coupled RLC interconnects. IEEE Trans
Computer-Aided Design of Integrated Circuits and Systems,
2006, 25(5): 892
[5] Kaushik B K, Sarkar S, Agarwal R P, et al. Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects. Microelectronics International, 2007, 24(3): 42
[6] Roy A, Mohmoud N, Chowdhury M H. Effects of coupling capacitance and inductance on delay uncertainty and clock skew.
Design Automation Conf, 2007: 184
[7] Kang S M, Leblebici Y. CMOS digital integrated circuits—
analysis and design. TMH, New York, 2003
[8] Roy A, Xu J, Chowdhury M H. Analysis of the impacts of signal
slew and skew on the behavior of coupled RLC interconnects for
different switching patterns. IEEE Trans VLSI Syst, 2010, 18(2):
338
[9] Kaushik B K, Sarkar S, Agarwal R P, et al. Crosstalk analysis and
055001-4
J. Semicond. 2014, 35(5)
[10]
[11]
[12]
[13]
Devendra Kumar Sharma et al.
repeater insertion in crosstalk aware coupled VLSI interconnects.
Microelectronics International, 2006, 23(3): 55
Sharma D K, Kaushik B K, Sharma R K. Effect of equal and
mismatched signal transition time on power dissipation in global
VLSI interconnects. International Journal of VLSI Design and
Communication Systems, 2012, 3(4): 111
Sharma D K, Kaushik B K, Sharma R K. Effect of coupling
parasitics and CMOS driver width on transition time for dynamic inputs. International Journal of Electronics, 2013, DOI:
10.1080/00207217.2013.794485
Li X C, Mao J F, Swaminathan M. Transient analysis of CMOSgate driven RLCG interconnects based on FDTD. IEEE Trans
Computer-Aided Design of Integrated Circuits and Systems,
2011, 30(4): 574
Afrooz K, Abdipour A, Tavakoli A, et al. Time domain analysis
of lossy nonuniform transmission line using FDTD technique.
Proc Asia-Pacific Conf Applied Electromagnetics, 2007
[14] Sharma D K, Mittal S, Kaushik B K, et al. Dynamic crosstalk analysis in RLC modeled interconnects using FDTD method. IEEE
Intl Conf Computer and Communication Technology (ICCCT),
2012: 326
[15] Ismail Y I, Friedman E G. Figures of merit to characterize the
importance of on-chip inductance. IEEE Trans VLSI Syst, 1999,
7(4): 442
[16] Deutsch A, Kopcsay G V, Restle P J, et al. When are
transmission-line effects important for on-chip interconnections.
IEEE Trans Microw Theory Tech, 1997, 45(10): 1836
[17] Paul C R. Analysis of multiconductor transmission lines. NY:
Wily Interscience, 1994
[18] Paul C R. Incorporation of terminal constraints in the FDTD analysis of transmission lines. IEEE Trans Electromag Compatibility, 1994, 36(2): 85
055001-5