COURSE OBJECTIVES (UPDATED 03/15)
Library Delay Modeling
[4] Define propagation delay, slew/transition time.
[4] Define timing arcs, unateness.
[3] Show how unateness concept is incorporated for static timing analysis.
[3] Understand the NLDM (nonlinear delay modeling) form for cell delay modeling.
[3] List the required parameters for extracting cell delay from library.
[2] For a given cell description in NLDM form, answer timing-related questions.
[3] Explain state-dependent modeling with an example.
[3] Show extrapolating cell delay if no exact entry in lookup table.
Readings
CH1, CH2, CH3
of timing book
Clock Synthesis
[5] Define clock parameters.
[4] List causes of uncertainty in clock network parameters.
[3] Explain clock network synthesis objectives.
[2] Explain the impact of clock parameters on clock synthesis objectives.
[3] Explain different clock topologies, their pros and cons.
[2] Write setup/hold checks in an example circuit.
[4] Write setup/hold checks in generic case.
[5] Explain the steps in clock tree synthesis.
[4] Explain high-level idea of MMM algorithm for clock tree topology generation.
[5] Modeling a given interconnect as distributed RC.
[5] Compute delay of an interconnect tree using the Elmore model.
[3] Explain all the steps in the zero-skew algorithm (Tsay 1993).
[2] Solve example on tapping point computation in the Tsay algorithm.
[3] Explain need for applying the snaking technique.
[3] Explain all the steps in the DME algorithm (Kahng 1993).
[3] Explain the benefits of defining merging segments and tiled rectangular region.
Readings
Tsay1993
Kahng 1992
Slides (W2, W3)
Retiming and Clock Skew Scheduling
[3] Write clock skew scheduling formulation for long and short paths in the circuit.
[3] Write setup/hold checks for all types of design paths (IN/FF, FF/FF, FF/OUT)
[4] Combine a range of clock skews to be passed to clock synthesis stage.
[3] Understand the basic retiming equation.
[2] Apply forward and backward retiming at a node for the general case.
[2] Apply the same for special cases (different FF types, set/reset conditions).
[1] Formulate an instance of retiming problem as ILP for min-delay and min-area.
[2] Apply steps yielding to min-delay formulation (e.g. computing weight and delay
matrixes).
Readings
Slides (W4, W5)
Crosstalk
[5] Define different types of capacitances of a route in a multi-layer design.
[4] Explain the impact of technology scaling on different capacitance types.
[4] Explain different types of crosstalk-induced noise.
[2] Explain all factors impacting crosstalk-induced noise.
[3] Modeling parallel and coupled RC lines with equivalent capacitance.
[2] Compute equivalent coupling capacitance using Miller factor.
Readings
Slides (W6, W7,
W8), ICCAD2008
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ECE902 Digital System Fundamentals
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Define switching windows for static timing analysis.
Understand chicken-egg problem in crosstalk analysis for switching windows.
Explain the need for pruning in crosstalk analysis.
Understand the source of complexity in crosstalk analysis.
Explain different types of pruning.
Explain an effective order for applying different types of pruning.
Understand components in a typical design flow for handling crosstalk.
List a number of crosstalk prevention mechanisms.
List a number of techniques for fixing a detected crosstalk-induced noise.
Understand the correlation between functional and delay noise.
Ability to list possible pros or cons of using a crosstalk noise repair mechanism.
Understand maximum-weight aggressor (MWA) selection problem.
Write MWA as an Integer Linear Program for a given problem instance.
Incorporate provided (new) logic exclusivity constraint in the ILP.
Spring 2010
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ECE902 Digital System Fundamentals
Spring 2010
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