High Speed SRAM
128K-Word By 8 Bit
Rev. No.
1.2
Copyright
History
Add green code in part no.
CS18HS10245
Issue Date
Jul.22,2005
Remark
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P1
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
DESCRIPTION
The CS18HS10245 series products are 131,072-words by 8-bits static RAM fabricated with
advanced 8" wafer submicron CMOS technology. Using unique CMOS peripheral circuits and
special poly-load 4-transistor memory cells, the CS18HS10245 series products exhibit very
high-speed performance with single +5-volt power supply while requiring very low power and
no clock or refreshing to operate. The CS18HS10245 is packed in a standard 32L SOJ-300mil,
32L SOP-330mil, 32L STSOP-8x13.4mm, 32L TSOP(I)-8x20mm and 32L PDIP-300mil.
FEATURES
1. 131,072-word x 8-bit organization
2. Operation voltage: 4.5~5.5V
3. Fully static operation - no clock or refreshing required
4. LVTTL-compatible inputs and outputs
5. Common I/O capability
6. Low power consumption
Active: 180/160/140 mA（Max.）
Standby: 5 mA
7. Very high speed access: 10/12/15 ns（Max.）
8. Output Enable（ OE ）available for very fast access
Product Family
Part No.
Operating
Vcc.
Temp
Range
Speed (ns)
Supply Current
mA (Max.)
CS18HS10245CC
32 SOP-330mil
CS18HS10245SC
CS18HS10245DC
CS18HS10245EC
CS18HS10245TC
Copyright
Package Type
0~70oC
4.5~5.5V
10
180
32 SOJ-300mil
12
160
32STSOP-8x13.4mm
15
140
32TSOP-8x20mm
32PDIP-300mil
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P2
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
PIN CONFIGURATIONS
NC
1
32
VDD
A16
2
31
A 15
A14
3
30
CS2
A 12
4
29
WE
A7
5
28
A 13
A6
6
27
A8
A5
7
26
A9
25
A 11
A4
8
A3
9
24
OE
A2
10
23
A 10
A1
11
22
CS1
A0
12
21
I/O 8
I/O1
13
20
I/O 7
I/O 2
14
19
I/O 6
I/O 3
15
18
I/O 5
Vss
16
17
I/O 4
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
32
16
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
32L TSOP(I)-8x20mm
32L STSOP (I)-8x13.4mm
32L PDIP-300mi
32L SOP - 330 mil
32L SOJ – 300 mil
BLOCK DIAGRAM
A8
A9
A12
A14
A16
A3
A4
A5
A6
A7
I/O 1〜I/O 8
Row
Address
Buffer
8
•
CS1
WE
•
Output
Data
Control
•
•
•
1024
Row
Decoders
Input
Data
Control
8
CS2
10
Memory Cell
Array
1024 Rows
1024 Columns
•
8
Sense/Switch
1024
Column
Decoders
7
Column Address
Buffer
A15 A13 A11 A10 A2 A1 A0
OE
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P3
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
PIN DESCRIPTIONS
Symbols
Functions
A0~A16
Address Inputs
I/O1〜I/O8
Data Inputs / Outputs
CS 1, CS2
Chip Select Input
WE
OE
Write Enable Input
Output Enable Input
VDD
Power Supply
VSS
Ground
TRUTH TABLE
CS
CS2
OE
WE
Mode
I/O1〜I/O8
VDD Current
H
X
X
X
Not Selected
High Z
Isb, Isb1
X
L
X
X
Not Selected
High Z
Isb, Isb1
L
H
H
H
Output Disable
High Z
IDD
L
H
L
H
Read
Data Out
IDD
L
H
X
L
Write
Data In
IDD
ABSOLUTE MAXIMUM RATINGS
Parameters
Supply Voltage to Vss
Input/Output to Vss
Rating
Unit
-0.5 to +7.0
V
-0.5 to VDD +0.5
V
1.0
W
-65 to +150
℃
0 to +70
℃
Allowable Power Dissipation
Storage Temperature
Operating Temperature
OPERATING RANGE
Range
Commercial
Copyright
Ambient Temperature
o
0~70 C
Vcc
5V±10%
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P4
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
DC ELECTRICAL CHARACTERISTICS
(VDD = 5V, Vss = 0V, Ta = 0 to 70℃)
Parameters
Symbols
Test Conditions
Min.
Typ.
Max
Unit
Input Low Voltage
VIL
-
-0.5
-
+0.8
V
Input High Voltage
VIH
-
+2.7
-
VDD+0.5
V
Input Leakage Current
ILI
VIN = VSS to VDD
-10
-
+10
μA
VI/O = VSS to VDD, CS = VIH
-10
-
+10
μA
ILO
Output Low Voltage
VOL
IOL = +8.0mA
-
-
0.4
V
Output High Voltage
VOH
IOH = -4.0mA
2.4
-
-
V
-
-
180
mA
-
-
160
mA
-
-
140
mA
-
-
10
mA
-
-
5
mA
Output Leakage Current
Operating Power
Supply Current
IDD
Standby Power Supply
Current
ISB
ISB1
or OE = VIH or WE = VIL
CS = VIL, I/O = 0 mA
10
Cycle = MIN
12
Duty = 100%
15
CS = VIH, Cycle = MIN
Duty = 100%
CS ≧ VDD -0.2V
Note: Typical characteristics are measured at VDD = 5V, Ta = 25℃
AC Characteristics:
Capacitances
(VDD = 5V, Ta = 25℃, f = 1 MHz)
Parameters
Symbols
Conditions
Max.
Unit
Input Capacitance
CIN
VIN = 0V
6
pF
Input/Output Capacitance
CI/O
VOUT = 0V
8
pF
Note: These parameters are sampled but not 100% tested.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P5
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
AC Test Conditions
Parameters
Conditions
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3 ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 30 pF, IOH/IOL = -4 mA / 8 mA
AC Test Loads and Waveforms
R1 = 480 ohm
R1 = 480 ohm
5V
OUTPUT
5V
•
•
30 pF
Including
Jig and
Scope
R2 = 255 ohm
OUTPUT
•
•
5 pF
Including
Jig and
Scope
R2 = 255 ohm
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW)
3.0V
90%
0V
Copyright
10%
3 ns → ←
90%
10%
→ ← 3 ns
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P6
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
AC Performances:
(VDD = 5V, VSS = 0V, Ta = 0 to 70℃)
(1) Read Cycle
Parameters
Symbols CS18HS10245-10 CS18HS10245-12 CS18HS10245-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
TRC
10
-
12
-
15
-
ns
Address Access Time
TAA
-
10
-
12
-
15
ns
Chip Select Access Time
TACS
-
10
-
12
-
15
ns
Output Enable to Output Valid
TAOE
-
6
-
7
-
8
ns
Chip Selection to Output in Low Z
TCLZ*
3
-
3
-
3
-
ns
Output Enable to Output in Low Z
TOLZ*
0
-
0
-
0
-
ns
Chip Deselection to Output in High Z
TCHZ*
-
5
-
6
-
7
ns
Output Disable to Output in High Z
TOHZ*
-
5
-
6
-
7
ns
Output Hold from Address Change
TOH
3
-
3
-
3
-
ns
*These parameters are sampled but not 100% tested
(2) Write Cycle
Parameters
Symbols CS18HS10245-10 CS18HS10245-12 CS18HS10245-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
TWC
10
-
12
-
15
-
ns
Chip Selection to End of Write
TCW
8
-
10
-
12
-
ns
Address Valid to End of Write
TAW
8
-
10
-
12
-
ns
Address Setup Time
TAS
0
-
0
-
0
-
ns
Write Pulse Width
TWP
8
-
10
-
12
-
ns
Write Recovery Time
TWR
0
-
0
-
0
-
ns
Data Valid to End of Write
TDW
6
-
8
-
10
-
ns
Data Hold from End of Write
TDH
0
-
0
-
0
-
ns
Write to Output in High Z
TWHZ*
-
5
-
6
-
7
ns
Output Disable to Output in High Z
TOHZ*
-
5
-
6
-
7
ns
TOW
0
-
0
-
0
-
ns
Output Active from End of Write
These parameters are sampled but not 100% tested
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P7
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
Timing Waveforms
Read Cycle 1
(Address Controlled)
TRC
Address
TOH TAA
TOH
DOUT
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
TACS
DOUT
TCHZ
TCLZ
Read Cycle 3
(Output Enable Controlled)
TRC
Address
TAA
OE
TAOE
CS1
Copyright
DOUT
TOH
TOLZ
T
TACS
2004 March Chiplus Semiconductor
Corp. All rights reserved.
T OHZ .
TCLZ
CHZ
Rev. 1.2
P8
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
Write Cycle 1
（ OE Clock）
TWC
Address
TWR
OE
TCW
CS1
TAW
WE
TAS
TOHZ
DOUT
TWP
(1,4)
TDW
TDH
DIN
Write Cycle 2
( OE = VIL Fixed)
TWC
Address
CS1
WE
TWR
TCW
TAW
TAS
TWP
TOH
TWHZ
DOUT
(1,4)
TDW
TOW
(2)
(3)
TDH
DIN
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P9
High Speed SRAM
128K-Word By 8 Bit
CS18HS10245
Notes:
1.
During this period, I/O pins are in the output state, so input signals of opposite phase to
the outputs should not be applied.
2.
The data output from DOUT are the same as the data written to DIN during the write
cycle.
3.
DOUT provides the read data for the next address.
4.
Transition is measured ±500mV from steady state with CL = 5pF.
This parameter is
guaranteed but not 100% tested.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P 10
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
PACKAGE DIMENSIONS
-
32 SOP - 330 mil
b
WITH PLATING
c c1
b1
BASE METAL
SECTION A-A
SYMBOL
b1
c
c1
0.15
_
0.15
_
0.584 1.194
2.680
0.35
_
20.320 11.176 13.792 1.118
Nom. 2.821 0.229
0.35
_
20.447 11.303 14.097 1.270
0.834 1.397
Max. 2.997 0.356
2.820
0.50
0.46
0.32
0.28
20.574 11.430 14.402 1.422 1.084
0.004 0.1000 0.014
_
0.014
_
0.006
_
0.006
_
0.800 0.440
Nom. 0.111 0.009 0.1055
Max. 0.118 0.014 0.1110 0.020
0.018 0.012
Min.
inch
-
y
b
2.540
A1
A
Min.
mm
e
A2
2.645 0.102
UNIT
0.104
D
E
0.805 0.445
0.011 0.810 0.450
E1
L
L1
_
_
0.543 0.044
0.023 0.047
0.1
_
0.555 0.050
0.033 0.055
_
0.567
0.043
0.056
1.600
0.063 0.004
0°
_
10°
0°
_
10°
32 SOJ – 300 mil
SYMBOL
mm
inch
Copyright
b
c
2.41
0.41
0.18
20.83
2.54
0.46
0.20
20.96
A
A1
A2
Min.
3.10
Nom.
3.35
2.08
_
Max.
3.61
_
2.67
0.51
0.33
21.08
7.75
Min.
0.122
0.095
0.016
0.007
0.820
0.295
Nom. 0.132
0.082
_
0.100
0.018
0.008
0.825
Max. 0.142
_
0.105
0.020
0.013
0.830
UNIT
D
E
8.53
bsc
0.336
bsc
E1
7.49
7.62
0.300
0.305
E2
e
6.78
bsc
1.27
bsc
0°
_
10°
0.267 0.050
bsc
bsc
0°
_
10°
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P 11
High Speed SRAM
CS18HS10245
128K-Word By 8 Bit
-
32STSOP – 8x13.4mm
12°(2x)
12°(2x)
e
HD
cL
32
16
17
b
E
1
Seating Plane
y
12°(2X)
"A"
D
A
A2
GAUGE PLANE
0
A1
17
16
SEATING PLANE
0.254
A
A
L
12°(2X)
L1
"A" DATAIL VIEW
b
WITH PLATING
c c1
1
32
b1
BASE METAL
SECTION A-A
SYMBOL
A
A1
A2
b
b1
c
c1
D
E
e
HD
L
L1
y
1.00
0.05
0.95
0.17
0.17
7.90
0.40
13.20
0.40
0.70
_
0.10
1.00
0.22
0.20
0.10
_
11.70
Nom. 1.10
0.10
_
11.80
8.00
0.50
13.40
0.50
0.80
_
1.20
8.10
0.60
13.60
0.70
0.90
UNIT
Min.
mm
0.15
1.05
0.27
0.23
0.21
0.16
11.90
Min. 0.0393 0.002
0.037
0.007
0.007
0.520 0.0157 0.0275
0.1
_
0.009
0.008
0.004
_
0.311 0.016
0.039
0.004
_
0.461
Nom. 0.0433 0.004
0.465
0.315 0.020
0.528 0.0197 0.0315
_
Max. 0.0473 0.006
0.041
0.011 0.009
0.008 0.006
0.469
0.319
0.536 0.0277 0.0355 0.004
Max.
inch
8°
0°
_
8°
12°(2X)
32TSOP – 8x20mm
12°(2X)
-
0.024
0°
_
e
HD
16
17
b
32
E
CL
1
Seating Plane
y
12°(2x)
A
A2
"A"
D
GAUGE PLANE
0
A1
SEATING PLANE
0.254
A
A
12°(2x)
L
L1
"A" DETAIL VIEW
17
16
b
WITH PLATING
c c1
1
b1
BASE METAL
32
SECTION A-A
SYMBOL
A
A1
A2
b
b1
c
c1
D
E
e
HD
L
L1
y
1.00
0.05
0.95
0.17
0.17
7.90
0.40
19.80
0.40
0.70
_
0.10
1.00
0.22
0.20
0.10
_
18.30
Nom. 1.10
0.10
_
18.40
8.00
0.50
20.00
0.50
0.80
_
1.20
0.15
1.05
0.27
0.23
0.21
0.16
18.50
8.10
0.60
20.20
0.70
0.90
0.1
_
UNIT
Min.
mm
Max.
Nom. 0.0433 0.004 0.039
0.007 0.007 0.004
_
0.009 0.008
Max. 0.0473 0.006
0.011 0.009
Min. 0.0393 0.002 0.037
inch
Copyright
0.041
0.004 0.720
_
0.724
0.008 0.006
0.311 0.016 0.779 0.0157 0.0275
0.315 0.020
0.728 0.319 0.024
0.787 0.0197 0.0315
_
0.795 0.0277 0.0355 0.004
0°
_
8°
0°
_
8°
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P 12
High Speed SRAM
128K-Word By 8 Bit
-
CS18HS10245
32PDIP – 300mil
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P 13