Reduction of Voltage Stress in the Full Bridge
BIBRED by Duty Ratio and Phase Shift Control
R.W. Erickson
M. A. Johnston
Department of Electrical and Computer Engineering
University of Colorado at Boulder
Boulder, Colorado 80309-0425
Storage Technology Corporation
2270 South 88th Street
Louisville, Colorado 80028-0279
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Abstract
A new control scheme is presented
which provides simultaneous control of the
output voltage and the energy storage capacitor
voltage in the full-bridge Boost Integrated with
Buck RectifiedEnergy storage/Dc-dc converter
(full-bridge BIBRED). The new control scheme
solves the problem of wide voltage excursions
for the energy storage capacitor voltage under
variable load conditions. A low frequency, large
signal AC equivalent circuit is presented. The
steady state governing equations are given.
Mode boundaries for correct operation as a high
quality rectifier are established.
The control
circuit used to implement the new control
scheme is discussed.
Experimental results
validate the concept of the new control scheme.
1.
INTRODUCTION
A . Review of the BIBRED Family of Converters
The BIBRED (Boost Integrated with Buck
Rectifierfinergy storage/Dc-dc converter) family of
converters are derived [l] by integrating the high power
factor input of the boost converter operating in the
discontinuous conduction mode, the wide bandwidth output
control of a buck type DC-DC converter, and an energy
storage capacitor which is independent of the load. The
resulting topologies eliminate the transistor present in the
boost converter by integrating it with the transistor(s) in the
buck type converter. Low harmonic input currents are
achieved without active regulation by virtue of the input
inductors of the boost input stage operating in the
discontinuous conduction mode [2]. Energy storage is
performed by a capacitor which is separated from the load by
a switching network. Thus, energy storage takes place more
efficiently at a high voltage, and the hold-up time of the
converter is large per unit volume of capacitance. It has
been demonstrated by [l] that the output voltage of this
family of converters can be regulated with wide bandwidth
by duty ratio control or switching frequency control, letting
the energy storage capacitor voltage run unregulated.
flows into both legs of the full bridge, thus distributing the
current stresses more evenly. Both input inductors are
connected to the same source. As a result of the phase
difference in the two halves of the bridge circuit, the ripple
currents in the input inductors partially cancel each other,
reducing the ripple current in the AC line.
The inductors L l a and L i b in Fig. 1 are the
discontinuous conduction mode input inductors. Together
with 4 2 and 44, they form the effective boost input stage of
the converter. The energy storage function of the converter
is performed by capacitor C1. MOSFETs Q1 through 4 4
plus D2 through D5 are the full bridge devices, which, with
the isolation transformer and the center tapped output, form
the full bridge converter.
Fig. 2 shows typical switching waveforms for the dualfed full bridge BIBRED. This is one of the many possible
combinations of switching sequences which are possible
with this converter. These switching waveforms are used in
deriving the large-signal equations for the converter, and they
provide insight into its operation.
C . Motivation For the New Control Scheme
By integrating the boost and buck converters together,
the transistor of the boost converter and its associated drive
circuitry are eliminated. The price for simplifying the drive
requirements is that the energy storage capacitor voltage is
left unregulated. It varies over a wide range of voltages for
variations in the input voltage or the load. For a practical
design in which either of these parameters vary, the resulting
.
B . The Dual-Fed Full Bridge BIBRED
load
Fig. 1 shows a schematic diagram of the dual-fed full
bridge BIBRED. This topology differs from the single-fed
full bridge BIBRED in that the input current is split, and
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v2
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Fig. 1. The dual-fed full bridge BIBRED
849
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the converter. The modeling approach is based on the "lossfree resistor" (LFR)modeling technique. The AC equivalent
circuit contains an LFR to model the high quality
rectification of the converter, and a DC transformer to model
the DC to DC conversion process. Steady state analysis is
performed following the procedure developed in [l]. A
closed form goveming equation for the converter is found by
performing a curve fit. Mode boundaries for correct
operation of this converter as a high quality rectifier are
established. The mode boundaries determine the minimum
and maximum duty ratio, and the corresponding load range.
In section 3, the control circuit used to implement the
new control scheme is discussed. A controller using two
conventional PWM control chips is presented. Phase
control is achieved by synchronizing one control chip to the
other, and varying the delay between the two. Duty ratio
control is accomplished using standard PWh4 techniques.
In section 4, experimental results are presented. The
results validate the new control scheme and the equations
which are derived.
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2.
STEADY-STATE ANALYSIS
A . Definition of Phase
Fig. 2. Typical switching waveforms for the dual-fed full bridge
BIBRED with the new control scheme.
converter will have expensive, high voltage components.
In this paper, it is demonstrated that the output voltage
and the energy storage capacitor voltage of the full bridge
BIBRED can be independently controlled by simultaneous
phase shift control and duty ratio control. Phase shifting the
conduction intervals of the legs of the full bridge, as shown
in Fig. 3, is used to control the output voltage. The duty
ratio, which controls the on time of the effective boost
input, is used to control the energy storage capacitor
voltage. Interaction between the two control loops is
minimized by placing their crossover frequencies several
orders of magnitude apart.
The original properties of the full bridge BIBRED are
preserved with this new control scheme. The phase control
loop which regulates the output voltage has wide bandwidth.
The input current has low harmonic content. Most
significantly,the additional control loop which regulates the
energy storage capacitor voltage allows the converter to be
designed with reasonable voltage stresses over a range of
output loads and input voltages.
The full bridge BIBRED presented in this work uses
two simultaneous means of control. The duty ratio, or the
fraction of a switching period in which the lower switches of
the bridge are on, is used to regulate the energy storage
capacitor voltage. The output voltage is controlled by
varying the overlap, or phase, of the two legs of the full
bridge.
Typically phase is defined in degrees, with 180 degrees
corresponding to zero percent overlap. For the sake of
simplicity, the phase was defined as shown in Fig. 3. This
figure shows the gate voltages for the lower MOSFETs of
the two legs of the full bridge shown in Fig. 1 (Vgate for
Q2 and Vgate for Q4), and the resulting voltage vp that is
impressed across the primary of the isolation transformer.
The energy transmitted to the load is a function of the
duty cycle and the fractional overlapping of the legs of the
full bridge. It can be seen by inspecting the voltage
waveform across the primary of the transformer, VP in Fig.
3, that overlapping the legs of the full bridge has the effect
of reducing the energy transmitted to the load by the
D . Outline of Discussion
This paper presents a new control scheme which
provides simultaneous control of the output voltage and the
energy storage capacitor voltage in the dual-fed full bridge
BIBRED. The new control scheme utilizes simultaneous
duty ratio and phase control.
In section 2, a definition for phase is given which
simplifies the equations describing power flow in the
converter. A low frequency, large signal AC equivalent
circuit is presented which models the essential functions of
850
Fig. 3. Definition of phase shift for the full bridge BIBRED
fractional overlap. Thus, the quantity
$=
tnon overlapped
where Re = k
D ~ T ~
DTS
is useful in equations or equivalent circuit diagrams that
describe power flow in the converter. The simplicity of
defining the phase in this manner is that conversions
between phase in degrees and phase in fraction of nonoverlapped conduction intervals are not necessary. The
resulting equations have fewer terms and are simpler to
interpret. Note that the non-overlapping time interval is
defined as in Fig. 3 to be the portion of one gate pulse
which does not overlap with the other pulse, and not the
sum of the two non-overlapping intervals. The quantity
2D$Ts represents the total time of non-overlapping gate
pulses.
As they are defined in Fig. 3, the duty ratio and the
phase can both vary from zero to one. Additionally, it is
seen by examining Fig. 3 that the interval lengths DTs and
D$Ts cannot total more than one switching period Ts.
Thus, the expression
describes an additional constraint for the duty ratio D and the
phase $. Any increase in the duty ratio beyond the limits
placed by (2) will result in a reduction in the phase, as the
tail end of the gate pulse for Q4 overlaps the leading edge of
the gate pulse for Q2. Equation (2) can be simplified to
produce the expression
D(l
+$)<
(9)
(3)
1
Since the maximum "phase" is one, the constraint on !he
duty ratio in (3) only applies when the duty ratio is greater
than one-half.
B . A Low Frequency, Large Signal Model
The circuit diagram in Fig. 1 gives the names of the
circuit components and defines the relevant voltages and
currents for the equations that follow. Inspection of the
circuit in Fig. 1, inspection of the switching waveforms in
Fig. 2, and averaging over one switching cycle are used to
derive the state space averaged large signal equations given
in (4-8).
( i l ) = l ( v . + -3v1v2
- vg
Re
1
A low frequency, large signal AC equivalent circuit that
corresponds to (4-8) is shown in Fig. 4. This equivalent
circuit provides some intuition into the roles of the various
components in the converter, and can be used to derive the
equations for the control-to-output transfer functions. The
combination of the resistor and the dependent power source
at the input to the AC equivalent circuit is known as a LossFree Resistor (LFR) [3]. The power apparently consumed
by the effective resistance Re is delivered to the rest of the
circuit by the dependent power source. Thus, the input to
this AC equivalent circuit is loss-free, as is the input to the
ideal BIBRED. The input current to the AC equivalent
circuit, ig, is equal to the sum of the current through Re
plus the current through the dependent power source. The
current through Re is simply vg/Re. The current through
the dependent power source is equal to the power vg2/Re,
divided by the voltage drop across the power source, V I - vg.
Thus, the input current is equal to
which agrees with (4).
The AC equivalent circuit in Fig. 4 provides some
intuition into operation of the converter, because it models
all the essential operations that the converter performs. At
the input to the equivalent circuit, the rectified line voltage
and the Loss Free Resistor model the low harmonic
rectification of the converter. Note that the input current is
a function of the duty ratio D and not the phase $, since the
effective resistance Re is a function of the duty ratio only,
and the energy storage capacitor voltage is approximately
constant over a line half-cycle for a good design.
The next part of the equivalent circuit models the energy
storage function of the converter. The output of the
dependent power source is connected to the energy storage
capacitor (which retains its actual value) and to the DC
transformer. The twice-line-frequency voltage fluctuations
in the energy storage capacitor can be determined based on
the difference between the dependent power source current,
which varies over the line half-cycle, and the reflected output
current, which is constant.
(4)
Fig. 4. Low frequency, large signal AC equivalent circuit for the
dual-fed full bridge BIBRED.
a5;1
The DC transformer models the dependency of the
power transfer in the converter upon the duty ratio, the
phase, and the turns ratio of the actual isolation transformer.
The factor of two in the turns ratio of the DC transformer
accounts for the symmetry of the two conduction intervals
of length DqTs per switching period, as shown in Fig. 2.
The output filter components and the load resistance all
retain their actual values, which provide some intuition into
the dynamic response of the output of the converter at
frequencies much less than the switching frequency. The
high frequency switching ripple in the output filter
components is not modeled, since these were specifically
neglected in deriving the low frequency, large signal AC
equivalent model.
C . Steady State Solution
The steady state solution for the converter is found
using the procedure developed in [l]. The details of the
derivation are not given here, but can be found in [4].
Steady state analysis is performed by averaging (5-7) over a
line half-cycle. A non-separable transcendental equation is
formed, and it is integrated over a line half-cycle, for the case
of a sinusoidal input voltage. A curve fit is then performed
on the resulting equation, and a closed form approximate
expression for the energy storage capacitor voltage V I is
found. Substituting in the relationship between the energy
storage capacitor voltage and the output voltage yields an
expression for the output voltage as a function of the peak
input voltage. The result is
t 13)
The minimum allowable duty ratio can be calculated by
realizing that the output control loop will saturate when the
phase $ equals one. The result is
One implication of this lower boundary on the duty ratio is
that there must be a minimum load at all times for proper
regulation to occur. A minimum duty ratio at the input
means there is a minimum input current and a minimum
input power. If a minimum load is not present, then an
energy imbalance between the input and the output occurs,
resulting in the energy storage capacitor voltage increasing.
The expression for the minimum load is
= 90 nV2
Poutfun load
DO2v1
D . Mode Boundaries
Correct operation of this converter as a high quality
rectifier requires that the input inductors operate in
discontinuous conduction mode. This limitation results in
an upper boundary for the duty ratio.
(15)
Equation (15) assumes that V2 and V I are regulated, and
that there are no variations in the peak input line voltage.
This equation is useful because it relates the load dynamic
range to the nominal values of various design parameters.
Greater dynamic range will be achieved for a smaller fullload phase and larger full-load duty ratio, since this leaves
the controller greater freedom to compensate for a load
change.
3.
0 =-2 9 v1 -V2
n
2DoV1
where I$O and Do are the full load values of the
control variables $ and D, respectively.
where AO= .426 and
The constant AO results from the curve fit that was
performed in solving the transcendental equation. This
solution is valid for a rectified sinusoidal input voltage,
whose frequency is much smaller than the switching
frequency.
The steady state relationship between the output
voltage, the energy storage capacitor voltage, and the control
inputs D and $, is found using (6). The result is
[
- ,$ - nVz
Poutmin load
CONTROL
Previous work [l] demonstrated that the full bridge
BIBRED could be controlled by a simple duty ratio scheme.
This control scheme provides both high bandwidth output
regulation and low harmonic input currents. The
disadvantage of having only one control variable is that the
energy storage capacitor voltage (VIin Fig. 1) can vary over
an unacceptably wide voltage range for variations in load and
input voltage. It is shown in this paper that by adding a
second variable to the control scheme, the energy storage
capacitor voltage can be regulated in addition to the output
voltage, allowing the design of a converter that will operate
over a wide range of loads and input voltages, with
reasonable peak voltage stresses.
The output of a full bridge type converter can be
controlled by varying the phase, or overlap, of the
conduction intervals of the two legs of the full bridge. This
feature of a full bridge converter has been demonstrated
before by [5]. The crossover frequency for this control loop
is made as large as possible, to insure wide bandwidth
regulation of the load voltage.
At the input to the equivalent AC circuit in Fig. 4,the
852
effective resistance Re is a function of duty ratio only, and
not phase. Thus, varying the duty ratio varies the input
current. With the output voltage held constant by the wide
bandwidth output control loop, the load draws constant
power. Since the input current and hence the input power is
a function of the duty ratio and the energy storage capacitor
voltage, varying the duty ratio must result in a change in the
capacitor voltage, since the output draws constant power.
Thus, duty ratio control may be used to regulate the energy
storage capacitor voltage.
One may also qualitatively explain the role that duty
ratio control plays by considering the effective boost input
stage that all members of the BIBRED family of converters
are derived from. The inductors L1a and L l b in Fig. 1 are
the discontinuous conduction mode input inductors.
Together with 4 2 and Q4, they form the effective boost
input stage of the converter. Since the output power is held
constant by the wide bandwidth phase control loop, varying
the duty ratio controls the boost ratio of the effective boost
input.
It has been demonstrated before by [2] that the input
inductors of a boost converter operating in the discontinuous
conduction mode naturally emulate a resistive input with the
duty ratio held constant. This feature allows the crossover
frequency of the duty ratio control loop to be placed at a
frequency much lower than twice the line frequency. A low
crossover frequency is desired for this control loop, since
that prevents increased current harmonics from being injected
into the line, especially at twice the line frequency.
Although the output voltage is a function of both the
duty ratio and the phase, the two control loops can normally
be treated as being decoupled since their crossover
frequencies differ by several orders of magnitude.
A block diagram for the control circuit used in this
experiment is presented in Fig. 5. This control circuit does
have some disadvantages. In order to ensure that the slave
PWM chip truly acts as a slave and does not precede the
master, the sawtooth waveform for the slave chip is operated
at a 10% lower frequency [6]. Since both PWM chips use
the same error signal to produce the duty ratio of their
outputs, the slave with its longer switching period also has
a longer pulse width. Thus, the full bridge is not operated
truly symmetrically, and the blocking capacitor in series
with the primary of the isolation transformer (C3 in Fig. 1)
has some DC voltage across it. Thus the "optional"
blocking capacitor C3 is not optional with this control
scheme. Additionally, because there is a DC voltage across
the blocking capacitor, only one of the two output rectifiers
(D6 and D7 in Fig. 1) conducts during the intervals when
they would normally both conduct the freewheeling output
inductor current. The consequence of this is a larger voltage
spike across the conducting rectifier when it is turned off.
4.
EXPERIMENTAL RESULTS
Using the design procedure developed in [4], an
experimental 50 watt converter was designed. While the
dual-fed full bridge BIBRED is probably more appropriate
for power levels greater than 500 watts, a 50 watt converter
was built to demonstrate the validity of the new control
scheme. The converter has a 42 [VI DC output voltage, and
a 60 [Hz], 110 [Vlrms sinusoidal input. The switching
frequency is 50 k[Hz], where the switching period is as
shown in Fig. 2. The energy storage capacitor voltage is
regulated at 300 [VI. This voltage was selected because it
offers a good compromise between producing low harmonic
inputs, having a long hold-up time, and allowing
components with reasonable voltage ratings to be used. The
measured component values are given in Table I.
Table I1 lists the design operating parameters and the
operating parameters that were measured in the experiment.
Most of the values were very close to the design values.
The experimental duty ratio was larger than the designed
TABLE I
MEASUREDCOMPONENTVALUESFORTHEEXPERIMENTAL
CONVERTER
Parameter
Transformer Tums Ratio
Input Inductors L l a = L l b
Energy Storage Capacitor, C1
Output Filter Capacitor, C2
Output Filter Inductor, L2
Value
3.05
1.43 m[H]
330 W I
2.0 P[FI
1.41 m[H]
TABLE II
MEASURED OPEXATING
S-P
K l R THE
EXPERIMENTALCONVERTER
Parameter
Switching Frequency, fs
Input Voltage, vp
Line Frequency, fline
Output Voltage, V2
Energy Storage Capacitor Voltage,
V1
Output Power (full load), Po
Output Power (minimum load),
Pmin
Duty Ratio (full load), Do
Phase (full load), q0
Fig. 5. Block diagram for the variable phase, variable duty ratio
controller
853
Value
Design
value
50.3 k[Hz] 50 k w z ]
110
110
[Vlrms
[VIrms
60 [Hzl
60 [Hzl
42.0 [VI
42 [VI
299 [VI
300 [VI
[wl 50 [wl
10.2 [wl 13.5 [W]
50.0
.45
.48
.4
.52
master
slave
Fig. 6. Gate voltage waveforms for the lower MOSFETs
(Q2 and 4 4 in Fig. 1) of the full bridge.
duty ratio, since the design equations do not take into
consideration the losses in the circuit. Since the full-load
duty ratio was larger than the designed value, the output load
range was also larger than anticipated, as predicted by (15).
The measured load range was 5 to 1, as compared to the 3.7
to 1 range that the converter was designed for. By
substituting the measured operating parameters and the
actual turns ratio of the transformer into (15), a load range of
4.4 to 1 is calculated. Part of the error between the
calculated load range and the measured load range can be
attributed to the accuracy of the measurements of the duty
ratio and the phase. Figure 6 shows oscilloscope traces of
the gate drive waveforms, showing the duty ratio and the
phase.
The line voltage and line current waveforms were
measured, and are presented in Fig. 7. The line voltage and
line current waveforms demonstrate that the converter draws
high quality input current waveforms.
5.
CONCLUSIONS
This paper proposes a new control scheme which
provides simultaneous control of the output voltage and the
energy storage capacitor voltage in the dual-fed full bridge
f-1
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BIBRED. The new control scheme utilizes simultaneous
duty ratio and phase control. A new definition for phase is
given which simplifies the equations which describe power
flow in the converter. The new definition eliminates the
need for conversions between phase in degrees and phase in
fractional overlap of conduction pulses.
A low frequency, large signal AC model for the dual-fed
full bridge BIBRED with the new control scheme is
presented. The modeling approach is based on the Loss-Free
Resistor (LFR)modeling technique [4]. The AC equivalent
circuit contains an LFR to model the high quality
rectification of the converter, and a DC transformer to model
the DC conversion process. The equivalent circuit retains
the original component values, which facilitates analysis and
design of the converter. The steady state governing
equations for the converter with the new control scheme are
given. The steady state analysis involves performing a
curve fit to solve a transcendental equation. Mode
boundaries for correct operation of this converter as a high
quality rectifier are established. At one limit, the mode
boundaries dictate the minimum load required to prevent the
output control loop from saturating. At the other limit, the
maximum duty ratio can be calculated which prevents the
input inductors from operating in the continuous conduction
mode. The control scheme presented in this paper requires
that the input inductors operate in the discontinuous
conduction mode, for high quality rectification to be
achieved.
The control circuit used to implement the new control
scheme is discussed. The approach taken uses two
conventional PWM control chips, with one chip
synchronized to the other. Phase control was achieved by
varying the delay between the two chips. Duty ratio control
was implemented using standard PWM techniques.
Experimental results validate the new control scheme
and the equations which are derived. In the circuit that was
built, the energy storage capacitor voltage was regulated at
300 [VI, the output was regulated at 42 [VI, and a 5 to 1
load range was achieved.
Further work in this area could explore the possibility
of letting the input inductors operate in the continuous
conduction mode, and controlling the input current. The
benefit would be decreased switching losses, decreased RMS
input currents, and decreased EMI.
ACKNOWLEDGMENTS
M. A. Johnston would like to thank the members of the
Power Systems Business Unit at Storage Technology
Corporation for their support and technical assistance while
he was a graduate student at the University of Colorado at
Boulder.
REFERENCES
Fig. 7. Line voltage and current measurements, demonstrating
the high power factor input.
[l] M. Madigan, "Single Phase Integrated High Quality
Rectifier-Regulators," Ph.D. thesis, University of
Colorado at Boulder, July 1992.
854
[2] S . Freeland, "Input Current Shaping for Single-phase
AC-DC Power Converters," Ph.D. thesis, part 11,
California Institute of Technology, October 1987.
[3] S . Singer, "The Application of Loss-Free Resistors in
Power Processing Circuits," IEEE Transactions on
Power Electronics, vol. 6, no. 3, October 1991.
[4] M. A. Johnston, "Full Bridge Boost Integrated With
Buck Rectifier Energy Storage /DC-DC Regulator",
Master's thesis, University of Colorado at Boulder,
August 1993.
[5] 0. D.Patterson, D. M. Divan, "Pseudo-ResonantFull
Bridge DCDC Converter," PESC Records, 1987, pp.
424-430.
[q Unitrode Applications Note U- 111, "Practical
Considerations in Current Mode Power Supplies,"
Unitrode Linear Integrated Circuits Data and
Applications Handbook, April 1990, pp. 9-134 to 9135.
855