JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 9, NO. 3, SEPTEMBER 2011
211
Very Low Power, Low Voltage, High Accuracy, and
High Performance Current Mirror
Hassan Faraji Baghtash, Khalil Monfaredi, and Ahmad Ayatollahi
Abstract⎯A novel low power and low voltage
current mirror with a very low current copy error is
presented and the principle of its operation is discussed.
In this circuit, the gain boosting regulated cascode
scheme is used to improve the output resistance, while
using inverter as an amplifier. The simulation results
with HSPICE in TSMC 0.18 μm CMOS technology are
given, which verify the high performance of the
proposed structure. Simulation results show an input
resistance of 0.014 Ω and an output resistance of 3 GΩ.
The current copy error is favorable as low as 0.002%
together with an input (the minimum input voltage of
vin,min~ 0.24 V) and an output (the minimum output
voltage of vout,min~ 0.16 V) compliances while working
with the 1 V power supply and the 50 μA input current.
The current copy error is near zero at the input current
of 27 μA. It consumes only 76 μW and introduces a very
low output offset current of 50 pA.
Index Terms⎯Current mirror/source, high accurate,
high output resistance, low power, low voltage.
1. Introduction
Low power low voltage (LPLV) circuits become more
interesting because of increasing demand for portable and
mobile devices. On the other hand, technology down
scaling trend necessitates supply voltage reduction at VLSI
(very large scale integrated circuit) circuit design. Reducing
the power supply degrades the performance of all of the
analog circuits. This is also true for the current mirror
which is one of the most essential building blocks in VLSI
circuits. Hence, as a result of power supply reduction,
current mirror’s performance including input and output
impedances and input and output compliance voltages
degrades, making it unsuitable for LPLV applications. Thus
many researchers deal with the low voltage current mirror’s
designing issues[1]–[5]. The most important design
parameters of current mirror are current accuracy (copy
error) and input and output resistance. Many researches
Manuscript received February 15, 2011; revised April 25, 2011. This
work was supported by the Iran University of Science and Technology.
H. F. Baghtash, K. Monfaredi, and A. Ayatollahi are with the Electrical
and Electronic Engineering Department, Iran University of Science and
Technology, Tehran, Iran. (hfaraji@iust.ac.ir; khmonfaredi@iust.ac.ir;
ayatollahi@iust.ac.ir)
Digital Object Identifier: 10.3969/j.issn.1674-862X.2011.03.003
were reported to improve these parameters. The cascode
current mirror[6] and the regulated cascode (RGC) current
mirror[7] are used to increase output impedance. An
improved active feedback current mirror (IAFCCM)[8] and
a three-stage feedback current mirror[9] are proposed to
improve the accuracy. The IAFCCM exhibits better
accuracy compared with RGC current mirror while its
output impedance is equivalent to the RGC current mirror.
Although, the accuracy and output impedance of the threestage feedback current mirror are better than cascode, RGC,
and IAFCM current mirrors, but all of these circuits suffer
from high input and output voltage level (low input and
output voltage swing) and high input resistance. In [10] a
circuit with lower input and output voltage level and lower
input resistance than those reported in [7]–[9] was
presented. Meanwhile, the output impedance of the circuit
proposed in [10] is equivalent to the RGC current mirror.
Unfortunately, this circuit has a relatively poor accuracy
and uses a very complicated circuitry to adaptively bias
cascode transistors, which causes the power consumption
and chip area to increase. Recently, some low voltage
circuits were introduced in [11] and [12]. Although these
circuits’ complexities are less than that of [10] while
providing the same current transfer error, they introduce
some offset to the output current maintaining relatively
high current transfer error issue. Moreover, the circuit
proposed in [11] needs deliberately designed biasing
network and has relatively complex circuitry. On the other
hand, the circuit of [12] needs floating gate transistors
requiring more expensive technology for implementation.
Both circuits in [11] and [12] consume relatively more
power.
In this work, a very high performance current mirror is
designed which presents very low current copy error (high
accuracy), low input and output voltage, low input
resistance, high output resistance, relatively low power
consumption, and high bandwidth. The proposed current
mirror is discussed in next section. In Section 3 the
simulation results are revealed. The last section concludes
the paper.
2. Proposed Current Mirror
The conceptual schematic of the proposed circuit is
shown in Fig. 1. The circuit is composed of transistors M1,
M 2 , M 3 , M 1C , M 2C , and amplifiers Amp1 and Amp2.
JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 9, NO. 3, SEPTEMBER 2011
212
Amp1 is utilized to adjust the gate voltage of the mirror
transistors by amplified version of the input voltage. In this
case, the amplified version of the input node voltage which
is applied to the current mirror transistors gate must have the
same sign. In other words, Amp1 must be a positive gain
amplifier. This structure decreases the input resistance A1
times, where A1 is the voltage gain of the amplifier Amp1.
Moreover, despite the diode connected input stage in which
the minimum input voltage is VTH+VDSAT (where VTH is
threshold voltage and VDSAT is drain-source saturation
voltage of MOS transistor), the minimum input voltage of
the proposed structure is limited to the maximum value of
VDSAT or VinA1,Min, where VinA1,Min is the minimum input
voltage of amplifier Amp1. For output stage, a special
regulated cascode scheme is used by utilizing the negative
gain amplifier (i.e. Amp2) to further increase the output
resistance. This arrangement also helps the proposed current
mirror to have a very high accurate current copy. Fig. 3
shows transistor level implementation of the proposed
current mirror. The Amp1 and Amp2 are implemented by
using two cascaded simple inverter stages (transistors M1A to
M4A) and a simple inverter (transistors M5A and M6A),
respectively. Using small signal analysis for Fig. 3, the
amplifiers’ gains (A1 and A2 are gains of Amp1 and Amp2,
respectively) are obtained as
IIout
out
IIinin
Amp2
Amp1
A1
-A 2
M3
M 1C
M 2C
M1
M2
Fig. 1. Conceptual schematic of the proposed current mirror.
Output current (μA)
1000
800
600
400
200
0
0
200
400
600
Input current (μA)
800
1000
Fig. 2. Output DC current in terms of input one.
A1 =
IIooutu t
Iinin
M 1C
M1
M 2A
M 4A
M 6A
cc
M 1A
M 3A
M 5A
g
g
M3
M1A
ds1A
+g
+g
− A2 = −
M 2C
M2
Fig. 3. Transistor level implementation of the proposed current
mirror.
Transistors M1, M2, M1C, and M2C configure the selfcascode scheme in order to increase the mirror transistors
effective channel length and thus accuracy. But it is worth
noting that, in self-cascode scheme, the current mirror
accuracy is sensitive to the mismatches between the
drain-source voltages of mirror transistors, M1 and M2, but
the equivalency of the drain-source voltages of mirror
transistors are much better than the simple transistor whose
drain-source voltage is directly affected by the output and
input node voltages. For further improving the accuracy of
the proposed circuit, amplifiers Amp1 and Amp2 are used
to adjust the drain voltages of M1C and M2C to have
relatively equal values. This along with voltage mismatch
attenuation provided by M1C and M2C introduces more
favorably balanced voltage on drains of mirror transistors.
This can be observed from the experiment results in Fig. 2.
In order to facilitate the input current sink process,
where g
M1A
, g
, g
M 2A
M3A
M 2A
⋅
g
g
ds 2A
g
g
ds3A
+g
M 5A
+g
ds5A
, g
M 3A
M 4A
+g
+g
M 4A
(1)
ds 4A
M 6A
(2)
ds 6A
, g
M5A
, and g
M6A
are
trans-conductance of MOSFET transistors M1A–M6A,
,g
,g
,g
,g
, and g
respectively and g
ds1A
ds2A
ds3A
ds4A
ds5A
ds6A
are trans-admittance of MOSFET transistors M1A–M6A,
respectively.
For the input and output resistance of the current mirror,
we have
Rin =
1
g M1 A1
Rout = − A2
where g
M1
,g
M2
,g
M2 C
, and g
(3)
g M 2 g M 2C g M3
g
M3
ds1
g
ds 2C
g
(4)
ds3
are trans-conductance of
MOSFET transistors M1, M2, M2C, and M3, respectively and
g ,g
, and g
are trans-admittance of MOSFET
ds1
ds2C
ds3
transistors M1, M2C, and M3, respectively.
A very low input resistance and a very high output
resistance are surmised using (3) and (4). Utilizing the
inverter to implement the amplifier provides at least two
advantages. First, the inverter is very simple and power
213
FARAJI et al.: Very Low Power, Low Voltage, High Accurate and High Performance Current Mirror
Output current (μA)
100
Transistor
M1, M2
M1C, M2C, M3
M1A
M2A
M3A
M4A
M5A
M6A
W/L (µm/µm)
9/0.18
90/0.45
36.9/0.9
0.36 /10.8
9 /1.8
0.9 /1.8
36 /0.54
0.36 /9
40
20
0.2
0.4
0.6
Output voltage (V)
0.8
1.0
Fig. 4. Output current versus output voltage Iin stepped from zero
to 100 μA in steps of 20 μA.
1.0
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
Input current (mA)
0.8
1.0
Current transfer error (%)
Fig. 5. Output DC current in terms of input one applying the
voltage supply variations from 0.095V to 1.05V in 0.01V steps.
0.10
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.10
0
0.2
0.4
0.6
Input current (×10−4A)
0.8
1.0
Fig. 6. Current transfer error versus input current applying power
supply variation from 0.95V to 1.05V in 0.01V steps.
0.355
0.303
Input voltage (V)
Table 1: Ratios of width and length of the MOSFET transistors
60
0
3. Simulation Results
HSPICE simulations are carried out using TSMC 0.18
μm CMOS technology utilizing single 1 V power supply.
The ratios of width W and length L, i.e. W/L, of the
MOSFET transistors are chosen as Table 1.
The input current, Iin, is taken to have DC value of 50
μA. Fig. 4 shows the output current versus output voltage
with Iin stepped from 0 μA to 100 μA in steps of 20 μA. The
output resistance of approximate 3 GΩ is achieved from
simulation results. The minimum output voltage to operate
in high impedance mode took values from 0.1 V to 0.21 V.
Fig. 4 also shows very small offset current down to 50 pA.
In Fig. 5, the output current in terms of the input one in
presence of power supply variations is shown to prove the
robustness of the circuit against voltage supply variations.
The current transfer error versus input current is shown in
Fig. 6 while varying the power supply from 0.95 V to 1.05
V in 0.01 V steps. As the figure shows, the current copy
error is zero at input current about 27 μA. However, it stays
under 0.019% for currents ranging from 5 nA up to 100 μA.
80
0
Output current (mA)
efficient and second, due to complementary (NMOS and
PMOS) transistors, the amplifier can operate in very low
voltages. This allows the current mirror to get very high
input and output compliances and very low power supplies
become feasible. The Miller compensation technique is
used to compensate the operational bandwidth of the
proposed structure by means of the capacitance, Cc with the
value of 0.5 PF as shown in Fig. 3. Since the inverter can
operate in either saturation or sub-threshold regions, thus
when using it as an amplifier, the amplifier becomes
interestingly very suitable for low voltage applications. The
main disadvantage regarding the operation of the inverter in
sub-threshold region is related to the decrement in
amplifiers’ gain which leads to current mirror’s input
impedances, output impedances, and current accuracy
degradation. In spite of this, fortunately, the total
performance of the current mirror is still significantly high
for many applications. Due to low input resistance along
with high output resistance, very small voltage variations
occur in drain nodes of M1C and M2C transistors and thus a
very high accuracy is achieved.
0.255
0.202
0.155
0.10
0.055
00
0
0.2
0.4
0.6
Input current (mA)
0.8
1.0
Fig. 7. Input voltage in terms of input current applying voltage
supply variations from 0.095V to 1.05V in 0.01V steps.
JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 9, NO. 3, SEPTEMBER 2011
214
References
1.4
1.2
[1]
Iout/Iin
1.0
0.8
0.6
0.4
0.2
0
10−2
100
102
104
106
Frequency (Hz)
108
1010
Fig. 8. Frequency response of the proposed circuit.
Table 2: Results of this work compared with some other high
performance works
Item
Iin(µA)
Vin(V)
Vout(V)
Rin (Ω)
Rout (Ω)
BW (MHz)
CTE*%
P(W)
Vsup. (V)
Tech.
(µm-CMOS)
Proposed
work
Ref.
[8]
Ref.
[9]
50
0.245
0.17
0.014
3G
52
0.002@
50
NA
NA
NA
18.6G
52
0.019@
100
NA
NA
NA
NA
NA
0.001@
(Iin=50µA)
(Iin=100µA)
(Iin=100µA)
76µ
1
0.18
TSMC
NA
5
3
NA
3.3
0.35
lP4M
Ref.
[10]
Ref.
[11]
Ref.
[12]
50
100
50
NA
NA
NA
NA 0.23 ~ 0.46 0.15
NA
0.012
0.01
NA
2.3G
8G
0.1
220
200
0.05
0.05
0.1
NA
1.8
0.18
TSMC
NA
1.8
0.5
AMI
NA
3
0.5
AMI
∗: CTE is the abbreviation of “Current transfer error”.
Fig. 7 exhibits the input voltage variations in terms of
input current variations with power supply stepped from
0.095 V to 1.05 V in 0.01 V steps. For a DC sweep of input
current, Iin, from 1 μA to 500 μA, the maximum input
voltage variation was found to be 7 μV. This corresponds to
an input resistance of approximately 0.014 Ω. The total
power consumption of the proposed current mirror is about
76 μW. The frequency response of proposed circuit is
depicted in Fig. 8. The comparative results of this work
with some other works are given in Table 2.
4. Conclusions
A very low power, low voltage, and high accurate
current mirror is proposed in this paper. The proposed
current mirror also has a very low input resistance of 14
mΩ and a very high output resistance of 3 GΩ. Simulations
are performed using TSMC 0.18 µm CMOS technology
with HSPICE using a single 1 V power supply to verify the
high performance of the proposed circuit. This simulation
shows very high current accuracy, very low power
consumption, very low input and output voltages of 0.24 V
and 0.17 V respectively, and low input and high output
resistances together with a very wide current dynamic range.
The proposed circuit also has a very low offset current.
S. Sharma, S. S. Rajput, L. K. Magotra, and S. S. Jamuar,
“FGMOS based wide range low voltage current mirror and
its applications,” in Proc. of 2002 Asia-Pacific Conf. on
Circuits and Systems, Singapore, 2002, pp. 331–334.
[2] S. S. Rajput and S. S. Jamuar, “A current mirror for low
voltage, high performance analog circuits,” Analog
Integrated Circuits and Signal Processing, vol. 36, no. 3, pp.
221–233, 2003.
[3] S. Sharma, S. S. Rajput, L. K. Mangotra, and S. S. Jamuar,
“FGMOS current mirror: behaviour and bandwidth
enhancement,” Analog Integrated Circuits and Signal
Processing, vol. 46, no. 3, pp. 281–286, 2006.
[4] S. S. Rajput and S. S. Jamuar, “Advanced current mirrors for
low voltage analog designs,” in Proc. of 2004 IEEE
International Conf. on Semiconductor Electronics, Malaysia,
2004, pp. 258–263.
[5] S. J. Azhari, Kh. Monfaredi, and H. F. Baghtash, “A novel
ultra low power high performance atto-ampere cmos current
mirror with enhanced bandwidth,” Journal of Electronic
Science and Technology, vol. 8, no. 3, pp. 251–256, 2010.
[6] P. E. Allen and D. R. Holberg, CMOS Analog Circuit
Design, 2nd ed. Oxford: Oxford University Press, 2002, ch.
4, pp. 134–143.
[7] E. Saclunger and W. Guggenbuhl, “A high-swing
high-impedance mos cascode circuit,” IEEE Journal of
Solid-state Circuits, vol. 25, no. 1, pp. 289–298, 1990.
[8] A. Zeki and H. Kuntman, “Accurate and high output
impedance current mirror suitable for CMOS current output
stages,” Electronics Letters, vol. 33, no. 12, pp. 1042–1043,
1997.
[9] K.-H. Cheng, C.-C. Chen, and C.-F. Chung, “Accurate
current mirror with high output impedance,” in Proc. of the
8th IEEE International Conf. on Electronics, Circuits and
Systems, Malta, 2001, pp. 565–568.
[10] L. Sanchez-Gonzalez and G. Ducoudray-Acevedo, “High
accuracy self-biasing cascode current mirror,” in Proc. of the
49th IEEE International Midwest Symposium on Circuits
and Systems, Puerto Rico, 2006, pp. 465–468.
[11] M. S. Sawant, J. Ramírez-Angulo, A. J. López-Martín, and
R. G. Carvajal, “New compact implementation of a very
high performance CMOS current mirror,” in Proc. of the
48th IEEE Midwest Symposium on Circuits and Systems,
Cincinnati, 2005, pp. 840–842.
[12] A. Garimella, L. Garimella, J. Ramirez-Angulo, A. J.
López-Martín, and R. G. Carvajal, “Low-voltage high
performance compact all cascode CMOS current mirror,”
Electronics Letters, vol. 41, no. 25, pp.1359–1360, 2005.
Hassan Faraji Baghtash was born in
Miyandoab, Iran, in 1985. He received the
B.Sc. and M.Sc. degrees from Urmia
University in 2007 and Iran University of
Science and Technology (IUST) in 2009,
respectively. He is the author or coauthor of
more than twenty national and international
papers and also collaborated in several
research projects. He has been working with Electronic Research
FARAJI et al.: Very Low Power, Low Voltage, High Accurate and High Performance Current Mirror
Center Group, since 2007 and cooperating with Islamic Azad
University-Miyandoab Branch, West Tehran Branch and also
Miyandoab Sama College since 2008. He was also the reviewer of
2010 Electronic and Computer Scientific Conference (ECSC2010)
held in Islamic Azad University, Miyandoab Branch. He is
currently pursuing his Ph.D. degree with Electrical and Electronic
Engineering Department, IUST. His current research interests
include current mode integrated circuit design, low voltage, low
power circuit and systems, analog microelectronics and RF
design.
Khalil Monfaredi was born in Miyandoab,
Azarbayjane Gharbi, Iran, in 1979. He
received the B.Sc. and M.Sc. degrees from
Tabriz University in 2001 and IUST in 2003,
respectively. He has been working with
Electronic Research Center Group since 2001
and has been an academic staff with Islamic
Azad University, Miyandoab Branch since
2006. He has served as the Research and Educational Assistant of
Miyandoab Sama College since 2009. He is the author or coauthor
of more than twenty national and international papers and has
215
collaborated in several research projects. He is also the founder of
the Electronic Department in Islamic Azad University, Miyandoab
Branch and was the Chairman of 2010 Electronic and Computer
Scientific Conference (ECSC2010) held in Islamic Azad
University, Miyandoab Branch. He is currently pursuing his Ph.D.
degree with the Electrical and Electronic Engineering Department,
IUST. His current research interests include current mode
integrated circuit design, low voltage, low power circuit and
systems, and analog microelectronics and data converters.
Ahmad Ayatollahi was born in Tehran, Iran,
in 1954. He received the B.S. degree in
electronic engineering from IUST in 1976,
and obtained the M.S. and Ph.D. degrees
from Manchester University in 1986 and
1990, respectively. Since 1976 he has been
with the Department of Electrical
Engineering, IUST. He is currently an
associate professor and works with both electronic and biomedical
engineering groups. His research interests include electronic
circuit design, analysis of biomedical signals, and signal and
image processing.