SOI Low Frequency Noise and Interface Trap Density Measurements
With the Pseudo MOSFET
V.A. Kushner, J. Yang, J.Y. Choi, T.J. Thornton, and D.K. Schroder
Department of Electrical Engineering and Center for Solid State Electronics Research,
Arizona State University, Tempe, AZ 85287-5706, USA
Low frequency noise (LFN) is important in analog and digital
circuits. In analog circuits it affects the performance of low-noise
amplifiers and the phase noise (1) of voltage-controlled oscillators
(2). In digital circuits it becomes more important as the supply
voltage is reduced and it degrades substrate noise coupling. Lowfrequency noise is due to interactions of the channel carriers with
oxide/semiconductor interface traps and oxide charges and is very
dependent on the quality of the oxide/semiconductor interface and
noise measurements can give important information about such
interfaces and defects (3). Silicon-on-insulator devices have two
oxide/semiconductor interfaces and the bottom interface is
generally worse than the top interface. Most LFN measurements
are made after MOSFET fabrication, but it is desirable to
characterize such materials without fabricating devices. In this
paper we discuss silicon-on-insulator (SOI) low-frequency noise
and interface trap density measurements using a Ground-SignalGround (GSG) pseudo-MOSFET structure with minimum
fabrication.
Advantages and Fabrication of GSG Pseudo MOSFET
The pseudo MOSFET (Ψ-MOSFET) is a simple, yet powerful, device to characterize
various aspects of SOI wafers and is routinely used for incoming wafer inspection to
determine material parameters (3-7). It comes in the point contact and the mercury probe
(HgFET) configurations. The point-contact Ψ-MOSFET simply requires two probes on
an SOI wafer. However, the contact geometry is poorly defined leading to questions in
the interpretation of the Id-Vg data. The HgFET has the advantage of well-defined
source/drain contacts, but it has an Hg/Si interface and all the vagaries that accompany
metal/Si contacts, where barrier heights change with time due to surface state changes (5),
(7). The Ψ-MOSFET is routinely used for current-voltage, mobility, threshold voltage,
etc. measurements. However, to our knowledge is has not been used for noise
measurements. Yet, it is a convenient test structure for such measurements.
Motivation for Ground-Signal-Ground Ψ-MOSFET
Attempts to measure LFN of point contact Ψ-MOSFETs have not been successful
because of repeatability problems. It has not been possible to place the point probes
consistently on the same spots and apply the same pressure (6). Thus the results have had
significant variance from one measurement to the next one with the same operating point.
Mercury probes also have not been very suitable for LFN measurements due to their
dependence on the sample surface conditions (7).
For reproducible measurements we use deposited metal electrodes on the SOI wafer
forming Schottky barrier source/drain contacts, and using the substrate as the gate. This
allows us to use GSG probes for noise and frequency response measurements. Titanium
was chosen for the contacts on p-type SOI wafers, because it has almost equal electron
and hole barrier heights. Thus the titanium GSG Ψ-MOSFET allows us to analyze all
regions from accumulation to deep inversion, which is not possible with conventional
MOSFETs.
Fabrication of GSG Ψ-MOSFETs
The GSG Ψ-MOSFET is fabricated on an SOI substrate. GSG pads provide a stable
silicon contact and good shielding from environment noise. The silicon island structure
has a well defined device region compared to the traditional point probe pseudo
MOSFET.
(a)
(b)
Figure 1. (a) Cross section through the dashed line on (b); (b) top view of the GSG
Ψ-MOSFET. The unconnected island on the right is a gate contact artifact of the GSG
FET mask.
The cross section of device structure is shown in Fig. 1(a). The fabrication is very
straightforward. A p-type boron-doped bonded wafer, doped to 5x1014 cm-3, is used. The
silicon film and buried oxide thicknesses are 191 nm and 392 nm. To define the silicon
island, the wafer is patterned with photoresist and dry etched with reactive ion etching
(RIE). The silicon island has a dimension of 400 µm by 110 µm. After forming the
silicon island, the device is coated by photoresist then a GSG pattern, shown in Fig. 1(b),
is transferred to the device by lithography. The device is cleaned in 5% buffered oxide
etch (BOE) for 1 minute to remove the native oxide and to terminate the contact region
silicon surface with hydrogen bonds. Immediately after the HF rinse, 150 nm Ti and 150
nm Al films are deposited in sequence with electron beam evaporation. Titanium is
selected as the contact metal due to its work-function near the mid-gap of silicon. Biasing
the substrate with different polarity voltages, allows both electron and hole characteristics
to be extracted. The Al layer provides better step coverage and acts as a protection layer
for the Ti film as well. The GSG pad is then formed by the liftoff process after metal
deposition. As the last step, the device was sintered for 30 seconds to get a good Ti/Si
contact. To avoid forming titanium silicide, the sintering temperature was set to 450°C.
A micrograph of the finished device is shown in Fig. 2. High precision optical
measurements on pseudo n-MOSFETs yield a gate length of 25 µm and a gate width of
760 µm (two 380 µm fingers).
Figure 2. Micrograph of the pseudo n-MOSFET with 25 µm gate length and 760 µm gate
width. The device structure is a GSG “two finger gate” pseudo n-MOSFET.
DC Measurements
Measurement Setup and Results
Measurements are made with the HP-4156B semiconductor parameter analyzer
utilizing one GSG probe with three electrodes (Fig. 3). The two outer electrodes are
shorted and grounded, connecting to the source of the Ψ-MOSFET. The center electrode
carries the signal and connects to the drain. The gate voltage Vg is applied to the substrate
through the probe station chuck. All voltages are referred to the grounded GSG ΨMOSFET source.
Figure 3. Ground signal ground (GSG) probe on the source (two outside contacts) and the
drain (the contact in the middle).
The device has good control in both accumulation (Fig. 4(a)) and inversion (Fig. 4(b)).
The significant range of currents in both regions is possible through the Ti drain and
source contacts with the Schottky barrier height (0.56 to 0.6 eV). However, it leads to
some complications. The OFF current changes significantly with an increase of the
absolute drain voltage in the range of 1 to 5 V: from 1.2 nA up to 15 nA for negative
drain bias (Fig. 5(a)) and from 1 nA up to 120 nA for positive drain bias (Fig. 5(b)). The
maximum ON current reaches a few milliamperes in the accumulation regime (Fig. 5(a))
and a few hundred microamperes in the inversion regime (Fig. 5(b)), but is very different
for positive and negative drain voltages (Figs. 6 and 7). These DC parameters make the
GSG Ψ-MOSFET a suitable device for noise spectroscopy. However, caution needs to be
exercised to account for the influence of the Schottky junctions, because such junctions
introduce additional noise.
-4
10-4
10
V = -9, -8,.., 0, 1 V
-5
10-5
Drain Current (A)
Drain Current (A)
g
10-6
10-7
10-8
10
10
-9
-10
10
V = 2, 3,.., 10 V
10-6
g
10-7
-8
10
10-9
10-10
10-11
-5 -4 -3 -2 -1 0
-11
1
2
3
4
10
5
-5 -4 -3 -2 -1 0
Drain Voltage (V)
1
2
3
4
5
Drain Voltage (V)
(a)
(b)
Figure 4. GSG n-MOSFET drain current versus drain voltage in (a) accumulation, (b)
depletion and inversion regions.
10-3
10-3
V = -5, -3, -1 V
d
Drain Current (A)
Drain Current (A)
-4
10
-5
10
10-6
-7
10
-9
-30
d
10-5
10-6
10-7
10-8
10-8
10
V = 1, 3, 5 V
10-4
-20
-10
0
10
Gate Voltage (V)
(a)
20
30
10-9
-30
-20
-10
0
10
20
30
Gate Voltage (V)
(b)
Figure 5. GSG n-MOSFET drain current versus gate voltage for (a) negative, (b) positive
drain voltages.
Basic GSG Ψ-MOSFET Model
Traditional point or mercury Ψ-MOSFETs often demonstrate behavior characteristic
of long-channel MOSFETs because of almost ohmic drain and source contacts, achieved
by point contact damage in the point-contact (4) or by low barrier height for either holes
or electrons in the HgFET (7). Contrary to that, the GSG Ψ-MOSFET DC characteristics
are more complex (Figs. 4-7), because for any bias conditions the drain current has to
flow through one forward biased Schottky diode, the silicon film, controlled by the gate
(substrate voltage in our case), and through the reverse-biased Schottky diode. Also the
source contact area is twice as large as the drain contact area, making the GSG
Ψ-MOSFET highly asymmetrical. Edge effects may cause some other secondary effects
in spite of the large contact areas.
1.5 10-5
Vd = -1 V
2 10-4
1 10-5
1 10-4
5 10-6
Vd = 1 V
0 100
Transconductance (S)
Drain Current (A)
3 10-4
0
-28 -24 -20 -16 -12 -8
-4
0
Gate Voltage (V)
Figure 6. The reverse-biased Schottky junction at Vd = 1V causes a significant decrease in
the drain current and transconductance in the accumulation region.
n-MOS
dominated
-5
2 10
Schottky junction
dominated
3 10-6
Drain Current (A)
d
V = -1 V
d
2 10-6
1 10-5
1 10-6
0
4
8
12
16
20
24
28
Transconductance (S)
V =1V
0
Gate Voltage (V)
Figure 7. The asymmetrical device structure and the Schottky junctions cause a threshold
voltage shift and a drain current reduction for Vd = -1V versus Vd = 1V in the depletion
and inversion regions.
In order to simplify the device analysis we can assume that the device behaves as a
long channel MOSFET in series with a reverse-biased Schottky diode. This means that
the drain current is dominated by the lowest of the MOSFET or the Schottky contacts
currents for any given bias conditions. Hence, we approximate the drain current of the
GSG Ψ-MOSFET as
Id =
I MOS I Schottky
I MOS + I Schottky
[1]
where the MOSFET current IMOS (Vg, Vd) in accumulation or strong inversion follows the
simple MOSFET equation (10)
I MOS = µ eff C BOX
V ⎞
W⎛
⎜V g − Vth, FB − d ⎟⎟Vd
⎜
L⎝
2 ⎠
[2]
and the Schottky diode current ISchottky is given by (11)
⎛ qφ b
I Schottky = AA * T 2 exp ⎜ −
⎝ kT
⎤
⎞⎡
⎛ qV d ⎞
⎟ ⎢ exp ⎜
⎟ − 1⎥
⎠⎣
⎝ nkT ⎠
⎦
[3]
where µeff is the effective mobility, CBOX the buried oxide capacitance/unit area, W the
gate width, L the gate length, Vd the drain voltage, Vg the gate voltage, Vth the threshold
voltage for the inversion region, VFB the flatband voltage for the accumulation region, A
the area of the Schottky contact, A* Richardson’s constant, T the temperature, φB the
effective Schottky barrier height, and n the ideality factor.
GSG Ψ-MOSFET Noise Spectroscopy
Low Frequency Noise Measurements
The probe station for the D.C. measurements was also configured for low frequency
noise measurements. Of particular interest is the low frequency 1/f noise behavior which
is associated with traps at the Si/BOX interface. The measurement configuration is shown
schematically in Fig. 8. It can be used for the direct measurement of the drain current
noise spectral density, SId. However, by applying a small signal voltage to the gate of the
device the overall transfer function of the device plus current amplifier can be measured.
From the known response of the current amplifier the transfer function of the MOSFET
can then be deduced and used to determine the gate-referred noise voltage spectral
density SVg.
Ioffset
Stanford
SR 570 LNA
R
Switch
DUT
Reference
Source
Agilent 35670A
Low-pass
filter
VDS
HP 4156B
VGS
Figure 8. Schematic illustration of the setup used to measure the LFN spectrum (adapted
from (12)).
The low-frequency drain current noise spectral density (SId) follows the 1/f relation in
the accumulation as well as in the inversion regions of the bottom Si/BOX interface (Figs.
9 and 10). SId is proportional to Id2 in inversion (Fig. 11), which is consistent with nMOSFETs (8). However SId is proportional to Id1.75 in the accumulation region (Fig. 11),
that can be explained by volume conduction in weak accumulation, with interface traps
having less influence on the active carriers.
The gate-referred noise voltage power spectrum SVg is determined from SId and the
GSG Ψ-MOSFET transconductance gm (8) (Figs. 12 and 13). SVg is almost independent of
the drain current in the accumulation region and shows a weak dependence in strong
accumulation (Fig. 12). The same is found for the depletion and weak inversion regions.
However in strong inversion the device transconductance decreases drastically (Fig. 7)
due to the influence of the reversed biased drain Schottky junction. As a result we see a
significant increase in the drain referred noise spectrum (Fig. 13).
10-17
I=
d
-18
-5
10
2x10
-5
10
-19
(A /Hz)
10
2
10
Id
S
5x10-6
-20
2x10-6
10-6
-21
10
5x10-7
-22
10
-7
2x10
-23
10
-7
10
0
10
1
10
2
10
3
10
4
10
Frequency (Hz)
Figure 9. SId vs. frequency for Ψ-n-MOSFET in accumulation at Vd = -1 V.
10-17
10-18
I=
d
-19
10-5
S
Id
(A2/Hz)
10
5x10-6
10-20
-6
2x10
-21
10
10
10-22
5x10-7
-6
2x10-7
-23
10
-7
10
100
101
102
103
104
Frequency (Hz)
Figure 10. SId vs. frequency for Ψ-n-MOSFET in inversion at Vd = 1 V.
Careful examination of the plots in Figs. 9 and 10 show that in the accumulation
region (Fig. 9) the slopes of curves between 10 and 100Hz change from 1/f to less steep
slopes. Also the plots for the inversion region keep 1/f slope throughout the entire range
of frequencies. Such phenomena may be caused by the generation-recombination (G-R)
noise component due to defects in the depletion region of the gate Schottky contact or
because of interface traps (13, p. 212 and 203).
-17
10
-18
2
SId (A /Hz)
10
10-19
Inversion:
S =4.284x10-8I
Id
2.022
d
-20
10
Accumulation:
10-21
-10 1.750
d
S =4.008x10 I
Id
-22
10
10-7
10-6
10-5
Drain Current (A)
Figure 11. SId vs. Id at f = 1Hz in accumulation and inversion of the Si/BOX interface.
10-7
Id=
2x10-5
-8
10-5
5x10-6
-9
10
2x10-6
Vg
(V2/Hz)
10
S
10-6
5x10-7
10-10
2x10-7
10-11
100
10-7
101
102
103
104
Frequency (Hz)
Figure 12. SVg vs. frequency for Ψ-n-MOSFET in accumulation at Vd = -1 V. The increase
of the gate-referred noise spectral density occurs in strong accumulation.
In order to extract the defect parameters, the LFN measurements are done for
different drain voltages in the accumulation region (Figs. 14, 15). The drain current is
held constant at 1µA by adjusting the gate voltage. The plot on Fig. 14 confirms our
hypothesis about the generation-recombination process in the depleted region of the drain
Schottky junction: the G-R Lorentzian noise peaks (13, p. 201) dominate for reversebiased (positive) drain voltages and not for negative Vd. Nevertheless, we cannot rule out
the possibility of interface trap participation. The noise spectrum curves do not change
with the increase of the drain voltage from 1 to 5 V (Figs. 14, 15). This is because the
silicon film is fully depleted under the gate, the drain current is kept constant and the
Ψ-MOSFET channel is uniform in the source to drain direction.
10-7
Id=
-5
10
10-8
(V2/Hz)
5x10-6
-6
2x10
10-9
-6
S
Vg
10
-7
5x10
10-10
2x10-7
10-7
-11
10
0
1
10
2
10
3
10
4
10
10
Frequency (Hz)
Figure 13. SVg vs. frequency for Ψ-n-MOSFET in inversion at Vd = 1 V. The increase of
the gate-referred noise spectral density occurs in the strong inversion.
10-17
-18
10
V =1,2,..,5 (V)
d
2
SId (A /Hz)
-19
10
10-20
-21
10
10-22
Vd=-1 (V)
-23
10
0
10
1
10
2
10
3
10
4
10
Frequency (Hz)
Figure 14. SId vs. frequency for Ψ-n-MOSFET in accumulation at constant Id=1 µA and
Vd = -1, 1, 2…, 5 V.
The f*SVg versus frequency plot on Fig. 15 helps to extract the zero-frequency plateau
values of the Lorentzians (13, p. 206), since it is easier to find maxima of the curves on
Fig. 15 than the corner frequencies on Fig. 14.
f*SVg (1/Hz)
10-5
V =1,2,...,5 (V)
d
10-6
-7
10
0
10
1
10
2
3
10
4
10
10
Frequency (Hz)
Figure 15. f*SVg vs. frequency for Ψ-n-MOSFET in accumulation at constant Id=1 µA
and Vd =1, 2…, 5 V.
Analysis of LFN Data
In order to derive meaningful parameters from the measured data we need to
determine the GSG Ψ-MOSFET LFN sources and the types of noise. The current noise
power spectral density SId(f) can be written as the sum of flicker noise, generationrecombination noise, shot noise and thermal noise (8)
S Id ( f ) =
C1
C2 / f0
+
+ C3 + C4
f
1 + ( f / f0 )2
[4]
where C1 is the amplitude of the flicker noise, C2/f0 the zero-frequency plateau value,
C3=2qISchottky the Schottky contact shot noise spectrum and C4=8kTgm/3 denotes the
MOSFET thermal noise. The depletion and inversion plots in Fig. 10 show only a 1/f
noise component. The generation-recombination component is present on the
accumulation plot in Fig. 9, but the Lorentzian plateaus are obscured by the 1/f
component, making it impossible to extract C2/f0 (13). The G-R defects parameters can be
extracted from plots in Fig. 14 and Fig. 15 where the G-R component of LFN dominates.
The 1/f LFN behavior in the linear part of the inversion region can be explained by
the unified correlated model (9) where the carrier number and mobility fluctuations are
taken into account in a correlated fashion
SVg ( f ) =
kTq 2
2
1 + αµ eff N N T ( E F )
2
γfWLC BOX
(
)
[5]
where γ is the attenuation coefficient, µeff the effective carrier mobility, α the Coulombic
scattering parameter, N the number of channel carriers/unit area, CBOX the buried oxide
capacitance per unit area, WL the gate area and NT(EF) the oxide-trap density (cm-3eV-1)
(9).
The input voltage referred noise spectral density SVg is calculated from the frequency
response data. The interface and border trap density at the quasi-Fermi level NT(EFn) is
extracted as NT(EFn) = 9.4x1018 cm-3eV-1 for weak inversion and 4.1x1018 cm-3eV-1 for
accumulation, which corresponds to 1.9x1012 cm-2eV-1 and 8.2x1011 cm-2eV-1 for the 2
nm Si/BOX interface. The NT(EFn) values are higher than for conventional SOI
MOSFETs, which are typically 1x1017 cm-3eV-1 (14), because the SOI Si film/buried
oxide interface is worse than the MOSFET gate oxide/Si interfaces, leading to a higher
trap density.
Interface trap densities can also be extracted from the G-R noise component of LFN
(Fig. 15), if we assume that the Si/BOX interface traps cause the Lorentzians (11, p. 204).
The density of the noisy interface traps can be approximated at the gate bias Fermi level
by
2
S Vg ( 0 ) f 0 C BOX
WL
[6]
N it ( E Fn ) =
2
2π q
where SVgf0 are the maxima of the curves on Fig. 15. This gives Nit(EFn)=3.2x1010 cmeV-1 at f0=6.625 Hz from the first maximum and Nit(EFn)=2.2x1011cm-2eV-1 at f0=7074.5
Hz from the second maximum. These numbers are four times lower than the ones from
the 1/f noise component, indicating that the G-R noise is most likely caused by defects in
the depletion region of the Schottky drain junction. However, there may be an alternative
explanation. LFN behavior, similar to Fig. 14, is observed in reversed biased Schottky
diodes (15). In order to determine the source of G-R noise components the LFN
measurements need to be done on Ψ-MOSFET with a partially depleted channel under
the drain Schottky contact. This also gives the vertical distribution of defect densities in
the device channel. Such measurement involves low drain and high gate voltage biases.
This has not been done due to equipment limitations. Another approach involves the use
of the probe station with a temperature controlled chamber (13, p. 214).
2
Conclusions
A new approach for SOI wafer characterization has been proposed allowing noise
measurements with the pseudo MOSFET structure. This approach allows SOI wafer
noise measurements before conventional device fabrication. A new ground-signal-ground
(GSG) Ψ-MOSFET has been developed and characterized. Consistent and repeatable
low-frequency noise measurements have been made on the Ψ-MOSFET for the first time.
DC and noise measurement data have been explained and the Si/SiO2 interface trap
densities at the pseudo-Fermi levels have been extracted. The GSG Ψ-MOSFET noise
spectroscopy can be further expanded through controlled temperature measurements,
providing an opportunity for the trap density/energy level spectroscopy, similar to the
DLTS measurements (11).
References
1. B. Razavi, IEEE Journal of Solid-State Circuits, 31, 331-343 (1996).
2. M. Borremans, B. de Muer, M. Steyaert, Electronics Letters, 36, 857-858 (2000).
3. H. Wong, Microelectron. Reliab. 43, 585-599, (2003); C. Claeys, A. Mercha, and E.
Simoen, J. Electrochem. Soc. 151, G307-G318 (2004).
4. S. Cristoloveanu, D. Munteanu, and M. S. T. Liu, IEEE Trans. Electron Dev. 47,
1018-1027 (2000).
5. H.J. Hovel, Solid-State Electron. 47, 1311-1333 (2003).
6. S. G. Kang, D. K. Schroder, IEEE Trans. Electron Dev. 49, 1742-1747 (2002).
7. J. Y. Choi, S. Ahmed, T. Dimitrova, J. T. C. Chen, and D. K. Schroder, IEEE Trans.
Electron Dev. 51, 1164-1168 (2004).
8. A. van der Ziel, Noise in Solid State Devices and Circuits, Wiley, NY (1986).
9. K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, IEEE Trans. Electron Dev. 37, 654665 (1990).
10. S. Cristoloveanu and S. S. Li, Electrical Characterization of SOI Materials and
Devices. Boston, MA: Kluwer (1995).
11. D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed., p. 169,
Wiley, New York (1998).
12. A. Blaum et al., A New Robust On-Wafer 1/f Noise Measurement and
Characterization System, Proc. IEEE Int. Conf. on Microelectronic Test Structures,
14, p. 125-130 (2001).
13. N. B. Lukyanchikova in Noise and Fluctuations Control in Electronic Devices, 201203, American Scientific Publishers (2002).
14. S. Haendler, J. Jomaah, G. Ghibaudo, F. Balestra, Microelectronics Reliability, 41,
855-860 (2001).
15. H. Ouacha, M. Mamor, M. Willander, A. Ouacha, F. D. Auret, J. Appl. Phys., Vol. 87,
3858-3863 (2000).