The Art of Engineering, AMPLIFIED
®
Design Tools, Flows and
Methodologies for SOI:RF
Jim McMahon
Custom IC Flow Solutions
Outline
• Background
• Advantages of SOI for RF/Wireless Applications
– Process Selection
• RF Design Implementation Challenges
–
General Challenges
–
SOI CMOS-Specific Challenges
• Design Enablement
– RF SoC and SiP Design Flows
– Key Tools and Capabilities
– Process Design Kits (PDKs) for RF SOI Design
• Summary
10/21/2009
SOI for RF Design
• History
– SOI Processes Available Commercially Since ~1998
– RF SOI-based Products Available Since ~1999
• Past Focus – Use Driven by Performance
• Present and Future – Use Driven by System Integration (SoC)
– The radio becomes a peripheral in a multi-function SoC
Hitachi dual-band GSM/DCS
transceiver IC – 0.35um
BiCMOS c1999
10/21/2009
SOI CMOS Advantages
• System Integration (Size/Weight/Cost/Power)
– Isolation – Reduced Substrate Noise, Latch-up Elimination
– Process Integration – Bipolar/LDMOS/High Voltage
– RF Active Devices, Passives, Switches, etc.
• Performance
– Power Efficiency – Standby/Leakage + Digital Speed vs. Power
– Device Performance – Ft/Fmax/Linearity
– Passives – High-Q (low loss)
10/21/2009
Simple Process Technology Feature
Comparison for RF Implementation
1=Best / 4=Worst
Process
Bulk
Technology CMOS
Bulk
BiCMOS
(SiGe)
SOI
CMOS
GaAs
HBT
Cost
1
2
3
4
Noise*
4
2
3
1
Power
Efficiency
4
3
2
1
Passives
4
3
1
2
Integration
3
2
1
4
TOTALS
16
12
10
12
Summary
#3
#2 (tie)
#1
#2 (tie)
*Intrinsic Device Noise
•Simple/Unweighted Comparison Favors SOI CMOS
10/21/2009
Design Constraints vs. Manufacturing
Process Capabilities
Performance
Performance
••
••
••
••
••
••
Power
Power
Speed
Performance
Speed
Linearity
Linearity
Noise
Noise
Reliability
Reliability
…
…
••
••
Cost
••
••
••
••
Time
Time
Time(to
(tomarket)
market)
••
••
••
10/21/2009
Dev.
Dev.Cycle
Cycle
Design
DesignIterations
Iterations
Yield
Ramp-up
Yield Ramp-up
Cost
Cost
Finished
FinishedWafer
Wafer
Die
Area
Die Area
Yield
Yield
Development
Development
Resources
Resources
…
…
General RFIC Implementation Challenges
• RF System Co-Design
• Multiple Design Disciplines – RF, Analog, Digital => Mixed-Signal Co-Design
• RF-Accurate Device Models – Predictive of Noise, Linearity, etc.
• Passive Component Design – Electromagnetic simulation for custom RF
structures: Inductors, Transformers, …
• Electrical Functional and Performance Verification - Wide Dynamic Ranges,
Wide Frequency Ranges, …
• Physical Electrical Verification – Interconnect Parasitics (RLCk), Substrate
Effects, Signal Integrity, Electromigration, …
• Low Power
• Package Co-Design
• Cost
10/21/2009
Differentiating SOI Design Challenges for
RFICs
• All Process Options Have Their Own Specific Areas of Concern for RF:
– Bulk CMOS – Substrate Noise, Passive Component Modeling, …
– GaAs - Device modeling, ESD, BEOL , …
– SOI CMOS – Device Modeling, Floating Body, Self-Heating…
• But…Most Challenges are the Same -> Minimal Impact to the Design Flow
and Tool Feature Requirements
• This Reality Reflected in Current Design Tools
– Less tool specialization than in the past modeling and circuit simulation tools
converging – e.g. frequency domain vs. time-domain analysis techniques.
• Must also Consider Impacts to the Rest of the Design Flow (e.g. Digital) as
Applicable
Design
Challenges
10/21/2009
Flows
Tools
Custom Mixed-Signal Design Methodology
Conceptual View
Analysis
Digital & D/MS
Analog & A/MS
FastSPICE
Transistor
Preliminary estimate
Pre-layout abstract
Post-layout abstract
Meet-in-the-middle approach
For parallel, layout-aware design evolution
10/21/2009
Top-down
speed
Floorplan/route
Mixed level
Calibrated HDL
RF & RF/MS
Physical design
Behavioral HDL
Mixed level
Extraction
Simulation
Models
Silicon-accurate analysis
Full-chip/system specification
Bottom-up
accuracy
Major Custom AMS/RF Design Sub-Flows
System-Level
Design
Block-Level Design
Analog/RF
Design
Analog/RF
Migration
Digital Block
Design
Digital Block
Migration
Review
Review
Review
Review
Block-Level Implementation
Analog/RF Block
Implementation
Digital Block
Implementation
Review
Review
Chip-Level
Integration
10/21/2009
Basic RF Block Design and Implementation
Flow
System Design
System-to-RFIC
Specification Sign-off
Testbenches
Models
Block Implementation
Circuits
Models
Calibrated
HDL Models
Package
Design
E-M Component
Analysis & Design
Continuous Design
Evolution
SOI Details
Schematic Capture
Circuit Design
and Simulation
Block Layout
DRC/LVS
Parasitic Extraction
and Re-simulation
Top-level
Integration & Verification
Design
Constraints
Tape Out
10/21/2009
Device modeling:
Floating body effects,
LF noise, sidewall and
oxide capacitances
(BSIMSOI)
Additional DRC rules:
Bulk terminal handling,
substrate coupling
analysis, parasitic C
handling
Starting Point: System-Level Design
Item
Unit
Ant_port
Cable_l
oss
BPF
T/R
Signal_AGC
1-tone Blck at 20 MHz
1-tone Blck at 25 MHz
1-tone Blck at 40 MHz
2-tone IM3
Noise
dB
dB
dB
dB
dB
-1
-1
1
100
100
90,4
-1
-1
-1
-1
-1
-1,5
-1,5
1,5
100
100
90,4
-1,5
-1,5
-1,5
-20
-20
-1
-1
1
100
100
90,4
-1
-1
-1
-1
-1
dB
dB
-1
-1,00
-2,5
-2,50
-3,5
-3,50
real
dB
1,3
1,0
dBm
dBc
-36
dBm
dBV
dBm
dBV
dBm
dBV
dBm
dBV
dBm
dBV
dBm
dBV
dBm
dBV
dBm
dBV
-10
-23
-76
-89
-76
-89
-53
-66
-45
-58
-35
-48
-36,0
-49,0
-100,6
-113,6
40
2,0
2,9
20
-37
-274
-10,50
-23,50
-76,50
-89,50
-76,50
-89,50
-53,50
-66,50
-45,50
-58,50
-35,50
-48,50
-100,6
-113,6
-11
-24
-77
-90
-77
-90
-54
-67
-46
-59
-36
-49
-311,0
-323,0
-100,6
-113,6
-1
-1
1
100
100
90,4
-1
-1
-1
-1
-1
-11,75
-24,75
-77,75
-90,75
-77,75
-90,75
-54,75
-67,75
-46,75
-59,8
-36,8
-49,8
-311,7
-323,7
-100,4
-113,4
15
15
2,1
5
12
-4,6
0
0
0
0
0
-4,5
Signal_min
-4,50
2,0
2,9
VGA#1
LPF
VGA#2
15
12
16
20
6,4
0
0
0
0
0
10,00
12
16
18
6,4
-40
-50
-60
-120
-130
15,00
12
16
17
6,4
0
0
0
0
0
2,0
3,0
-318
-12,5 -13,00
-25,5
-20-26,00
-78,5 -79,00
-91,5 -92,00
-78,5
-40-79,00
-91,5 -92,00
-55,5 -56,00
-68,5
-60-69,00
-47,5 -48,00
-60,5 -61,00
-37,5
-80-38,00
-50,5 -51,00
-312,5 -313,0
-324,5
-100-325,0
-100,1 -100,6
-113,1 -113,6
-13,5
-26,5
-79,5
-92,5
-79,5
-92,5
-56,5
-69,5
-48,5
-61,5
-38,5
-51,5
-313,5
-325,5
-101,1
-114,1
-14,00
-27,00
-80,00
-93,00
-80,00
-93,00
-57,00
-70,00
-49,00
-62,00
-39,00
-52,00
-314,0
-326,0
-101,6
-114,6
Level diagram
22
32,00
P1dB
-14,50
-27,50
-80,5
-93,5
-80,5
-93,5
-57,5
-70,5
-49,5
-62,5
-39,5
-52,5
-314,5
-326,5
-102,1
-115,1
-14,50
-27,50
-73,00
-86,00
-73,00
-86,00
-50,00
-63,00
-42,00
-55,00
-32,00
-45,00
-228,2
-234,2
-94,6
-107,6
-32,5
-58
-14,50
-27,50
-65,5
-78,5
-65,5
-78,5
-42,5
-55,5
-34,5
-47,5
-24,5
-37,5
-142,0
-142,0
-87,1
-100,1
Noise level
-49,5
-59,5
-69,5
-148,0
-158,0
IM3
42,00
52,00
67,00
5,5
7,4
6,6
8,2
7,0
8,4
5,2
7,1
-44
-98
Sig_max
27,00
67,0
Blck@40MHz
2,0
3,0
-59
0 -316
-5
2
9
15
-0,6
-5
-5
-5
-5
-5
Blck@25MHz
2,0
2,9
-58
11,5
21,5
2,8
-3,5
10
-13,1
0
0
0
0
0
10,5
Sig_AGC
10,50
Blck@20MHz
-57
-314
-37,5
-37,5
-93
-8,75
-16,75
-59,75
-67,75
-59,75
-67,75
-36,75
-44,75
-28,75
-36,75
-18,75
-26,75
-116,2
-116,2
-76,3
-89,3
-3,00
-6,00
-54
-57
-54
-57
-31
-34
-23
-26
-13
-16
-90,5
-90,5
-65,5
-78,5
-3,75
-8,50
-51,12
-59,50
-51,12
-59,50
-27,13
-36,50
-20,13
-28,50
-11,38
-18,50
-45,2
-93,0
-32,8
-79,0
-107
-167,5
-367
-167,5
-367
-4,50
-11,00
-48,25
-62
-48,25
-62
-23,25
-39
-17,25
-31
-9,75
-21
-5,25
-11,00
-45,37
-54,50
-45,37
-54,50
-19,38
-31,50
-14,38
-23,50
-8,13
-13,50
-5,99
-11,00
-42,49
-47
-42,49
-47
-15,50
-24
-11,50
-16
-6,50
-6
-6,37
-11,00
-39,62
-42,00
-41,06
-42,00
-13,56
-44,00
-10,06
-36,00
-5,69
-31,00
-6,74
-11,00
-36,74
-37
-39,62
-37,0
-11,63
-64,00
-8,63
-56,00
-4,88
-56,00
-7,87
-11,00
-33,87
-29,50
-35,30
-29,50
-5,81
-56,50
-4,31
-48,50
-2,44
-48,50
-9,0
-11,0
-31,0
-22,0
-31,0
-22,0
-95,5
-88,0
-80,5
-75,5
-70,5
-63,0
-55,5
-79,4
-71,8
-64,2
-58,8
-53,4
-45,8
-38,1
12,8
-49,0
-41,0
-41,0
-120
Summary
A
A
#2
#1
ix
C
O
M
os
s
10/21/2009
VG
C
/C
n
l
e_
Receiver RF & analog BB chain
VG
D
D
A
u
al
R
LN
B
T/
l
ab
t
or
_p
nt
F
BP
C
dB
A
SNR
DCOC
-||-
dBV
Signal_min
dB
dB
dB
dBm
dBm
D/C Mix
LNA
F
LP
Component
Device spec
Stage Power Gain
Stage Voltage Gain
NF_device
IIP3_device
IIP2_device
Input P1dB (dBm)
Att @ 20MHz
Att @ 25MHz
Att @ 40MHz
Att @ 120MHz
Att @ 140MHz
Gain/Loss
G_p_ytd
G_v_ytd
Noise
F_ytd
NF_ytd
Non-linearity
2-tone Blck level
IM3 rejection
Level
Signal_max
Balun
T/R
L
System-Level Design Example:
Matlab/Simulink Cosimulation
10/21/2009
System-Level Design: Top-Down Behavioral
Modeling and Trade-Off Analysis
RF PB test bench
System BB test bench
10/21/2009
Symbol
Specification
Spec
Meas
Units
G
Cascaded Gain
69
71.87
dBV
Rx_NF
Receiver Cascaded Noise Figure
12.7
7.21
dB
IIP3
rd
-13
-29.17
dBm
Input-Referred 3 Order Intercept
RF Block Design Flow –Circuit Design,
Analysis & Optimization, Layout
Implementation & Verification
RF Design Environment
Schematic Capture
Schematic entry
Passive component design
Design constraint entry
Parasitic estimation
10/21/2009
Verification
Parasitic sensitivity
Design centering
Yield optimization
Behavioral model calibration
Layout Implementation & Verification
PCells/Module generation
Custom floor/cell planning
Constraint driven placement
Electrically aware routing
Post layout extraction/verification
Multi-Level/Multi-Mode Simulation
Engines Optimized for Each Verification Task
FastSPICE
High performance and
capacity simulation and analysis
AMS Designer
Verification of RF/Analog/Digital
Blocks, Subsystem and SoC Level
SpectreRF/SPICE
Scope
Circuit-level simulation
RF analysis
Mixed-signal
subsystem
µP
Block-level
RF
Full Chip
SOI-Specific Device Models
Body, history, parasitic bipolar effects
PLL
Memory
Verification cycle
16
10/21/2009
RF-Specific Circuit Analyses
Examples from SpectreRF
Harmonic Balance
Shooting Newton
Verification of RF transceivers
Analysis of highly
nonlinear circuits
Spectre RF
Large Signal
Small Signal
PSS, QPSS
Oscillator
PAC, PXF, PSP
QPAC, QPXF, QPSP
Envelope
Perturbation
Noise
AM, PM, FM
autonomous
Rapid IP2, IP3
Distortion Summary
Pnoise, QPnoiise
Sampled noise, jitter
10/21/2009
Mixed-Level AMS Design Verification
HED
ROM
Verilog-D
Application
Specific
Logic
RAM
uP
VHDL-D
SPICE
Test
Verilog-AMS
Complex
RF
USB
VHDL-AMS
PLL
AMS
Custom
DSP
Schematic
Extracted
CONFIG
10/21/2009
Physical Verification and
Parasitic Extraction
(Interconnect RLCk + Substrate)
GDSII
• Requirements
DFII
OA
Physical
Verification
– High performance & accuracy
– Coupled and decoupled Capacitances
QRC
– Mutual and self Inductances
– Smart filters for netlist reduction
– RF-specific needs
• Skin and proximity effects
Extraction
Drawn
Devices
Substrate
R&C
RLCK
• 3D substrate modeling
DFII/OA
DSPF
SPEF
Circuit Re-Simulation
(Verification)
10/21/2009
RFIC Top-Level Functional Verification
Pin-correct transmitter and
receiver loopback testbench
including PLL and
ADC/DAC
Sim time 1.5 mins for 8us
modulated IQ test signal
10/21/2009
RF IC (Top-Level Bottom-Up Driven) Performance
Verification
~60x speed-up vs. transient
10/21/2009
RF System-in-Package (SiP) Implementation
SoC/SiP Co-Design
SiP Implementation
PCB schematic capture
Passive component design
RF/mixed-signal simulation
Design constraints entry
Post-layout simulation
Signal-Integrity analysis
EM analysis
22
10/21/2009
Die stack editing
Die abstract import/export
Connectivity-driven layout
Constraints-driven layout
Shape editing
Automated routing
EM analysis
3D Visualization & Verification
Manufacturability checks
Manufacturing data prep.
Constraints-driven layout
Shape editing
Automated routing
EM analysis
Cadence Virtuoso®-Based RF IC Design and
Implementation Flow
MATLAB/Simulink
System
Design
System-to-RFIC
VSE
/ ADE / MMSIM
Verilog-A(MS),
Standard/Custom
Specification
Sign-offLibraries
Testbenches
SOI Details
Block Implementation
Circuits
Models
Calibrated
VDCM
HDL Models
Package
Allegro
RF
Design
SiP
E-M Component
Analysis & Design
Virtuoso
MMSIM / AMS
Designer
Continuous
Design
Hierarchy
Editor
Evolution
Models
Virtuoso Schematic
Schematic Capture
Editor L/XL
Circuit
ADE Design
GXL
MMSIM
and Simulation
(Spectre)
Block Layout
Layout XL
Virtuoso
Assura
DRC/LVS/ERC
DRC/LVS
Parasitic Extraction
QRC
and Re-simulation
Virtuoso
GXL
Top-level
Assura&&Verification
QRC
Integration
Design
Constraints
Tape Out
10/21/2009
Device modeling:
Floating body effects,
LF noise, sidewall and
oxide capacitances
(BSIMSOI)
Additional DRC rules:
Bulk terminal handling,
substrate coupling
analysis, parasitic C
handling
Cadence Product Platforms
Custom Point of View
Digital Point of View
Digital
Verification
Full Custom
Verification/
Implementation
Incisive®
Digital
Implementation
Virtuoso®
Encounter®
Silicon/Package/Board Integration
Allegro®
10/21/2009
Mixed-Signal Design Implementation
Analog
P
Analog
P
Analog
RF
Support full custom
objects: PCells,
MPPs, guard rings
Analog
Analog portions
locked for editing
and floorplanner
adjusts digital
Digital connectivity
automatically
maintained during
custom editing
Digital
Analog
RF
Digital
Analog
OpenAccess: Each domain understands
the other without translation
10/21/2009
P
Analog
View full custom
layers Poly,
Diffusion, etc
Virtuoso
P
Analog
Encounter
Advanced Process Support for RF Design
• Mature Process Design Kits (PDKs)
– Provides RF/AMS Design Flow Enablement
– Minimum Required Content:
•
•
•
•
Technology Files
Component Libraries
Device Model Libraries
DRC/LVS/ERC/Layout Finishing Rule Decks
– Available Directly from the Foundries
– “Hides” many of the SOI-Specific Implementation Details
• Cadence Methodology Kits and Foundation Flows
– Most Applicable to RF Design Challenges:
• RF, RF SiP, and AMS Methodology Kits
• AMS Foundation Flow
– Offer:
• Detailed Flow Documentation Covering Best Practices
• Reference Design Examples (RDKs) on a Generic Representative
Process (Unfortunately these are Bulk CMOS processes)
– Free…to Cadence Customers
10/21/2009
Cadence AMS Foundation Flow (AMSFF)
Reference Design Database (RDK)
802.11b Frac-N PLL – Generic 90nm CMOS
10/21/2009
Summary
• SOI CMOS Offers Compelling Opportunities for RF SoCs
– Performance Advantages
– Integration Advantages
• Minor Differences in Design Challenges Compared to Bulk CMOS
– No Changes to the RF/AMS IC Design and Implementation Flows
– Same Design Tool Suites Used for Both Technologies
– Most Technology-Specific Differences Captured within the Confines of the
PDK
• SOI CMOS PDKs and Training Available from Multiple Sources
• RF and AMS Methodology Kits Available Assisting the Adoption of
Latest Advanced Flows for General Custom IC Design and
Implementation Challenges
10/21/2009
The Art of Engineering, AMPLIFIED
®
Thank-You!
©2006 Cadence Design Systems, Inc.