CMOS-MEMS Variable Capacitors for Reconfigurable RF Circuits
Submitted in partial fulfillment of the requirements for
the degree of
Doctor of Philosophy
in
Electrical and Computer Engineering
John R. Reinke
B.E.E., Electrical Engineering, University of Minnesota
M.S., Electrical Engineering, Carnegie Mellon University
Carnegie Mellon University
Pittsburgh, PA
May, 2011
© John Reinke 2011
All rights reserved.
ii
Acknowledgements
First, I am grateful to Tamal Mukherjee and Gary Fedder for serving as my advisors during
my graduate studies at Carnegie Mellon University. Their guidance has been invaluable, and their
commitment to producing quality students has made the CMU MEMS lab a nurturing
environment. Their sense of humor and understanding helped immensely during the inevitable
frustrations of research.
My colleagues from the MEMS lab have been both helpful and entertaining. Leon Wang has
provided many important insights as he served as resident circuits guru. Peter Gilgunn has
inspired me to work harder and always strive for excellence. Nathan Lazarus and Yu-Jen Fang
were always willing to participate in random musings about science and technology. Abhishek
Jajoo, Sarah Bedair, and Fernando Alfaro helped me get my research off the ground. Amy Wung
and Kristen Dorsey deserve much credit for actually trying to foster a social environment within
the lab.
Many thanks to Suresh Santhanam and the staff of the Nanofabrication Facility for the many
CMOS-MEMS chips they have fabricated. They have battled through phenomenon such as the
mystery gunk and always managed to produce quality devices.
Last but certainly not least, I am thankful for the support of my family back home in
Minnesota. My family has been a needed refuge during holidays and vacations. I am truly lucky
to have them in my life.
This work was funded by the Industrial Technology Research Institute (ITRI) and by
government support under and awarded by DoD, Air Force Office of Scientific Research,
National Defense Science and Engineering Graduate (NDSEG) Fellowship, 32 CFR 168a.
iii
Abstract
Microelectromechanical systems (MEMS) variable capacitors have demonstrated excellent
performance in terms of tuning ratio and quality factor (Q) at radio frequencies (RF). These
characteristics can enhance existing RF circuits and enable frequency-reconfigurable circuits.
However, MEMS are typically not monolithically integrated with complementary metal-oxidesemiconductor (CMOS) processes. To achieve integration with CMOS, this work uses maskless
post-CMOS processing to create two types of CMOS-MEMS variable capacitors, the gap-tuning
capacitor and the digital capacitor. To show that these capacitors enable frequency-reconfigurable
circuits, the digital capacitor was used to develop the first CMOS-MEMS phase shifter.
The CMOS-MEMS gap-tuning capacitor uses lateral electrothermal actuation to control the
gap between electrodes. A mechanical latch maintains the capacitance without consuming static
power. This capacitor achieved series and shunt tuning ratios up to 6.9:1 and 5.7:1, respectively,
with a Q of 80 at 1 GHz. Millions of actuation cycles were demonstrated without failure
However, the gap-tuning capacitor had several disadvantages, specifically large device variation,
a non-linear distribution of capacitance values, and low capacitance density, which inspired
development of the digital capacitor.
The CMOS-MEMS digital capacitor consists of many switched capacitors that are organized
into capacitive bits to produce a linear distribution of capacitance values. This capacitor uses
both vertical electrothermal actuation and lateral electrostatic actuation to achieve large tuning
ratios without sacrificing capacitance density. The maximum capacitance state is maintained by
electrostatic force to prevent static power consumption. The digital capacitor achieved series and
shunt tuning ratios up to 73:1 and 19:1, respectively, with a Q of 369 at 1 GHz. Compared with
that of the gap-tuning capacitor, the capacitance density was increased by 5x and the device
variation was reduced by 4x. Reliability tests revealed evidence of mechanical fatigue after
iv
millions of actuation cycles, but no catastrophic failures occurred.
The CMOS-MEMS phase shifter consists of a micromachined transmission line periodically
loaded with digital capacitors. The digital capacitors were modified to achieve a shunt tuning
ratio of 7.2:1 with a Q of 18.8 at 30 GHz. The phase shifter produced an average insertion loss
and maximum phase shift of 2.9 dB and 337.5°, respectively, at 32 GHz.
v
Table of Contents
Chapter 1. Introduction ............................................................................................................... 1
1.1. Motivation ........................................................................................................................ 1
1.2. MEMS Variable Capacitors ............................................................................................. 2
1.3. Thesis Statement .............................................................................................................. 9
1.4. Contributions .................................................................................................................. 10
Chapter 2. CMOS-MEMS Background.................................................................................... 12
2.1. CMOS-MEMS Process .................................................................................................. 12
2.2. Electrothermal Actuation ............................................................................................... 17
Chapter 3. Gap-tuning Capacitor .............................................................................................. 23
3.1. Motivation ...................................................................................................................... 23
3.2. Topology ........................................................................................................................ 28
3.3. Analysis .......................................................................................................................... 33
3.4. Design............................................................................................................................. 38
3.5. Characterization ............................................................................................................. 41
3.6. Discussion ...................................................................................................................... 57
Chapter 4. Digital Capacitor ..................................................................................................... 61
4.1. Motivation ...................................................................................................................... 61
4.2. Topology ........................................................................................................................ 64
4.3. Analysis .......................................................................................................................... 67
4.4. Design............................................................................................................................. 74
4.5. Characterization ............................................................................................................. 78
4.6. Discussion ...................................................................................................................... 99
Chapter 5. Phase Shifter ......................................................................................................... 102
5.1. Motivation .................................................................................................................... 102
5.2. Topology ...................................................................................................................... 104
5.3. Analysis ........................................................................................................................ 108
5.4. Design........................................................................................................................... 111
5.5. Characterization ........................................................................................................... 114
5.6. Discussion .................................................................................................................... 123
Chapter 6. Conclusions ........................................................................................................... 126
6.1. Summary ...................................................................................................................... 126
6.2. Contributions ................................................................................................................ 128
6.3. Future Work ................................................................................................................. 130
6.4. Final Thoughts.............................................................................................................. 135
References ................................................................................................................................... 137
Appendix A. Electrical Characterization ................................................................................ 142
A.1. Network Analyzer Settings .......................................................................................... 142
A.2. Open-short De-embedding ........................................................................................... 143
A.3. Extracting an Equivalent Circuit Model....................................................................... 145
A.4. Matlab Code ................................................................................................................. 157
Appendix B. List of Cadence Layouts .................................................................................... 166
vi
List of Tables
Table 1.1: Variable Capacitor Characteristics ................................................................................ 6
Table 3.1: Gap-Tuning Capacitor Design Parameters .................................................................. 40
Table 3.2: Electrical Characteristics of the Gap-tuning Capacitor ............................................... 45
Table 3.3: Gap-Tuning Capacitor Results..................................................................................... 58
Table 4.1: Digital Capacitor Design Parameters ........................................................................... 77
Table 4.2: Electrical Characteristics of the Initial Digital Capacitor ............................................ 83
Table 4.3: Electrical Characteristics of the Updated Digital Capacitor ........................................ 98
Table 4.4: Digital Capacitor Results ........................................................................................... 100
Table 5.1: Phase Shifter Design Parameters ............................................................................... 112
Table 5.2: Electrical Characteristics of the Phase Shifter Digital Capacitor .............................. 118
Table 5.3: Electrical Characteristics of the Phase Shifter ........................................................... 122
Table 5.4: Comparison of Phase Shifters .................................................................................... 124
Table 6.1: Comparison of Integrated Variable Capacitors.......................................................... 129
Table B.2: List of Cadence Libraries .......................................................................................... 166
Table B.1: List of Cadence Layouts ............................................................................................ 166
vii
List of Figures
Fig. 1.1. Diagram of capacitance tuning by changing the (a) gap (b) overlap area (c) dielectric.
All capacitors have length L, width W, and gap g before part of the structure undergoes
displacement d. Capacitance calculations ignore the effects of fringing fields. ............................. 2
Fig. 2.1. Cross-section of the CMOS-MEMS process flow (a) beginning with CMOS chip (b)
after the vertical oxide etch (c) after the vertical silicon etch (d) after silicon release etch. ......... 13
Fig. 2.2. SEM image of (a) 20 µm squared released from the substrate (b) 60 µm square anchored
to the substrate. These test structures were fabricated using the 0.18 µm BiCMOS process from
TowerJazz. .................................................................................................................................... 14
Fig. 2.3. Diagram of a vertical electrothermal actuator beam. The polysilicon resistor for heating
can either be lumped near the anchor point or distributed along the length of the actuator beam.20
Fig. 2.4. Diagram of a lateral electrothermal actuator beam. The offset metal layers are switched
to the opposite side of the beam halfway along the length to produce guided-end motion at the
tip. ................................................................................................................................................. 21
Fig. 2.5. Microscope image of lateral electrothermal actuator (a) deflected due to residual stress
(b) after heating. (c) Focused-ion beam image of electrothermal actuator beam cross-section. ... 22
Fig. 3.1. Concept of the actuation method for the gap-tuning capacitor. ...................................... 24
Fig. 3.2. SEM image of the (a) 1st (b) 2nd (c) 3rd (d) 4th design of the gap-tuning capacitor. ........ 25
Fig. 3.3. Vertical misalignment of capacitive beams viewed as (a) SEM image (b) diagram. The
observed vertical misalignment is not as exaggerated as in the diagram but still significant
enough to affect the tuning ratio. .................................................................................................. 26
Fig. 3.4. SEM image of the (a) 1st (b) 2nd (c) 3rd design of the mechanical latch for gap-tuning
capacitors. ..................................................................................................................................... 27
Fig. 3.5. Diagram of gap-tuning capacitor. Arrows denote the directions of self-assembly and
electrothermal actuation displacements for both the gap and latch actuators. Resistor symbols
indicate the location of embedded polysilicon resistors used for electrothermal actuation. The
specific numbers of capacitive, actuator, and interconnect beams are not representative of the
numbers of beams used in the actual device. ................................................................................ 28
Fig. 3.6. Vertical curling of CMOS-MEMS beams. Anchoring MEMS beams at a common
location prevents vertical misalignment. ...................................................................................... 29
Fig. 3.7. SEM image of the mechanical latch for the gap-tuning capacitor. As pictures, the latch
is engaged in an intermediate capacitance position, neither minimum nor maximum capacitance.
....................................................................................................................................................... 31
Fig. 3.8. SEM image of the gap actuator for the gap-tuning capacitor. The shading of the actuator
beams changes half-way along their length because the offset metal layers are switched to the
other side of the beams. ................................................................................................................ 31
Fig. 3.9. Thermal isolation unit viewed as (a) SEM image (b) cross-section diagram. The metal 3
and metal 4 pictured in the diagram are not floating; these metals are connected to ground along a
different cross-section. .................................................................................................................. 32
Fig. 3.10. Cross-section of CMOS-MEMS beams used in the electrothermal gap-tuning
capacitor. ....................................................................................................................................... 33
Fig. 3.11. Diagram of capacitive beams for displacement x. ........................................................ 34
Fig. 3.12. Electric field magnitude for cross-sections of capacitive beams in both minimum and
maximum capacitance positions. The white, unmeshed areas represent the discrete metal layers
of the CMOS-MEMS beams. ........................................................................................................ 35
viii
Fig. 3.13. Capacitance per unit length as a function of vertical offset for different gaps. Vertical
misalignment between capacitive beams has a much larger impact when the gap is small. ........ 36
Fig. 3.14. SEM image of CMOS-MEMS variable capacitor. ....................................................... 41
Fig. 3.15. Microscope image of the gap-tuning capacitor in (a) maximum capacitance position (b)
minimum capacitance position. The latch appears retracted because voltage was applied to the
heating resistors in the latch actuator. ........................................................................................... 42
Fig. 3.16. Microscope image of the latch at position (a) 1 (b) 2 (c) 3 (d) 4 (e) 5 (f) 6. Each
position corresponds to a different capacitance value at which the variable capacitor can be
maintained without consuming power. ......................................................................................... 42
Fig. 3.17. Microscope image of capacitive beams pushed into mechanical contact (a) for the bestperforming capacitor (b) for a capacitor with significant lateral curling. The amount of curling is
small but still has significant effects of the minimum effective air gap. ...................................... 42
Fig. 3.18. Optical profilometer image of electrothermal gap-tuning capacitor. The capacitive
beams are vertically aligned to within 1.6 µm. ............................................................................. 43
Fig. 3.19. S-parameter magnitude as a function of frequency for (a) the minimum capacitance
position (b) the maximum capacitance position. S12 is not plotted because S12 and S21 are
equivalent for passive networks. ................................................................................................... 44
Fig. 3.20. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements.
Circuit element values are extracted from measured 2-port network parameters. ........................ 44
Fig. 3.21. Lumped impedances as a function of frequency for (a) the minimum capacitance
position (b) the maximum capacitance position. The series impedance behaves like an RLC
circuit, and the shunt impedances are capacitive below 10 GHz. The self-resonance frequency is
greater than 20 GHz for the minimum capacitance position and decreases to 11 GHz for the
maximum capacitance position. .................................................................................................... 44
Fig. 3.22. Quality factor as a function of frequency. This plot shows the Q for the maximum
capacitance position. ..................................................................................................................... 47
Fig. 3.23. Plot of series capacitance versus latch position. Error bars indicate the 1-σ standard
deviation between different devices based on 7 measurements. ................................................... 48
Fig. 3.24. Capacitance as a function of actuator voltage. Continuous tuning is possible with the
latch retracted. Hysteresis is caused by capacitive beams sticking together as they are being
pulled apart.................................................................................................................................... 48
Fig. 3.25. Capacitance as function of DC bias voltage. With the latch retracted (unlatched),
capacitance beams snap together using less than 5 V. With the latch in place, up to 14 V can be
applied before electrostatic pull-in occurs. ................................................................................... 49
Fig. 3.26. Electrothermal actuator frequency response. The thermal 3 dB frequency limits the
speed of both the gap and latch actuators. .................................................................................... 51
Fig. 3.27. Electrothermal actuator transient response. The 90% rise time is 4.9 ms. .................. 51
Fig. 3.28. Temperature profile of gap-tuning capacitor viewed with quantum infrared
microscope. Voltage is applied to resistors in (a) the gap actuator only (b) the latch actuator only
(c) both the gap and latch actuators. ............................................................................................. 54
Fig. 3.29. Latched capacitance as a function of ambient temperature. While latched in position,
the capacitance remains stable up to 65°C. ................................................................................... 55
Fig. 3.30. Minimum and maximum capacitance as a function of actuation cycles for two DUT‟s.
Maximum capacitance decreased as the variable capacitor was cycled between latch positions. 57
Fig. 3.31. SEM images of mechanical latch after failure (a) zoomed out (b) zoomed in. Repeated
impacts of the latch interface created sub-micron debris on the latch. ......................................... 57
Fig. 4.1. Concept of the actuation method for the switched capacitor. ......................................... 62
ix
Fig. 4.2. Diagram of CMOS-MEMS switched capacitor viewed from above (a) with annotations
(b) with circuit schematic; (c) SEM image of four CMOS-MEMS switched capacitors in parallel.
....................................................................................................................................................... 64
Fig. 4.3. Steady-state thermal circuit for the CMOS-MEMS switched capacitors. ...................... 66
Fig. 4.4. Cross-section of the switched capacitor along the rotor electrode. ................................ 67
Fig. 4.5. Diagram of CMOS-MEMS switched capacitor viewed (a) from above with nominal
layout dimensions (b) from the side with the rotor electrode deflected vertically into minimum
capacitance position. Line A–A’ and line B–B’ show the positions of the cross-sections along the
rotor electrode and stator electrode, respectively. ......................................................................... 68
Fig. 4.6. Normalized parameters as a function of MIM capacitor length. Tuning ratio and
capacitance density are normalized to their respective values for the optimum MIM capacitor
length of 35 µm. ............................................................................................................................ 75
Fig. 4.7. Normalized parameters as a function of actuator beam length. Tuning ratio, capacitance
density, and quality factor are normalized to their respective values for an actuator beam length
of 90 µm to illustrate the tradeoffs necessary for increased tuning ratios. ................................... 76
Fig. 4.8. SEM image of 3-bit digital capacitor. Bits are separated by dummy structures to
improve the temperature uniformity of the electrothermal actuators. Floating electrodes appear
darker due to charging................................................................................................................... 78
Fig. 4.9. Microscope picture of CMOS-MEMS switched capacitors (a) in minimum capacitance
position before actuation (rotor electrodes are deflected out of focus) (b) after electrothermal
actuation (c) in maximum capacitance position after electrostatic actuation. .............................. 79
Fig. 4.10. Profilometer image of bit 3 of the digital capacitor (a) before actuation (b) after
actuation. The rotor beams are not visible when deflected upwards because their angle with
respect to the chip surface is too large for their profile to be captured by the Wyko unless settings
are modified which sacrifice the quality of the image. ................................................................. 79
Fig. 4.11. Microscope image of the 3-bit digital capacitor in state (a) 0 (b) 1 (c) 2 (d) 3 (e) 4 (f) 5
(g) 6 (h) 7. Each capacitive bit is controlled independently to select the desired capacitance. .... 80
Fig. 4.12. S-parameter magnitude as a function of frequency for (a) the minimum capacitance
state (b) the maximum capacitance state. S12 is not plotted because S12 and S21 are equivalent for
passive networks. .......................................................................................................................... 82
Fig. 4.13. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements.
Circuit element values are extracted from measured 2-port network parameters. ........................ 82
Fig. 4.14. Lumped impedances as a function of frequency for (a) the minimum capacitance state
(b) the maximum capacitance state. The behavior of |1/(Y11+Y12)| is explained by silicon
remaining beneath the suspended MIM capacitor. The self-resonance frequency is greater than 40
GHz for the minimum capacitance position and decreases to 11.4 GHz for the maximum
capacitance position. ..................................................................................................................... 82
Fig. 4.15. Quality factor as a function of frequency. This plot shows the Q for the maximum
capacitance position with port 2 connected to ground. ................................................................. 84
Fig. 4.16. Plot of series capacitance versus state. Error bars indicate the 1-σ standard deviation
between different devices based on 7 measurements. ................................................................... 85
Fig. 4.17. Plot of series capacitance during an actuation cycle. The x-axis is arbitrary; all
measured points shown were allowed to reach steady-state and maintained for approximately one
minute. “Electrothermal” and “electrostatic” are abbreviated as “ET” and “ES”, respectively. The
plotted data represents a single actuation cycle from a single device and thus may vary over time
or between different devices. ........................................................................................................ 86
Fig. 4.18. Electrothermal actuator frequency response. ................................................................ 87
x
Fig. 4.19. Simulated temperature profile of electrothermal actuator. Symmetry boundary
conditions are applied so the simulation represents an array of many switched capacitors in
parallel........................................................................................................................................... 89
Fig. 4.20. Series capacitance of a 3-bit digital capacitor as a function of ambient temperature. .. 91
Fig. 4.21. SEM images of surface damage caused by repeated temperature cycling at 250°C. The
white boxes indicate the locations of the embedded heating resistors. ......................................... 92
Fig. 4.22. Vertical gap during heating as a function of the number of actuation cycles. A positive
gap indicates that the tip of the rotor electrodes are deflected above the stator electrodes. ......... 93
Fig. 4.23. Diagram of capacitive bit with (a) interwoven actuator beams resulting in large
parasitic capacitance (b) updated topology to reduce parasitic capacitance. ................................ 95
Fig. 4.24. SEM image of 3-bit digital capacitor updated to reduce parasitic capacitance. The
chunk of debris was left in place since manual removal could damage the actuators. ................. 96
Fig. 4.25. Microscope image of the updated 3-bit digital capacitor in state (a) 0 (b) 1 (c) 2 (d) 3
(e) 4 (f) 5 (g) 6 (h) 7. Each capacitive bit is controlled independently to select the desired
capacitance. ................................................................................................................................... 96
Fig. 4.26. S-parameter magnitude as a function of frequency for (a) the minimum capacitance
state (b) the maximum capacitance state. S12 is not plotted because S12 and S21 are equivalent for
passive networks. .......................................................................................................................... 97
Fig. 4.27. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements.
Circuit element values are extracted from measured 2-port network parameters. ........................ 97
Fig. 4.28. Lumped impedances as a function of frequency for (a) the minimum capacitance
position (b) the maximum capacitance position. The series impedance behaves like an RLC
circuit, and the shunt impedances are capacitive below 10 GHz. The self-resonance frequency is
greater than 40 GHz for the minimum capacitance position and decreases to 10 GHz for the
maximum capacitance position. .................................................................................................... 97
Fig. 4.29. Quality factor as a function of frequency for the updated digital capacitor. This plot
shows the Q for the maximum capacitance position with port 1 connected to ground. ............... 99
Fig. 5.1. Schematic of phased antenna array. Phase shifters create a variable time delay between
antennas to enable electronic beam steering. .............................................................................. 103
Fig. 5.2. Schematic of distributed MEMS phase shifter (for N = 3 sections) as (a) distributed
components (b) lumped component (c) lumped components with a single shunt capacitances. 104
Fig. 5.3. Diagram of the CMOS-MEMS switched capacitor viewed from above (a) with
annotations (b) with circuit schematic; (c) SEM image of eight CMOS-MEMS switched
capacitors in parallel. .................................................................................................................. 105
Fig. 5.4. Cross-section of the phase shifter (a) along the rotor electrode of a switched capacitor
(b) along a section of transmission line without a switched capacitor........................................ 106
Fig. 5.5. Schematic of 4-bit digital capacitor used in the phase shifter. ..................................... 107
Fig. 5.6: SEM image of phase shifter digital capacitor. The rotor electrodes are vertically
deflected into the minimum capacitance state. “D” indicates dummy bits which are included for
temperature uniformity. .............................................................................................................. 113
Fig. 5.7: SEM image of one CMOS-MEMS phase shifter section. ............................................ 114
Fig. 5.8: SEM image of the CMOS-MEMS phase shifter composed of eight phase shifter
sections. ....................................................................................................................................... 114
Fig. 5.9: Microscope image of CMOS-MEMS digital capacitor (a) before actuation (b) after
actuation in state 10 (1010) with bits 4 and 2 turned on. ............................................................ 115
xi
Fig. 5.10. S-parameter magnitude as a function of frequency for (a) the minimum capacitance
state (b) the maximum capacitance state. S12 is not plotted because S12 and S21 are equivalent for
passive networks. ........................................................................................................................ 116
Fig. 5.11. Equivalent circuit model in terms of (a) Z-parameters and (b) lumped circuit elements.
Circuit element values are extracted from measured 2-port network parameters. ...................... 117
Fig. 5.12. Lumped impedances as a function of frequency for (a) the minimum capacitance
position (b) the maximum capacitance position. The series impedance behaves like an RLC
circuit, and the shunt impedances are capacitive below 10 GHz. The self-resonance frequency is
greater than 40 GHz for the minimum capacitance position and decreases to 10 GHz for the
maximum capacitance position. .................................................................................................. 117
Fig. 5.13. Quality factor as a function of frequency for the digital capacitor used in the phase
shifter. This plot shows the Q for the maximum capacitance position with port 2 left floating. 119
Fig. 5.14: Capacitance of phase shifter digital capacitor as a function of state. State 3 (0011)
indicates that the two least significant bits are turned on. .......................................................... 120
Fig. 5.15: Measured phase shift as a function of frequency for all 16 states. Phase shift is negative
because the time delay increases with increasing capacitance. ................................................... 121
Fig. 5.16: Measured insertion loss as a function of frequency for all 16 states. ......................... 121
Fig. 5.17: Measured reflection as a function of frequency for all 16 states. ............................... 122
Fig. 5.18. S-parameter magnitude as a function of frequency for (a) the minimum phase shift
state (b) the maximum phase shift state. S12 is not plotted because S12 and S21 are equivalent for
passive networks. ........................................................................................................................ 123
Fig. 5.19: Comparison of passive phase shifters. The average insertion loss is plotted versus the
minimum operating frequency. ................................................................................................... 124
Fig. A.1. Layout view of (a) open test structure (b) short test structure (c) DUT. Measurements of
the open and short test structures are necessary to remove the parasitic effects of the probe pads
using open-short de-embedding. „G‟ and „S‟ represent „ground‟ and „signal‟, respectively. ..... 143
Fig. A.2. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements.
Circuit element values are extracted from measured 2-port network parameters. ...................... 147
Fig. A.3. Lumped impedance magnitude as a function of frequency for the maximum capacitance
position. The extracted model is compared with measured data. ............................................... 147
Fig. A.4. Series capacitance as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 148
Fig. A.5. Series resistance as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 148
Fig. A.6. Shunt capacitances as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 149
Fig. A.7. Quality factor as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 150
Fig. A.8. S-parameter magnitude as a function of frequency. The extracted model is compared
with measured data. S12 is not plotted because S12 and S21 are equivalent for passive networks.
..................................................................................................................................................... 151
Fig. A.9. Equivalent circuit model in terms of (a) Z-parameters and (b) lumped circuit elements.
Circuit element values are extracted from measured 2-port network parameters. ...................... 152
Fig. A.10. Lumped impedance magnitude as a function of frequency. The extracted model is
compared with measured data. .................................................................................................... 152
Fig. A.11. Capacitance to ground as a function of frequency. The extracted model is compared
with measured data. .................................................................................................................... 153
xii
Fig. A.12. Shunt resistance as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 153
Fig. A.13. Series resistances as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 154
Fig. A.14. Series inductances as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 155
Fig. A.15. Quality factor as a function of frequency. The extracted model is compared with
measured data.............................................................................................................................. 156
Fig. A.16. S-parameter magnitude as a function of frequency. The extracted model is compared
with measured data. S12 is not plotted because S12 and S21 are equivalent for passive networks.
..................................................................................................................................................... 156
xiii
Chapter 1.
Introduction
This chapter introduces the subject of CMOS-MEMS variable capacitors by outlining the
motivation and goals of this work. Section 1.1 proposes multi-band radio as the motivation for
developing MEMS variable capacitors. Section 1.2 explains why CMOS-MEMS variable
capacitors are necessary when semiconductor variable capacitors are readily available. The thesis
statement is presented in Section 1.3, and the contributions of this work are listed in Section 1.4.
1.1. Motivation
Consumer radio systems are transmitting and receiving data over an increasing number of
frequency bands. Modern cellular phones use four different frequency bands for transmitting
voice and a fifth frequency band for wireless local area networking [1]. Multiple frequency bands
are required to provide different functions and so that the total bandwidth is large enough to
accommodate many users. Multi-band operation is currently achieved by using multiple narrowband circuits, each of which is capable of operation over a single frequency band. For example,
dual- and quad-band receivers simply include two or four low-noise amplifiers, respectively [2],
[3]. Similarly, dual-band and quad-band transmitters require two or four power amplifiers,
respectively [4], [1]. As the trend for operation over more frequency bands continues, the current
implementation of multi-band radio systems requires more circuits and thus becomes more
expensive.
To reduce the cost of multi-band radio, there are two possible solutions: wide-band circuits
and reconfigurable circuits. Wide-band circuits with a bandwidth spanning multiple frequency
bands would eliminate the need for multiple circuits, but the performance of wide-band circuits
is inferior to that of narrow-band circuits. The ideal solution is reconfigurable circuits, which are
Chapter 1: Introduction
1
tunable narrow-band circuits capable of reconfiguration between different frequency bands.
Reconfigurable circuits have the potential to eliminate the need for multiple circuits while
providing performance typical of narrow-band circuits.
The performance of reconfigurable circuits has been limited by the available tunable
devices. Because many devices must be integrated onto a single CMOS chip to minimize cost,
the tunable devices available at RF are semiconductor variable capacitors. These variable
capacitors perform poorly when designed for large tuning capabilities. To enable reconfigurable
circuits for multi-band radio, this work proposes to use MEMS variable capacitors.
Gap Tuning
d
g–d
C
 0 LW
g d
Area Tuning
d
C
Movable Dielectric
Metal
L–d
d
 0 L  d W
g
C
L–d
 0 d   r L  d W
g
Dielectric (εr > 1)
All objects
have width W
into the page
(a)
(b)
(c)
Fig. 1.1. Diagram of capacitance tuning by changing the (a) gap (b) overlap area (c) dielectric. All capacitors have
length L, width W, and gap g before part of the structure undergoes displacement d. Capacitance calculations ignore
the effects of fringing fields.
1.2. MEMS Variable Capacitors
MEMS variable capacitors are electrical devices whose capacitance value is controlled
through mechanical actuation. Capacitance tuning is accomplished by mechanically changing the
gap [5], overlap area [6], or dielectric [7] between the capacitive electrodes (see Fig. 1.1).
Depending on the nature of the actuation, the tuning range can be continuous from minimum
capacitance to maximum capacitance or consist of a set of achievable discrete capacitance values.
Devices with continuous tuning range are often referred to as variable capacitors or varactors
Chapter 1: Introduction
2
whereas devices with two states, on and off, are referred to as capacitive switches or switched
capacitors. Devices that achieve many discrete capacitance values by using many independently
controlled switched capacitors are referred to as digital capacitors.
1.2.1. Characteristics of MEMS Variable Capacitors
The electrical performance of MEMS variable capacitors is described by three primary
metrics. The tuning ratio, TR, is the ratio of maximum capacitance, Cmax, to minimum
capacitance, Cmin.
TR 
C max
C min
.
(1.1)
The quality factor, Q, is the ratio of energy stored to energy dissipated when charge is stored on
a capacitor. Typically, Q is limited by the series resistance, Rs, of the metal path.
Q
1
CRs
,
(1.2)
where ω is the electrical frequency and C is the capacitance. The self-resonance frequency, ωres,
is the frequency at which the variable capacitance resonates due to parasitic inductance, L.
 res 
1
LC
,
(1.3)
Above the self-resonance frequency, the total imaginary impedance is inductive meaning that the
device no longer functions as a capacitor. All three of these metrics should be maximized to
optimize a variable capacitor.
Several other characteristics of MEMS variable capacitors are also important. Capacitance
density is the ratio of the maximum capacitance to the device area, which is important when the
variable capacitor is monolithically integrated with other devices. The actuation voltage or
Chapter 1: Introduction
3
actuation power is the specified voltage or power required for mechanical actuation. Switching
time is the time required to change the capacitance, which can differ depending on the state of
the variable capacitance. For example, the turn-on time of switched capacitors is often different
from the turn-off time. Reliability is the measure of the lifetime of a variable capacitor, often
characterized by the number of actuation cycles achieved before failure. Power handling is
defined as the maximum power that can be transmitted through the variable capacitors, typically
assuming a 50-Ω source and load impedance. Power handling is limited by either the maximum
voltage or maximum current a variable capacitor can tolerate. Linearity refers to the relationship
between the voltage applied across the capacitor terminals and the stored electrical charge.
Ideally, the charge increases linearly with applied voltage, but all capacitors are nonlinear to
some extent. The linearity of a variable capacitor is often characterized by measuring the 3rdorder input-referred intercept power (IIP3) of a circuit using that variable capacitor.
The mechanical actuation of MEMS variable capacitors can be electrostatic, electrothermal,
piezoelectric, or magnetic. Actuation characteristics vary according to the particular actuator
design, but several generalizations can be stated about the actuation types that hold true for most
designs. Electrostatic actuation produces small displacements (< 10 µm) using high actuation
voltages (> 10 V). The other three types of actuation, electrothermal actuation, piezoelectric
actuation, and magnetic actuation, are at first glance superior because those types produce large
displacements (> 10 µm) using low actuation voltages (< 10 V). Large displacements are
required for high tuning ratios, and low actuation voltages are desirable so that the variable
capacitor can be easily controlled. However, piezoelectric actuation and magnetic actuation are
limited because those two types require piezoelectric and magnetic materials, respectively, which
are difficult to integrate with semiconductors. In contrast, electrostatic actuation and
Chapter 1: Introduction
4
electrothermal actuation can be used with any MEMS technology because those two types of
actuation only require materials that are electrically conductive. Electrothermal actuation requires
power for heating, typically on the order of milliwatts, and the switching time is limited by the
thermal time constant, typically on the order of milliseconds. Because electrical time constants
are on the order of nanoseconds, the switching time of electrostatic actuation is limited only by
the mechanical response, typically on the order of microseconds. Electrostatic actuation is by far
the most popular type of MEMS actuation because the choice of materials is virtually unlimited,
the power consumption is negligible, and the switching time is fast.
1.2.2. Advantages of MEMS Variable Capacitors
Because semiconductor variable capacitors are more mature than MEMS variable
capacitors, semiconductor variable capacitors must be discussed to illustrate the advantages of
MEMS variable capacitors. The three types of semiconductor variable capacitors available in a
standard CMOS process are the diode varactor, the metal-oxide-semiconductor (MOS) varactor,
and the switched metal-insulator-metal (MIM) capacitor. All three of these types have switching
times on the order of nanoseconds and large capacitance densities (> 100 pF/mm2). The diode
varactor and the MOS varactor have high Q‘s (> 100 at 1 GHz), but the tuning ratios of these
varactors are small (< 5:1). Both varactors are fundamentally nonlinear devices because the
varactors only have two electrical terminals such that the applied voltage directly affects the
capacitance value. The switched MIM capacitor, which consists of a MIM capacitor in series
with the channel of a metal-oxide-semiconductor field-effect transistor (MOSFET), has a third
terminal, the gate of the MOSFET, which controls the capacitance and thus is more linear.
Switched MIM capacitors can be designed for large tuning ratios (> 5:1), but Q decreases as the
Chapter 1: Introduction
5
tuning ratio increases. This tradeoff occurs because, for large tuning ratios, the MOSFET must be
small to minimize parasitic capacitance, but a small MOSFET has high channel resistance, which
degrades the Q. None of the semiconductor variable capacitors can simultaneously achieve both
large tuning ratio (> 10:1) and high Q (> 100 at 1 GHz).
TABLE 1.1: VARIABLE CAPACITOR CHARACTERISTICS
Parameter
Switched MIM
Capacitor
University of
University of
University of
Imperial
California– Los California – San California – San College London
Angeles [8]
Diego [9]
Diego [10]
[11]
MEMS
MEMS
MEMS
MEMS
8.6 pF
192 fF
1.00 pF
600 fF
270 fF
63 fF
51 fF
60 fF
Type
CMOS
Cmax
1.11 pF
Cmin
111 fF
Shunt Tuning
10:1
31:1
3.0:1
Ratio
Q at 1 GHz*
9
9
1940
FoM
90
279
5820
(TRshunt*Q)
Self-Resonance
NA
2.7 GHz
> 30 GHz
Frequency*
Capacitance
1000 pF/mm2
NA
≈ 9.5 pF/mm2
Density
Switching
MOSFET
Electrostatic
Electrostatic
Method
Tuning Range
Digital
Analog
Digital
Switching Time
~ 1 ns
NA
< 0.5 µs
Actuation
3.3 V
40 V
32 V
Voltage
Actuation
≈ 0**
≈ 0**
≈ 0**
Energy for 1 pF
* The parameter corresponds to the maximum capacitance state.
* *The power consumed for actuation is negligible.
19.6:1
10:1
265
352
5194
3520
> 10 GHz
17 GHz
≈ 12.8 pF/mm2
12 pF/mm2
Electrostatic
Electrostatic
Digital
8 µs
Analog
NA
40 V
30 V
≈ 0**
≈ 0**
MEMS variable capacitors have demonstrated several advantages over semiconductor
variable capacitors. For comparison, Table 1.1 presents the performance of several MEMS
variable capacitors along with that of a switched MIM capacitor simulated for the 0.35 µm
BiCMOS process from TowerJazz Semiconductor. First, MEMS variable capacitors can provide
the combination of large tuning ratio (> 5:1) and high Q (> 100 at 1 GHz). Large tuning ratios are
made possible by the mechanical displacements produced by MEMS actuators, and the Q‘s are
high because MEMS variable capacitors are composed entirely of metal. Semiconductor devices
Chapter 1: Introduction
6
are limited in Q due to their close proximity to and inclusion of silicon, which is a poor electrical
conductor at RF. The figure of merit (FoM) introduced in Table 1.1 is the product of the shunt
tuning ratio and the Q at 1 GHz for the maximum capacitance.
FoM  TRshunt * Q .
(1.4)
Second, MEMS variable capacitors are highly linear because mechanical motion is attenuated
beyond the mechanical resonance frequency, which is typically less than 10 MHz [12]. As a
result, the variable capacitance is not significantly affected by the applied RF voltage. Third, the
power handling of MEMS variable capacitors is often excellent because large voltages (> 10 V)
can be applied without causing electrical breakdown [13].
Due to their advantages, MEMS variable capacitors have been applied to both enhance
existing RF circuits and enable new applications. MEMS capacitive switches proposed to serve
as transmit-receive switches have demonstrated reduced insertion loss when compared with stateof-the-art semiconductor switches [14]. Phase shifters for phased antenna arrays have been
improved using either MEMS variable capacitors or MEMS capacitive switches [15]. MEMS
variable capacitors have been combined with fixed inductors or transmission lines to form highQ tunable resonators for a number of applications. The phase noise of voltage controlled
oscillators has been improved by replacing the semiconductor variable capacitors with MEMS
variable capacitors [16], [17]. Reconfigurable filters have been enabled by the large tuning ratios
available with MEMS variable capacitors [18]. Antenna tuners have been developed to alleviate
source-load mismatch between power amplifiers and antennas [19]. Using this work, narrowband RF circuits, specifically low-noise amplifiers [20] and power amplifiers [21], have been
made reconfigurable by MEMS variable capacitors.
However, there are drawbacks to MEMS variable capacitors. When compared with
Chapter 1: Introduction
7
semiconductor variable capacitors, MEMS variable capacitors are slow, typically switching in
milliseconds or microseconds as opposed to nanoseconds. Capacitance density is low
(< 100 pF/mm2) due to the large dimensions of the MEMS structure, which are typically on the
order of tens or hundreds of microns. For electrostatically actuated MEMS, power consumption
is negligible but the required voltage is often large, on the order of tens of volts [13]. The
opposite is true of electrothermally actuated MEMS; the required voltage is small, on the order of
volts, but power consumption is significant, on the order of tens of milliwatts [22]. Reliability is
not guaranteed since RF MEMS can fail from dielectric charging [23], mechanical creep or
fatigue, or from degradation related to repeated mechanical contact [24].
Fortunately, many of these drawbacks can either be mitigated or tolerated by the target
applications. Faster switching times are desired but not explicitly required for antenna tuners and
many reconfigurable networks. The large area consumption of MEMS is acceptable because, to
form resonators, MEMS variable capacitors are often combined with spiral inductors or
transmission lines, both of which have dimensions on the order of hundreds of microns or larger.
Large voltages for electrostatic actuation can be provided by on-chip CMOS charge pumps if
high voltage CMOS is available [25]. Mechanical latches or electrostatic force [26] can be used
to eliminate the static power consumption of electrothermal actuation [27]. Research on the
reliability of RF MEMS has yielded methods to mitigate dielectric charging [28] and ultimately
achieve billions of actuation cycles without failure [9].
1.2.3. Monolithic Integration
Despite their excellent performance, MEMS variable capacitors are not widely used in RF
circuits because most MEMS variable capacitors are not monolithically integrated with CMOS.
Chapter 1: Introduction
8
Monolithic integration is required because the inclusion of MEMS variable capacitors into RF
circuits as discrete components is simply too expensive to warrant their use. This requirement is
challenging because MEMS fabrication is complicated by the need for integration.
The structural and sacrificial layers necessary for MEMS require additional processing
beyond that of a standard CMOS process, especially when integration with CMOS is required.
Low-temperature micromachining can be used to fabricate MEMS devices directly on top of an
existing CMOS process [29]. Alternatively, MEMS can be fabricated on a separate substrate and
flip-chip bonded onto a CMOS chip [30], [31]. Both methods of integration grant the MEMS
designer the freedom to select the materials and layer thicknesses, but this freedom comes at the
cost of additional lithography steps, which ultimately increases the cost of any system using such
integrated MEMS.
To solve this problem, the post-CMOS micromachining process in [32], hereafter called the
―CMOS-MEMS process‖ can be used for monolithic integration of MEMS devices without using
additional lithography steps. The CMOS-MEMS process uses maskless, post-CMOS etching to
create MEMS devices composed of the metal-dielectric stack of a foundry CMOS process. The
resulting MEMS structure can consist of multiple metal layers connected in parallel for low
resistance. The air gap between the MEMS structure and the remaining silicon substrate is
approximately 50 µm, which minimizes parasitic capacitance to the resistive silicon. Polysilicon
resistors can be embedded within the MEMS structure to act as heaters for low-voltage
electrothermal actuation [22]. These features make CMOS-MEMS a natural choice for
integrating MEMS variable capacitors in a low-cost manner.
1.3. Thesis Statement
MEMS variable capacitors have demonstrated significant advantages over semiconductor
Chapter 1: Introduction
9
variable capacitors but are not cost-effective if included in electrical systems as discrete
components. The typical methods available for monolithically integrating MEMS variable
capacitors with CMOS require additional lithography steps, which increases cost. The CMOSMEMS process is an alternative method for integrating MEMS with CMOS without using
additional lithography steps. Thus, using the CMOS-MEMS process, CMOS-MEMS variable
capacitors can be designed with performance comparable to that of other integrated
MEMS variable capacitors and enable the design of low-cost reconfigurable RF circuits.
To assess the performance of CMOS-MEMS variable capacitors, devices were designed,
fabricated, and characterized. The electrical characteristics were measured to calculate the tuning
ratio, Q, and self-resonance frequency. Actuation methods were tested to determine the switching
times along with voltage and power requirements. The effects of repeated actuation were
analyzed to determine reliability. Results are compared with that of other integrated MEMS
variable capacitors.
To show that CMOS-MEMS variable capacitors enable the design of reconfigurable RF
circuits, a CMOS-MEMS phase shifter was designed, fabricated, and characterized. The
electrical characteristics were measured to calculate the phase shift and insertion loss. Results are
compared with that of other MEMS phase shifters.
1.4. Contributions
The first contribution of this work, the design and characterization of a CMOS-MEMS
electrothermal gap-tuning capacitor, is presented in Chapter 3. The gap-tuning capacitor uses
lateral electrothermal actuation to control the capacitive gap between interdigitated electrodes. A
mechanical latch, also controlled by electrothermal actuation, was used to maintain the capacitive
Chapter 1: Introduction
10
gap without consuming static power for heating. The gap-tuning capacitor requires 4 V and 15
mW for electrothermal actuation and can be reconfigured in 30 ms. The average measured tuning
ratio is 4.9:1, and the measured Q for the maximum capacitance state is 80 at 1 GHz. Reliability
testing demonstrated that the lifetime exceeds millions of actuation cycles.
Chapter 4 presents the second contribution of this work, the design and characterization of
CMOS-MEMS digital capacitors. The digital capacitors are composed of many independently
controlled CMOS-MEMS switched capacitors, which can be toggled on or off using a
combination of vertical electrothermal and lateral electrostatic actuation. Electrostatic force is
used to maintain the maximum capacitance state without consuming static power. The digital
capacitors can be switched in 1 ms using 4 V for electrothermal actuation and 20 V for
electrostatic actuation. The average measured tuning ratio is 61:1, and the measured Q for the
maximum capacitance state is 369 at 1 GHz. Reliability testing demonstrated millions of
actuation cycles successfully but revealed a drift in the actuation characteristics after 10 million
cycles. These digital capacitors represent the state-of-the-art for CMOS-MEMS variable
capacitors.
The design and characterization of a 4-bit CMOS-MEMS phase shifter for phased antenna
arrays is presented in Chapter 5 as the third contribution of this work. The phase shifter is
composed of a micromachined transmission line periodically loaded with CMOS-MEMS digital
capacitors. The digital capacitors are modified to achieve a Q of 18.8 at 30 GHz for the
maximum capacitance state and a tuning ratio of 7.2:1. Measured results demonstrate the
required phase shift of 337.5° at 32 GHz with an average insertion loss of 2.9 dB. This phase
shifter is the first RF MEMS phase shifter to be monolithically integrated with CMOS.
Chapter 1: Introduction
11
Chapter 2.
CMOS-MEMS Background
This chapter presents the CMOS-MEMS process that is used to fabricate the MEMS
variable capacitors presented in this work. Section 2.1 describes the process flow along with
several characteristics of CMOS-MEMS structures relevant to variable capacitors. Section 2.2
discusses how the CMOS-MEMS process is used to create both lateral and vertical
electrothermal actuators.
2.1. CMOS-MEMS Process
The CMOS-MEMS process is used to fabricate MEMS that are monolithically integrated
with standard CMOS. The process can be applied to any CMOS technology provided that the
placement of metal layers can be controlled by layout. CMOS technologies with strict metal fill
requirements cannot be used for CMOS-MEMS since the metal fill blocks the post-CMOS
etching. The CMOS-MEMS process can be applied to CMOS from different foundries and from
different technology generations, such as 0.35 µm or 0.18 µm. The CMOS-MEMS devices
fabricated for this work all use the 0.35 µm BiCMOS process from TowerJazz. This CMOS
process provides four aluminum metal layers, one thick top metal and three thin metals, one
polysilicon layer, and tungsten vias. The minimum width and spacing for the thick top metal is
2.6 µm and 1.9 µm, respectively. The minimum width and spacing for the three thin metals are
both 0.5 µm.
2.1.1. Process Flow
The CMOS-MEMS process consists of maskless, post-CMOS etching to create MEMS
structures from the metal-dielectric stack of a standard CMOS process (see Fig. 2.1) [32]. First,
Chapter 2: CMOS-MEMS
12
the exposed oxide is anisotropically etched using a CHF3/CF4/O2 reactive ion etch (RIE). During
the oxide etch, the top-most metal layer acts as a mask both to define the resulting MEMS
structure and to protect devices such as transistors which require the silicon substrate. The oxide
etch exposes the silicon surface in areas which contain no metal. Next, the exposed silicon is
anisotropically etched using an SF6/O2 RIE. This anisotropic silicon etch is necessary to create a
large vertical air gap (≈ 50 µm) between the resulting MEMS structure and the bottom of the
silicon etch pit. Finally, the silicon is etched isotropically using SF6 plasma to release the
resulting MEMS structures from the substrate. The isotropic silicon etch is timed such that
narrow structures are undercut while wide structures remain anchored to the substrate (see Fig.
2.2).
Key:
Metal 1
(a)
(b)
(c)
(d)
Metal 2
Metal 3
Metal 4
Oxide
Via
Silicon
Fig. 2.1. Cross-section of the CMOS-MEMS process flow (a) beginning with CMOS chip (b) after the vertical oxide
etch (c) after the vertical silicon etch (d) after silicon release etch.
Chapter 2: CMOS-MEMS
13
50 µm
20 µm
(a)
(b)
Fig. 2.2. SEM image of (a) 20 µm squared released from the substrate (b) 60 µm square anchored to the substrate.
These test structures were fabricated using the 0.18 µm BiCMOS process from TowerJazz.
2.1.2. CMOS-MEMS Characteristics
The CMOS-MEMS process is very flexible because a wide variety of beams can be created.
CMOS-MEMS beams can consist of a single metal layer, such as a metal-1 beam, or multiple
metal layers, such as a metal-321 beam. Beams consisting of multiple metal layers can carry
multiple independent signals or be connected in parallel to serve as low-resistance wires. Both
vias and polysilicon can be embedded within the CMOS-MEMS beams. Embedded polysilicon is
encased in oxide and thus does not etch during the isotropic silicon etch. Fig. 2.1(d) shows three
examples of released CMOS-MEMS beams. The left beam is a metal-321 beam with metal 1 and
2 offset layers. The middle beam is a metal-4321 beam with vias and polysilicon. The right beam
is a metal-1 beam.
Several characteristics of the CMOS-MEMS process are particularly beneficial for RF
MEMS. First, the large vertical air gap (≈ 50 µm) below the MEMS structure minimizes parasitic
capacitance to the silicon substrate. Since silicon is a poor conductor at RF, coupling to the
silicon must be avoided to maximize the Q of CMOS-MEMS variable capacitors. Second,
Chapter 2: CMOS-MEMS
14
CMOS processes often include a thick metal layer to minimize the series resistance of on-chip
spiral inductors. This thick metal layer is useful for minimizing the series resistance of variable
capacitors. Third, polysilicon resistors can be embedded in the CMOS-MEMS beams to enable
electrothermal actuation. These resistors allow the temperature of electrothermal actuator beams
to be controlled using an applied voltage.
During the vertical oxide etch, a passivation layer is deposited on the side-walls of the
CMOS-MEMS beams. This side-wall polymer is required for the oxide etch to be anisotropic.
The polymer layer also prevents the titanium-tungsten adhesion layers, which are deposited
above and below the aluminum metal layers as part of the CMOS process, from etching during
the silicon release etch. Without sufficient side-wall polymer, the aluminum metal layers can
delaminate and peel away from the oxide. The side-wall polymer is a dielectric material of
unknown relative permittivity. Since observations of the thickness in SEM images approximately
match the thickness calculated from capacitance measurements, the relative permittivity is
expected to be near unity. The thickness of the side-wall polymer determines the effective air gap
between CMOS-MEMS beams pushed into mechanical contact (≈ 0.2 µm). The air gap is
referred to as effective because there is no actual air gap, simply a gap containing side-wall
polymer whose permittivity is assumed to be equal to that of air. This effective air gap limits the
maximum capacitance per unit length between two CMOS-MEMS beams. Note that CMOSMEMS beams pushed into mechanical contact do not short circuit. Shorting would be
unexpected because aluminum has a native oxide that prevents electrical contact. The side-wall
polymer is believed to further help prevent electrical breakdown. Two CMOS-MEMS beams in
mechanical contact can withstand greater than 30 V before electrical breakdown occurs.
Electrical breakdown typically occurs when more than 50 V has been applied. Breakdown
Chapter 2: CMOS-MEMS
15
destroys the MEMS structures unless the current is limited by a resistor.
After the silicon release etch, all CMOS-MEMS beams curl vertically with a radius of
curvature specific to their metal-dielectric stack. Because beams composed of multiple metal and
dielectric layers are thicker, these beams curl much less than those composed of a single layer of
metal and dielectric. Metal-1 beams can be used to achieve large vertical deflections whereas
metal-4321 beams can be used when vertical curling is unwanted. Most beams curl up away from
the silicon, but the direction depends on the particular CMOS process. Because metal and
dielectric have different temperature coefficients of expansion (TCE), the stress difference
between the two materials, and hence the radius of curvature, is temperature dependent.
CMOS-MEMS beams are prone to another type of curling, referred to as unintended lateral
curling. Unintended lateral curling is fundamentally different from the vertical curling associated
with residual stress because this curling occurs even for beams with symmetric cross-sections.
For example, a metal-1 beam has an asymmetric cross-section for the purpose of vertical curling
because the beam consists of metal on top and dielectric on bottom. Thus vertical curling is
expected. The metal-1 beam has a symmetric cross-section for the purpose of lateral curling
because the beam cross-section is uniform in the lateral direction. Thus lateral curling is not
expected. Yet the fact remains that all CMOS-MEMS beams curl laterally, even when such
curling is not intended.
Unintended lateral curling has been observed in many CMOS-MEMS devices and occurs to
a greater extent for beams which are long and narrow. The cause of this curling is unknown
because the cross-sections of the affected beams are symmetrical such that there is no apparent
reason for curling in one direction or the other. Several theories exist to explain this curling.
Because beams with the same local geometry on the same die curl the same direction, the
Chapter 2: CMOS-MEMS
16
problem may be caused by the CMOS-MEMS process. Further optimization of the process, such
as a reduction in the thickness of the sidewall polymer, has been theorized to reduce the curling
but has not yet been demonstrated. Misalignment of the metal layers may contribute to
unintended lateral curling but cannot be solely responsible since beams composed of only a
single metal layer still curl.
2.2. Electrothermal Actuation
Electrothermal actuation produces mechanical displacements using the thermal expansion of
materials. The actuation is controlled by a voltage applied to a resistor, which causes electrical
power to be dissipated as heat. That heat causes a temperature change resulting in thermal
expansion. The electrothermal actuators used in this work are thermal bimorphs or, if the
actuators include more than two layers, thermal multi-morphs. Thermal bimorphs are beams that
consist of two materials with different temperature coefficients of expansion (TCE). Neglecting
the thin (< 100 nm) titanium-tungsten adhesion layers, the materials used in this work are
aluminum, which has a TCE of 23.1 µK-1, and oxide, which has a TCE of 0.5 µK-1 [33]. Because
the TCE are different, any change in temperature causes a difference in mechanical stress
between the two materials. This stress difference results in a temperature-dependent bending
moment applied along the length of a beam, which causes the beam to curl in a circular arc.
As discussed in Section 2.1.2, all CMOS-MEMS beams, thermal bimorphs included, deflect
at room temperature according to the particular metal-dielectric stack. This vertical deflection
occurs immediately after the beams are released from the substrate and is thus referred to as the
self-assembly displacement. This displacement is caused by residual stress in the CMOS
materials after fabrication, so the magnitude and direction of the displacement depends on the
Chapter 2: CMOS-MEMS
17
CMOS process. Heating the beams above room temperature typically produces displacement in
the opposite direction of self-assembly. The temperature to which the beams must be heated to
reduce the total displacement to zero is defined as the zero-stress temperature. For the 0.35 µm
BiCMOS process used in this work, the zero-stress temperature is approximately 180°C.
The analysis necessary to calculate the temperature-dependant deflection of thermal multimorphs is presented in [22]. Consider a simple thermal bimorph with length L and width w that
consists of one layer of metal with thickness hm on top one layer of oxide with thickness ho.
Assuming that the position of the neutral axis is near the metal-oxide interface, [22] calculates
the vertical displacement at the tip, z(L), according to the dimensions of the bimorph.
z L  
wL2
4EI eff

o ho
2

  m hm 2 ,
(2.1)
where (EI)eff is the effective flexural rigidity and σo and σm represent the mechanical stress in the
oxide and metal, respectively. The mechanical stress results from thermal expansion and thus
depends on the change in temperature, ∆T.
  ET ,
(2.2)
where α is the TCE and E is the Young‘s modulus of the material. The change in temperature is
relative to the zero-stress temperature, T0.
  E T0  Ta  ,
(2.3)
where Ta is the temperature of the actuator beam. Substituting (2.3) into (2.1) yields the vertical
displacement as a function of the actuator beam temperature.
zL  
wL2
4EI eff

o E o ho
2

  m E m hm 2 T0  Ta  ,
(2.4)
The dimensions and material characteristics of the actuator beam cross-section can be lumped
into a single parameter defined as the sensitivity of the actuator beam cross-section, S.
Chapter 2: CMOS-MEMS
18
S
w
4EI eff

o E o ho
2
  m E m hm 2
.
(2.5)
This sensitivity simplifies the expression for the vertical displacement of the actuator beam.
zL  SL2 T0  Ta  ,
(2.6)
Note that once the sensitivity is determined for a particular actuator beam cross-section, the
length of the actuator beam can be scaled to provide the necessary displacement. The radius of
curvature, ρ, is calculated using the length and tip displacement of the actuator beam.

L2
2 z L 
,
(2.7)
Experimental results from [22] provided both the zero-stress temperature and the actuator
cross-section sensitivity for a variety of different cross-sections. For the CMOS-MEMS variable
capacitors presented in this work, the actuator beam cross-sections with the largest sensitivity
were chosen to maximize displacement. The length of the actuator beams were determined by
(2.6) or (2.7) to achieve the required displacement or radius of curvature, respectively.
2.2.1. Vertical Electrothermal Actuators
The vertical electrothermal actuators used in this work are metal-1 beams, which closely
resemble ideal thermal bimorphs (see Fig. 2.3). The heating resistor can be distributed along the
length of the actuator beam or lumped at the anchor points. For the 0.35 µm BiCMOS process
used in this work, the direction of the self-assembly displacement is up, away from the silicon,
but this direction can vary according to the particular CMOS process. Measurements of test
structures showed that a 35 µm long actuator beam without polysilicon deflected by 1.30 µm at
room temperature (25°C). Using (2.7) the radius of curvature resulting from the self-assembly
displacement was calculated to be 471 µm. This calculated radius of curvature is used in the
Chapter 2: CMOS-MEMS
19
design of the digital capacitor presented in Section 4.4. Assuming that the zero-stress temperature
for this actuator is 180°C, the sensitivity of the actuator beam cross-section was calculated to be
6.84 m-1K-1 using (2.6).
Side View
Cross-sections
Self-assembly displacement due
to residual stress
No displacement after heating
to the zero-stress temperature
Key:
Metal 1
Actuator beam without
polysilicon resistor
Actuator beam with polysilicon
resistor
Oxide
Silicon
Fig. 2.3. Diagram of a vertical electrothermal actuator beam. The polysilicon resistor for heating can either be
lumped near the anchor point or distributed along the length of the actuator beam.
2.2.2. Lateral Electrothermal Actuators
The lateral electrothermal actuators used in this work are metal-321 beams with metal-2 and
metal-1 offset to one side of the beam (see Fig. 2.4). The lateral electrothermal actuator beams
are far from ideal thermal bimorphs since both the top metal and most of the oxide must span the
width of the actuator beam. These thermal multi-morphs operate according to the same principles
as a thermal bimorph except that only the offset metal layers contribute a temperature-dependent
stress difference that causes displacement. If the offset metal layers are confined to one side of
the actuator beams, the lateral actuator beams will curl in a circular arc similar to the vertical
electrothermal actuator beams. This type of curling is undesirable for many applications since the
non-zero angle at the tip prevents many actuator beams from being connected in parallel to drive
Chapter 2: CMOS-MEMS
20
a single structure. To achieve a zero angle at the tip, the offset metal layers are switched to the
opposite side of the beam halfway along the length to produce guided-end motion. This guidedend configuration is equivalent to two half actuator beams connected in series. Since the
displacement is proportional to the length squared, the guided-end actuator produces half the
displacement of a non-guided-end actuator of the same length.
Top View
Cross-sections
Self-assembly displacement due
to residual stress
A
A’
B
B’
B
A’
B’
No displacement after heating
to the zero-stress temperature
Key:
A
Metal 1
Metal 2
Metal 3
Oxide
Fig. 2.4. Diagram of a lateral electrothermal actuator beam. The offset metal layers are switched to the opposite side
of the beam halfway along the length to produce guided-end motion at the tip.
For the 0.35 µm BiCMOS process used in this work, the actuator beam cross-section that
maximizes displacement for a given length consists of 1 µm wide metal-3 with 0.5 µm wide
metal-2 and metal-1 offset layers. The actuator beam width is too narrow to accommodate
polysilicon, so the heating resistors are lumped at anchor points. For this cross-section, a 100 µm
long actuator beam in guided-end configuration deflected by 2.42 µm at room temperature
(25°C). The measured zero-stress temperature for that actuator was 175.7°C. Using, (2.6) the
sensitivity of the actuator beam cross-section was calculated to be 1.61 m-1K-1. This calculated
sensitivity is used in the design of the gap-tuning capacitor presented in Section 3.4. Using (2.7)
Chapter 2: CMOS-MEMS
21
for a lateral actuator beam not in guided-end configuration, the radius of curvature resulting from
the self-assembly displacement is 1.0 mm. Fig. 2.5 shows microscope images of 14 lateral
electrothermal actuator connected in parallel and a focused-ion beam image of cross-section of a
single actuator beam.
(a)
(b)
(c)
Fig. 2.5. Microscope image of lateral electrothermal actuator (a) deflected due to residual stress (b) after heating.
(c) Focused-ion beam image of electrothermal actuator beam cross-section.
Chapter 2: CMOS-MEMS
22
Chapter 3.
Gap-tuning Capacitor
The CMOS-MEMS variable capacitors presented in this section use lateral electrothermal
actuation to control the gap between interdigitated capacitive beams. Mechanical latches are used
to maintain the gap without consuming static power for heating. CMOS-MEMS gap-tuning
capacitors had been developed prior to this work, so Section 3.1 explains the problems with
previously developed CMOS-MEMS gap-tuning capacitors that serve as motivation. Section 3.2
presents the improved topology of the gap-tuning capacitor. Section 3.3 presents an analysis of
the topology linking the degrees of freedom to performance metrics. Section 3.4 describes how
that analysis was used to define the geometry of the gap-tuning capacitor. Section 3.5 presents
characterization results of the fabricated design. Section 3.6 discusses the various advantages and
disadvantages of the resulting gap-tuning capacitor.
3.1. Motivation
There are two problems that MEMS variable capacitors must solve to enable frequencyreconfigurable circuits for multi-band radio. First, the variable capacitors must have large tuning
ratios so that the circuits can be reconfigured for operation over a wide range of frequencies.
Second, the variable capacitors must be controlled using on-chip voltages. Generating control
voltages off-chip requires additional discrete components, which defeats the purpose of
monolithic integration with CMOS. Ideally, the required control voltages are below the supply
voltage of the CMOS process to avoid the need for CMOS charge pumps, which consume both
power and area. Electrothermal actuation is the solution to both problems since electrothermal
actuators produce the large displacements (> 10 µm) necessary for large tuning ratios and require
only low voltages (< 5 V). However, electrothermal actuation introduces a third problem since
Chapter 3: Gap-tuning Capacitor
23
electrothermal actuators require power for heating. To use electrothermal actuation without
consuming static power for heating, the CMOS-MEMS gap-tuning capacitor includes a
mechanical latch.
3.1.1. Concept
The gap-tuning capacitor uses lateral electrothermal actuation to control both the gap
between the capacitive beams and the position of the mechanical latch (see Fig. 3.1). After the
MEMS structure is released from the substrate by the CMOS-MEMS process, the electrothermal
actuators self-assemble such that the capacitive beams are pushed into mechanical contact,
resulting in maximum capacitance. To reconfigure the gap-tuning capacitor, both actuators are
heated to simultaneously disengage the latch and change the gap between the capacitive beams.
Then, the actuator controlling the latch is cooled to cause the latch to engage and maintain the
new position of the capacitive beams. Finally, the actuator controlling the gap is cooled so that
no static power is consumed for heating.
Maximum capacitance is
maintained by self-assembly
Both actuators are heated to
reverse the self-assembly
Minimum capacitance is
maintained by the latch
actuation
self-assembly
self-assembly
self-assembly
Key:
actuation
Latch interface
Actuator Beams
self-assembly
Capacitive beams
Fig. 3.1. Concept of the actuation method for the gap-tuning capacitor.
Chapter 3: Gap-tuning Capacitor
24
The combination of lateral electrothermal actuation and mechanical latching is not limited to
gap-tuning capacitors. The same actuation method could be applied to create an area-tuning
capacitor. Gap-tuning was pursued over area-tuning because gap-tuning has the potential to
create a large maximum capacitance when the capacitive beams are pushed into mechanical
contact. Area-tuning capacitors typically maintain an air gap, which results in lower maximum
capacitances.
(a)
(b)
(c)
(d)
Fig. 3.2. SEM image of the (a) 1st (b) 2nd (c) 3rd (d) 4th design of the gap-tuning capacitor.
3.1.2. Related Work
Prior to this work, four generations of electrothermal gap-tuning capacitors had been
designed and characterized (see Fig. 3.2). The common goal in every design was to use
electrothermal actuation to control the lateral gap between capacitive beams. Most designs
Chapter 3: Gap-tuning Capacitor
25
included a mechanical latch designed to maintain a given capacitive gap without consuming
power for heating. While performance metrics such as Q and capacitance density were
considered, achieving a large tuning ratio was the primary focus.
The first two designs (see Fig. 3.2(a) and Fig. 3.2(b)) included methods for both lateral and
vertical actuation but did not achieve tuning ratios greater than 1.5:1 [34]. The vertical curling of
CMOS-MEMS beams was not anticipated, so, as a result, the capacitive beams were vertically
misaligned (see Fig. 3.3), which limited the maximum. The third design (see Fig. 3.2(c))
achieved the first significant tuning ratio of 3.5:1 by focusing purely on lateral actuation to
control the capacitance gap [35]. The fourth design (see Fig. 3.2(d)) was a refinement of the third
design but still suffered from vertical misalignment between the capacitance beams, which
limited the tuning ratio to approximately 3:1. The common trend in these previous designs was a
failure to compensate for the vertical curling of CMOS-MEMS beams.
Side View
Misaligned beams
(b)
(a)
Fig. 3.3. Vertical misalignment of capacitive beams viewed as (a) SEM image (b) diagram. The observed vertical
misalignment is not as exaggerated as in the diagram but still significant enough to affect the tuning ratio.
The previous designs had two other problems, both associated with routing the RF signal
through the electrothermal actuator. First, since the effective RF circuit and thermal circuit
shared the same metal path, the transient power consumption of the electrothermal actuators
could not be decreased without sacrificing Q. Increasing the length of the metal path to increase
thermal isolation would result in increased electrical resistance and decreased Q. Second, the
Chapter 3: Gap-tuning Capacitor
26
actuators contained separate routing for actuation control signals, which are low frequency
voltages that act as high frequency ground. The close proximity between the RF routing and the
actuation control routing caused large parasitic capacitances to ground (on the order of 100 fF) in
the equivalent circuit.
Mechanical latches were included in the previous designs to hold the variable capacitance
constant without consuming power for heating (see Fig. 3.4). All latch designs used the selfassembly displacement of electrothermal actuators to close a gap at room temperature. Initial
designs were intended to hold part of the capacitor in place with static friction [34] (see Fig.
3.4(a) and Fig. 3.4(b)). All such latches failed because friction was not strong enough compared
with mechanical forces applied by the lateral actuators. The first successful latch pushed a peg
into a slot connected to a moveable set of capacitive beams [27] (see Fig. 3.4(c)). This peg-andslot latch could accommodate multiple positions using multiple slots, but the number of slots was
limited by the width of the gap required to accommodate a minimum width peg.
(b)
(a)
st
nd
(c)
rd
Fig. 3.4. SEM image of the (a) 1 (b) 2 (c) 3 design of the mechanical latch for gap-tuning capacitors.
The aforementioned problems associated with the previous designs of CMOS-MEMS gaptuning capacitors served as motivation for the topology presented in this work. The gap-tuning
capacitor topology was updated to ensure vertical alignment between the capacitive beams,
which was expected to increase the tuning ratio. The RF routing was separated from the actuation
Chapter 3: Gap-tuning Capacitor
27
control routing to decrease parasitic capacitance and enable thermal isolation for lower transient
power consumption. The latch was modified to provide a greater number of positions for a given
capacitive gap.
Latch actuator
Latch
actuation
self-assembly
RF interconnect
y
z
La
x
Gap actuator
actuation
self-assembly
Port 2
Port 1
Capacitive beams
Thermal isolation / Open circuit
Fig. 3.5. Diagram of gap-tuning capacitor. Arrows denote the directions of self-assembly and electrothermal
actuation displacements for both the gap and latch actuators. Resistor symbols indicate the location of embedded
polysilicon resistors used for electrothermal actuation. The specific numbers of capacitive, actuator, and interconnect
beams are not representative of the numbers of beams used in the actual device.
3.2. Topology
Fig. 3.5 shows the topology of the CMOS-MEMS gap-tuning capacitor. The majority of the
area consists of interdigitated capacitive beams, whose lateral gap determines the series
capacitance between Port 1 and Port 2. One set of capacitive beams is fixed and connected
directly to a pad (Port 1). The other set of capacitive beams is movable and electrically connected
to a second pad (Port 2) through the RF interconnect. The position of the movable capacitive
beams is controlled by the displacement of the gap actuator. The latch actuator controls the
position of the latch, which can be engaged to hold the movable capacitive beams in place
without consuming static power for heating. Polysilicon resistors are embedded in the actuators
Chapter 3: Gap-tuning Capacitor
28
to control the temperature and resulting displacement. The gap-tuning capacitor is operated by
applying voltages to those resistors. Thermal isolation units are included to thermally isolate the
actuators from both their anchors and the capacitive beams.
The structure of the CMOS-MEMS gap-tuning capacitor was designed to ensure vertical
alignment between the capacitive beams. Because all CMOS-MEMS beams curl vertically at
room temperature, the capacitive beams will be vertically misaligned if those beams are anchored
at opposite ends of the etch pit (see Fig. 3.6). Any vertical misalignment reduces the maximum
capacitance, which negatively impacts both the tuning ratio and capacitance density. To avoid
misalignment, the gap actuator and RF interconnect are ―U‖-shaped so that both the stator and
rotor capacitive beams share a common anchor location. The ―U‖-shaped structures still curl
vertically due to residual stress, but one section of the ―U‖-shape curls upwards whereas the other
section curls downwards, such that the two tips of the ―U‖-shape are vertically aligned.
Top View
Side View
Anchored at
opposite ends
Misaligned beams
Common anchor
location
Aligned beams
Fig. 3.6. Vertical curling of CMOS-MEMS beams. Anchoring MEMS beams at a common location prevents vertical
misalignment.
The RF interconnect is necessary to electrically isolate the RF signal from the actuation
control signals, which results in low parasitic capacitance to ground. This interconnect
Chapter 3: Gap-tuning Capacitor
29
contributes to the series resistance of the gap-tuning capacitor and acts as a mechanical load for
the gap actuator. The ideal RF interconnect would have low series resistance for high Q and a
low spring constant to enable large displacements. However, low series resistance requires short
and wide structures whereas long and narrow structures are required for a low spring constant. To
compromise between these two extremes, the RF interconnect consists of many narrow beams
connected in parallel to provide a low-resistance yet mechanically flexible electrical connection.
These beams appear similar to those of the electrothermal actuator but have different crosssections. The RF interconnect beams are not as wide and do not contain offset metal layers.
The electrothermal actuators provide a self-assembly displacement which causes the latch to
remain engaged without heating the actuators (see Fig. 3.5). The offset metal layers in each of the
actuators are oriented such that the gap actuator self-assembles in the positive x-direction and the
latch actuator self-assembles in the negative y-direction. These self-assembly displacements
cause the latch to act as a limit-stop which prevents the gap actuator from pushing the capacitive
beams into mechanical contact. Heating the actuators produces electrothermal actuation in the
opposite direction of self-assembly, which is necessary to reconfigure the gap-tuning capacitor.
To change the capacitance, the latch actuator is first heated to disengage the latch, which allows
the gap actuator to move freely. Then, the gap actuator is heated to select the desired capacitive
gap. Finally, removing power from the latch and gap actuators, in turn, allows the latch to close
such that the capacitor is held at a new position without consuming static power for heating.
The latch consists of interlocking stair-step structures with a 2 µm pitch to provide 6
positions across the 10 µm air gap (see Fig. 3.7). The latch actuator is composed of two actuators
side-by-side so that latch position is not significantly affected by x-direction forces applied by the
gap actuator. The choice to include two identical stair-step structures was arbitrary, and in
Chapter 3: Gap-tuning Capacitor
30
hindsight, seems unnecessary.
5 µm
Fig. 3.7. SEM image of the mechanical latch for the gap-tuning capacitor. As pictures, the latch is engaged in an
intermediate capacitance position, neither minimum nor maximum capacitance.
Each electrothermal actuator consists of many actuator beams with three heating resistors for
temperature control (see Fig. 3.8). Multiple actuator beams are connected in parallel to supply the
relatively large force necessary to push the RF interconnect. Each resistor was initially wired to a
separate control voltage so that the thermal circuit could be experimentally characterized by
using the resistors simultaneously as both heating elements and temperature sensors.
50 µm
Rb
Actuator
beams
Heating
resistors
Rc
Ra
Thermal isolation
Fig. 3.8. SEM image of the gap actuator for the gap-tuning capacitor. The shading of the actuator beams changes
half-way along their length because the offset metal layers are switched to the other side of the beams.
Thermal isolation units are placed at actuator anchor points to lower the power consumption
of the actuators (see Fig. 3.9). The actuator for gap control is also thermally isolated from the
Chapter 3: Gap-tuning Capacitor
31
capacitive beams to prevent those beams from heating significantly. Because the thermal
conductivity of aluminum (250 W/m/K) is much greater than that of oxide (≈ 1 W/m/K), the
length and width of the metal path determines the thermal resistance of a CMOS-MEMS
structure. A CMOS-MEMS structure without a continuous metal path would maximize thermal
resistance. However, a metal path is required since the heating resistors must be electrically
connected. The thermal isolation units, similar to those used in other thermal CMOS-MEMS
devices [22], increase the thermal resistance by lengthening the metal path available for heat
conduction. To create a long metal path while minimizing area, the metal is meandered between
metal 1 and metal 2 and passed through a series of vias. The vias help to increase thermal
resistance since the thermal conductivity of tungsten (170 W/m/K) is lower than that of
aluminum.
B
Resistor
A
5 µm
A
Key:
Metal 4
B
Metal 1
Metal 2
Metal 3
Oxide
Via
Silicon
(a)
(b)
Fig. 3.9. Thermal isolation unit viewed as (a) SEM image (b) cross-section diagram. The metal 3 and metal 4
pictured in the diagram are not floating; these metals are connected to ground along a different cross-section.
The gap-tuning capacitor was designed in a 4-metal 0.35 µm BiCMOS process from
TowerJazz Semiconductor. Fig. 3.10 shows the resulting cross-sections of several different
beams used in the gap-tuning capacitor. All four metals are aluminum. The capacitive beams are
metal-4321 beams with the maximum density of vias to both maximize the capacitive overlap
Chapter 3: Gap-tuning Capacitor
32
area and minimize series resistance. Since metal-4 is a thick top metal requiring larger widths,
the interconnect beams and actuator beams are metal-321 beams. The smaller width and spacing
of metal-321 beams are necessary for achieving large mechanical displacements. Metal-2 and
metal-1 are offset within the actuator beams to form lateral electrothermal actuators as described
in Section 2.2.2. A metal-4 ground plane serves as the perimeter for the MEMS structure.
Interconnect
Beams
Capacitive
Beams
Actuator
Beams
≈ 10 µm
≈ 50 µm
Key:
Metal 1
Metal 2
Metal 3
Oxide
Via
Silicon
Metal 4
Fig. 3.10. Cross-section of CMOS-MEMS beams used in the electrothermal gap-tuning capacitor.
3.3. Analysis
Assuming a parallel plate capacitance, the series capacitance of the gap-tuning capacitor, Cs,
is defined by the maximum gap, gmax, and the displacement of the movable set of capacitive
beams, x.


1
1
,
C s  N c  0 Lc h


 g max  x g max  x 
(3.1)
where Nc, Lc, and h are the number, overlap length, and height of the capacitive beams,
respectively. The minimum capacitance occurs for zero displacement.
C s,min 
2 N c  0 Lc h
,
g max
Chapter 3: Gap-tuning Capacitor
(3.2)
33
gmax+x gmax-x
Capacitive
beams have
height h out
of the page
Lc
Nc=2 for this
example
Fig. 3.11. Diagram of capacitive beams for displacement x.
The maximum capacitance occurs when the movable capacitive beams are pushed into
mechanical contact with the fixed capacitive beams. The maximum capacitance per unit length
for two CMOS-MEMS beams pushed into mechanical contact is determined by the thickness of
the side-wall polymer deposited during the CMOS-MEMS process. Capacitive test structures
were used to calculate an effective minimum air gap, which can be used in conjunction with the
height of the metal-dielectric stack to calculate the maximum capacitance. This effective air gap
is a non-physical parameter which accounts for the thickness of the side-wall polymer, the effects
of fringing fields, and the possibility that the permittivity of the side-wall polymer is greater than
the permittivity of free space. The maximum capacitance can be calculated using the effective
minimum air gap, gmin.

1
1
Cs  N c  0 Lc h

 2g
 max  g min g min

.


(3.3)
The expression for maximum capacitance can be simplified assuming that the minimum gap is
much less than the maximum gap.
Chapter 3: Gap-tuning Capacitor
34
Cs,max 
N c  0 Lc h
.
g min
(3.4)
The tuning ratio is calculated using the (3.2) and (3.4).
C s,max
C s,min

g max
2g min
(3.5)
4 µm
4 µm
Minimum Capacitance
Min
.
Maximum Capacitance
Electric Field Magnitude
Max
Fig. 3.12. Electric field magnitude for cross-sections of capacitive beams in both minimum and maximum
capacitance positions. The white, unmeshed areas represent the discrete metal layers of the CMOS-MEMS beams.
The capacitance calculations above can be refined using finite element analysis (FEA) to
account for fringing fields. A 2-D electrostatic analysis was used to calculate the capacitance per
unit length between two CMOS-MEMS beams as the gap was varied (see Fig. 3.12). The
permittivity of the side-wall polymer was assumed to be equal to the permittivity of free space.
For large gaps, the capacitance is increased by fringing fields above and below the capacitive
beams. For small gaps, the capacitance is decreased because electric fields become concentrated
between the discrete metal layers that form only part of the capacitive beams. Given a 10 µm
maximum gap and a 0.25 µm minimum gap, the tuning ratio calculated with FEA is
approximately half as large as that calculated with (3.5).
Chapter 3: Gap-tuning Capacitor
35
The 2-D electrostatic analysis was used to vary the vertical misalignment of the capacitive
beams. Capacitance per unit length was simulated for several different gaps as the difference in
vertical position between the fixed and movable capacitance beams was increased (see Fig. 3.13).
The capacitance for small gaps is much more sensitive to vertical misalignment than that of large
gaps, which underscores the need to minimize this misalignment.
Capacitance / Length (aF/µm)
250
10 µm gap
2 µm gap
200
1 µm gap
0.3 µm gap
150
100
50
0
0
2
4
6
8
10
Vertical Misalignment (µm)
Fig. 3.13. Capacitance per unit length as a function of vertical offset for different gaps. Vertical misalignment
between capacitive beams has a much larger impact when the gap is small.
The electrothermal actuator provides a displacement according to its geometry and the
temperature of the actuator beams. The position, or tip displacement, of an unloaded actuator,
xunloaded, can be determined by the length of the actuator beams.
x unloaded  2S a La 2 T0  Ta  ,
(3.6)
where Sa is the sensitivity of the actuator beam cross-section in m-1K-1 and La, Ta, and T0 are the
length, actuator beam temperature, and zero-stress temperature (≈ 180°C for this work) defined
by the fabrication process, respectively. The unloaded displacement evaluates to zero when the
actuator beam temperature is equal to the zero-stress temperature. A factor of two is included
because the actuator consists of two sets of guided-end beams folded in series (see Fig. 3.5). The
Chapter 3: Gap-tuning Capacitor
36
sensitivity can be calculated from the geometry of the actuator beam cross-section using the
equations presented in [22].
The actuator must push the beam flexure comprising the RF interconnect, so the loaded
displacement, x, includes a term based on the relative spring constants of the actuator and
interconnect, ka and ki, respectively. Furthermore, the temperature of the actuator depends on
both the ambient temperature, Tr, and the power dissipated as heat in the polysilicon resistors, P.
Incorporating these terms into (3.6) yields an expression for the loaded displacement.
x
ka
ka  ki
2S a La 2 T0  Tr  K th P  ,
(3.7)
where Kth is the effective thermal resistance observed as heat is dissipated in the three resistor
locations. Note that the loaded displacement is greater than zero unless the actuator is heated to a
temperature greater than the zero-stress temperature. By setting the displacement equal to the
maximum gap and the actuator power to zero, (3.7) is used to calculate the maximum ambient
temperature, Tr,max, at which the actuator pushes the capacitive beams into mechanical contact.
Tr,max  T0 
k a  k i g max
k a 2 S a La 2
,
(3.8)
In addition to a requirement on ambient temperature, the voltage across the capacitive beams
must be sufficiently small such that the beams are not clamped together by electrostatic force.
The voltage V across the capacitor beams creates an electrostatic force, Fe, pulling the beams
together.
Fe 
V 2 dC s
,
2 dx
(3.9)
Using the approximation in (3.4) and evaluating x at gmin results in a simple expression for the
electrostatic force.
Chapter 3: Gap-tuning Capacitor
37
Fe 
V 2 C s,max
2 g min
.
(3.10)
The mechanical restoring force of the gap actuator under normal operation, Fm, is the force
applied to move the capacitive beams from maximum to minimum capacitance position.
Fm  k a  k i g max  g min  ,
(3.11)
The voltage at which the gap actuator can no longer separate the capacitive beams occurs when
the electrostatic force equally opposes the mechanical restoring force. Combining (3.10) and
(3.11) yields the maximum applied voltage, Vmax.
Vmax 
2 g min k a  k i g max  g min 
.
C s,max
(3.12)
If the frequency of the applied voltage is much greater than the mechanical resonance frequency
of the gap actuator, then the electrostatic force is determined by the root-mean-squared (RMS)
value of the voltage. This voltage is what ultimately limits the power handling of the gap-tuning
capacitor. However, an explicit number representing the maximum power cannot be calculated
without knowing how the gap-tuning capacitor is to be used in a circuit.
The quality factor of the series capacitance depends on the series resistance, Rs, which is
primarily determined by the resistance of the RF interconnect.
Q
1
,
2fR s C s
(3.13)
where f is the frequency of operation. The series resistance can be calculated using the sheet
resistances of the metal layers in combination with the geometry of the design.
3.4. Design
Measurements from several test structures were used during design of the electrothermal
Chapter 3: Gap-tuning Capacitor
38
gap-tuning capacitor. The optimum actuator beam cross-section was determined using
measurements of the self-assembly displacement of electrothermal actuators. An actuator beam
consisting of a 1-µm metal-3 top metal with 0.5-µm metal-2 and metal-1 offset layers produces
the maximum displacement for a given actuator beam length, La. The corresponding actuator
beam cross-section sensitivity, Sa, and the zero-stress temperature, T0, were derived by measuring
the displacement with the actuator heated to a known temperature. Based on capacitance
measurements of previous CMOS-MEMS gap-tuning capacitors, the minimum effective air gap,
gmin, was estimated to be 0.3 µm.
The maximum gap, gmax, was chosen to be 10 µm to increase the tuning ratio beyond that of
previous electrothermal gap-tuning capacitors. Choosing the maximum gap determined the
tuning ratio according to (3.5) in conjunction with FEA results. The number and dimensions of
the capacitive beams were selected to create a maximum capacitance of approximately 400 fF.
Since capacitive beams that are too long and too narrow can curl laterally resulting in decreased
maximum capacitance, the beam length and width were set to 220 µm and 4 µm, respectively.
The lateral curling resulting from these dimensions was expected to be minimal based on
qualitative observations of test structures. To achieve the desired maximum capacitance, the
number of capacitive beams, Nc, was set to 8 according to (3.4). These parameters define the
structure of the capacitive beams.
The gap actuator was designed in tandem with the RF interconnect to provide the
displacement necessary to traverse the maximum gap. The width of the interconnect beams, wi,
was set to 0.5 µm, which is the minimum metal width for the 0.35 µm BiCMOS process, so that
the spring constant of the actuator beams, ka, would be larger than that of the interconnect beams,
ki. The length of the interconnect beams, Li, was set equal to that of the actuator beams, La, so
Chapter 3: Gap-tuning Capacitor
39
that the resulting device would fit in a rectangular area. Equal amounts of area were devoted to
the actuator beams and interconnect beams, which, in conjunction with the beam cross-sections,
determined the ratio of the actuator beams spring constant to that of the interconnect beams. The
actuator beam length was scaled to 210 µm to increase the displacement according to (3.7).
Using (3.8), the resulting maximum ambient temperature, Tr,max, was calculated to be 86°C. That
maximum temperature was deemed sufficient since many consumer electronics must operate at
ambient temperatures up to 70°C.
Table 3.1: Gap-Tuning Capacitor Design Parameters
Geometry
Value
Constants
Value
gmax
10 µm
gmin*
0.3 µm
Lc
220 µm
Sa**
1.61 m-1K-1
wc
4 µm
T0**
176°C
Nc
8
La
210 µm
Calculation
Value
wa
1 µm
Cs,min
52.9 fF
wo
0.5 µm
Cs,max
399 fF
Na
14
Tuning Ratio
7.5:1
Li
210 µm
ka
0.50 N/m
wi
0.5 µm
ki
0.14 N/m
Ni
18
Tr,max
86°C
Vmax
3.1 V
Q at 1 GHz
210
* Estimation based on measured data
** Parameter extracted from measured data
The number of actuator beams, Na, and number of interconnect beams, Ni, were scaled to 14
and 18, respectively, to increase the Q. Increasing the number of interconnect beams increases
the width of metal available for conduction which lowers the series resistance, Rs. Based on the
sheet resistances provided by the 0.35 µm BiCMOS design manual, the series resistance was
calculated to be 1.9 Ω. Using (3.13), the minimum Q for the maximum capacitance, Cs,max, was
calculated to be 210 at 1 GHz.
Multiple design iterations were necessary to reach an area-efficient design with sufficient Q
Chapter 3: Gap-tuning Capacitor
40
and tuning ratio. The air gaps between the MEMS structure and the metal-4 ground plane were
set to 20 µm to minimize parasitic capacitance to ground. Table 3.1 lists all the parameters used
in the design of the CMOS-MEMS electrothermal gap-tuning capacitor presented in this work.
Fig. 3.14 shows an SEM image of the fabricated device.
RF interconnect
Latch actuator
Port 2
Port 1
Latch
Capacitive beams
200 µm
Gap actuator
Fig. 3.14. SEM image of CMOS-MEMS variable capacitor.
3.5. Characterization
All fabricated electrothermal gap-tuning capacitors correctly self-assembled to close the
10 µm capacitive gap at room temperature. The gap-tuning capacitors were actuated using no
more than 3 V and 15 mW (see Fig. 3.15). The mechanical latch was successful at maintaining
each of the six latch positions without consuming power (see Fig. 3.16). While all the capacitors
successfully demonstrated basic functionality, effective minimum air gap varied from device to
device due to unintended lateral curling (see Fig. 3.17).
Chapter 3: Gap-tuning Capacitor
41
(a)
(b)
Fig. 3.15. Microscope image of the gap-tuning capacitor in (a) maximum capacitance position (b) minimum
capacitance position. The latch appears retracted because voltage was applied to the heating resistors in the latch
actuator.
(a)
(b)
(c)
(d)
(e)
(f)
Fig. 3.16. Microscope image of the latch at position (a) 1 (b) 2 (c) 3 (d) 4 (e) 5 (f) 6. Each position corresponds to a
different capacitance value at which the variable capacitor can be maintained without consuming power.
(a)
(b)
Fig. 3.17. Microscope image of capacitive beams pushed into mechanical contact (a) for the best-performing
capacitor (b) for a capacitor with significant lateral curling. The amount of curling is small but still has significant
effects of the minimum effective air gap.
Chapter 3: Gap-tuning Capacitor
42
The vertical profile of the variable capacitor was measured with a Veeco optical
profilometer (see Fig. 3.18). The interdigitated capacitive beams curl out-of-plane but maintain
vertical alignment. The worst-case misalignment, 1.6 µm, occurs at the tips of the movable
capacitive beams, which, according to 2D cross-section FEA simulations (see Fig. 3.13), results
in a 13% reduction in tuning ratio if that misalignment is constant over the length of the beams.
However, misalignment varies along the length of the capacitive beams, so the tuning ratio is
reduced by less than 13% due to vertical misalignment.
13.2
5.0
0.0
-5.0
Vertical Deflection (µm)
10.0
-8.1
Fig. 3.18. Optical profilometer image of electrothermal gap-tuning capacitor. The capacitive beams are vertically
aligned to within 1.6 µm.
3.5.1. Electrical Performance
The digital capacitors were electrically characterized using the method described in
Appendix A for all six latch positions. Fig. 3.19 shows the S-parameters for the minimum
capacitance and maximum capacitance positions. Fig. 3.20 shows the equivalent circuit model in
terms of Y-parameters and lumped circuit elements. Fig. 3.21 shows the lumped impedances for
Chapter 3: Gap-tuning Capacitor
43
the minimum capacitance and maximum capacitance positions. The equations listed below were
10
10
0
0
S-parameters (dB)
S-parameters (dB)
used to calculate the equivalent circuit element values (see Fig. 3.20(b)).
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-10
-20
-30
-10
-20
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-30
-40
-40
0.1
1
0.1
10
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 3.19. S-parameter magnitude as a function of frequency for (a) the minimum capacitance position (b) the
maximum capacitance position. S12 is not plotted because S12 and S21 are equivalent for passive networks.
Port 1
Port 2
-Y21
Y11+Y12
Port 1
Rs
Cs
Ls
Port 2
C2g
Y22+Y21
1E+5
1E+5
1E+4
1E+4
Impedance (Ω)
Impedance (Ω)
(b)
(a)
Fig. 3.20. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements. Circuit element
values are extracted from measured 2-port network parameters.
1E+3
1E+2
1E+1
|1/-Y21| (Measured)
|1/(Y11+Y12)| (Measured)
|1/(Y22+Y21)| (Measured)
Extracted Model
1E+0
1E-1
0.1
1
1E+3
1E+2
1E+1
|1/-Y21| (Measured)
|1/(Y11+Y12)| (Measured)
|1/(Y22+Y21)| (Measured)
Extracted Model
1E+0
1E-1
10
0.1
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 3.21. Lumped impedances as a function of frequency for (a) the minimum capacitance position (b) the maximum
capacitance position. The series impedance behaves like an RLC circuit, and the shunt impedances are capacitive
below 10 GHz. The self-resonance frequency is greater than 20 GHz for the minimum capacitance position and
decreases to 11 GHz for the maximum capacitance position.
Chapter 3: Gap-tuning Capacitor
44
2
  

1 
 
 res  .
Cs 
imag  1 Y21 
Ls 
1
 resCs 2
(3.14)
.
(3.15)
Rs  real 1 Y21  .
C1g 
C 2g 
1
 * imag 1 Y11  Y21 
1
 * imag 1 Y22  Y21 
Q
imag 1 Y11 
real1 Y11 
(3.16)
.
(3.17)
.
(3.18)
.
Table 3.2: Electrical Characteristics of the Gap-tuning Capacitor
Latch
Cs (fF)
Ls (nH)
Rs (Ω)
C1g (fF)
C2g (fF)
Position
± 1.1%
± 6.4%
± 20%
± 9.2%
± 5.7%
1
54.5
NA*
13.4
13.1
30.3
2
56.1
NA*
13.3
13.1
29.7
3
61.2
NA*
12.2
13.0
28.6
4
73.4
NA*
10.8
12.9
27.4
5
111
569
8.15
12.6
26.4
6
373
536
4.56
10.9
25.1
* Inductance value could not be extracted since the self-resonance frequency exceeded 20 GHz
(3.19)
Q (1 GHz)
± 22%
71
71
71
72
80
80
The electrical characteristics of the best-performing electrothermal gap-tuning capacitor are
presented in Table 3.2. The latch position 1 is the minimum capacitance position and latch
position 6 is the maximum capacitance position. Measurement uncertainties were derived from
multiple measurements of the same latch position and thus do not include systematic offsets
based on the particular network analyzer calibration or probe contact resistance. As designed, the
Chapter 3: Gap-tuning Capacitor
45
series capacitance, Cs, increases with latch position as the capacitive gap decreases. The shunt
capacitances, C1g and C2g, decrease slightly with latch position due to fringing electric fields
originating from the bottom of the capacitive beams. As the capacitive gap decreases, more of the
fringing electric field lines will terminate on the capacitive electrodes rather than the silicon
substrate resulting in decreased capacitance to ground.
Note that the measured series resistance reported in Table 3.2 changes according to the latch
position. This change in resistance was unexpected since the metal path that determines the series
resistance is not altered by the latch position. Even after considering the skin effect, the
proximity effect, parasitic capacitance to the silicon substrate, and the possibility of
piezoresistance, such a significant change in resistance could not be explained. Only after
subsequent measurements of the digital capacitor, which is presented in Chapter 4, was the cause
determined to be the noise floor of the VNA. The noise floor prevented accurate measurement of
a small real impedance in series with a large imaginary impedance. Accurate measurements of
series resistance were achieved after lowering the IF bandwidth of the VNA from the default
setting of 35 kHz to 500 Hz. Since the noise floor is directly proportional to the IF bandwidth,
this modification decreased the noise floor by nearly two orders of magnitude. However, since
many of the gap-tuning capacitors were damaged during reliability testing, updated
measurements are not available. The series resistance presumably remains constant regardless of
the latch position although this has not been verified through measurement.
Since the measured Q is calculated using the measured series resistance, the Q was also
limited by the noise floor of the VNA and thus does not agree with calculated predictions.
Assuming a constant series resistance, the Q should decrease as the capacitance increases.
However, the Q reported in Table 3.2, which is the Q with port 2 connected to ground, remains
Chapter 3: Gap-tuning Capacitor
46
approximately constant for different latch positions. The measured Q for the maximum
capacitance is 80, which is significantly lower than the calculated value of 210. The measured Q
as a function of frequency still fits well with the trend according to (3.19) (see Fig. 3.22) but
Quality Factor
should be considered only a rough approximation.
100
90
80
70
60
50
40
30
20
10
0
Quality Factor (De-embedded)
Extracted Model
1
2
3
4
5
6
Frequency (GHz)
Fig. 3.22. Quality factor as a function of frequency. This plot shows the Q for the maximum capacitance position.
The series capacitance of the electrothermal gap-tuning capacitor was measured at each of
the 6 latch positions for 7 different devices (see Fig. 3.23). The distribution of capacitance values
is nonlinear because the latch positions are evenly spaced over the 10 µm capacitive gap. The
average gap-tuning capacitor tuned from 54.9 fF to 269 fF, an average tuning ratio of 4.9:1. The
best-performing gap-tuning capacitor tuned from 54.5 fF to 373 fF, a tuning ratio of 6.8:1. The
variation between devices, measured by standard deviation, differs greatly depending on the latch
position. The minimum capacitance ranged from 54.0 fF to 55.3 fF while maximum capacitance
ranged from 214 fF to 373 fF. The standard deviation for the minimum capacitance is only 1.0%,
but the standard deviation from the maximum capacitance is 18%. The average standard
deviation for all states is 4.9%.
Chapter 3: Gap-tuning Capacitor
47
Series Capacitance (fF)
400
350
300
250
200
150
100
50
0
1
2
3
4
5
6
Latch Position
Fig. 3.23. Plot of series capacitance versus latch position. Error bars indicate the 1-σ standard deviation between
different devices based on 7 measurements.
400
Data Points
Latch Positions
Capacitance (fF)
350
300
250
200
150
100
50
0
0
1
2
3
4
Actuator Power (mW)
Fig. 3.24. Capacitance as a function of actuator voltage. Continuous tuning is possible with the latch retracted.
Hysteresis is caused by capacitive beams sticking together as they are being pulled apart.
Series capacitance was measured as the power applied to the heating resistors was varied
while the latch was retracted. The resulting data shows a smooth transition from maximum
capacitance to minimum capacitance as the input power is decreased, or as the gap is closed (see
Fig. 3.24). However, hysteresis occurs when increasing the actuator power which suggests there
is some adhesion force between the capacitive beams, possibly due to humidity in the laboratory
Chapter 3: Gap-tuning Capacitor
48
environment. This adhesion force was always overcome by the actuator, so the capacitive beams
did not become permanently stuck.
A bias-T was included to measure the series capacitance as a function of the DC voltage
applied across the capacitive beams. While the capacitor was unlatched, electrostatic pull-in
occurred with less than 5 V applied (see Fig. 3.25). At maximum capacitance, electrostatic force
flattened the capacitive beams causing the capacitance to increase by up to 14%. While the
capacitor was latched with a 2 µm air gap, which is the latch position most vulnerable to
electrostatic pull-in, up to 14 V could be applied before pull-in was observed. All other latched
capacitance positions were maintained for DC voltages up to 20 V, which is expected due to their
larger air gaps.
500
Capacitance (fF)
450
400
Position 4
350
Position 5
300
Position 6
250
Unlatched
200
150
100
50
0
0
5
10
15
20
DC Bias (V)
Fig. 3.25. Capacitance as function of DC bias voltage. With the latch retracted (unlatched), capacitance beams snap
together using less than 5 V. With the latch in place, up to 14 V can be applied before electrostatic pull-in occurs.
The electrothermal gap-tuning capacitor was tested over a range of RF power to determine
the maximum root-mean-squared (RMS) voltage at which the actuator could overcome the
electrostatic force between the capacitive beams. Port 1 of the capacitor was connected to an
Agilent E8241 signal generator while port 2 was connected to an Agilent E4440 spectrum
Chapter 3: Gap-tuning Capacitor
49
analyzer. The latch was retracted with the capacitor placed in maximum capacitance position.
While testing with a frequency of 4 GHz, the limit at which the gap actuator would no longer
retract occurred when 16 dBm was delivered to the load, which amounts to 4.2 VRMS applied
across the capacitive beams. This measured voltage is greater than the calculated maximum
voltage of 3.1 VRMS, likely because the maximum capacitance was reduced to due unintended
lateral curling.
3.5.2. Switching Speed
A computer microvision system was used to measure the frequency response of the
electrothermal actuation. A sinusoidal actuation voltage was applied to the heating resistors
within the electrothermal actuators in conjunction with a DC bias necessary to prevent the
capacitive gap from closing entirely. Because mechanical displacement is proportional to the
square of the voltage, the raw displacement data includes a double-frequency component.
However, this double-frequency component is filtered such that the resulting response represents
the frequency-dependant conversion from electrical power to mechanical displacement (see Fig.
3.26). The thermal 3 dB frequency occurs at 60 ± 5 Hz while mechanical resonance occurs at 5.1
± 0.1 kHz and 13.7 ± 0.1 kHz for the gap and latch actuators, respectively. Thus the switching
speed is limited by the thermal time constant (≈ 2.7 ms) rather than the mechanical response.
The microvision system was also used to measure the transient response of the
electrothermal actuation (see Fig. 3.25). The frequency of actuation was set to 50 Hz, and the
displacement was recorded at each of 100 phase points. The measured 90% rise time was
4.9 ± 0.1 ms. Note that displacement is not observed until approximately 1 ms after power has
been applied to the actuator. This delay occurs because, without applied power, the capacitive
Chapter 3: Gap-tuning Capacitor
50
beams are pushed into mechanical contact, and the contact force must be relieved by a change in
Displacement Amplitude(µm)
temperature before displacement can occur.
10
Gap Actuator
Latch Actuator
1
0.1
0.01
0.001
Thermal 3dB
frequency ≈ 60 Hz
Mechanical resonance
frequency ≈ 5.1 kHz and
≈ 13.7 kHz
0.01
0.1
1
10
100
Frequency (kHz)
Fig. 3.26. Electrothermal actuator frequency response. The thermal 3 dB frequency limits the speed of both the gap
and latch actuators.
16
6
Position
Power
5
12
4
10
8
3
6
2
4
Power (mW)
Displacement (µm)
14
1
2
0
0
0
5
10
15
20
Time (ms)
Fig. 3.27. Electrothermal actuator transient response. The 90% rise time is 4.9 ms.
Reconfiguration of the gap-tuning capacitor requires many thermal time constants because
three successive temperature changes are needed to change the latched capacitance. First, the
latch and gap actuators must be heated to disengage the latch and set the capacitive gap,
respectively. Second, the gap actuator must cool to engage the latch. Third, the latch actuator
Chapter 3: Gap-tuning Capacitor
51
must cool to settle into the latch position. Each of these temperature changes can take multiple
thermal time constants depending on how much power is used to heat the actuators. Reliable
operation of the variable capacitor has been demonstrated using 30 ms for reconfiguration, a
relatively conservative actuation method which provides 3.7 thermal time constants for each
temperature change. The times required for heating could be decreased by using a different
voltage pulse or by using a closed-loop control system. However, the times required for cooling
cannot be decreased and will always be limited by the thermal time constant.
3.5.3. Thermal Aspects
The electrothermal actuators controlling the gap-tuning capacitors contain embedded
polysilicon resistors at three locations (see Fig. 3.5). In a prototype of the variable capacitor, each
of these resistors was wired to a separate control voltage, such that the resistors could act as both
heating elements and as temperature sensors to characterize the thermal circuit of the actuator.
First, power was dissipated in Ra while observing the change in resistance for all three resistors,
Ra, Rb, and Rc. Using the temperature coefficient of resistivity, the changes in each resistance
were used to calculate the temperature change at each resistor location. Based on the temperature
changes, three thermal resistances were calculated using the power dissipated in Ra. Repeating
the process with power dissipated in Rb and then Rc yielded the thermal resistance matrix,
 Ta   K aa
T    K
 b   ba
 Tc   K ca
K ab
K bb
K cb
K ac   Pa 
K bc   Pb  ,
K cc   Pc 
(3.20)
ΔTx and Px represent the temperature change and power dissipated at location x, respectively. Kxy
is the temperature change at location x when unit power is dissipated at location y.
A uniform temperature at all three resistor locations was necessary to remain consistent with
Chapter 3: Gap-tuning Capacitor
52
previous modeling and characterization of electrothermal actuators and to maximize
displacement for a given maximum temperature. The thermal resistance matrix was used to
calculate resistor values such that a single control voltage, Vh, applied to the resistors in parallel
would create a uniform temperature.
1 Ra 
1 R   1
 b
2
1 Rc  Vh
 K aa
K
 ba
 K ca
K ab
K bb
K cb
1
K ac 
K bc 
K cc 
 Ta 
T  .
 b
 Tc 
(3.21)
Since the electrothermal actuators retract completely at approximately 180°C, all three ΔT‘s were
set to 155°C, sufficient temperature change given an ambient temperature of 25°C. Voltage Vc
was set to 3 V, slightly below the specified 3.3 V supply of the 0.35 µm BiCMOS process. For
the gap actuator, (3.21) computes Ra, Rb, and Rc, to be 3.4 kΩ, 3.7 kΩ, and 4.8 kΩ, respectively.
1 3.4k
1 3.7k  1


2
1 4.8k 3V 
46.9KW -1 9.1KW -1
5.2KW -1 


-1
45.2KW -1 11.6KW -1 
 8.5KW
 5.0KW -1 11.7KW -1 60.6KW -1 


1
155K 
155K  .


155K 
(3.22)
For the latch actuator, (3.21) computes Ra, Rb, and Rc, to be 1.8 kΩ, 1.9 kΩ, and 2.7 kΩ,
respectively.
1 1.8k 
1 1.9k   1


2
1 2.7k 3V 
25.5KW -1

-1
 3.0KW
 2.1KW -1

3.4KW -1
24.8KW -1
5.6KW
-1
1
2.5KW -1  155K 

5.8KW -1  155K  .
35.0KW -1  155K 

(3.23)
Both the electrical resistances and thermal resistances for the latch actuator are approximately
half of those of the gap actuator. This difference is expected because the latch actuator consists of
two actuators with a total of six heating resistors rather than three. Note that, for both the gap and
latch actuator, Ra is the smallest resistance and Rc is the largest resistance. The relative sizes of
the resistances was expected since Ra is near the anchor, which requires the most power to heat,
and Rc is near the capacitive beams, which requires the least power to heat (see Fig. 3.5).
Chapter 3: Gap-tuning Capacitor
53
The electrothermal gap-tuning capacitor was later updated to include the resistor values
calculated using (3.21). A Quantum Focus infrared microscope was used to visualize the
temperature profile while the actuators were heated (see Fig. 3.28). During this measurement, the
substrate was heated to 30°C to provide a known reference temperature. The actuators were
heated to low temperatures (< 50°C) to avoid mechanical displacements which would invalidate
the reference measurement recorded before heating the actuators. The infrared microscope
measures the emitted infrared energy and calculates the temperature assuming a constant
emissivity, which is derived from the reference measurement. The calculated temperature should
be considered only a rough estimate because the emissivity of aluminum varies with temperature.
Nonetheless, the measured temperature profiles do show that the actuators are effectively
thermally isolated from their anchor points and the capacitive beams. The actuator temperatures
are higher when both the gap and latch actuators are heated, which suggests thermal cross-talk
between the actuators. This thermal cross-talk could be further analyzed using the resistors as
temperature sensors.
50oC
45oC
40oC
35oC
30oC
(a)
(b)
(c)
Fig. 3.28. Temperature profile of gap-tuning capacitor viewed with quantum infrared microscope. Voltage is applied
to resistors in (a) the gap actuator only (b) the latch actuator only (c) both the gap and latch actuators.
The electrothermal gap-tuning capacitor was tested over a range of temperatures to verify
the maximum ambient temperature at which the actuators would maintain the desired latch
position. Capacitance was measured while the probe station chuck temperature was varied from
Chapter 3: Gap-tuning Capacitor
54
25°C to 100°C with the capacitor latched in a particular position (see Fig. 3.29). Up to 65°C, the
capacitor maintains its capacitance to within 0.5% of the nominal (25°C) value. Beyond 65°C,
two modes of failure were observed. At higher capacitance positions, the gap actuator retracts as
the temperature increases causing a decrease in capacitance. At lower capacitance positions, the
latch actuator retracts as temperature increases causing the device to slip into a higher
capacitance position. Although this latch failure appears to occur at 95°C, the latch actuator is
incapable of closing the latch for temperatures greater than 65°C. The fact that both actuators fail
400
120
350
110
300
Position 6
Position 5
100
250
Position 4
Position 3
90
Position 2
Position 1
200
80
150
70
100
60
50
50
25
50
75
Temperature
( oC)
Capacitance (fF)
Capacitance (fF)
at the same temperature is not coincidental since both actuators are of similar design.
100
Fig. 3.29. Latched capacitance as a function of ambient temperature. While latched in position, the capacitance
remains stable up to 65°C.
3.5.4. Reliability Tests
Each capacitance position of the electrothermal gap-tuning capacitor was tested to verify
that capacitance values were repeatable. The variable capacitor was un-latched, actuated to the
specified gap, and re-latched ten times for each latch position for two different devices. Measured
capacitance values varied less than 0.3% from the average capacitance for each particular latch
Chapter 3: Gap-tuning Capacitor
55
position.
A shaker table was used to test whether large accelerations would cause the electrothermal
gap-tuning capacitor to slip into a different latch position. Measurements of the latched
capacitance were recorded prior to testing. The shaker table was used to drive the CMOS-MEMS
chip through sinusoidal motion at 50 Hz. The frequency was chosen to be significantly less than
the mechanical resonant frequency so that any displacement due to the acceleration would reach
steady-state equilibrium. The peak acceleration was ramped up to 40 g and maintained for
approximately 10 seconds. The capacitance was then measured to see if a change had occurred.
This test was repeated for both maximum and minimum capacitance positions with the applied
acceleration in three orthogonal directions. As a result of 40 g of acceleration, the minimum and
maximum capacitance varied by less than 0.1% and 1%, respectively.
To assess reliability over time, two electrothermal gap-tuning capacitors were cycled at
15 Hz between the minimum and maximum capacitance latch positions over several days.
During this time, the chuck temperature was held constant at 25°C with the DUT open to the
general laboratory atmosphere. The full duration amounts to millions of impacts between the
capacitive beams. Testing was stopped intermittently so that the capacitance could be measured.
For both capacitors, a decrease in maximum capacitance was observed with increasing
cycles (see Fig. 3.30). The first capacitor continued to operate beyond 5 million cycles with no
catastrophic failures. The latch of the second capacitor failed after approximately 5 million
cycles. While shifting to maximum capacitance position, the latch began sliding beneath the
movable capacitive beams rather than making contact with the corresponding interface. An
inspection of the defective latch revealed damage to the surface of the metal covering the heating
resistors and sub-micron debris scattered around the latch interface (see Fig. 3.31). Whether the
Chapter 3: Gap-tuning Capacitor
56
latch failure was caused by repetitive mechanical impacts or by prolonged heating is unclear.
Capacitance (fF)
500
400
300
Cs,max
Cs,max (DUT
(DUT#1)
#1)
Cs,min (DUT
Cs,min
(DUT#1)
#1)
Cs,max (DUT
Cs,max
(DUT#2)
#2)
C
(DUT
#2)
Cs,min
s,min (DUT #2)
200
100
0
1000
103
10000
104
100000
105
1000000
106
10000000
107
Cycles
Fig. 3.30. Minimum and maximum capacitance as a function of actuation cycles for two DUT‘s. Maximum
capacitance decreased as the variable capacitor was cycled between latch positions.
5 µm
20 µm
(a)
(b)
Fig. 3.31. SEM images of mechanical latch after failure (a) zoomed out (b) zoomed in. Repeated impacts of the latch
interface created sub-micron debris on the latch.
3.6. Discussion
The CMOS-MEMS electrothermal gap-tuning capacitor presented in this work has
demonstrated significant advantages when compared with gap-tuning capacitors developed in
Chapter 3: Gap-tuning Capacitor
57
previous work (see Table 3.3). Increasing the maximum gap from 5 µm to 10 µm increased the
series tuning ratio from 2.5:1 to 6.9:1. The inclusion of the RF interconnect to isolate the RF
signal from the actuation control signals resulted in significantly less parasitic capacitance to
ground. The two parasitic capacitances, C1g and C2g, were decreased from 71 fF and 425 fF to
12.6 fF and 27.9 fF, respectively. The Q for the maximum capacitance at 1 GHz was increased
from 54 to 80. The improved mechanical latch increased the number of latch positions from two
to six. Compared with previous work, the only drawback of this work is a slight decrease in
capacitance density, which is unavoidable since a larger maximum gap is required for larger
tuning ratios.
Table 3.3: Gap-Tuning Capacitor Results
Name
Previous design
This work
Tuning ratio (series)
2.5:1
6.9:1
Tuning ratio (shunt)
2.0:1
5.7:1
Q (1 GHz) for Cs,max*
54
80
Self-resonance frequency for Cs,max
11.3 GHz
11.3 GHz
Cs,max
380 fF
373 fF
Cs,min
150 fF
54.5 fF
C1g**
71 fF
12.6 fF
C2g**
425 fF
27.9 fF
Rs for Cs,max
7.2 Ω
4.5 Ω
Ls for Cs,max
522 pH
536 pH
Area
0.19 mm2
0.26 mm2
Capacitance Density
2.0 pF/ mm2
1.4 pF/ mm2
Actuation Method
electrothermal
electrothermal
Control
2 latch positions
6 latch positions
Voltage
3V
3V
Power
NA****
15 / 0 mW***
Switching Time
NA****
30 ms
Cs,max Standard Deviation
NA****
18%
Integration
maskless post-CMOS etching
maskless post-CMOS etching
* Quality factor is calculated from a fit to measured data ranging from 1 GHz to 4 GHz
** Shunt capacitances are averaged over all capacitor states
*** Power is only consumed during switching
**** Value is not reported but is expected to be similar to that of this work
The tests on reliability and repeatability show that an individual gap-tuning capacitor is
Chapter 3: Gap-tuning Capacitor
58
reliable at producing repeatable capacitance values. However, a comparison between gap-tuning
capacitors from different chips revealed significant device-to-device variation in the maximum
capacitance (see Fig. 3.23). This variation is caused by lateral curling of the interdigitated
capacitance beams, which is an undesirable aspect of the CMOS-MEMS process that is not fully
understood. The long, narrow capacitance beams are prone to curling on the order of tenths of
microns, which causes uneven mechanical contact when the beams are pushed together in
maximum capacitance position. For the seven devices measured, the minimum capacitance
ranged from 54.0 fF to 55.3 fF while the maximum capacitance ranged from 214 fF to 372 fF.
This variation in maximum capacitance is problematic when implementing the gap-tuning
capacitor in reconfigurable circuits with multiple LC tanks requiring the same resonance
frequency.
While the number of latch positions has been increased, the distribution of latched
capacitance values is not practical. Because the latch positions are distributed linearly every
2 µm, the series capacitance varies in a nonlinear manner with respect to the latch position (see
Fig. 3.23). A different distribution of latch positions could yield more useful capacitance values.
For example, the spacing of the latch positions could be redesigned to create a linear variation in
capacitance, or even a linear variation in the resonance frequency of an LC tank. However, the
minimum size of the latch positions is limited by ion milling which occurs during the vertical
oxide etch of the CMOS-MEMS process. This ion milling creates rounded corners which can
prevent the latch from correctly engaging. Latches designed with a 1 µm step size slipped out of
position, so the practical limit for the size of latch steps is somewhere between 1 µm and 2 µm.
Thus, decreasing the number of latch positions would be necessary to modify the distribution of
capacitance values.
Chapter 3: Gap-tuning Capacitor
59
Several other issues limit the practical use of the gap-tuning capacitor. The capacitance
density is very low compared with that of semiconductor variable capacitors and still low
compared with that of other integrated MEMS variable capacitors. Increasing the capacitance
density is possible but requires a smaller maximum gap resulting in reduced tuning ratio. The self
resonance frequency is limited to approximately 10 GHz due to the need to loop the current
through the RF interconnect to achieve vertical alignment between the capacitance beams. These
problems could not be resolved using the gap-tuning capacitor topology and ultimately lead to
the development of the CMOS-MEMS digital capacitor, which is presented in Chapter 4.
Chapter 3: Gap-tuning Capacitor
60
Chapter 4.
Digital Capacitor
The CMOS-MEMS variable capacitors presented in this section are ―digital‖ because they
consist of multiple independently controlled capacitive bits. The capacitive bits can be toggled on
and off through a combination of vertical electrothermal and lateral electrostatic actuation. Each
capacitive bit consists of many unit cells, which are referred to as CMOS-MEMS switched
capacitors. Section 4.1 explains how the digital capacitor was developed to overcome the
disadvantages of the gap-tuning capacitor. Section 4.2 presents the switched capacitor topology.
Section 4.3 presents an analysis of the topology linking the degrees of freedom to performance
metrics. Section 4.4 describes how that analysis was used to define the geometry of the switched
capacitor. Section 4.5 presents characterization results of the fabricated design. Section 4.6
discusses the results and presents several ideas for further improvement.
4.1. Motivation
The CMOS-MEMS digital capacitor was designed specifically to address the shortcomings
of the gap-tuning capacitor. The primary goals of the design were to improve the tuning ratio,
capacitance density, distribution of capacitance values, self-resonant frequency, and device-todevice variation. Secondary goals such as simplifying the design for subsequent modification by
a circuit designer, increasing the switching speed, decreasing the power consumption, and
increasing the quality factor were considered but were not the primary factors driving the design.
To achieve these goals, a unique method of actuation was developed.
4.1.1. Concept
The digital capacitor uses a combination of vertical electrothermal and lateral electrostatic
Chapter 4: Digital Capacitor
61
actuation (see Fig. 4.1) to toggle the capacitance of a capacitive bit. The minimum capacitance is
limited by the large vertical gap created by the self-assembly displacement of the electrothermal
actuator. After vertical electrothermal actuation, lateral electrostatic actuation is used to snap the
capacitive electrodes into mechanical contact, resulting in a large maximum capacitance. The
resulting electrostatic force is used to hold the electrodes together without consuming power for
electrothermal actuation.
Side View
Top View
After release etch
After vertical electrothermal actuation
After lateral electrostatic actuation
Electrothermal actuator
Capacitive electrodes
Fig. 4.1. Concept of the actuation method for the switched capacitor.
Many of the benefits of this actuation method, which are experimentally quantified in
Section 4.5, can be realized from a qualitative discussion. Vertical electrothermal actuation
alleviates the need for large lateral air gaps, so large tuning ratios can be achieved simultaneously
with large capacitance densities. Lateral electrostatic actuation applies large forces between the
capacitive electrodes and thus does not require the CMOS-MEMS beams to be absolutely
straight. Unintended lateral curling can be tolerated as long as that curling is not so large as to
interfere with the vertical electrothermal actuation, so device-to-device variation is small. The
unit cell necessary to enable actuation is small and can be repeated in parallel to form capacitive
Chapter 4: Digital Capacitor
62
bits. The capacitive bits can be sized in a binary fashion (1C, 2C, 4C, etc.) to produce a linear
distribution of capacitance values. Furthermore, because current flows straight through the
structure, parasitic inductance should be minimized.
4.1.2. Related Work
MEMS variable capacitors have been previously developed which use actuation schemes
similar to that presented in this work. The MEMS variable capacitors in [8] and [37] use different
methods of vertical electrostatic actuation to lower rotor electrodes into plane with stator
electrodes, but no further actuation is used to close the remaining lateral gap. Similar to this
work, the MEMS switch in [26] uses a combination of vertical electrothermal and vertical
electrostatic actuation to achieve low-voltage actuation without static power consumption.
However, the 3-bit digital capacitors presented in this work are the first MEMS capacitive
devices to control both the gap and overlap area between capacitive electrodes using vertical and
lateral actuation.
Many MEMS digital capacitors, or devices which provide multiple discrete capacitance
values, have also been developed. The choice to provide discrete tuning is often mandated by the
bi-stable nature of the typical electrostatic gap-tuning capacitor [29]. Most digital capacitors are
combinations of identical switched capacitors, often adapted from capacitive switches, which
require multiple independent control signals [38], [39]. Alternatively, some digital capacitors
consist of switched capacitors with varying electrostatic pull-in voltages such that only a single
control signal is needed to vary the capacitance [40]. The digital capacitor presented in this work
is similar to those adapted from capacitive switches in that an array of identical capacitors is
controlled using multiple actuation signals.
Chapter 4: Digital Capacitor
63
Key:
Metal 1
Thermal
Isolation
Metal 2
Electrothermal
Actuator Beam
Metal 3
Metal 4
Rotor Electrodes
Stator Electrodes
Signal Beams
(a)
RDC VES
VET
RHeat
Port 1
CMIM
(b)
Port 2
(c)
Fig. 4.2. Diagram of CMOS-MEMS switched capacitor viewed from above (a) with annotations (b) with circuit
schematic; (c) SEM image of four CMOS-MEMS switched capacitors in parallel.
4.2. Topology
The CMOS-MEMS switched capacitor (see Fig. 4.2(a)) is a symmetrical unit cell which can
be repeated in parallel to provide the specified amount of variable capacitance. The relative
position of the stator and rotor electrodes defines the series capacitance between the two
electrical terminals. The rotor electrodes are connected to an electrothermal actuator beam which,
due to its design for a large stress gradient, is initially deflected upward such that the vertical gap
limits the minimum capacitance. The actuator beam contains an embedded polysilicon resistor
which is heated to lower the rotor beams into plane with the stator beams. Then, a voltage is
Chapter 4: Digital Capacitor
64
applied between the capacitive electrodes to cause lateral electrostatic pull-in, resulting in a
maximum capacitance limited by the thickness of the sidewall polymer.
The switched capacitor is electrically connected according to the overlaid schematic shown
in Fig. 4.2(b). The electrostatic actuation voltage, VES, is routed to the stator electrodes through
an on-chip resistor made sufficiently large (1 MΩ) as to not significantly affect the RF electrical
characteristics. The stator electrodes are connected to the bottom plate of a MIM capacitor that is
included to block the large electrostatic actuation voltage (20 V), which could damage other
devices connected to Port 2. The electrothermal actuation voltage, VET, is connected to the
heating resistor, RHeat, though a thermal isolation structure designed to confine heat within the
actuator. Thermal isolation is achieved by lengthening the metal path using a series of vias (see
Section 3.2), which also increases electrical resistance. To avoid routing the RF signal through
the resistive thermal isolation structure, a pair of signal beams is included to connect Port 1 to the
rotor electrodes. Fig. 4.2(c) shows an SEM image which illustrates how multiple switched
capacitors are combined in parallel within a capacitive bit.
Fig. 4.3 shows an approximate thermal circuit for the switched capacitor, which is only valid
for steady-state analysis since the thermal capacitances have not been included. Tactuator, Tbeam,
and Tanchor are the temperatures of the electrothermal actuator beam, signal beams, and anchor,
respectively. Pheat is the power dissipated in the heating resistor. Risolation is the thermal resistance
of the thermal isolation structure. Rair is the thermal resistance of the lateral air gap between the
actuator beam and the signal beams, and Roxide is the thermal resistance of the oxide connecting
the end of the actuator beam to the end of the signal beams. Because there is no metal path
connecting the end of the actuator beam to the rotor electrodes, an explicit thermal isolation
structure is not necessary at that location. Rbeam is the thermal resistance of the signal beams. This
Chapter 4: Digital Capacitor
65
thermal circuit shows that the temperature of the signal beams will increase when the
electrothermal actuator beam is heated. However, this circuit should be considered only a rough
approximation since the actual temperature distributions along the beams are not uniform. The
heating resistor embedded in the actuator beam is lumped near the thermal isolation structure,
which results in a temperature gradient along the actuator beam. The thermal resistance of the
lateral air gap is distributed, which results in another temperature gradient along those beams.
Finite element analysis is required to accurately simulate the temperature distribution.
Tactuator
Roxide
Pheat
Rair
Risolation
Tbeam
Rbeam
Tanchor
Fig. 4.3. Steady-state thermal circuit for the CMOS-MEMS switched capacitors.
The CMOS-MEMS switched capacitor was designed in a 4-metal, 0.35 µm BiCMOS
process from TowerJazz Semiconductor. All four metals are aluminum. Fig. 4.4 shows the crosssection of a switched capacitor after the CMOS-MEMS process. Because metal-4 is a thick top
metal requiring large line widths and gaps, the use of metal-4 is limited to routing between
multiple switched capacitors. Both the stator and rotor capacitive beams are metal-321 beams to
maximize the capacitive area without sacrificing the small line widths associated with the thin
metal layers. The electrothermal actuator is a metal-1 beam which, due to the small thickness of
the resulting metal-dielectric stack, provides the smallest radius of curvature resulting in large
vertical displacements. The signal beams are also metal-1 beams to minimize the mechanical
load placed on the actuators.
Chapter 4: Digital Capacitor
66
Capacitive
Actuator Electrode
Beam
≈ 10 µm
MIM
Capacitor
≈ 50 µm
Key:
Metal 1
Metal 2
Metal 3
Oxide
Via
Silicon
Metal 4
Fig. 4.4. Cross-section of the switched capacitor along the rotor electrode.
4.3. Analysis
Analysis of the CMOS-MEMS switched capacitor is difficult due to the complex
distribution of electric fields and temperature gradients. Finite element analysis (FEA) or results
from measured test structures are required for a high degree of precision. The analysis that
follows involves many approximations to enable design by hand calculations.
After the MEMS structure is released from the substrate, the CMOS-MEMS beams curl
vertically according to their temperature-dependant radii of curvature. The vertical deflection, zr,
of the rotor electrode is a function of distance along its length, x, and depends on the length of the
electrothermal actuator, La (see Fig. 4.5). Assuming small-angle displacements,
z r x  
La
2
2 a

La x
a

x2
2 r
,
(4.1)
where ρa and ρr are the radii of curvature for the actuator beam and rotor electrode, respectively.
Since the metal dielectric stack for the rotor electrode is thicker and composed of more
alternating metal and dielectric layers than the actuator beam, ρa is much smaller than ρr.
Neglecting the curvature of the capacitive electrodes, the vertical gap between electrodes, gz, is
Chapter 4: Digital Capacitor
67
expressed as the vertical deflection minus the height of the electrodes, hc.
g z x  
La
2
2 a
wb
 hc 
wc
wa
La x
(4.2)
a .
Lc,o
B
4(wc+gy)
B’
A
gy A’
-La
0
(a)
Thick metal stack for routing
between capacitive bits
x
Lc,m
hc
Radius of
curvature ρa
MIM
capacitor
gz(x) zr(x)
hc
A
-La
0B
Lc,m, A’
B’
x
(b)
Key:
Metal 1
Metal 2
Metal 3
Metal 4
Oxide
Via
Fig. 4.5. Diagram of CMOS-MEMS switched capacitor viewed (a) from above with nominal layout dimensions (b)
from the side with the rotor electrode deflected vertically into minimum capacitance position. Line A–A’ and line B–
B’ show the positions of the cross-sections along the rotor electrode and stator electrode, respectively.
The vertical gap between the capacitive electrodes limits the minimum MEMS capacitance,
CMEMS,min, but, for a precise calculation, finite element analysis is required to account for the
lateral fringing fields, the dielectric layers, and the angle of the rotor electrode with respect to the
stator electrode. However, there are two approximations which result in a simplified expression
of the minimum MEMS capacitance. An array of many switched capacitors in parallel results in a
Chapter 4: Digital Capacitor
68
row of rotor electrodes deflected above a row of stator electrodes. Provided that the lateral
spacing from electrode to electrode is small compared with the vertical gap between the stator
and rotor electrodes, the rows of electrodes can be approximated as continuous sheets of metal.
Then, because small-angle displacements result in approximately vertical electric fields, the
capacitance is calculated as an integral over the overlap length of the electrodes, Lc,o.
C MEMS, min  
Lc,m
Lc,m  Lc,o
 0 4wc  g y 
dx
g x 
(4.3)
.
where ε0 is electrical permittivity of free space and wc and gy are the widths of the capacitive
electrodes and lateral capacitive gap, respectively. Evaluating this expression results in
C MEMS,min 
 0 4wc  g y  a
La




Lc,o

ln 1 
 L  L  La  hc  a

c,m
c,o
2
La 

.
(4.4)
The maximum MEMS capacitance is process dependant and, thus, must be experimentally
characterized and scaled according to the length of the electrodes. The capacitance created by
two electrodes pulled into mechanical contact by electrostatic actuation depends on the nature of
the mechanical contact which occurs between the beams. This capacitance also depends upon the
thickness of a passivation layer deposited on the sides of CMOS-MEMS beams during the
vertical oxide etch. Measured data from capacitance test structures is used to extract an effective
lateral air gap, gmin,eff, which is a constant in the expression for maximum MEMS capacitance,
CMEMS,max.
C MEMS,max 
2 0 Lc,o hc
g min,eff
,
(4.5)
where hc is the height of the metal-dielectric stack for the rotor and stator electrodes. A factor of
two is included because each CMOS-MEMS switched capacitor contains two capacitive gaps.
Chapter 4: Digital Capacitor
69
The MEMS capacitance density, C'MEMS, is calculated by dividing the maximum capacitance by
the MEMS area.
C ' MEMS 
2 0 Lc,o hc
4wc  g y La  2 Lc,m  Lc,o g min,eff
.
(4.6)
The MEMS tuning ratio, TRMEMS, is calculated using (4.4) and (4.5).
TR MEMS 
2 La Lc,o hc




Lc,o

 a g min,eff 4wc  g y ln 1 
La
hc  a


Lc,m  Lc,o 

2
La 

.
(4.7)
This tuning ratio represents the maximum achievable tuning ratio without including the MIM
capacitance.
The MIM capacitance, CMIM, is calculated using the dimensions and capacitance density of
the MIM capacitor, C'MIM.
C MIM  k f C ' MIM LMIM 4wc  g y 
,
(4.8)
where kf is the fill factor and LMIM is length of the MIM capacitor. The fill factor accounts for
holes in the MIM capacitor which are necessary to ensure the structure releases during the
CMOS-MEMS process.
Both the minimum series capacitance, Cs,min, and maximum series capacitance, Cs,max, are
calculated as the series combination of the MEMS capacitance and the MIM capacitance.
Cs,min 
Cs,max 
C MEMS,min C MIM
C MEMS,min  C MIM .
C MEMS,max C MIM
C MEMS,max  C MIM .
Chapter 4: Digital Capacitor
(4.9)
(4.10)
70
The series tuning ratio, TRs, is calculated using (4.9) and (4.10).
TRs 
Cs,max
.
Cs,min
(4.11)
The area, A, is calculated using the dimensions.
A  4wc  g y La  2 Lc,m  Lc,o  LMIM 
.
(4.12)
The series capacitance density, C's, is defined the maximum series capacitance divided by the
area.
C 's 
Cs,max
A
.
(4.13)
The series resistance, Rs, is determined using the sheet resistances of the metal-dielectric
stacks and the geometry of the CMOS-MEMS switched capacitor. Given that metal 1, metal 2,
and metal 3 have the same sheet resistance, Rsheet, the series resistance expression is simplified
because the signal beams have a sheet resistance which is three times that of the capacitive
electrodes.
 L
Lc,m
Rs  Rsheet  a 
 2w
 b 6 wc

,


(4.14)
where wb is the width of the signal beams. The Q for the maximum capacitance is calculated
using (4.5) and (4.14).
Q
1
Rs C s,max
,
(4.15)
where ω is the frequency in radians per second.
The relative spring constants of the actuator beam, ka, and the signal beams, kb, determine
the temperature to which the actuator beam must be heated to lower the rotor electrodes into
Chapter 4: Digital Capacitor
71
plane with the stator electrodes. For full vertical actuation, CMOS-MEMS beams must be
uniformly heated to a zero-stress temperature, T0, which depends on the thermal coefficients of
expansion and residual stresses of the CMOS layers. If the signal beams remain near ambient
temperature, Troom, due to thermal isolation of the electrothermal actuator, then the actuator beam
must be heated to an average maximum temperature, Tmax, above the zero-stress temperature.
 2k  k
a
Tmax  T0  Troom  b
 k
a


T
.
 room

(4.16)
Since the actuator beam and signal beams have the same length and cross-section, the average
maximum temperature is expressed in terms of the relative widths of the actuator beam, wa, and
the signal beams, wb.
 2w  w
a
Tmax  T0  Troom  b

wa


T
.
 room

(4.17)
The electrothermal actuator voltage, VET, necessary to achieve the maximum temperature
depends on the thermal conductance, G, the resistance of the heater resistor, RHeat, and the change
in temperature.
VET
2
RHeat
 GTmax  Troom  .
(4.18)
The dimensions of the capacitive electrodes determine the electrostatic actuation voltage,
VES, necessary to pull the electrodes into mechanical contact. The pull-in voltage for a suspended
parallel-plate capacitor is well known but is not directly applicable because the capacitive
electrodes consist of two cantilevers anchored at opposite ends. Nonetheless, the required voltage
still scales in the same manner according to the gap, capacitance, and spring constant. Finite
element analysis was used to determine a constant (1.81 ± 0.03) with which to modify the typical
pull-in voltage expression. The uncertainty in this constant was determined by the range of
Chapter 4: Digital Capacitor
72
voltages between which pull-in occurred.
VES  1.81
8k y g y
3
,
27 0 Lc,o hc
(4.19)
where ky is the spring constant of a capacitive electrode for a point force applied at the tip of the
beam.
The vertical mechanical restoring force, Fm, which pulls the capacitive electrodes apart
depends on the vertical spring constant, kz, and the vertical displacement at the tip of the
electrothermal actuator, zr(0), calculated using (4.1).
Fm  k z z r 0 .
(4.20)
The electrostatic holding force, FES, which opposes the mechanical restoring force, is calculated
based on the maximum MEMS capacitance.
FES 
2
dz
VES  0 Lc,o
2
2
VES dC

g min,eff
.
(4.21)
The normal force exerted between the capacitive electrodes, Fn, by the applied voltage
determines the force due to friction, Ff, which also opposes the mechanical restoring force.
Fn 
2
dx
VES  0 Lc,o hc
2
2
V ES dC

g min,eff
2
Ff  u f Fn ,
.
(4.22)
(4.23)
where uf is the coefficient of static friction for side-wall polymer in contact with side-wall
polymer. Note that the signs of FES and Ff are opposite that of Fm. The combination of the force
due to friction and the electrostatic holding force must be greater than the mechanical restoring
force so that the capacitive electrodes can be held in maximum capacitance position without
consuming power for electrothermal actuation.
Chapter 4: Digital Capacitor
73
Fm  FES  Ff  0 .
(4.24)
4.4. Design
The CMOS-MEMS switched capacitor was designed to enable a 3-bit digital capacitor with
large tuning ratio, high capacitance density, and sufficient Q for operation at multi-GHz
frequencies. These performance metrics cannot be simultaneously optimized and are valued
differently depending on the particular circuit application. The design that follows is intended as
a general purpose switched capacitor which achieves a tuning ratio of approximately 50:1 while
maximizing capacitance density.
Design began with the geometry of the capacitive electrodes. Equations (4.6) and (4.7) show
that decreasing the y-direction pitch increases the capacitance density and tuning ratio, so wc and
gy were chosen to be 1 µm and 1.5 µm, respectively, near the minimum achievable by the
CMOS-MEMS process. The electrode length, Lc,m, is limited for a given electrode width, wc,
because CMOS-MEMS beams which are long and narrow tend to curl laterally, which interferes
with vertical actuation if the amount of curling exceeds the lateral gap. Thus Lc,m was chosen to
be 95 µm, short enough to avoid lateral curling greater than gy and long enough to provide a
relatively small actuation voltage according to (4.19). Since alternate versions of the switched
capacitor with 135 µm long electrodes failed consistently due to excessive lateral curling, 95 µm
is near the maximum electrode length for this design. The electrode overlap length, Lc,o, was set
to 90 µm. These decisions defined the structure and spacing of the capacitive electrodes, which
sets the maximum MEMS capacitance.
The length of the MIM capacitor, LMIM, was chosen to maximize the series capacitance
density, C's. The MIM capacitance should be large to maximize the series capacitance but not so
Chapter 4: Digital Capacitor
74
large that the MIM capacitor area dominates the area of the MEMS structure. Equations (4.5) (4.13) were used to plot the tuning ratio and capacitance density as a function of MIM capacitor
length. Fig. 4.6 shows that, based on the MEMS and MIM capacitance densities, C'MEMS and
C'MIM, the series capacitance density is optimized for a MIM capacitor length of 35 µm, which
results in a MIM capacitance 5.2x that of the maximum MEMS capacitance. To account for the
possibility of an increased MEMS capacitance, the MIM capacitor length was set to 45 µm,
which lowers the capacitance density by 7% but increases the series tuning ratio by 4%.
Normalized Parameters
1.4
Tuning Ratio
1.2
Capacitance Density
1
0.8
0.6
optimum capacitance
density at ≈ 35 µm
0.4
0.2
0
0
20
40
60
80
100
MIM Capacitor Length (µm)
Fig. 4.6. Normalized parameters as a function of MIM capacitor length. Tuning ratio and capacitance density are
normalized to their respective values for the optimum MIM capacitor length of 35 µm.
Design of the electrothermal actuator is all that remains to define the geometry of the
switched capacitor. The actuator beam length, La, determines the tradeoff between MEMS
capacitance density, MEMS tuning ratio, and series resistance according to (4.6), (4.7), and
(4.14), respectively. To produce a tuning ratio in excess of 40:1, La was chosen to be 90 µm. By
increasing La, larger tuning ratios can be achieved at the expense of both capacitance density and
Q (see Fig. 4.7). For example, increasing the actuator beam length to 120 µm increases the tuning
ratio by 87% but decreases the capacitance density and quality factor by 11% and 20%,
Chapter 4: Digital Capacitor
75
respectively. Parameters wa and wb were chosen to be 3.5 µm and 1 µm, respectively, so that the
actuator beam has a larger spring constant than that of the two signal beams. These widths
resulted in a calculated maximum temperature of 267°C according to (4.16).
Normalized Parameters
2.5
Tuning Ratio
Capacitance Density
2
Quality Factor
1.5
1
0.5
0
75
90
105
120
135
Actuator Beam Length (µm)
Fig. 4.7. Normalized parameters as a function of actuator beam length. Tuning ratio, capacitance density, and quality
factor are normalized to their respective values for an actuator beam length of 90 µm to illustrate the tradeoffs
necessary for increased tuning ratios.
The resistance of the heating resistor, RHeat, was chosen to be 3 kΩ according to (4.18) to
achieve the calculated maximum temperature using an electrothermal actuation voltage, VET, of
3.5 V. The thermal conductance, G, was calculated based on heat conduction through the thermal
isolation structure and through the air gap separating the signal beams from the actuator beam.
Both the signal beams and the metal 4 beams, which are mechanically anchored but undercut by
the isotropic silicon etch, were assumed to be thermally grounded to provide a worst-case
estimate of the electrothermal actuator power consumption.
Equations (4.20) through (4.23) were used to compare the mechanical restoring force, Fm,
with the electrostatic holding force, FES, and the force due to friction, Ff. The mechanical
restoring force was 3.0 µN, the electrostatic holding force was 1.3 µN, and the normal force, Fn,
was 33.0 µN. According to (4.24), the capacitive electrodes will be held in the maximum
Chapter 4: Digital Capacitor
76
capacitance position for coefficients of static friction as low as 0.03, which encompasses the vast
majority of materials, using only the minimum electrostatic actuation voltage necessary for pullin. Table 4.1 lists all the parameters used in the design of the CMOS-MEMS switched capacitor
presented in this work.
Table 4.1: Digital Capacitor Design Parameters
Geometry
Value
Calculation
Value
La
90 µm
CMEMS,min
0.70 fF
Lc,m
95 µm
CMEMS,max
38.9 fF
Lc,o
90 µm
C'MEMS
16.5 pF/mm2
wa
3.5 µm
TRMEMS
56:1
wb
1 µm
CMIM
261 fF
wc
1 µm
Cs,min
0.70 fF
gy
1.5 µm
Cs,max
33.8 fF
LMIM
45 µm
TRs
48:1
A
1900 µm2
Constants
Value
C'
14.4 pF/mm2
h c*
4.68 µm
Rs
4.0 Ω
ρa *
471 µm
Q (1 GHz)
1170
gmin,eff*
0.19 µm
Tmax
267°C
kf
0.58
ky
0.20 N/m
C'MIM
1 fF/µm2
G
16.8 µW/K
T 0*
178°C
RHeat
3 kΩ
VET
3.4 V
VES
12.7 V
kz
0.76 N/m
Fm
3.0 µN
FES
1.3 µN
Fn
33.0 µN
* Parameter extracted from measured data
The 3-bit digital capacitor was designed using an array of 35 switched capacitors in parallel
(see Fig. 4.8) to achieve a maximum capacitance of at least 1 pF. Larger or smaller maximum
capacitances can be achieved by scaling the number of parallel switched capacitors. Such scaling
does not affect the Q since any increase in maximum capacitance is accompanied by a
corresponding decrease in series resistance. The 3 bits consist of 5, 10, and 20 switched
capacitors, respectively, sized in a binary fashion to create a linear range of eight different
Chapter 4: Digital Capacitor
77
capacitance values. The digital capacitor was limited to 3 bits for testing purposes; the same
topology could be used to produce a digital capacitor with higher capacitance resolution.
Bit 1
Port 2 Bit 2
Bit 3
MIM
Capacitor
Port 1
Actuators
Electrodes
100 µm
Fig. 4.8. SEM image of 3-bit digital capacitor. Bits are separated by dummy structures to improve the temperature
uniformity of the electrothermal actuators. Floating electrodes appear darker due to charging.
4.5. Characterization
The CMOS-MEMS switched capacitors were successfully toggled between minimum and
maximum capacitance positions using vertical electrothermal actuation and lateral electrostatic
pull-in (see Fig. 4.9 and Fig. 4.10). Each capacitive bit was controlled independently to select any
of the eight capacitor states (see Fig. 4.11). Electrothermal actuation required a maximum of 4 V
and 70 mW to control the 35 switched capacitors while electrostatic actuation required 20 V.
Electrostatic force was capable of maintaining the maximum capacitance position when power to
the heating resistors was removed. Except when otherwise specified, all measurements were
recorded after electrostatic pull-in with the electrothermal actuation turned off. All
characterization was performed with the capacitors exposed to the general laboratory atmosphere.
Chapter 4: Digital Capacitor
78
(a)
(b)
(c)
Fig. 4.9. Microscope picture of CMOS-MEMS switched capacitors (a) in minimum capacitance position before
actuation (rotor electrodes are deflected out of focus) (b) after electrothermal actuation (c) in maximum capacitance
position after electrostatic actuation.
10.1
9.0
3.0
1.0
-1.0
-3.0
8.0
6.0
4.0
2.0
0.0
-2.0
-4.5.0
-5.1
(a)
Vertical Deflection (µm)
5.0
Vertical Deflection (µm)
7.0
11.2
10.0
(b)
Fig. 4.10. Profilometer image of bit 3 of the digital capacitor (a) before actuation (b) after actuation. The rotor beams
are not visible when deflected upwards because their angle with respect to the chip surface is too large for their
profile to be captured by the Wyko unless settings are modified which sacrifice the quality of the image.
Out of a total of 10 variable capacitors, each on a separate CMOS die, 7 were functional and
the remaining 3 failed to actuate into maximum capacitance position. Failure was caused by
lateral curling of the rotor and stator electrodes to an extent such that the bottom of the rotor
electrodes collided with the top of the stator electrodes during electrothermal actuation. This
collision prevented the rotor electrodes from being lowered into the plane with the stator
Chapter 4: Digital Capacitor
79
electrodes and from being subsequently snapped into maximum capacitance position. The
functional devices exhibited varying amounts of the same lateral curling, but not enough to
prevent vertical actuation. To improving the yield, the length of the capacitive electrodes should
be reduced, which decreases tuning ratio and capacitance density.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
Fig. 4.11. Microscope image of the 3-bit digital capacitor in state (a) 0 (b) 1 (c) 2 (d) 3 (e) 4 (f) 5 (g) 6 (h) 7. Each
capacitive bit is controlled independently to select the desired capacitance.
The capacitive electrodes also curl vertically, which is potentially problematic because
vertical misalignment between the capacitive electrodes can reduce the capacitive overlap area.
Similar to that of the electrothermal actuator beams, the vertical curling of the capacitive
electrodes is temperature dependant and caused by residual stress. However, the magnitude of
this vertical curling is smaller because the capacitive electrodes are composed of a thicker metaldielectric stack using multiple metal layers. Measurements from a Wyko optical profilometer
show that the capacitive electrodes deflect vertically by 0.7 ± 0.05 µm relative to their anchor
position. This deflection is undesirable but tolerable because the measured height of the
capacitive electrodes is 4.68 µm, larger than the vertical deflection.
Chapter 4: Digital Capacitor
80
4.5.1. Electrical Performance
The digital capacitors were electrically characterized using the method described in
Appendix A for all eight capacitor states. Fig. 4.12 shows the S-parameters for the minimum
capacitance and maximum capacitance states. Fig. 4.13 shows the equivalent circuit model in
terms of Y-parameters and lumped circuit elements. Fig. 4.14 shows the lumped impedances for
the minimum capacitance and maximum capacitance positions states. The equations listed below
were used to calculate the equivalent circuit element values (see Fig. 4.13(b)).
2
  

1 
 
 res  .
Cs 
imag  1 Y21 
Ls 
1
 resCs 2
(4.25)
.
(4.26)
Rs  real 1 Y21  .
C1g 
C 2g 
1
 * imag 1 Y11  Y21 
1
 * imag 1 Y22  Y21 
Q
imag 1 Y11 
real1 Y11 
.
Chapter 4: Digital Capacitor
(4.27)
.
(4.28)
.
(4.29)
(4.30)
81
10
0
0
S-parameters (dB)
S-parameters (dB)
10
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-10
-20
-30
-10
-20
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-30
-40
-40
0.1
1
0.1
10
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 4.12. S-parameter magnitude as a function of frequency for (a) the minimum capacitance state (b) the maximum
capacitance state. S12 is not plotted because S12 and S21 are equivalent for passive networks.
Port 1
Port 2
-Y21
Y11+Y12
Port 1
Rs
Cs
Ls
Port 2
C2g
Y22+Y21
1E+5
1E+5
1E+4
1E+4
Impedance (Ω)
Impedance (Ω)
(b)
(a)
Fig. 4.13. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements. Circuit element
values are extracted from measured 2-port network parameters.
1E+3
1E+2
1E+1
|1/-Y21| (Measured)
|1/(Y11+Y12)| (Measured)
|1/(Y22+Y21)| (Measured)
Extracted Model
1E+0
1E-1
0.1
1
1E+3
1E+2
1E+1
|1/-Y21| (Measured)
|1/(Y11+Y12)| (Measured)
|1/(Y22+Y21)| (Measured)
Extracted Model
1E+0
1E-1
10
0.1
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 4.14. Lumped impedances as a function of frequency for (a) the minimum capacitance state (b) the maximum
capacitance state. The behavior of |1/(Y11+Y12)| is explained by silicon remaining beneath the suspended MIM
capacitor. The self-resonance frequency is greater than 40 GHz for the minimum capacitance position and decreases
to 11.4 GHz for the maximum capacitance position.
Chapter 4: Digital Capacitor
82
The electrical characteristics of a typical 3-bit digital capacitor are presented in Table 4.2.
The state indicates which of the capacitive bits were active (for example, state 6 (110) means that
the two most significant bits are active). Measurement uncertainties were derived from multiple
measurements of the same capacitor state and thus do not include systematic offsets based on the
particular network analyzer calibration or probe contact resistance. As designed, the series
capacitance, Cs, increases linearly with state. The shunt capacitances, C1g and C2g, change slightly
with state primarily due to varying amounts of capacitance to the silicon substrate, which lies
approximately 50 µm below the MEMS structure. For minimum capacitance, the rotor electrodes
are deflected vertically and shielded from the silicon substrate by the stator electrodes. As the
state increases, more rotor electrodes are lowered into plane with the stator electrodes, so the
associated shunt capacitance, C2g, increases slightly. Conversely, the shunt capacitance
associated with the stator electrodes, C1g, decreases as the capacitance to the silicon substrate is
shared with the rotor electrodes.
Table 4.2: Electrical Characteristics of the Initial Digital Capacitor
Cs (fF)
Ls (nH)
Rs (Ω)
C1g (fF)
C2g (fF)
State
± 0.4%
± 0.2%
± 0.8%
± 0.2%
± 0.2%
0 (000)
23.0
NA*
NA**
75.0
478.5
1 (001)
243.5
0.214
2.34
72.8
480.9
2 (010)
435.5
0.209
1.18
72.1
481.3
3 (011)
640.2
0.182
1.11
70.0
484.1
4 (100)
736.4
0.177
1.02
68.6
485.5
5 (101)
1015
0.149
0.66
66.2
489.1
6 (110)
1178
0.153
0.48
65.3
488.8
7 (111)
1397
0.140
0.37
62.1
492.5
* Inductance value could not be extracted since the self-resonance frequency exceeded 40 GHz
** Resistance could not reliably be extracted from the small capacitance
Q (1 GHz)
± 0.4%
NA**
35
55
68
75
94
110
125
Note that the data presented in Table 4.2 corresponds to a digital capacitor for which the
isotropic silicon etch was incomplete. Parts of the MIM capacitor which should have been
suspended were proven to be anchored to the substrate by probing the structure. The unreleased
Chapter 4: Digital Capacitor
83
sections contribute a parasitic capacitance to the silicon substrate, which is a complex RC
network whose effective resistance and capacitance vary with frequency. This lossy parasitic
capacitance is responsible for the behavior of |1/(Y11+Y12)| shown in Fig. 4.14 and also increases
the C1g and decreases the Q presented in Table 4.2. The measured Q increases with state since Cs,
the high quality series capacitance, increases with state relative to C1g, the lossy shunt
capacitance. Fig. 4.15 shows the measured Q for the maximum capacitance (state 7) along with a
fit to the data according to (4.30). The disparity between measured data and the extracted model
is similarly caused by the parasitic capacitance to the silicon substrate.
200
Quality Factor (De-embedded)
Quality Factor
180
Extracted Model
160
140
120
100
80
60
40
20
0
1
2
3
4
5
6
Frequency (GHz)
Fig. 4.15. Quality factor as a function of frequency. This plot shows the Q for the maximum capacitance position
with port 2 connected to ground.
The series capacitance of the digital capacitor was measured at each of the eight states for
seven different devices (see Fig. 4.16). Measured data shows the capacitor was successful in
producing a distribution of capacitance values which matches a linear trend with an R2 of 0.9997.
The average digital capacitor tunes from 22.6 fF to 1374 fF, an average tuning ratio of 61:1. The
best-performing digital capacitor tuned from 19.8 fF to 1360 fF, a tuning ratio of 69:1. The
variation between devices, measured by standard deviation, differs slightly depending on the
Chapter 4: Digital Capacitor
84
capacitor state. The standard deviation for the maximum capacitance is 4.6% while the standard
deviation averaged over all states is 7.2%. The standard deviation for state 6 appears large but is
only 6.4%, less than the average. The largest standard deviation, which is not apparent from Fig.
4.16, is that of state 1 at 13.3%, but that standard deviation is primarily due to poor performance
of the least significant capacitance bit for a single device. The variation between devices could be
due to variation in the thickness of the side-wall polymer deposited during the vertical oxide etch
Series Capacitance (fF)
of the CMOS-MEMS process.
1400
1200
1000
800
600
400
200
0
0
1
2
3
4
5
6
7
State
Fig. 4.16. Plot of series capacitance versus state. Error bars indicate the 1-σ standard deviation between different
devices based on 7 measurements.
Series capacitance was measured as the 3-bit digital capacitor was slowly stepped through
one actuation cycle (see Fig. 4.17). First, as predicted by theory, the measured capacitance
increased gradually as the voltage applied to the electrothermal actuator resistors (VET) was
increased. After electrothermal actuation, measured results temporarily diverged from the
predicted theory. Once the rotor electrodes were lowered into the plane with the stator electrodes
but before an electrostatic actuation voltage was applied, the tips of several electrodes displaced
laterally into mechanical contact with their corresponding electrodes (see Fig. 4.9(b)). This lateral
Chapter 4: Digital Capacitor
85
deflection explains the unpredicted jump in series capacitance. Since only the electrode tips
rather than the full length of the electrodes moved into mechanical contact, the displacement
appeared to be partial electrostatic pull-in. After the electrostatic actuation voltage (VES) reached
a certain threshold, typically around 6 V – 10 V, the electrode tips that partially pulled-in were
seen to retract, which caused the measured capacitance to resume agreement with theory. The
observed partial pull-in does not occur on the first actuation cycle but does occur for all
subsequent cycles. The fact that electrostatic force between conductors decreased with increasing
voltage is evidence of dielectric charging, enough trapped charge such that an applied voltage of
approximately 10 V is necessary to counteract this effect.
1200
Measurement
Theory
1000
800
600
400
200
VET (V)
0
4
after heating,
partial pull-in
from charging
electrostatic
pull-in
applied voltage
counteracts
charging effect
20
3
15
2
10
1
5
0
Turn on ET Turn on ES Turn off ET Turn off ES
actuation
actuation
actuation
actuation
VES (V)
Series Capacitance (fF)
1400
0
Fig. 4.17. Plot of series capacitance during an actuation cycle. The x-axis is arbitrary; all measured points shown
were allowed to reach steady-state and maintained for approximately one minute. ―Electrothermal‖ and
―electrostatic‖ are abbreviated as ―ET‖ and ―ES‖, respectively. The plotted data represents a single actuation cycle
from a single device and thus may vary over time or between different devices.
After electrostatic pull-in, represented by the large increase in capacitance from
Chapter 4: Digital Capacitor
86
approximately 200 fF to greater than 1100 fF, the capacitance continues to increase gradually as
power applied to the heating resistors is ramped down. Presumably, this occurs because some
rotor electrodes are lowered too far and, thus, settle into a higher capacitance position as the
temperature is decreased. As the electrostatic actuation voltage is ramped down, capacitance
decreases gradually until one or more capacitance bits suddenly disengage.
4.5.2. Switching Speed
A computer microvision system was used to measure the frequency response of the vertical
electrothermal actuation similar to the method presented in Section 3.5.2. Mechanical motion
was recorded as a sinusoidal voltage with a DC bias was applied to the heating resistors within
the electrothermal actuators. The thermal 3 dB frequency occurs at 503 ± 39 Hz while
mechanical resonance occurs at 37.9 ± 2.9 kHz (see Fig. 4.18). Thus, the switching speed is
limited by the thermal time constant (≈ 0.32 ms) rather than the mechanical response.
Z-displacement (µm)
10
1
Thermal 3dB
Frequency ≈ 500 Hz
0.1
Mechanical Resonance
Frequency ≈ 38 kHz
0.01
10
100
1000
10000
100000
Frequency (Hz)
Fig. 4.18. Electrothermal actuator frequency response.
The switched capacitors were typically switched on by applying voltage to the
electrothermal actuator resistors for 1 ms, or about 3 thermal time constants. During the last
Chapter 4: Digital Capacitor
87
100 µs of electrothermal actuation, the electrostatic actuation voltage was increased from 0 V to
20 V and then maintained as necessary, often for up to several minutes. Faster electrothermal
actuation can be achieved by using higher voltages to heat the electrothermal actuator at a faster
rate. However, to avoid applying excessively high voltages which could damage the limited
number of devices, the absolute minimum switching time was not determined. The shortest
demonstrated switching time was 0.6 ms, or about two thermal time constants. Note that this
switching time is the time necessary for electrothermal actuation and subsequent electrostatic
pull-in. Since Fig. 4.17 shows that the maximum capacitance continues to increase after
electrostatic pull-in while the temperature decreases, several thermal time constants may be
required after the switching time for the capacitance to settle into its final value. Because the
switched capacitors cannot be switched off until the after the actuators have cooled, switching
faster than the thermal time constant would not be practical.
The switched capacitors were typically switched off by lowering the electrostatic actuation
voltage from 20 V to 0 V for 1 ms without applying any voltage the electrothermal actuator
resistors. This method of switching off the capacitors should cause the rotor electrodes to vibrate
at the mechanical resonance frequency. Based on the measured resonance frequency and
mechanical Q, any vibration of the rotor electrodes should settle to within 2% of its initial
displacement in 0.41 ms. Since switching between two digital capacitor states often involves
turning on some bits while turning off other bits, the switching time is limited by the slower
transition, which is the time required to switch on a capacitance bit.
4.5.3. Thermal Aspects
The heating resistors embedded in the electrothermal actuator beams were used as
Chapter 4: Digital Capacitor
88
temperature sensors to characterize the temperature necessary for actuation. The heater resistance
was monitored as the power dissipated in the resistors was increased. Based on the measured
temperature coefficient of resistivity, the maximum operating temperature necessary to lower the
rotor electrodes into plane with the stator electrodes was calculated to be 249.5 ± 5.4°C. Because
the electrothermal actuators are thermally isolated from the bulk of the substrate, this temperature
is applied only to the MEMS structure and thus does not significantly affect other on-chip CMOS
devices.
250
225
200
150
125
100
Temperature ( C)
175
75
50
25
Fig. 4.19. Simulated temperature profile of electrothermal actuator. Symmetry boundary conditions are applied so
the simulation represents an array of many switched capacitors in parallel.
The temperature profile of the electrothermal actuator beam when heated was simulated
using Comsol finite element analysis (see Fig. 4.19). Measurements of the temperature profile
were not possible since the quantum infrared microscope lacks the resolution required for the
small widths of the actuator beams and signal beams. The temperature of the actuator beams
when heated is not uniform because the heating resistor is lumped near the base of the actuator
Chapter 4: Digital Capacitor
89
beam. Heat conduction, primarily through the air, causes the temperature to decrease along the
length of the actuator beams. Some of that heat is transferred to the signal beams running parallel
to the actuator beams, which causes the temperature of the signal beams to increase along their
length.
The capacitance of the digital capacitor was measured over a range of ambient temperatures
to assess the temperature sensitivity inherent to electrothermal actuation. The maximum
capacitance position is not significantly affected by temperature change since the capacitive
electrodes are locked together by electrostatic force. However, for the minimum capacitance
position, increasing the ambient temperature causes the electrothermal actuators to lower the
rotor electrodes closer to the stator electrodes, which increases the minimum capacitance. While
varying the ambient temperature from 25°C to 100°C, the minimum series capacitance of the
digital capacitor increased from 20.0 fF to 35.1 fF (see Fig. 4.20). Over the same temperature
range, the maximum capacitance varied between 1443 fF and 1485 fF, a variation less than 3%
of the nominal (25°C) capacitance value. The theoretical maximum ambient temperature at
which the digital capacitor could still function is approximately 180°C, which is the zero-stress
temperature for the electrothermal actuator beams. However, operation at that temperature would
not be practical since the capacitive electrodes would be in the same plane without requiring
electrothermal actuation and the tuning ratio would decrease to less than 10:1. A more practical
maximum ambient temperature of 85°C would result in a minimum tuning ratio still greater than
40:1.
Chapter 4: Digital Capacitor
90
2000
1750
50
1500
40
1250
30
1000
750
20
500
10
250
0
Max. Capacitance (fF)
Min. Capacitance (fF)
60
0
25
40
55
70
85
100
Temperature ( C)
o
Fig. 4.20. Series capacitance of a 3-bit digital capacitor as a function of ambient temperature.
4.5.4. Reliability Tests
To assess the short-term reliability of the digital capacitor, the series capacitance was
measured after each of twenty actuation cycles for all eight capacitance positions. The
capacitance for each position was repeatable with a worst-case standard deviation less than 1.4%
of the average capacitance value. The average standard deviation for any given position was
0.5% of the average capacitance value.
To assess the long-term reliability of the digital capacitor, automated measurements were
setup to measure the series capacitance as the capacitor was cycled between minimum and
maximum capacitance. However, these tests failed much sooner than expected, lasting only hours
rather than days. The digital capacitor operated correctly until electrostatic pull-in failed to occur.
Adjusting the voltage applied to the heating resistors caused electrostatic pull-in to temporarily
resume until the problem occurred again. Repeated actuation was causing a shift in the vertical
position of the rotor electrodes when power was applied to the heating resistors.
Chapter 4: Digital Capacitor
91
An inspection of the digital capacitor after repeated actuation revealed damage on the
surface of the electrothermal actuators, which is peculiar for several reasons (see Fig. 4.21).
While the damage is greatest at the location of the heating resistors, damage is not confined to
that maximum temperature location and often appears farther down the length of the beam where
the temperature is reduced. Also, the damaged regions are not continuous along the length of the
actuator beam. Damage only occurred on the electrothermal actuator beams and never on the
signal beams which experienced the same mechanical motion. Since the signal beams are
significantly cooler than the actuator beams, these observations suggest that the damage must be
caused or at least accelerated by high temperature. However, damage only occurs from
temperature cycling; heating the actuators to a constant temperature of 250°C for more than
12 hours did not produce visible surface damage. Thus this damage is classified as thermallyinduced mechanical fatigue.
Key
= resistor
Key
20 µm
= resistor
5 µm
(a)
(b)
Fig. 4.21. SEM images of surface damage caused by repeated temperature cycling at 250°C. The white boxes
indicate the locations of the embedded heating resistors.
To measure the mechanical fatigue, two digital capacitors were cycled between room
temperature (23 ± 2°C) and a specified maximum temperature for more than 40 million cycles.
The first capacitor was cycled with a maximum temperature of 250°C, the nominal temperature
Chapter 4: Digital Capacitor
92
necessary to operate the digital capacitor. The second capacitor was cycled with a more
conservative maximum temperature of 180°C, which is insufficient to enable subsequent
electrostatic actuation for the current design. The frequency of actuation was set to 100 Hz to
allow ample time (> 15 thermal time constants) for the actuator beams to reach their maximum
temperatures. Testing was stopped intermittently while a Wyko optical profilometer was used to
measure the vertical gap between the rotor and stator electrodes. The voltage and current applied
to the heating resistors was also monitored to verify that the heater resistance remained constant
Vertical Gap w/ Heating (µm)
to within 1% of the nominal value.
9
7
5
Cycling at Low Temp. (≈ 180oC)
3
Cycling at High Temp. (≈ 250oC)
1
-1
-3
-5
1.E+03
103
1.E+04
104
1.E+05
105
1.E+06
106
1.E+07
107
1.E+08
108
# Cycles
Fig. 4.22. Vertical gap during heating as a function of the number of actuation cycles. A positive gap indicates that
the tip of the rotor electrodes are deflected above the stator electrodes.
As a result of repeated temperature cycling, the vertical gap between the rotor and stator
electrodes during heating decreased from 7.8 µm to 5.8 µm and from 0.3 µm to -4.6 µm for
maximum temperatures of 180°C and 250°C, respectively (see Fig. 4.22). A vertical gap of zero
indicates that the rotor and stator electrodes are perfectly aligned for electrostatic actuation. For
both temperatures, repeated actuation caused the rotor electrode to move to a progressively lower
position while the total actuation stroke (nominally 28 – 29 µm) remained constant to within 8%.
Chapter 4: Digital Capacitor
93
Typically, electrostatic pull-in still occurs for vertical gaps up to approximately 1 – 2 µm but fails
for larger gaps. Thus the current digital capacitor designed to operate at 250°C will not exceed
10 million cycles unless the actuation voltage is dynamically adjusted to account for the fatigue.
Digital capacitors designed to operate at 180°C will exceed 10 million cycles, longer than
capacitors operating at higher temperatures.
Several qualitative observations are worth noting due to their potential impact on reliability.
These observations are atypical results that are not always repeatable and do not occur for every
digital capacitor. Occasionally, a capacitive bit that has been actuated into maximum capacitance
position would not return to minimum capacitance position after the electrostatic actuation
voltage was lowered to zero. The stuck capacitive bit could usually be unstuck using repeated
electrothermal actuation. Rarely, after actuating a capacitance bit, DC current caused by the
electrostatic actuation voltage would flow through the capacitive electrodes. Monitoring the
current while varying the electrostatic actuation voltage revealed a diode-like current-voltage
relationship which turned on at 10 V. Presumably, this diode-like behavior is electrical
breakdown occurring between the capacitive electrodes. On one occasion, the digital capacitor
was left in maximum capacitance position after all voltages had been disconnected and remained
in that position over night. The capacitor could not be returned to minimum capacitance position
using electrothermal actuation. The measured DC resistance between the electrostatic actuation
voltage and port 2 was approximately 1 MΩ, the resistance of the bias resistor. The fact that the
resistance was measurable at DC suggests that one or more capacitive electrodes became fused
together.
Chapter 4: Digital Capacitor
94
4.5.5. Updated Topology
For the initial 3-bit digital capacitor presented above, the shunt capacitance connected to
port 2, C2g, was large, comparable with the maximum series capacitance, Cs, (see Table 4.2). If
the digital capacitor is used as a shunt capacitor, then port 2 can be connected to ground so that
C2g does not affect electrical performance. However, if the digital capacitor is used as a series
capacitor, then C2g is a large parasitic capacitance to ground. This parasitic capacitance is large
because the signal beams carrying the RF signal were interwoven with the grounded
electrothermal actuators (see Fig. 4.23(a)). To reduce this parasitic capacitance, the topology was
updated such that the actuator beams are lumped together, separate from the signal beams
carrying the RF signal (see Fig. 4.23(b)). This modification was expected to reduce C2g by an
order of magnitude without significantly affecting other electrical and mechanical characteristics.
(a)
(b)
Fig. 4.23. Diagram of capacitive bit with (a) interwoven actuator beams resulting in large parasitic capacitance (b)
updated topology to reduce parasitic capacitance.
The updated 3-bit digital capacitor (see Fig. 4.24) was successfully actuated into all eight
capacitor states (see Fig. 4.25), each of which was electrically characterized using the method
described in Appendix A. Fig. 4.26 shows the S-parameters for the minimum capacitance and
maximum capacitance states. Fig. 4.27 shows the equivalent circuit model in terms of Yparameters and lumped circuit elements. Fig. 4.14 shows the lumped impedances for the
minimum capacitance and maximum capacitance states. Equations (4.25) through (4.29) were
Chapter 4: Digital Capacitor
95
used to calculate the equivalent circuit element values (see Fig. 4.27(b)).
100 µm
MIM
Capacitor
Port 1
Bit 3
Bit 2
Electrodes
Actuators
Actuators
Port 2
Bit 1
Fig. 4.24. SEM image of 3-bit digital capacitor updated to reduce parasitic capacitance. The chunk of debris was left
in place since manual removal could damage the actuators.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
Fig. 4.25. Microscope image of the updated 3-bit digital capacitor in state (a) 0 (b) 1 (c) 2 (d) 3 (e) 4 (f) 5 (g) 6 (h) 7.
Each capacitive bit is controlled independently to select the desired capacitance.
Chapter 4: Digital Capacitor
96
10
0
0
S-parameters (dB)
S-parameters (dB)
10
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-10
-20
-30
-10
-20
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-30
-40
-40
0.1
1
0.1
10
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 4.26. S-parameter magnitude as a function of frequency for (a) the minimum capacitance state (b) the maximum
capacitance state. S12 is not plotted because S12 and S21 are equivalent for passive networks.
Port 1
Port 2
-Y21
Y11+Y12
Port 1
Rs
Cs
Ls
Port 2
C2g
Y22+Y21
1E+5
1E+5
1E+4
1E+4
Impedance (Ω)
Impedance (Ω)
(b)
(a)
Fig. 4.27. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements. Circuit element
values are extracted from measured 2-port network parameters.
1E+3
1E+2
1E+1
|1/-Y21| (Measured)
|1/(Y11+Y12)| (Measured)
|1/(Y22+Y21)| (Measured)
Extracted Model
1E+0
1E-1
0.1
1
1E+3
1E+2
1E+1
|1/-Y21| (Measured)
|1/(Y11+Y12)| (Measured)
|1/(Y22+Y21)| (Measured)
Extracted Model
1E+0
1E-1
10
0.1
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 4.28. Lumped impedances as a function of frequency for (a) the minimum capacitance position (b) the maximum
capacitance position. The series impedance behaves like an RLC circuit, and the shunt impedances are capacitive
below 10 GHz. The self-resonance frequency is greater than 40 GHz for the minimum capacitance position and
decreases to 10 GHz for the maximum capacitance position.
Chapter 4: Digital Capacitor
97
Table 4.3: Electrical Characteristics of the Updated Digital Capacitor
Cs (fF)
Ls (nH)
Rs (Ω)
C1g (fF)
C2g (fF)
Q1 (1 GHz)
Q2 (1 GHz)
State
± 0.4%
± 0.2%
± 0.8%
± 0.2%
± 0.2%
± 0.4%
± 0.4%
0 (000)
18.3
NA*
NA**
33.5
55.4
NA**
NA**
1 (001)
234.1
0.293
2.52
33.0
55.6
170
341
2 (010)
444.7
0.256
1.28
33.1
56.0
193
329
3 (011)
648.3
0.239
0.99
31.4
57.9
190
289
4 (100)
795.4
0.226
0.76
30.9
58.7
199
293
5 (101)
960.8
0.198
0.56
29.5
60.0
223
336
6 (110)
1130
0.200
0.50
28.4
61.5
222
317
7 (111)
1335
0.191
0.42
27.9
61.9
240
369
* Inductance value could not be extracted since the self-resonance frequency exceeded 40 GHz
** Resistance could not reliably be extracted from the small capacitance
The electrical characteristics of the updated 3-bit digital capacitor are presented in Table 4.3.
As designed, the series capacitance, Cs, series inductance, Ls, and series resistance, Rs, are similar
to those of the initial digital capacitor presented in Table 4.2. The shunt capacitance
corresponding to port 1, C1g, was reduced from an average of 69.0 fF to an average of 31.0 fF,
primarily because the silicon beneath the digital capacitor had been completely etched away. The
shunt capacitance corresponding to port 2, C2g, was reduced from an average of 485.1 fF to an
average of 58.4 fF, which was the goal of the updated design.
Table 4.3 includes two different quality factors, Q1 and Q2. Q1 is the quality factor seen
looking into port 1 with port 2 connected to ground.
Q1 
imag 1 Y11 
real1 Y11 
.
(4.31)
Q2 is the quality factor seen looking into port 2 with port 1 connected to ground.
Q2 
imag 1 Y22 
real1 Y22 
.
(4.32)
Only a single quality factor was reported for the initial digital capacitor in Table 4.2 because the
shunt capacitance, C2g was large compared with the series capacitance, Cs. Using the initial
digital capacitor as a shunt capacitor with port 1 connected to ground would result in a tuning
Chapter 4: Digital Capacitor
98
ratio of only 3.8:1, an unacceptable sacrifice for moderately increased Q. However, since C2g has
been reduced in the updated digital capacitor, two configurations with a large shunt tuning ratio
are possible. Looking into port 1 with port 2 connected to ground, the tuning ratio is 26:1 with a
Q of 240 at 1 GHz for the maximum capacitance position. Looking into port 2 with port 1
connected to ground, the tuning ratio is 19:1 with a Q of 369 at 1 GHz for the maximum
capacitance position. Fig. 4.29 shows the measured Q2 for the maximum capacitance along with
Quality Factor
a fit to the data according to (4.32).
500
450
400
350
300
250
200
150
100
50
0
Quality Factor (De-embedded)
Extracted Model
1
2
3
4
5
6
Frequency (GHz)
Fig. 4.29. Quality factor as a function of frequency for the updated digital capacitor. This plot shows the Q for the
maximum capacitance position with port 1 connected to ground.
4.6. Discussion
Compared with the electrothermal gap-tuning capacitor presented in Chapter 3, the 3-bit
digital capacitor has demonstrated improvements in tuning ratio and capacitance density by 10x
and 5x, respectively. Variation between devices, represented by the standard deviation of the
maximum capacitance, has decreased from 18% to 4.4%. While the transient actuation power has
increased, the energy per actuation (normalized to 1 pF of maximum capacitance) has decreased
Chapter 4: Digital Capacitor
99
from 670 µJ to 50 µJ because the switching time has improved from 30 ms to 1 ms. The series
inductance has been reduced below 200 pH, which maintains the self-resonance frequency near
10 GHz since the maximum capacitance has increased.
Table 4.4: Digital Capacitor Results
Name
Initial Digital Capacitor
Updated Digital Capacitor
Tuning ratio (series)
61:1
73:1
Tuning ratio (shunt)
16:1
19:1
Q (1 GHz) for Cs,max*
125
369
Self-resonance frequency for Cs,max
11.4 GHz
10.0 GHz
Cs,max
1374 fF
1335 fF
Cs,min
22.6 fF
18.3 fF
C1g**
69.0 fF
31.0 fF
C2g**
485.1 fF
58.4 fF
Rs for Cs,max
0.37 Ω
0.42 Ω
Ls for Cs,max
0.140 nH
0.191 nH
Area
0.16 mm2
0.17 mm2
Capacitance Density
8.6 pF/ mm2
7.9 pF/ mm2
Actuation Method
electrothermal / electrostatic
electrothermal / electrostatic
Control
3-bit digital
3-bit digital
Voltage
4 V / 20 V
4 V / 20 V
Power
70 / 0 mW***
70 / 0 mW***
Switching Time
1 ms
NA****
Cs,max Standard Deviation
4.4%
NA****
Integration
maskless post-CMOS etching
maskless post-CMOS etching
* Quality factor is calculated from a fit to measured data ranging from 1 GHz to 4 GHz
** Shunt capacitances are averaged over all capacitor states
*** Power is only consumed during switching
**** Value was not measured but is expected to be similar to those of the initial digital capacitor
The digital capacitor has two primary disadvantages when compared with the electrothermal
gap-tuning capacitor. The actuation scheme is more complicated and larger voltages are required
for electrostatic actuation. However, these drawbacks are minor because other examples of
integrated RF MEMS have shown that large voltages can be provided by CMOS charge pumps,
given that high-voltage CMOS is available, and that actuation control systems are necessary for
even a simple vertical electrostatic pull-in structure [38]. Thus future work should be focused on
improving the reliability of the digital capacitor.
Chapter 4: Digital Capacitor
100
The 3-bit digital capacitor produces repeatable capacitance values over short periods of time
but suffers from mechanical fatigue due to repeated electrothermal actuation. The current
lifetime, approximately 10 million cycles, limits the capacitor to applications that do not require
continuous switching. The observed fatigue does not cause sudden catastrophic failure of the
capacitor but mandates an adjustment of the electrothermal actuation voltage to align the
capacitive electrodes for electrostatic actuation. If a control system was designed to dynamically
adjust the electrothermal actuation voltage, the lifetime of the digital capacitor could be extended
at the cost of increased minimum capacitance over time. Alternatively, the digital capacitor
design could be modified to operate at lower temperatures, which may increase the lifetime by an
order of magnitude. Other solutions may exist such as using different materials for the
electrothermal actuators. Copper, which is readily available in more advanced CMOS processes,
may be more resistant to thermally-induced fatigue than aluminum due to a higher melting
temperature.
Chapter 4: Digital Capacitor
101
Chapter 5.
Phase Shifter
This section presents a 4-bit CMOS-MEMS phase shifter for phased antenna arrays. The
phase shifter is composed of a micromachined transmission line periodically loaded with CMOSMEMS 4-bit digital capacitors. MIM capacitors are embedded in the transmission line in series
with the digital capacitor bits to trade tuning ratio for increased capacitor Q. Section 5.1 explains
why the CMOS-MEMS phase shifter has been developed. Section 5.2 presents the phase shifter
topology. Section 5.3 presents an analysis of the topology linking the degrees of freedom to
performance metrics. Section 5.4 describes how that analysis was used to define the geometry of
the phase shifter and digital capacitors. Section 5.5 presents characterization results of the
fabricated design.
5.1. Motivation
Phase shifters are required for phased antenna arrays, which consist of many antennas each
driven by a phase shifter in series with a power amplifier (see Fig. 5.1). The phase shifters create
a variable time delay between the different antennas enabling the direction of the transmitted
beam to be steered electronically rather than mechanically. Beam steering is necessary to simply
improve the antenna gain for a specific direction or to enable more complex radar applications
which require continuous scanning [15]. For example, phased antenna arrays operating at
77 GHz are being developed for automotive collision avoidance systems [41]. Electronic beam
steering alleviates the need to mechanically shift or rotate the antenna, which potentially
improves both speed and reliability.
Chapter 5: Phase Shifter
102
∆φ1
∆φ2
∆φ3
Antennas
Power
Amplifiers
Phase
Shifters
Fig. 5.1. Schematic of phased antenna array. Phase shifters create a variable time delay between antennas to enable
electronic beam steering.
Phased antenna arrays can be large, sometimes requiring tens or hundreds of thousands of
components per array for military applications, so the cost and power consumption are primary
concerns. Both of these characteristics are influenced by the insertion loss of the phase shifters.
MEMS phase shifters have been developed to reduce phase shifter insertion loss by using RF
MEMS switches and variable capacitors [15]. Reduced phase shifter insertion loss enables a
reduction in both the number of required power amplifiers and the power consumption of phased
antenna arrays. However, previously developed MEMS phase shifters are not monolithically
integrated with CMOS.
MEMS phase shifters which are monolithically integrated with CMOS can be combined
with on-chip power amplifiers to further reduce the number of components required for phased
antenna arrays. Thus the goal of this work was to demonstrate the feasibility of MEMS phase
shifters which are monolithically integrated using the CMOS-MEMS process. Using this process,
a distributed MEMS phase shifter was fabricated in 0.35 µm BiCMOS with four metal layers.
The phase shifter is composed of a micromachined transmission line periodically loaded with 4bit CMOS-MEMS digital capacitors. The digital capacitors, originally presented in Chapter 4,
Chapter 5: Phase Shifter
103
were modified for increased Q resulting in an average phase shifter insertion loss of 2.9 dB at
32.0 GHz.
Phase Shifter Section
T-Line
Lsect
Cd
T-Line
Cd
Lsect
Cl’lsect
Lsect
Cd
Lsect
Cd Cl’lsect
Cd Cl’lsect
Lsect
Csect
T-Line
Cd
Lsect
Csect
Csect
Fig. 5.2. Schematic of distributed MEMS phase shifter (for N = 3 sections) as (a) distributed components (b) lumped
component (c) lumped components with a single shunt capacitances.
5.2. Topology
The CMOS-MEMS phase shifter is a distributed MEMS phase shifter composed of a
micromachined transmission line periodically loaded with CMOS-MEMS digital capacitors (see
Fig. 5.2(a)). The digital capacitors are spaced evenly along the transmission line such that the
phase shifter is composed of a number of identical sections. The variable capacitance of the
digital capacitor adds in parallel to the capacitance of the transmission line to form a distributed
MEMS transmission line (see Fig. 5.2(b)) [42]. The composite circuit is a discrete transmission
Chapter 5: Phase Shifter
104
line with tunable shunt capacitance (see Fig. 5.2(c)). Varying the capacitance changes the phase
velocity of the line resulting in a phase shift at the output.
Key:
Thermal
Isolation
Electrothermal
Actuator Beam
Signal Beams
Metal 1
Metal 2
Metal 3
Transmission
Line
Rotor
Electrodes
Metal 4
Rotor
Electrodes
Stator Electrodes
Stator Electrodes
Electrothermal
Actuator Beam
Thermal
Isolation
Signal Beams
(a)
VES RB
Port 1
VET
VET
RHeat
CMIM
CMIM
RHeat
Port 2
(b)
(c)
Fig. 5.3. Diagram of the CMOS-MEMS switched capacitor viewed from above (a) with annotations (b) with circuit
schematic; (c) SEM image of eight CMOS-MEMS switched capacitors in parallel.
The CMOS-MEMS digital capacitors used in the phase shifter are composed of many
CMOS-MEMS switched capacitors that are nearly identical to those described in Chapter 4 (see
Fig. 5.3). The dimensions of the electrothermal actuators and capacitive electrodes were left
unchanged to achieve the same actuation characteristics presented in Section 4.5.2. The switched
capacitors are mirrored on either side of the micro-machined transmission line for symmetry. The
stator electrodes are anchored to the transmission line whereas the rotor electrodes are anchored
to the metal-4 ground plane. Because only a shunt capacitance is required rather than a series
capacitance, the rotor electrodes are electrically connected to the ground plane.
Chapter 5: Phase Shifter
105
The CMOS-MEMS phase shifter was designed in a 4-metal, 0.35 µm BiCMOS process
from TowerJazz Semiconductor. All four metals are aluminum. Fig. 5.4 shows the resulting
cross-sections of the phase shifter after the CMOS-MEMS process. The micromachined
transmission line is composed of a metal-4321 beam with the maximum density of vias to
minimize series resistance. Near the switched capacitors, the transmission line is split into two
segments to ensure that the structure releases from the substrate during the CMOS-MEMS
process (see Fig. 5.4(a)). Splitting the line is necessary because the lateral gaps between the topmost metal layers are smaller in the vicinity of the switched capacitors. The majority of the
transmission line consists of a single segment since the lateral gaps between the transmission line
and the ground plane are large enough to guarantee release (see Fig. 5.4(b)).
Transmission Line
Actuator
Electrode
Electrode
Actuator
≈ 10 µm
≈ 50 µm
(a)
Ground Plane
Ground Plane
Transmission Line
≈ 10 µm
≈ 50 µm
(b)
Key:
Metal 1
Metal 2
Metal 3
Metal 4
Oxide
Via
Silicon
Fig. 5.4. Cross-section of the phase shifter (a) along the rotor electrode of a switched capacitor (b) along a section of
transmission line without a switched capacitor.
The micromachined transmission line provides high-Q series inductance such that the
insertion loss of the phase shifter is primarily dependant on the Q of the digital capacitors.
Characterization in Section 4.5.1 showed that the Q of the digital capacitor when used as a shunt
Chapter 5: Phase Shifter
106
capacitor is 125 at 1 GHz for the maximum capacitance. The Q increases to 160 at 1 GHz after
additional silicon etching is used to remove all silicon beneath the MEMS structure. Assuming
series resistance is the dominant loss mechanism, the capacitor Q decreases to 5.3 at 30 GHz,
which results in unacceptably large insertion losses. Note that this calculation is an
approximation since other factors such as skin depth and losses associated with the silicon
substrate affect the capacitor Q. To minimize insertion loss, the digital capacitors were modified
for increased Q at frequencies greater than 30 GHz.
Bit 1
Port 1
Bit 2
Bit 3
Bit 4
CMIM1
CMIM2
CMIM3
CMIM4
RB1 CMEMS1
RB2 CMEMS4
RB3 CMEMS3
RB4 CMEMS4
VES1 RMEMS1
VES2 RMEMS2
VES3 RMEMS3
VES4 RMEMS4
RHeat1
RHeat2
RHeat3
Port 2
RHeat4
VET
Fig. 5.5. Schematic of 4-bit digital capacitor used in the phase shifter.
Fig. 5.5 shows the schematic of the modified digital capacitor used in the phase shifter.
CMEMS[n] and RMEMS[n] are the capacitance and resistance, respectively, of the CMOS-MEMS
electrodes for bits n = 1 to 4. MIM capacitors, CMIM[n] are embedded in the transmission line and
connected in series with the MEMS capacitance. For the digital capacitors presented in Chapter
4, the MIM capacitors were connected in parallel to form a DC blocking capacitor with
capacitance much larger than the maximum MEMS capacitance. For the phase shifter, the MIM
capacitors are sized such that the MIM capacitance is smaller than the maximum MEMS
capacitance but much larger than the minimum MEMS capacitance. The net result is a decrease
in maximum capacitance which decreases tuning ratio but increases the Q to enable the design of
Chapter 5: Phase Shifter
107
a phase shifter with low insertion loss.
The MIM capacitors still function as DC blocking capacitors to enable capacitive bits to be
independently selected by their respective electrostatic actuation voltage, VES[n]. The bias
resistors, RB[n], are large, on the order of MΩ‘s, and composed of polysilicon with a sheet
resistance of 1 kΩ. These resistors connect the electrostatic actuation voltages to the stator
electrodes. The heating resistors, RHeat[n], are necessary for electrothermal actuation and do not
significantly affect RF performance. All digital capacitors are connected such that a single
electrothermal actuation voltage, VET, and four electrostatic actuation voltages, one for each bit,
control all sections of the phase shifter.
5.3. Analysis
The capacitances of the digital capacitor bits, Cd[n], n = 1 to 4, are determined by the
capacitances of the MEMS electrodes, CMEMS[n], and the MIM capacitances, CMIMS[n].
Cd[n ] 
C MEMS[n ]C MIM[n ]
C MEMS[n ]  C MIM[n ]
(5.1)
,
The total capacitance of the digital capacitor is the sum of the capacitive bits, which varies
depending on which bits are activated.
Cd  Cd[1]  Cd[ 2]  Cd[ 3]  Cd[ 4] ,
(5.2)
Assuming series resistance is the dominant loss mechanism, the Q can be calculated with the
effective series resistance, Rs.
Qmax 
1
C d,min Rs
,
Chapter 5: Phase Shifter
(5.3)
108
Qmin 
1
C d,max Rs
,
(5.4)
where ω is the electrical frequency. The maximum Q corresponds to the minimum capacitance
while the minimum Q corresponds to the maximum capacitance.
The capacitance of the digital capacitors, Cd, adds in parallel with the capacitance of the
transmission line resulting in the capacitance of one phase shifter section, Csect.
Csect, min  Cl ' lsect  Cd, min ,
(5.5)
Csect, max  C l ' lsect  C d, max ,
(5.6)
where Cl‘ and lsect are the transmission line capacitance per unit length and section length,
respectively. Assuming that the digital capacitor contributes negligible series inductance, the
inductance of one phase shifter section, Lsect, is determined by the transmission line inductance
per unit length, Ll‘, and section length.
Lsect  Ll 'lsect ,
(5.7)
Provided that the frequency of operation is much less than the Bragg frequency, fBragg, the
phase shifter performance can be approximated assuming that the variable capacitance is
distributed.
f Bragg, min 
1
 Lsect C sect, max
,
(5.8)
Alternatively, the impedance of the transmission line sections can be combined with that of the
digital capacitors in ABCD matrices. The resulting matrices can be cascaded to calculate phase
shifter performance without approximation [43]. However, for simplicity, the remainder of this
analysis assumes the variable capacitance is distributed. The loaded transmission line is also
assumed to have low loss.
Chapter 5: Phase Shifter
109
Rl '  Ll ' ,
(5.9)
Gl '  Cl ' ,
(5.10)
where Rl‘ and Gl‘ are the series resistance and shunt conductance per unit length of the
transmission line, respectively. Circuit simulation is used for the final calculation of phase shift
and insertion loss.
The characteristic impedance of the loaded transmission line, Z0, varies according to the
digital capacitance.
Z 0,max 
Z 0,min 
Lsect
(5.11)
C sect,min
,
Lsect
,
C sect,max
(5.12)
The characteristic impedance determines the maximum reflected power, S11,max, which occurs
when the total length of the phase shifter is such that the loaded transmission acts as a quarter
wavelength transformer.
S11,max  20 log 10
Z0
2
ZL 1
2
Z0
2
ZL 1
2
,
(5.13)
where ZL is the load impedance, which is 50 Ω for this work.
Assuming that the reflected power is negligible, the insertion loss, IL, can be calculated
based on the number of phase shifter sections, N, the digital capacitor Q, and transmission line
characteristics [43].
 C d,min Z L lsectZ i
ILmin  N 

 2Q
ZL
max

Chapter 5: Phase Shifter

,


(5.14)
110
 C d,max Z L l sectZ i
ILmax  N 

 2Q
ZL
min


,


(5.15)
where α and Zi are the loss per unit length and characteristic impedance, respectively, both
corresponding to the unloaded transmission line.
The phase constant, β, of the loaded transmission line varies according to the capacitance of
the phase shifter sections.
 min 
 max 
 LsectCsect,min
lsect
 LsectCsect,max
lsect
,
(5.16)
,
(5.17)
The maximum phase shift, ∆φmax, is determined by the difference in achievable phase constants
and is proportional to the number of phase shifter sections.
 max  Nlsect  max   min  .
(5.18)
Using (5.16) and (5.17) to expand (5.18) shows the maximum phase shift in terms of the
capacitance and inductance of each phase shifter section.
 max  N Lsect


Csect,min  Csect,max .
(5.19)
Note that the phase shift does not scale linearly with increasing capacitance, but rather as
difference of two square roots. The phase shift scales linearly with frequency, which indicates a
constant time delay rather than a constant phase shift over a given frequency range.
5.4. Design
The micromachined transmission line was designed to maximize transmission line quality
factor, QTL, which minimizes loss for a given phase shift. The unloaded characteristic impedance
Chapter 5: Phase Shifter
111
was chosen to be approximately 100 Ω, because the addition of digital capacitors reduces the
loaded characteristic impedance according to (5.11) and (5.12). The transmission line dimensions
were determined through iterative simulations with HFSS. The signal line was made 20 µm wide
with 20 µm air gaps to the ground plane. The line consists of all four metal layers with the
maximum density of vias. Mechanical supports are placed periodically along the line to minimize
deflection caused by the vertical force exerted by the electrothermal actuators. The simulated Sparameters of the micromachined transmission line were used to calculate the transmission line
parameters at 30 GHz (see Table 5.1). The unloaded characteristic impedance is 98.8 Ω, the loss
per unit length is 0.07 dB/mm, and the transmission line QTL is 43 at 30 GHz.
Table 5.1: Phase Shifter Design Parameters
Parameters
Value
Calculation
Value
CMEMS[1],min*
0.85 fF
Cd[1],min
1.44 fF
CMEMS[2],min*
0.85 fF
Cd[2],min
1.57 fF
CMEMS[3],min*
1.71 fF
Cd[3],min
3.13 fF
CMEMS[4],min*
3.41 fF
Cd[4],min
6.26 fF
CMEMS[1],max*
4.42 fF
Cd[1],max
1.44 fF
CMEMS[2],max*
4.42 fF
Cd[2],max
1.57 fF
CMEMS[3],max*
8.84 fF
Cd[3],max
3.13 fF
CMEMS[4],max*
17.7 fF
Cd[4],max
6.26 fF
CMIM[1]
2.02 fF
Cd,min**
18.6 fF
CMIM[2]
6.84 fF
Cd,max**
123 fF
CMIM[3]
12.7 fF
Qmax
123
CMIM[4]
24.7 fF
Qmin
18.6
l’
540 µm
Csect,min
33.7 fF
N
8
Csect,max
138 fF
ω
30 GHz
Lsect
189 pH
ZL
50 Ω
fBragg,min
62 GHz
R'
1.19 Ω/mm
Z0, max
75 Ω
L'
350 pH/mm
Z0, min
37 Ω
C'
36.0 fF/mm
S11,max
-10 dB
G'
39.1 MΩ-1/mm
ILmin
0.7 dB
Zi
98.8 Ω
ILmax
2.4 dB
α
0.069 dB/mm
βmin
0.94 rad/mm
β
0.689 rad/mm
βmax
1.90 rad/mm
QTL
43.4
∆φmax
223.8°
* Parameter extracted from measured data
** Includes parasitic capacitance from mechanical supports
Chapter 5: Phase Shifter
112
Using the simulated transmission line characteristics, the digital capacitors were designed to
shift the loaded characteristic impedance from 75 Ω to 37 Ω to ensure that S11 remained below
−10 dB according to (5.13). The characteristic impedance, determined by (5.11) and (5.12), was
controlled by sizing the MIM capacitors to create a 6.6:1 tuning ratio according to (5.1). Since
the MIM capacitors are embedded in the micromachined transmission line, there is a significant
oxide capacitance that adds in parallel with each of the MIM capacitances. The MIM
capacitances listed in Table 5.1 include the contributions of the oxide capacitances, which were
calculated using finite element analysis. Using (5.4), the capacitor Q was calculated to be 18.6 at
30 GHz for the calculated maximum capacitance of 123.3 fF. Fig. 5.6 shows one half of the
fabricated digital capacitors attached to the micromachined transmission line. The other half of
the digital capacitor is mirrored on the other side of the transmission line.
Bit 1 D
Bit 2
Bit 3
Bit 4
D
100 µm
MIM
Capacitors
Actuators
Electrodes
Fig. 5.6: SEM image of phase shifter digital capacitor. The rotor electrodes are vertically deflected into the minimum
capacitance state. ―D‖ indicates dummy bits which are included for temperature uniformity.
The length of one phase shifter section (see Fig. 5.7) was set to 540 µm resulting in a
minimum Bragg frequency of 62 GHz according to (5.8). The number of sections was limited to
eight by the size of the CMOS die. Using (5.18), (5.14), and (5.15), the maximum phase shift and
Chapter 5: Phase Shifter
113
average insertion loss were calculated to be 223.8° and 1.5 dB at 30 GHz. Note that the
calculated phase shift is less than 337.5°, which is the minimum phase shift required for sixteen
steps distributed linearly between 0° and 360°. However, the phase shift can be scaled by
increasing the number of sections, so a calculated phase shift of 223.8° was acceptable for
characterization. The fabricated phase shifter measures 4320 µm by 560 µm, a total area of
2.42 mm2 (see Fig. 5.8). Table 5.1 list all the parameters used for design of the phase shifter.
Digital
Capacitors
Transmission
Line
Ground
Plane
Mechanical
Supports
100 µm
Fig. 5.7: SEM image of one CMOS-MEMS phase shifter section.
Phase Shifter Section
G
S
G
540 µm
560 µm
G
S
G
1 mm
Fig. 5.8: SEM image of the CMOS-MEMS phase shifter composed of eight phase shifter sections.
5.5. Characterization
To verify the phase shifter design, both the phase shifter and a single copy of the digital
capacitor used in the phase shifter were characterized. All digital capacitors were controlled
Chapter 5: Phase Shifter
114
using the actuation methods presented in Chapter 4 except that capacitive bits were
independently selected using multiple electrostatic actuation voltages rather than multiple
electrothermal actuation voltages (see Fig. 5.9). Probe pads were included to access the heater
resistors for the dummy bits independently from those of the capacitive bits in case the dummy
bits required more power to reach a uniform temperature. In hindsight, multiple electrothermal
actuation voltages were unnecessary because a single electrothermal actuation voltage applied to
both the capacitive bits and dummy bits proved sufficient for actuation. The digital capacitors
required 4.8 V for electrothermal actuation and 20 V for electrostatic actuation. During
electrothermal actuation, a single digital capacitor consumed 40 mW while the phase shifter
consumed 320 mW. Each of the eight digital capacitors in the phase shifter operated identically,
which qualitatively demonstrates the uniformity of the electrothermal actuators.
(a)
(b)
Fig. 5.9: Microscope image of CMOS-MEMS digital capacitor (a) before actuation (b) after actuation in state 10
(1010) with bits 4 and 2 turned on.
5.5.1. Digital Capacitor Measurements
The digital capacitor used in the phase shifter was electrically characterized using the
method described in Appendix A for all sixteen capacitor states. Fig. 5.10 shows the Sparameters for the minimum capacitance and maximum capacitance states. Fig. 5.11 shows the
equivalent circuit model in terms of Z-parameters and lumped circuit elements. Fig. 5.11 shows
Chapter 5: Phase Shifter
115
the lumped impedances for the minimum capacitance and maximum capacitance states. The
equations listed below were used to calculate the equivalent circuit element values (see Fig.
5.11(b)).
Cg 
1
imag Z 21 
.
(5.20)
Rg  realZ 21  .
Ls1 
imag Z 11  Z 12 
(5.21)
.

(5.22)
Rs1  realZ11  Z12  .
Ls2 
imag Z 22  Z 21 

(5.23)
.
(5.24)
Rs2  realZ 22  Z 21  .
imag Z 11 
realZ 11 
10
10
0
0
S-parameters (dB)
S-parameters (dB)
Q
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-10
-20
-30
(5.25)
.
(5.26)
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-10
-20
-30
-40
-40
0.1
1
10
0.1
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 5.10. S-parameter magnitude as a function of frequency for (a) the minimum capacitance state (b) the maximum
capacitance state. S12 is not plotted because S12 and S21 are equivalent for passive networks.
Chapter 5: Phase Shifter
116
Port 1
Z11-Z12
Z22-Z21
Port 2
Port 1
Port 2
Rs1
Ls1
Rg Rs2
Z21
Ls2
Cg
(b)
(a)
1E+5
1E+5
1E+4
1E+4
Impedance (Ω)
Impedance (Ω)
Fig. 5.11. Equivalent circuit model in terms of (a) Z-parameters and (b) lumped circuit elements. Circuit element
values are extracted from measured 2-port network parameters.
|Z21| (Measured)
|(Z11-Z12)| (Measured)
|(Z22-Z21)| (Measured)
Extracted Model
1E+3
1E+2
1E+1
1E+3
1E+1
1E+0
1E+0
1E-1
1E-1
0.1
1
10
|Z21| (Measured)
|(Z11-Z12)| (Measured)
|(Z22-Z21)| (Measured)
Extracted Model
1E+2
0.1
1
10
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 5.12. Lumped impedances as a function of frequency for (a) the minimum capacitance position (b) the maximum
capacitance position. The series impedance behaves like an RLC circuit, and the shunt impedances are capacitive
below 10 GHz. The self-resonance frequency is greater than 40 GHz for the minimum capacitance position and
decreases to 10 GHz for the maximum capacitance position.
The electrical characteristics of the digital capacitor used in the phase shifter are presented in
Table 5.2. The state indicates which of the capacitive bits were active (for example, state 12
(1100) means that the two most significant bits are active). Measurement uncertainties are not
available since only a single device was measured due to lack of available CMOS-MEMS chips.
As designed, the shunt capacitance, Cg, increases linearly with state. Although there must be an
inductance in series with the shunt capacitance, no such inductance was measured because the
self-resonance frequency of the shunt impedance was greater than 40 GHz. The series
inductances, L1s and L2s, and series resistances, R1s and R2s, change slightly with state because the
different capacitive bits are located at different distances along the transmission line between port
Chapter 5: Phase Shifter
117
1 and port 2. The total sum of both series inductance and resistance stays approximately constant
with changing state.
Table 5.2: Electrical Characteristics of the Phase Shifter Digital Capacitor
State
Cg (fF)
Rg (Ω)
Ls1 (pH)
R1s (Ω)
Ls2 (pH)
0 (0000)
15.5
NA*
97.4
NA*
80.8
1 (0001)
24.2
NA*
81.9
NA*
96.7
2 (0010)
32.1
3.31
80.5
0.53
98.0
3 (0011)
37.9
3.08
76.1
0.52
102.5
4 (0100)
46.3
2.02
86.7
0.69
91.5
5 (0101)
54.1
1.92
81.7
0.69
96.7
6 (0110)
59.3
1.60
81.3
0.73
96.9
7 (0111)
64.6
1.55
78.7
0.73
99.6
8 (1000)
69.9
1.26
109.6
1.23
69.1
9 (1001)
77.2
1.10
104.0
1.18
75.7
10 (1010)
84.3
0.95
101.4
1.18
78.1
11 (1011)
89.3
0.91
98.6
1.17
81.3
12 (1100)
93.4
0.79
101.1
1.21
77.5
13 (1101)
102.1
0.65
97.5
1.18
81.8
14 (1110)
106.6
0.59
96.7
1.20
82.5
15 (1111)
111.6
0.54
94.5
1.20
85.1
* Resistance could not reliably be extracted from the small capacitance
R2s (Ω)
NA*
NA*
1.53
1.58
1.44
1.49
1.48
1.51
1.10
1.22
1.26
1.31
1.28
1.37
1.38
1.43
Q
(30 GHz)
NA*
NA*
63.3
46.2
46.6
38.8
38.6
35.2
25.4
24.5
23.3
22.0
21.0
20.3
19.4
18.8
The Q reported in Table 5.2 is the Q for the digital capacitor with port 2 unconnected, or left
floating. This Q calculation differs from that of the variable capacitors in Chapter 3 and Chapter
4 because those capacitors were connected in series between the two ports, which requires one
port to be grounded to produce a capacitor with a single terminal. Since the phase shifter digital
capacitor already has one terminal connected to ground, one port must be left floating to produce
a capacitor with a single terminal. Note that, unlike the updated digital capacitor presented in
Section 4.5.5, the measured Q decreases significantly with increasing state. This change in Q
occurs because the loss due to the series resistances, R1s and R2s, is comparable to the loss due to
the resistance of each capacitive bit, Rg, such that the total series resistance remains roughly
constant with state.
Fig. 5.13 shows the measured Q for the maximum capacitance state as a function of
Chapter 5: Phase Shifter
118
frequency. To calculate the extracted model, the self-resonance frequency was assumed to be
55 GHz, which provides the best fit between measurement and calculation. The measured Q is
noisy even though measurements were recorded with the IF bandwidth of the VNA lowered to
500 Hz. presumably, the measurement is simply limited by the accuracy of the VNA. The noise
increases at low frequencies as the series resistance becomes smaller in comparison with the
Quality Factor
imaginary impedance.
100
90
80
70
60
50
40
30
20
10
0
Quality Factor (De-embedded)
Extracted Model
10
20
30
40
Frequency (GHz)
Fig. 5.13. Quality factor as a function of frequency for the digital capacitor used in the phase shifter. This plot shows
the Q for the maximum capacitance position with port 2 left floating.
The series capacitance of the digital capacitor was measured at each of the sixteen states for
a single device (see Fig. 5.14). The measured capacitance as a function of state matches a linear
trend with an R2 of 0.9963. The digital capacitor tunes from 15.5 fF to 111.6 fF, a tuning ratio of
7.2:1. Device variation in terms of standard deviation is not available because only a single
device was measured.
Chapter 5: Phase Shifter
119
120
Capacitance (fF)
100
80
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
State
Fig. 5.14: Capacitance of phase shifter digital capacitor as a function of state. State 3 (0011) indicates that the two
least significant bits are turned on.
5.5.2. Phase Shifter Measurements
The phase shifter was electrically characterized using the method described in Appendix A.
S-parameters were measured for each of the sixteen states. The phase shift for a given state was
calculated by subtracting the phase of S21 for that state from the phase of S21 for State 0.
 state[x]  phaseS 21, state[0]   phaseS 21, state[x]  .
(5.27)
At 32.0 GHz, the phase shifter achieves a maximum measured phase shift of 337.5° for state 15
(see Fig. 5.15). The insertion loss is calculated as the magnitude of S21.
ILstate[x]  20 log 10 S 21,state[x] .
(5.28)
The insertion loss varies by state from 1.9 dB to 3.9 dB with an average of 2.9 dB at 32.0 GHz.
The return loss, RL, is calculated as the magnitude of S11.
RLstate[x]  20 log 10 S11,state[x] .
(5.29)
The return loss varies by state since changing the capacitance determines the characteristic
impedance of the distributed MEMS transmission line. The maximum return loss is -5.4 dB at
Chapter 5: Phase Shifter
120
30 GHz. The measured electrical characteristics of the phase shifter at 32 GHz are summarized in
Table 5.3.
The characteristics are presented at 32 GHz since that frequency is the minimum at
which the phase shifter produces sixteen steps between 0° and 360° phase shift.
Phase Shift (Degrees)
0
-45
-90
-135
-180
-225
Increasing
state
-270
-315
-360
0
10
20
30
Frequency (GHz)
40
Fig. 5.15: Measured phase shift as a function of frequency for all 16 states. Phase shift is negative because the time
delay increases with increasing capacitance.
Insertion Loss (dB)
0
-0.5
-1
-1.5
-2
-2.5
-3
Increasing
state
-3.5
-4
-4.5
-5
0
10
20
30
40
Frequency (GHz)
Fig. 5.16: Measured insertion loss as a function of frequency for all 16 states.
Chapter 5: Phase Shifter
121
0
Increasing state
Return Loss (dB)
-5
-10
-15
-20
-25
-30
-35
-40
0
10
20
30
40
Frequency (GHz)
Fig. 5.17: Measured reflection as a function of frequency for all 16 states.
TABLE 5.3: ELECTRICAL CHARACTERISTICS OF THE PHASE SHIFTER
State
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
Reflection
|S11| (dB)
-6.1
-13.5
-19.4
-14.9
-13.3
-14.8
-18.3
-21.0
-23.3
-28.7
-32.9
-52.2
-32.4
-23.1
-19.5
-17.9
Insertion Loss
|S21| (dB)
-2.7
-2.0
-1.9
-2.2
-2.3
-2.6
-2.6
-2.8
-2.8
-3.1
-3.2
-3.4
-3.4
-3.6
-3.7
-3.9
Phase Shift
∆φ (°)
0
-40.3
-75.8
-98.0
-127.2
-154.0
-173.0
-189.3
-206.1
-231.3
-254.4
-269.5
-285.7
-307.6
-322.8
-337.5
Phase Step
∆φn-∆φn-1 (°)
NA
-40.3
-35.8
-22.2
-29.2
-26.8
-19.0
-16.3
-16.8
-25.2
-23.1
-15.1
-16.2
-21.9
-15.2
-14.7
The de-embedded S-parameters for the phase shifter in state 0, zero phase shift, and state 15,
maximum phase shift, are plotted in Fig. 5.18. Note that the measured data does not match that of
the initial simulations, particularly for S11, which was designed to remain below −10 dB.
Analysis of the digital capacitor revealed additional series resistance and inductance which were
not included in the original model.
Presumably, these parasitics occur because the digital
Chapter 5: Phase Shifter
122
capacitors periodically break up the ground plane resulting in a longer return path for the current.
The additional resistance increased the insertion loss, and the additional inductance increased the
characteristic impedance resulting in a worse match, or larger S11, for state 0 and a better match,
or smaller S11, for state 15. Re-simulation of the phase shifter accounting for these parasitics
resulted in closer agreement between measurement and simulation.
0
-5
|S21|
-10
-15
-20
-25
-30
-35
-40
|S11|
Measured
Simulated
Re-simulated
S-Parameters (dB)
S-Parameters (dB)
0
-5
-10
-15
-20
-25
-30
-35
-40
Measured
Simulated
Re-simulated
|S21|
|S11|
0
10
20
30
40
20
30
40
Frequency (GHz)
Frequency (GHz)
(a)
(b)
Fig. 5.18. S-parameter magnitude as a function of frequency for (a) the minimum phase shift state (b) the maximum
phase shift state. S12 is not plotted because S12 and S21 are equivalent for passive networks.
0
10
5.6. Discussion
The CMOS-MEMS phase shifter is compared with a representative sample of other passive
phase shifters, both MEMS and non-MEMS, in Table 5.4. The frequencies listed in Table 5.4 are
the minimum frequencies at which the phase shifters produce an even distribution of phase shifts
up to 360°. For digital phase shifters, the insertion loss is averaged over all states. For analog
phase shifters, the insertion loss is recorded for a 180° phase shift.
The insertion loss of the phase shifter in this work, 2.9 dB, is less than that of GaAs phase
shifters but greater than that of other MEMS phase shifters (see Fig. 5.19). However, the CMOSMEMS phase shifter is the first MEMS phase shifter which can be monolithically integrated with
Chapter 5: Phase Shifter
123
CMOS using only maskless post-processing. Despite the increased insertion loss, this work
represents a significant achievement because only the MEMS phase shifter in this work could be
combined with on-chip CMOS power amplifiers to further reduce the number of components
required for phased antenna arrays.
Insertion Loss (dB)
Table 5.4: Comparison of Phase Shifters
Frequency
Insertion
Reference
MEMS?
Type
# Bits
(GHz)
Loss (dB)
[44]
yes
Reflect-Line
7
4
1.2
[45]
yes
Switched-Line
10
4
2.2
[46]
yes
Switched-Line
10
4
1.1
[47]
yes
Switched-Line
32
4
2.3
yes
[48]
Distributed
14
2
1.2
yes
[49]
Distributed
16
4
3
yes
[50]
Distributed
26
3
1.7
yes
This work
Distributed
32
4
2.9
yes
[48]
Distributed
38
2
1.5
yes
[51]
Distributed
60
2
2.2
yes
[52]
Distributed
94
analog
2.5
no
[50]
Distributed
6
analog
4
no
[53]
Distributed
6
analog
5.1
no
[54]
Distributed
20
analog
4.2
* Resistance could not reliably be extracted from the small capacitance
8
7
6
5
4
3
2
1
0
Switched-Line
Distributed
This Work
Substrate
Si
GaAs
GaAs
Si
SiO2
Si
SiO2
CMOS
SiO2
SiO2
SiO2
GaAs
GaAs
GaAs
Reflect-Line
GaAs
0 10 20 30 40 50 60 70 80 90 100
Frequency (GHz)
Fig. 5.19: Comparison of passive phase shifters. The average insertion loss is plotted versus the minimum operating
frequency.
The insertion loss of the CMOS-MEMS phase shifter was larger than expected due to the
Chapter 5: Phase Shifter
124
series resistance of the digital capacitor, measured as R1s and R2s (see Table 5.2). This series
resistance cannot be accounted for by the sheet resistance of the metal layers and is actually
frequency dependant, which suggests another source of loss. Further investigation of this loss
would require finite element analysis to account for how the digital capacitors break up the
ground plane of the transmission line and force the current to return through a longer path. The
bias resistors also warrant additional investigation since lumped resistors were used for
simulation. The bias resistors could be more accurately represented as a series resistance with a
distributed shunt capacitance to ground. This representation would add a low-Q parasitic
capacitance to simulation which may be responsible for the additional insertion loss.
Further optimization of the phase shifter design could also improve the insertion loss. The
design presented in Section 5.4 specifies the digital capacitor design after determining the
geometry of the micromachined transmission line. If the transmission line loss and phase velocity
can be parameterized, then the transmission line dimensions can be chosen specifically to
minimize insertion loss [43]. Such parameterization would require further simulation with HFSS
of transmission lines with varying dimensions. The only reason this optimization was not
performed was lack of available time.
The power consumption required for electrothermal actuation is potentially problematic.
Power is only consumed during the 1 ms switching time, resulting in 0.32 mJ consumed per
actuation cycle. This energy consumption is beneficial if the phase shifter is not switched often
but may limit this particular phase shifter to applications which do not require continuous
scanning. Thus a CMOS-MEMS phase shifter based purely on electrostatic actuation could
enable applications that require continuous scanning. The use of only electrostatic actuation
would also provide faster switching times.
Chapter 5: Phase Shifter
125
Chapter 6.
Conclusions
This chapter begins with Section 6.1, a summary of the three contributions of this work, the
CMOS-MEMS gap-tuning capacitor, the CMOS-MEMS digital capacitor, and the CMOSMEMS phase shifter. Next, the thesis statement is revisited and evaluated in Section 6.2 by
comparing the CMOS-MEMS variable capacitors of this work with other state-of-the-art variable
capacitors. Section 6.3 discusses several possibilities for future work on CMOS-MEMS variable
capacitors. Finally, concluding remarks on the viability of RF CMOS-MEMS are presented in
Section 6.4.
6.1. Summary
Prior to this work, MEMS variable capacitors had been developed performance superior to
that of semiconductor variable capacitors. The increased tuning ratios and higher quality factors
made possible by MEMS are desirable for enhancing existing RF circuits and enabling new
frequency-reconfigurable circuits. However, MEMS variable capacitors are not widely used in
RF circuits because most MEMS are not monolithically integrated with CMOS. Those MEMS
which are integrated require potentially expensive fabrication processes. To achieve monolithic
integration without expensive fabrication processes, this work used the CMOS-MEMS process to
create CMOS-MEMS variable capacitors.
The first CMOS-MEMS variable capacitor presented in this work is the gap-tuning capacitor
that uses lateral electrothermal actuation to control the capacitive gap between interdigitated
electrodes. A mechanical latch, also controlled by electrothermal actuation, was used to maintain
the capacitive gap without consuming static power for heating. The routing for the RF signal was
separated from that of the actuation signal to minimize parasitic capacitance to ground. The
Chapter 6: Conclusions
126
structure was designed to achieve vertical alignment between the capacitive beams. The gaptuning capacitor achieved series and shunt tuning ratios up to 6.9:1 and 5.7:1, respectively, with a
Q of 80 at 1 GHz for the maximum capacitance. The switching time was measured to be 30 ms.
Millions of actuation cycles were demonstrated without failure. Because the tuning ratio and Q
are greater than those of semiconductor variable capacitors, the gap-tuning capacitor was
fundamentally successful. However, practical implementation of circuits using the gap-tuning
capacitor was difficult due to the large variation in maximum capacitance, the non-linear
distribution of latched capacitance values, and the low capacitance density.
The second CMOS-MEMS variable capacitor presented in this work is the digital capacitor,
which was designed to overcome the limitations of the gap-tuning capacitor. The digital
capacitor consists of many CMOS-MEMS switched capacitors organized into independently
controlled capacitive bits. The capacitive bits are sized in increasing powers of two to produce a
linear distribution of capacitance values. The switched capacitors use a combination of vertical
electrothermal actuation and lateral electrostatic actuation to achieve large tuning ratios without
sacrificing capacitance density. Because the minimum capacitance state is maintained by residual
stress and the maximum capacitance state is maintained by electrostatic force, power for heating
is only consumed during actuation. The initial digital capacitor topology was updated to
minimize parasitic capacitance to ground. The updated digital capacitor achieved series and shunt
tuning ratios up to 73:1 and 19:1, respectively, with a Q of 369 at 1 GHz for the maximum
capacitance. Compared with the gap-tuning capacitor, the capacitance density was increased by
5x and standard deviation in maximum capacitance was reduced from 18% to 4.4%. The
switching time was decreased to 1 ms. Reliability tests revealed a drift in the actuation
characteristics after 10 million cycles due to thermally-induced mechanical fatigue, but no
Chapter 6: Conclusions
127
catastrophic failures occurred. These characteristics represent the state-of-the-art for CMOSMEMS variable capacitors.
The CMOS-MEMS phase shifter was developed as an application of CMOS-MEMS
variable capacitors. The CMOS-MEMS phase shifter consists of a micromachined transmission
line periodically loaded with CMOS-MEMS digital capacitors. The digital capacitors are
sufficiently distributed such that the circuit can be approximated as a transmission line with
variable capacitance per unit length. The digital capacitor was modified to enable operation at
frequencies beyond 30 GHz. The phase shifter digital capacitor achieved a shunt tuning ratio of
7.2:1 with a Q of 18.8 at 30 GHz for the maximum capacitance. The phase shifter produced an
average insertion loss and maximum phase shift of 2.9 dB and 337.5°, respectively, at 32 GHz.
This work represents the first MEMS phase shifter to be monolithically integrated with CMOS.
6.2. Contributions
The first goal of this work was to show that, using the CMOS-MEMS process, CMOSMEMS variable capacitors can be designed with performance comparable to that of other
integrated MEMS variable capacitors. To work towards this goal, CMOS-MEMS variable
capacitors were designed and characterized. Table 6.1 compares the characteristics of the best
performing variable capacitor of this work, the updated CMOS-MEMS digital capacitor
presented in Section 4.5.5, with that of several other MEMS variable capacitors capable of
monolithic integration with CMOS. Also included are the characteristics of one type of
semiconductor variable capacitor, the switched MIM capacitor simulated using the same CMOS
technology, TowerJazz 0.35 µm BiCMOS. The other two types of semiconductor variable
capacitors, the varactor diode and MOS varactor, are not included because, although their Q is
Chapter 6: Conclusions
128
higher than that of switched MIM capacitors, their tuning ratios are limited to less than 5:1. A
figure of merit (FoM), the product of the shunt tuning ratio, TRshunt, and Q, is presented for
comparison between variable capacitors with different tuning ratios.
FoM  TRshunt * Q .
(6.1)
This FoM remains constant if, by decreasing the maximum capacitance, tuning ratio is decreased
to increase Q.
Parameter
Type
Integration
Table 6.1: Comparison of Integrated Variable Capacitors
Switched MIM
University of
Raytheon
This Work
Capacitor
Waterloo [55]
Systems [29]
MEMS
Semiconductor
MEMS
MEMS
Maskless postMaskless post- Built on top of
CMOS
CMOS etching
CMOS etching
silicon
1.34 pF
1.11 pF
1.64 pF
33.2 pF
18.3 fF
111 fF
290 fF
1.5 pF
Cmax
Cmin
Shunt Tuning
19:1
10:1
5.6:1
Ratio
Q at 1 GHz*
369
9
≈ 180
FoM
7011
90
1008
(TRshunt*Q)
Self-Resonance
10 GHz
NA
> 20 GHz
Frequency*
Capacitance
7.9 pF/mm2
1000 pF/mm2
≈ 6.6 pF/mm2
Density
Switching
Electrothermal /
MOSFET
Electrostatic
Method
electrostatic
Tuning Range
Discrete
Discrete
Discrete
Switching Time
1 ms
~ 1 ns
NA
Actuation
4 V / 20 V
3.3 V
70 V
Voltage
Actuation
50 µJ
≈ 0**
≈ 0**
Energy for 1 pF
* The parameter corresponds to the maximum capacitance state.
** The energy consumed for actuation is negligible.
WiSpry [38]
MEMS
Built on top of
CMOS
8 pF
720 fF
22:1
11:1
< 20
160
< 440
1760
NA
> 5 GHz
NA
NA
Electrostatic
Electrostatic
Discrete
< 10 µs
Discrete
< 10 µs
55 V
30 V
≈ 0**
≈ 0**
Based on the FoM presented in Table 6.1, the CMOS-MEMS digital capacitor achieves a
superior combination of tuning ratio and Q compared with that of other MEMS variable
capacitors capable of monolithic integration with CMOS. The self-resonance frequency is
sufficiently high for use at mobile communications frequencies (1 GHz – 6 GHz). Compared to
Chapter 6: Conclusions
129
MEMS variable capacitors using only electrostatic actuation, the digital capacitor has a longer
switching time consumes power during actuation. However, if the digital capacitor is used in
frequency-reconfigurable circuits that do not require continuous switching, the slow switching
time and transient power consumption are not significant problems. Thus this work has satisfied
the first goal of the thesis statement by showing that CMOS-MEMS variable capacitors can be
designed with performance comparable to that of other integrated MEMS variable capacitors
The second goal of this work was to show that, CMOS-MEMS variable capacitors enable
the design of reconfigurable RF circuits. To prove this statement, the first CMOS-MEMS phase
shifter was designed using CMOS-MEMS variable capacitors. The phase shifter operated at
frequencies greater than 30 GHz, which demonstrates the potential for CMOS-MEMS to work at
even higher frequencies. The performance of the phase shifter, measured by the insertion loss, is
close to that of other MEMS phase shifters and better than that of semiconductor phase shifters.
Therefore, this work has also satisfied the second goal of the thesis statement by showing that
CMOS-MEMS variable capacitors enable the design of reconfigurable RF circuits.
6.3. Future Work
CMOS-MEMS variable capacitors have come a long way since their inception, but there are
still options for future work. The tuning ratio and Q have been significantly improved and are
superior to those of semiconductor variable capacitors, so future work should focus on improving
the characteristics which are inferior to those of semiconductor variable capacitors, specifically
capacitance density, switching time, reliability, and actuation voltage. This section presents
suggestions for further improvement based on process modifications, topology improvements,
and applications.
Chapter 6: Conclusions
130
6.3.1. CMOS-MEMS Process Modifications
Because this work focused on the design of CMOS-MEMS variable capacitors, the CMOSMEMS process was not modified. Process modifications were neglected in lieu of device design
because, at the time of this work, the CMOS-MEMS process was well established and optimized
for general purpose CMOS-MEMS. However, there are several options for future work related to
the CMOS-MEMS process which will specifically improve CMOS-MEMS variable capacitors.
A simple way to significantly improve CMOS-MEMS variable capacitors is to decrease the
thickness of the sidewall polymer deposited during the vertical oxide etch. Since this polymer
determines the maximum capacitance per unit length for two CMOS-MEMS beams pushed into
mechanical contact, any decrease in thickness would increase both the tuning ratio and
capacitance density of CMOS-MEMS variable capacitors. Control over this thickness has
previously been limited by the capabilities of the Plasma-Therm 790 RIE. Work is currently
underway to use the STS Aspect Advanced Oxide Etcher to perform the vertical oxide etch while
depositing less sidewall polymer. However, there are risks associated with depositing too little
sidewall polymer because this polymer prevents the titanium-tungsten barrier metals from
etching during the silicon release etch. Furthermore, if the polymer is too thin, the breakdown
voltage between two CMOS-MEMS beams pushed into mechanical contact may become too low
(< 20 V) for electrostatic pull-in. If these potential pitfalls can be averted, reducing the thickness
of the sidewall polymer would significantly improve any CMOS-MEMS capacitive devices.
Another method to improve CMOS-MEMS variable capacitors is to increase the lengths of
both the vertical silicon etch and the isotropic etch. Using the current CMOS-MEMS process, the
silicon etches create a substantial air gap (≈ 50 µm) between the MEMS structure and the
remaining silicon substrate. As large as this gap is, there is still significant parasitic capacitance
Chapter 6: Conclusions
131
(≈ 10 fF) that couples the MEMS structure to the silicon. Because the silicon is a poor conductor
at RF, this parasitic capacitance decreases the Q of CMOS-MEMS variable capacitors.
Capacitance to the silicon can be avoided by including grounded metal near all capacitive
electrodes but, similar to adding a ground shield beneath an inductor, adding grounded metal
increases the total parasitic capacitance, which causes the shunt tuning ratio to decrease. If more
silicon is removed, capacitance to the silicon can be minimized without increasing the total
amount of parasitic capacitance.
The third suggestion related to processing is not a process modification but instead regards
unintended lateral curling, which is believed to be caused by the CMOS-MEMS process.
Because unintended lateral curling of CMOS-MEMS beams is problematic for nearly all CMOSMEMS devices, a better understanding of this curling is needed to help the designer compensate
accordingly. Currently, information concerning this curling is based on qualitative observations.
Since even CMOS-MEMS beams of a single metal layer exhibit lateral curling, the phenomenon
is not entirely caused by misalignment of the metal layers. The sidewall polymer is believed to
contribute to lateral curling because sidewall polymer that has delaminated curls to a greater
extent than CMOS-MEMS beams. Thus unintended lateral curling may be alleviated by reducing
the thickness of the sidewall polymer. If not, statistical measurements of curling from multiple
CMOS-MEMS chips and multiple CMOS process runs are needed to fully understand the
phenomenon. Perhaps an upper bound for the magnitude of lateral curling can then be predicted
given the length and cross-section of a CMOS-MEMS beam.
6.3.2. Device Topology Improvements
The CMOS-MEMS variable capacitors presented in this work have three main
Chapter 6: Conclusions
132
disadvantages when compared with semiconductor variable capacitors: low capacitance density,
slow switching speed, and limited reliability. Capacitance density is nearly optimized by the
digital capacitor topology since the capacitive electrodes consist of a dense array of CMOSMEMS beams. Thus capacitance density should be improved through process modifications,
such as a reducing the thickness of the sidewall polymer, rather than changes to the device
topology. The slow switching speed and limited reliability are both a result of electrothermal
actuation. Both of these characteristics could be improved by changes to the device topology.
If the actuation can be accomplished using only electrostatic actuation without
electrothermal actuation, the switching speed will increase and the reliability will not be limited
by thermally induced mechanical fatigue. The sensitivity of the variable capacitance to changes
in ambient temperature should also decrease significantly. However, achieving the same tuning
ratio, Q, and capacitance density without electrothermal actuation will be difficult since
electrothermal actuation enables large vertical displacements. Because the CMOS-MEMS
process cannot produce a top and bottom electrode, there is no obvious method for vertical
electrostatic actuation. One method for achieving vertical electrostatic actuation without a top
electrode involves the use of fringing fields to pull vertically curled capacitive electrodes into the
same plane [37]. Perhaps this actuation method can be modified to also include lateral
electrostatic pull-in for achieving a large tuning ratio. Another technique that may be useful is a
method to produce upwards vertical deflection using electrostatic force without a top electrode.
By pulling one end of a MEMS beam down, the angle of the beam can be changed causing the
other end to tilt upwards [8]. These two actuation techniques can potentially be combined to
create a digital capacitor using vertical and lateral electrostatic actuation.
If a device topology can be developed to use only electrostatic force, the second challenge
Chapter 6: Conclusions
133
will be minimize the required actuation voltage. The high voltages (> 20 V) typically required for
electrostatic actuation are undesirable because those voltages can cause dielectric charging,
which eventually causes the capacitive electrodes to stick together even when the applied voltage
is reduced to zero. Furthermore, the CMOS process must include high-voltage transistors so that
those high voltages can be generated on-chip with integrated charge pumps. One idea to decrease
the required actuation voltage is to use resonant electrostatic actuation [56]. Rather than applying
only a DC voltage, a DC voltage can be combined with an AC voltage at the mechanical
resonance frequency. Because sinusoidal motion at resonance is amplified by the mechanical Q,
the necessary displacements can be achieved using lower voltages. The switching speed is
slowed by the need for resonance but could still switch faster than electrothermal actuation.
6.3.3. Potential Applications
In principle, any circuit that requires variable capacitors can be improved by replacing the
semiconductor variable capacitors with CMOS-MEMS variable capacitors. However, the
improvements to a given circuit must be sufficient to justify the large area consumption, slow
switching times, and added complexity inherent to MEMS. Frequency-reconfigurable circuits,
which use variable capacitors to select the frequency band of operation, are an example of a good
application of CMOS-MEMS variable capacitors. Circuits that perform band selection through
reconfiguration consume less area than those that perform reconfiguration by switching between
multiple versions of the same circuit. Furthermore, fast switching times are necessarily required
for frequency-reconfigurable circuits. A good application of CMOS-MEMS variable capacitors
that has yet to be explored is the impedance tuner.
Impedance tuners are circuits that maintain the impedance match between the output
Chapter 6: Conclusions
134
network of a power amplifier and the antenna. Such circuits are necessary to extend battery life in
mobile handsets because the impedance of an antenna is affected by the local surroundings.
Impedance tuners require tunable passive components with high Q to minimize loss because
these tuners are placed in series between the power amplifier and antenna. Fast switching times
are not required since the antenna impedance changes slowly in response to manual manipulation
of mobile handsets. Because the CMOS-MEMS process consists of maskless processing, a
CMOS-MEMS impedance tuner could extend battery life with little extra fabrication cost.
6.4. Final Thoughts
The field of RF MEMS is odd because there is no fundamental reason why mechanical
devices are needed to provide the functions of RF MEMS. RF MEMS devices typically involve
transduction of an electrical control signal into a mechanical displacement that determines
another electrical quantity. This use of the mechanical domain as an intermediary between
electrical signals is at first glance unnecessary since variable capacitance, switching, and tunable
resonance can all be provided by semiconductor devices. In contrast, MEMS is a natural choice
for inertial sensors since the purpose of sensors such as accelerometers and gyroscopes is to
sense a mechanical quantity.
Because the mechanical domain is not strictly required to provide the functions of RF
MEMS, RF MEMS devices are in direct competition with semiconductor devices. For now, RF
MEMS are competitive because MEMS can be constructed entirely from metal, without the need
for resistive semiconductor materials. But commercialization of RF MEMS has been slow due to
reliability problems introduced by the mechanical domain and also because RF MEMS have not
been monolithically integrated with CMOS.
Chapter 6: Conclusions
135
This work represents significant progress since RF CMOS-MEMS are monolithically
integrated with CMOS using maskless post-CMOS processing. However, even the maskless
processing required for CMOS-MEMS adds cost and complexity beyond that required for
semiconductor devices. In exchange, RF CMOS MEMS provide superior performance in terms
of tuning ratio and quality factor. The question that remains is whether or not there exists an
application that benefits sufficiently from this superior performance to justify that additional cost
and complexity. I sincerely hope so because I have thoroughly enjoyed the work.
Chapter 6: Conclusions
136
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Appendix A. Electrical Characterization
This appendix describes how the RF electrical characteristics of the CMOS-MEMS variable
capacitors were measured and used to calculate an equivalent circuit model. Section A.1
discusses the network analyzer settings that were used to measure two-port network parameters
for the gap-tuning capacitor, the digital capacitor, and the phase shifter. Section A.2 presents the
procedure for open-short de-embedding, which is used to remove the effects of the on-chip probe
pads from the measured data. Section A.3 shows how the measured two-port network parameters
were used to calculate the values of the equivalent circuit elements for both a π-model and a Tmodel. The Matlab code used to perform open-short de-embedding and to calculate the
equivalent circuit element values is included in Section A.4.
A.1. Network Analyzer Settings
An Agilent E8364A network analyzer was used to measure the RF electrical characteristics
of the CMOS-MEMS variable capacitors and the CMOS-MEMS phase shifter. Prior to
measurement, short-open-load-through (SOLT) calibration was performed to eliminate the
parasitic effects of the probes and cables using WinCal 3.1 software and the calibration substrate.
The probes used to make electrical contact with the probe pads are Infinity probes with 100 µm
pitch for ground-signal-ground (GSG) configuration. These probes were chosen because the
nickel probe tips provide a low contact resistance to aluminum. The network analyzer was set to
record 1601 measurements with a linear frequency range from 100 MHz to 40 GHz. The
intermediate filter (IF) bandwidth was lowered from the default 35 kHz to 500 Hz to reduce the
noise floor. Modification of the intermediate frequency is necessary to measure small resistances
in series with large imaginary impedances. Using these settings, two-port S-parameters were
Appendix A: Electrical Characterization
142
measured for the device under test (DUT) and the open-short de-embedding test structures (see
Fig. A.1).
G
G
G
G
G
S
S
S
S
S
G
G
G
G
G
(a)
(b)
G
DUT
S
G
(c)
Fig. A.1. Layout view of (a) open test structure (b) short test structure (c) DUT. Measurements of the open and short
test structures are necessary to remove the parasitic effects of the probe pads using open-short de-embedding. ‗G‘
and ‗S‘ represent ‗ground‘ and ‗signal‘, respectively.
A.2. Open-short De-embedding
Open-short de-embedding is a procedure used to remove the parasitic effects of the on-chip
probe pads from the measured data. The probe pads contribute shunt capacitance, series
resistance, and series inductance to the measured two-port network parameters of the DUT. Deembedding uses measurements of open and short test structures to calculate the two-port network
parameters of the DUT as if the probe pads were not present. The open test structure consists of
two sets of probe pads that are not connected, or open-circuited. The short test structure consists
of two sets of probe pads that are connected to ground, or short-circuited. Open-short deembedding was performed using the following steps.
1.
Three sets of S-parameters, Smeas, Sopen, and Sshort, were measured for the DUT, the open test
structure, and the short test structure, respectively.
2.
The three sets of S-parameters were converted to Y-parameters, Ymeas, Yopen, and Yshort. using
the following equations. These equations assume that both the source and load impedance
are 50 Ω.
Appendix A: Electrical Characterization
143
Y11 
Y12 
Y21 
Y22 
3.
1 - S11 1  S 22   S12 S 21
.
50 1  S11 1  S 22   S12 S 21
1
2S12
1
(A.1)
.
(A.2)
.
(A.3)
1  S11 1  S 22   S12 S 21
.
50 1  S11 1  S 22   S12 S 21
(A.4)
50 1  S11 1  S 22   S12 S 21
2S 21
1
50 1  S11 1  S 22   S12 S 21
1
The open Y-parameters were subtracted from both the DUT and the short Y-parameters to
remove the parallel capacitance of the probe pad.
4.
Ymeas '  Ymeas  Yopen .
(A.5)
Yshort'  Yshort  Yopen .
(A.6)
The resulting Y-parameters were converted to Z-parameters, Zmeas‘ and Zshort‘, using the
following equations.
Z 11 
Z 12 
Z 21 
Z 22 
5.
Y22
Y11Y22  Y12Y21
Y12
Y11Y22  Y12Y21
Y21
Y11Y22  Y12Y21
Y11
Y11Y22  Y12Y21
.
(A.7)
.
(A.8)
.
(A.9)
.
(A.10)
The short Z-parameters were subtracted from the DUT Z-parameters to remove the series
resistance and inductance of the probe pad.
Zde -embedded  Z meas'Zshort ' .
(A.11)
The resulting Z-parameters are de-embedded two-port network parameters that represent the
Appendix A: Electrical Characterization
144
electrical characteristics of the DUT as if the probe pads were not present. The de-embedded Zparameters were converted to Y- or S-parameters as needed for further calculations. The
following equations were used to convert Z-parameters to Y-parameters.
Y11 
Y12 
Y21 
Z 22 
Z 22
Z 11Z 22  Z 12 Z 21
 Z 12
Z 11Z 22  Z 12 Z 21
 Z 21
Z 11Z 22  Z 12 Z 21
.
(A.12)
.
(A.13)
.
(A.14)
.
(A.15)
Y11
Z 11Z 22  Z 12 Z 21
The following equations were used to convert Y-parameters to S-parameters. These equations
assume that both the source and load impedance are 50 Ω.
S11 
S12 
S 21 
S 22 
1 - 50Y11 1  50Y22   502 Y12Y21 .
1  50Y11 1  50Y22   502 Y12Y21
2 * 50Y12
(A.16)
.
(A.17)
.
(A.18)
1  50Y11 1  50Y22   502 Y12Y21
.
1  50Y11 1  50Y22   502 Y12Y21
(A.19)
1  50Y11 1  50Y22   502 Y12Y21
2 * 50Y21
1  50Y11 1  50Y22   502 Y12Y21
A.3. Extracting an Equivalent Circuit Model
After open-short de-embedding, the measured two-port network parameters represent the
DUT without probe pads as the DUT would be used in an integrated circuit. These network
parameters are sufficient for simulating the CMOS-MEMS variable capacitors but do not provide
Appendix A: Electrical Characterization
145
an intuitive understanding which would allow the variable capacitors to be parameterized and
subsequently modified during circuit design. To better understand the variable capacitors, further
calculations were performed to extract the element values of an equivalent circuit model. Two
different equivalent circuit models, a π-model and a T-model, were used for the variable
capacitors presented in this work.
A.3.1. π-Model
A π-model was used for the gap-tuning capacitor presented in Chapter 3 and both digital
capacitor presented in Chapter 4 because those variable capacitors are connected in series
between two probe pads. A π-model is better suited for series capacitors than a T-model since the
π-model contains a single series impedance to represent the series capacitance. The de-embedded
network parameters were transformed into Y-parameters and lumped into a π-model (see Fig.
A.2(a)). A plot of the lumped impedances shows that the series impedance can be modeled as a
series resistor-inductor-capacitor (RLC) circuit whereas the shunt impedances can be modeled as
capacitors for frequencies below the self-resonance frequency (Fig. A.3). The equivalent circuit
model was chosen to match the measured impedances (Fig. A.2(b)). The equations in this section
describe how to calculate the equivalent circuit element values. For each calculation, plots
comparing the measured data with the extracted model are presented to validate the proposed
model. All plots presented in this section correspond to the maximum capacitance state of the
updated digital capacitor presented in Section 4.5.5.
Appendix A: Electrical Characterization
146
Port 1
Port 2
-Y21
Y11+Y12
Rs
Port 1
C1g
Y22+Y21
Cs
Ls
Port 2
C2g
(b)
(a)
Fig. A.2. Equivalent circuit model in terms of (a) Y-parameters and (b) lumped circuit elements. Circuit element
values are extracted from measured 2-port network parameters.
Impedance Magnitude (Ω)
1E+5
1E+4
1E+3
1E+2
1E+1
|1/-Y21|
|1/(Y11+Y12)|
|1/(Y22+Y21)|
Extracted Model
1E+0
1E-1
0.1
1
10
Frequency (GHz)
Fig. A.3. Lumped impedance magnitude as a function of frequency for the maximum capacitance position. The
extracted model is compared with measured data.
All calculations of the equivalent circuit element values were averaged over frequencies
from 1 GHz to 4 GHz. First, the self-resonance frequency, ωres, was calculated as the frequency
for which the imaginary component of the series impedance was minimized. Then, the series
capacitance, Cs, was calculated using the self-resonance frequency and the imaginary component
of the series impedance (Fig. A.4).
Cs 
  

1 
 
res


2
imag  1 Y21 
.
(A.20)
The asymptote in the measured data is expected since the imaginary component of the series
Appendix A: Electrical Characterization
147
impedance approaches zero at the self-resonance frequency.
2000
Cs (Measured)
Capacitance (fF)
1800
Extracted Model
1600
1400
1200
1000
800
600
400
200
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Fig. A.4. Series capacitance as a function of frequency. The extracted model is compared with measured data.
The series inductance, Ls, was calculated from the self-resonance frequency and the series
capacitance.
Ls 
1
 res 2 C s
.
(A.21)
5
Rs (Measured)
4.5
Resistance (Ω)
4
Extracted Model
3.5
3
2.5
2
1.5
1
0.5
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Fig. A.5. Series resistance as a function of frequency. The extracted model is compared with measured data.
The series resistance, Rs, was calculated from the real part of the series impedance (see Fig. A.5).
Appendix A: Electrical Characterization
148
Rs  real  1 Y21  .
(A.22)
The increase in series resistance at higher frequencies could be due to the skin effect or due to the
noise floor of the network analyzer.
100
C1g (Measured)
C2g (Measured)
Extracted Model
Capacitance (fF)
90
80
70
60
50
40
30
20
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Fig. A.6. Shunt capacitances as a function of frequency. The extracted model is compared with measured data.
The shunt capacitances were calculated using the imaginary component of the shunt impedances
(see Fig. A.6).
C1g 
1
.
 * imag 1 Y11  Y21 
(A.23)
C2 g 
1
.
 * imag 1 Y22  Y21 
(A.24)
The shunt capacitances vary with frequency because the shunt impedances are not purely
capacitive. The shunt impedances are complex distributed networks because these impedances
include capacitance to the silicon substrate. Thus the total capacitance is constant at low
frequencies but appears to vary as the frequency approaches the self-resonance frequency.
The Q can be calculated by two different equations depending on how the two ports are
constrained. Both equations calculate the Q of the variable capacitor used as a shunt capacitor
with one port connected to ground. Q1 is the Q calculated looking into port 1 with port 2
Appendix A: Electrical Characterization
149
connected to ground.
Q1 
Im1 Y11 
Re1 Y11 
.
(A.25)
Q2 is the Q calculated looking into port 2 with port 1 connected to ground (see Fig. A.7).
Q2 
Im1 Y22 
Re1 Y22 
.
(A.26)
Calculating Q as Q1 ignores the effects of C2g whereas calculating Q as Q2 ignores the effects of
C1g. The Q is difficult to measure at low frequencies where the series resistance is small
compared to the large imaginary impedance of the capacitance. Note that both (A.25) and (A.26)
are approximations that are only valid for frequencies much less than the self-resonance
Quality Factor
frequency. This definition of Q equates to zero at the self-resonance frequency.
500
450
400
350
300
250
200
150
100
50
0
Quality Factor (De-embedded)
Extracted Model
1
2
3
4
5
6
Frequency (GHz)
Fig. A.7. Quality factor as a function of frequency. The extracted model is compared with measured data.
Equations (A.20) through (A.24) were used to calculate the Y-parameters of the extracted
model to provide a comparison between the measured and extracted lumped impedances (see
Fig. A.3). For frequencies from 1 GHz to 4 GHz, the lumped impedances of the extracted model
match the measured lumped impedances with a median error of 4.2%. The extracted YAppendix A: Electrical Characterization
150
parameters were converted to S-parameters to provide a comparison between the measured and
extracted S-parameters (see Fig. A.8). For frequencies from 1 GHz to 4 GHz, the S-parameters of
the extracted model match the measured S-parameters with a median error of 0.6%.
0
S-Parameters (dB)
-5
-10
-15
-20
-25
S11 (De-embedded)
S21 (De-embedded)
S22 (De-embedded)
Extracted Model
-30
-35
-40
0.1
1
10
Frequency (GHz)
Fig. A.8. S-parameter magnitude as a function of frequency. The extracted model is compared with measured data.
S12 is not plotted because S12 and S21 are equivalent for passive networks.
A.3.2. T-Model
A T-model was used for the phase shifter digital capacitor presented in Chapter 5 because
that variable capacitor is connected in shunt between two probe pads. A T-model is better suited
for shunt capacitors than a π-model since the T-model contains a single shunt impedance to
represent the shunt capacitance. The de-embedded network parameters were transformed into Zparameters and lumped into a T-model (see Fig. A.9(a)). A plot of the lumped impedances shows
that the shunt impedance can be modeled as a series resistor-capacitor (RC) circuit whereas the
series impedances can be modeled as series resistor-inductor (RL) circuits (Fig. A.10). The
equivalent circuit model was chosen to match the measured impedances (Fig. A.9 (b)). The
equations in this section describe how to calculate the equivalent circuit element values. For each
calculation, plots comparing the measured data with the extracted model are presented to validate
Appendix A: Electrical Characterization
151
the proposed model. All plots presented in this section correspond to the maximum capacitance
state of the phase shifter digital capacitor presented in Chapter 5.
Port 1
Z11-Z12
Z22-Z21
Port 2
Port 1
Port 2
Rs1
Ls1
Rg Rs2
Z21
Ls2
Cg
(b)
(a)
Fig. A.9. Equivalent circuit model in terms of (a) Z-parameters and (b) lumped circuit elements. Circuit element
values are extracted from measured 2-port network parameters.
1E+5
Impedance (Ω)
1E+4
1E+3
|Z21| (Measured)
|(Z11-Z12)| (Measured)
|(Z22-Z21)| (Measured)
Extracted Model
1E+2
1E+1
1E+0
1E-1
0.1
1
10
Frequency (GHz)
Fig. A.10. Lumped impedance magnitude as a function of frequency. The extracted model is compared with
measured data.
Similar to that of the π-model, the equivalent circuit element values were averaged over a
range of frequencies. However, since the phase shifter digital capacitor was designed for
frequencies greater than 30 GHz, results were averaged from 30 GHz to 35 GHz rather than from
1 GHz to 4 GHz. The capacitance to ground, Cg, was calculated using the imaginary component
of the shunt impedance (see Fig. A.11).
Cs 
1
imag Z 21 
.
Appendix A: Electrical Characterization
(A.27)
152
200
Cg (Measured)
180
Extracted Model
Capacitance (fF)
160
140
120
100
80
60
40
20
0
10
20
30
40
Frequency (GHz)
Fig. A.11. Capacitance to ground as a function of frequency. The extracted model is compared with measured data.
The shunt impedance contains capacitance to the silicon substrate, which has a significant
resistive component. Because the shunt impedance is not a simple RC circuit, both the
capacitance to ground and resistance to ground vary slightly with frequency. The resistance to
ground, Rg, was calculated from the real part of the shunt impedance (see Fig. A.12).
R s  real Z 21  .
(A.28)
3
Rs (Measured)
Resistance (Ω)
2.5
Extracted Model
2
1.5
1
0.5
0
10
20
30
40
Frequency (GHz)
Fig. A.12. Shunt resistance as a function of frequency. The extracted model is compared with measured data.
Appendix A: Electrical Characterization
153
The resistance to ground is noisy because that resistance is small compared with the large
imaginary impedance of the shunt capacitance. The series resistances, Rs1 and Rs2, were
calculated from the real part of the series impedances (see Fig. A.13).
3
(A.29)
R s 2  real Z 22  Z 21  .
(A.30)
Rs1 (measured)
Rs2 (measured)
Extracted Model
2.5
Resistance (Ω)
R s1  real Z 11  Z 12  .
2
1.5
1
0.5
0
10
20
30
40
Frequency (GHz)
Fig. A.13. Series resistances as a function of frequency. The extracted model is compared with measured data.
The series resistances are also noisy due to the large imaginary impedance. The series
inductances, Ls1 and Ls2, were calculated from imaginary part of the series impedances (see Fig.
A.14)
Ls1 
Ls 2 
imag Z11  Z12 

imag Z 22  Z 21 

.
(A.31)
.
(A.32)
Appendix A: Electrical Characterization
154
200
Ls1 (measured)
Ls2 (measured)
Extracted Model
Inductance (pH)
180
160
140
120
100
80
60
40
20
0
10
20
30
40
Frequency (GHz)
Fig. A.14. Series inductances as a function of frequency. The extracted model is compared with measured data.
Similar to that of the π-model, the Q can be calculated by two different equations depending
on how the two ports are constrained, and both equations calculate the Q of the variable capacitor
used as a shunt capacitor. Since the T-model only includes a shunt capacitance, one port must be
left floating to calculate the Q. Q1 is the Q calculated looking into port 1 with port 2 left floating
(see Fig. A.15).
Q1 
ImZ 11 
ReZ 11 
.
(A.33)
Q2 is the Q calculated looking into port 2 with port 1 left floating.
Q2 
ImZ 22 
ReZ 22 
.
(A.34)
Calculating Q as Q1 ignores the effects of Rs2 and Ls2 whereas calculating Q as Q2 ignores the
effects of Rs1 and Ls1. The Q is difficult to measure at low frequencies where the series resistance
is small compared to the large imaginary impedance of the capacitance. To calculate the
extracted model in Fig. A.15, the self-resonance frequency was assumed to be 55 GHz, which
provides the best fit between measurement and calculation. Note that both (A.33) and (A.34) are
Appendix A: Electrical Characterization
155
approximations that are only valid for frequencies much less than the self-resonance frequency.
Quality Factor
This definition of Q equates to zero at the self-resonance frequency.
100
90
80
70
60
50
40
30
20
10
0
Quality Factor (De-embedded)
Extracted Model
10
20
30
40
Frequency (GHz)
Fig. A.15. Quality factor as a function of frequency. The extracted model is compared with measured data.
S-parameters (dB)
10
0
S21 (De-embedded)
S11 (De-embedded)
S22 (De-embedded)
Extracted Model
-10
-20
-30
-40
0.1
1
10
Frequency (GHz)
Fig. A.16. S-parameter magnitude as a function of frequency. The extracted model is compared with measured data.
S12 is not plotted because S12 and S21 are equivalent for passive networks.
Equations (A.27) through (A.32) were used to calculate the Z-parameters of the extracted
model to provide a comparison between the measured and extracted lumped impedances (see
Fig. A.10). For frequencies from 30 GHz to 35 GHz, the lumped impedances of the extracted
Appendix A: Electrical Characterization
156
model match the measured lumped impedances with a median error of 0.6%. The extracted Zparameters were converted to S-parameters to provide a comparison between the measured and
extracted S-parameters (see Fig. A.16). For frequencies from 30 GHz to 35 GHz, the Sparameters of the extracted model match the measured S-parameters with a median error of
1.2%.
A.3.3. Discussion
The equivalent circuit models for both the π-model and the T-model are simplified
interpretations of the measured network parameters. These models capture the most important
aspects of the CMOS-MEMS variable capacitors but could certainly be improved if more
complexity is required. For example, the shunt impedances in the π-model could be modeled as
series RC circuits rather than just capacitors to account for the resistance of the silicon substrate.
The shunt impedance in the T-model could be modeled as a series RLC circuit rather than just a
series RC circuit to include the parasitic inductance. Many possibilities exist for expanding the
current model if a more complex model is required.
A.4. Matlab Code
Matlab scripts were used to perform open-short de-embedding and to calculate the
equivalent circuit element values from the de-embedded two-port network parameters. To use
these scripts, the directory name must be changed to the directory that contains the measured
two-port S-parameters. The file names for the DUT and open and short test structures must be
updated.
Appendix A: Electrical Characterization
157
A.4.1. π-model Script
%John Reinke
%3/7/2011
%Open-short de-embedding and extraction of equivalent circuit model parameters for pi-model capacitors
%Directory and file names
dir='C:\Documents and Settings\jreinke\Desktop\Jazz\Jazz032\RF\092010';
file_m=[dir '\cap1c15s7r.s2p']; %File containing DUT 2-port S-parameters
file_o=[dir '\gsg_open.s2p']; %File containing open 2-port S-parameters
file_s=[dir '\gsg_short.s2p']; %File containing short 2-port S-parameters
%Get 2-port S-parameters from capacitor file
[number,unit,parameter,format,type,load]=textread(file_m,'%s %s %s %s %s %s',1,'headerlines',5);
if strcmp(format,'RI')
[f,s11_real,s11_imag,s21_real,s21_imag,s12_real,s12_imag,s22_real,s22_imag]=textread(file_m,'%n %f %f %f
%f %f %f %f %f',-1,'headerlines',6);
s11_m=s11_real+j*s11_imag;
s21_m=s21_real+j*s21_imag;
s12_m=s12_real+j*s12_imag;
s22_m=s22_real+j*s22_imag;
elseif strcmp(format,'dB')
[f,s11_mag,s11_phase,s21_mag,s21_phase,s12_mag,s12_phase,s22_mag,s22_phase]=textread(file_m,'%n %f
%f %f %f %f %f %f %f',-1,'headerlines',6);
s11_m=10.^(s11_mag./20).*exp(j*pi/180*s11_phase);
s21_m=10.^(s21_mag./20).*exp(j*pi/180*s21_phase);
s12_m=10.^(s12_mag./20).*exp(j*pi/180*s12_phase);
s22_m=10.^(s22_mag./20).*exp(j*pi/180*s22_phase);
else
'incompatible file type'
return
end
%Get 2-port S-parameters from open file
[number,unit,parameter,format,type,load]=textread(file_o,'%s %s %s %s %s %s',1,'headerlines',5);
if strcmp(format,'RI')
[f,s11_real,s11_imag,s21_real,s21_imag,s12_real,s12_imag,s22_real,s22_imag]=textread(file_o,'%n %f %f %f
%f %f %f %f %f',-1,'headerlines',6);
s11_o=s11_real+j*s11_imag;
s21_o=s21_real+j*s21_imag;
s12_o=s12_real+j*s12_imag;
s22_o=s22_real+j*s22_imag;
elseif strcmp(format,'dB')
[f,s11_mag,s11_phase,s21_mag,s21_phase,s12_mag,s12_phase,s22_mag,s22_phase]=textread(file_o,'%n %f
%f %f %f %f %f %f %f',-1,'headerlines',6);
s11_o=10.^(s11_mag./20).*exp(j*pi/180*s11_phase);
s21_o=10.^(s21_mag./20).*exp(j*pi/180*s21_phase);
s12_o=10.^(s12_mag./20).*exp(j*pi/180*s12_phase);
s22_o=10.^(s22_mag./20).*exp(j*pi/180*s22_phase);
else
'incompatible file type'
return
end
%Get 2-port S-parameters from short file
[number,unit,parameter,format,type,load]=textread(file_s,'%s %s %s %s %s %s',1,'headerlines',5);
Appendix A: Electrical Characterization
158
if strcmp(format,'RI')
[f,s11_real,s11_imag,s21_real,s21_imag,s12_real,s12_imag,s22_real,s22_imag]=textread(file_s,'%n %f %f %f
%f %f %f %f %f',-1,'headerlines',6);
s11_s=s11_real+j*s11_imag;
s21_s=s21_real+j*s21_imag;
s12_s=s12_real+j*s12_imag;
s22_s=s22_real+j*s22_imag;
elseif strcmp(format,'dB')
[f,s11_mag,s11_phase,s21_mag,s21_phase,s12_mag,s12_phase,s22_mag,s22_phase]=textread(file_s,'%n %f %f
%f %f %f %f %f %f',-1,'headerlines',6);
s11_s=10.^(s11_mag./20).*exp(j*pi/180*s11_phase);
s21_s=10.^(s21_mag./20).*exp(j*pi/180*s21_phase);
s12_s=10.^(s12_mag./20).*exp(j*pi/180*s12_phase);
s22_s=10.^(s22_mag./20).*exp(j*pi/180*s22_phase);
else
'incompatible file type'
return
end
%Convert 2-port S-parameters to 2-port Y-parameters
z0=50;
D_m=(1+s11_m).*(1+s22_m)-s12_m.*s21_m;
y11_m=1/z0*((1-s11_m).*(1+s22_m)+s12_m.*s21_m)./D_m;
y12_m=-1/z0*2*s12_m./D_m;
y21_m=-1/z0*2*s21_m./D_m;
y22_m=1/z0*((1+s11_m).*(1-s22_m)+s12_m.*s21_m)./D_m;
D_o=(1+s11_o).*(1+s22_o)-s12_o.*s21_o;
y11_o=1/z0*((1-s11_o).*(1+s22_o)+s12_o.*s21_o)./D_o;
y12_o=-1/z0*2*s12_o./D_o;
y21_o=-1/z0*2*s21_o./D_o;
y22_o=1/z0*((1+s11_o).*(1-s22_o)+s12_o.*s21_o)./D_o;
D_s=(1+s11_s).*(1+s22_s)-s12_s.*s21_s;
y11_s=1/z0*((1-s11_s).*(1+s22_s)+s12_s.*s21_s)./D_s;
y12_s=-1/z0*2*s12_s./D_s;
y21_s=-1/z0*2*s21_s./D_s;
y22_s=1/z0*((1+s11_s).*(1-s22_s)+s12_s.*s21_s)./D_s;
%Subtract open response in Y-parameters
y11_mp=y11_m-y11_o;
y12_mp=y12_m-y12_o;
y21_mp=y21_m-y21_o;
y22_mp=y22_m-y22_o;
y11_sp=y11_s-y11_o;
y12_sp=y12_s-y12_o;
y21_sp=y21_s-y21_o;
y22_sp=y22_s-y22_o;
%Transform 2-port Y-parameters to 2-port Z-parameters
D_mp=y11_mp.*y22_mp-y12_mp.*y21_mp;
z11_mp=y22_mp./D_mp;
z12_mp=-y12_mp./D_mp;
z21_mp=-y21_mp./D_mp;
z22_mp=y11_mp./D_mp;
D_sp=y11_sp.*y22_sp-y12_sp.*y21_sp;
z11_sp=y22_sp./D_sp;
z12_sp=-y12_sp./D_sp;
Appendix A: Electrical Characterization
159
z21_sp=-y21_sp./D_sp;
z22_sp=y11_sp./D_sp;
%Subtract short response in Z-parameters
z11=z11_mp-z11_sp;
z12=z12_mp-z12_sp;
z21=z21_mp-z21_sp;
z22=z22_mp-z22_sp;
%Transform 2-port Z-parameters to 2-port Y-parameters
D=z11.*z22-z12.*z21;
y11=z22./D;
y12=-z12./D;
y21=-z21./D;
y22=z11./D;
%Transform 2-port Y-parameters to lumped impedances
imp_se=-1./y12; %Series impedance
imp_sh1=1./(y11+y12); %Shunt impedance 1
imp_sh2=1./(y22+y21); %Shunt impedance 2
%Convert frequency from Hz to rad/s
w=2*pi()*f;
%Find resonant frequency
[value,index]=min(abs(imag(smooth(imp_se,100))));
if (value < 10)
f0=f(index)
w0=2*pi*f0;
Cs_vs_f=(1-w.^2/w0.^2).*(-1./(w.*imag(imp_se)));
Cs=mean(Cs_vs_f(max(find(f<1e9)):max(find(f<4e9))))
Ls=1/(w0.^2*Cs)
else
f0=40e9
Ls=0
Cs_vs_f=-1./(w.*(imag(imp_se)-w.*Ls));
Cs=mean(Cs_vs_f(max(find(f<1e9)):max(find(f<4e9))))
End
%Calculate element values of equivalent circuit model
Rs_vs_f=real(imp_se);
Rs=mean(Rs_vs_f(max(find(f<1e9)):max(find(f<4e9))))
Q1_vs_f=-imag(1./y11)./real(1./y11);
Q2_vs_f=-imag(1./y22)./real(1./y22);
Q1_1GHz=mean(Q1_vs_f(max(find(f<1e9)):max(find(f<4e9))).*f(max(find(f<1e9)):max(find(f<4e9)))./(f0f(max(find(f<1e9)):max(find(f<4e9)))).*f0)/1e9*(f0-1e9)/f0
Q2_1GHz=mean(Q2_vs_f(max(find(f<1e9)):max(find(f<4e9))).*f(max(find(f<1e9)):max(find(f<4e9)))./(f0f(max(find(f<1e9)):max(find(f<4e9)))).*f0)/1e9*(f0-1e9)/f0
C1g_vs_f=-1./(w.*imag(imp_sh1));
C1g=mean(C1g_vs_f(max(find(f<1e9)):max(find(f<4e9))))
C2g_vs_f=-1./(w.*imag(imp_sh2));
C2g=mean(C2g_vs_f(max(find(f<1e9)):max(find(f<4e9))))
%Calculate de-embedded 2-port S-parameters
s11=((1-z0.*y11).*(1+z0.*y22)+z0.*y12.*z0.*y21)./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
s12=-2*z0.*y12./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
Appendix A: Electrical Characterization
160
s21=-2*z0.*y21./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
s22=((1+z0.*y11).*(1-z0.*y22)+z0.*y12.*z0.*y21)./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
%Calculate modeled lumped impedances
imp_sei=Rs+j*w*Ls+1./(j*w*Cs);
imp_sh1i=1./(j*w*C1g);
imp_sh2i=1./(j*w*C2g);
%Calculate modeled 2-port Y-parameters
y11i=1./imp_sh1i+1./imp_sei;
y12i=-1./imp_sei;
y21i=-1./imp_sei;
y22i=1./imp_sh2i+1./imp_sei;
%Calculate modeled 2-port S-parameters
s11i=((1-z0.*y11i).*(1+z0.*y22i)+z0.*y12i.*z0.*y21i)./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
s12i=-2*z0.*y12i./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
s21i=-2*z0.*y21i./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
s22i=((1+z0.*y11i).*(1-z0.*y22i)+z0.*y12i.*z0.*y21i)./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
Appendix A: Electrical Characterization
161
A.4.2. T-model Script
%John Reinke
%3/7/2011
%Open-short de-embedding and extraction of equivalent circuit model parameters for T-model capacitors
%Directory and file names
dir='C:\Documents and Settings\jreinke\Desktop\Jazz\Jazz032\RF\091910';
file_m=[dir '\cap1c1s15.s2p']; %File containing DUT 2-port S-parameters
file_o=[dir '\gsg_open.s2p']; %File containing open 2-port S-parameters
file_s=[dir '\gsg_short.s2p']; %File containing short 2-port S-parameters
%Get 2-port S-parameters from capacitor file
[number,unit,parameter,format,type,load]=textread(file_m,'%s %s %s %s %s %s',1,'headerlines',5);
if strcmp(format,'RI')
[f,s11_real,s11_imag,s21_real,s21_imag,s12_real,s12_imag,s22_real,s22_imag]=textread(file_m,'%n %f %f %f
%f %f %f %f %f',-1,'headerlines',6);
s11_m=s11_real+j*s11_imag;
s21_m=s21_real+j*s21_imag;
s12_m=s12_real+j*s12_imag;
s22_m=s22_real+j*s22_imag;
elseif strcmp(format,'dB')
[f,s11_mag,s11_phase,s21_mag,s21_phase,s12_mag,s12_phase,s22_mag,s22_phase]=textread(file_m,'%n %f
%f %f %f %f %f %f %f',-1,'headerlines',6);
s11_m=10.^(s11_mag./20).*exp(j*pi/180*s11_phase);
s21_m=10.^(s21_mag./20).*exp(j*pi/180*s21_phase);
s12_m=10.^(s12_mag./20).*exp(j*pi/180*s12_phase);
s22_m=10.^(s22_mag./20).*exp(j*pi/180*s22_phase);
else
'incompatible file type'
return
end
%Get 2-port S-parameters from open file
[number,unit,parameter,format,type,load]=textread(file_o,'%s %s %s %s %s %s',1,'headerlines',5);
if strcmp(format,'RI')
[f,s11_real,s11_imag,s21_real,s21_imag,s12_real,s12_imag,s22_real,s22_imag]=textread(file_o,'%n %f %f %f
%f %f %f %f %f',-1,'headerlines',6);
s11_o=s11_real+j*s11_imag;
s21_o=s21_real+j*s21_imag;
s12_o=s12_real+j*s12_imag;
s22_o=s22_real+j*s22_imag;
elseif strcmp(format,'dB')
[f,s11_mag,s11_phase,s21_mag,s21_phase,s12_mag,s12_phase,s22_mag,s22_phase]=textread(file_o,'%n %f
%f %f %f %f %f %f %f',-1,'headerlines',6);
s11_o=10.^(s11_mag./20).*exp(j*pi/180*s11_phase);
s21_o=10.^(s21_mag./20).*exp(j*pi/180*s21_phase);
s12_o=10.^(s12_mag./20).*exp(j*pi/180*s12_phase);
s22_o=10.^(s22_mag./20).*exp(j*pi/180*s22_phase);
else
'incompatible file type'
return
end
%Get 2-port S-parameters from short file
[number,unit,parameter,format,type,load]=textread(file_s,'%s %s %s %s %s %s',1,'headerlines',5);
Appendix A: Electrical Characterization
162
if strcmp(format,'RI')
[f,s11_real,s11_imag,s21_real,s21_imag,s12_real,s12_imag,s22_real,s22_imag]=textread(file_s,'%n %f %f %f
%f %f %f %f %f',-1,'headerlines',6);
s11_s=s11_real+j*s11_imag;
s21_s=s21_real+j*s21_imag;
s12_s=s12_real+j*s12_imag;
s22_s=s22_real+j*s22_imag;
elseif strcmp(format,'dB')
[f,s11_mag,s11_phase,s21_mag,s21_phase,s12_mag,s12_phase,s22_mag,s22_phase]=textread(file_s,'%n %f %f
%f %f %f %f %f %f',-1,'headerlines',6);
s11_s=10.^(s11_mag./20).*exp(j*pi/180*s11_phase);
s21_s=10.^(s21_mag./20).*exp(j*pi/180*s21_phase);
s12_s=10.^(s12_mag./20).*exp(j*pi/180*s12_phase);
s22_s=10.^(s22_mag./20).*exp(j*pi/180*s22_phase);
else
'incompatible file type'
return
end
%Convert 2-port S-parameters to 2-port Y-parameters
z0=50;
D_m=(1+s11_m).*(1+s22_m)-s12_m.*s21_m;
y11_m=1/z0*((1-s11_m).*(1+s22_m)+s12_m.*s21_m)./D_m;
y12_m=-1/z0*2*s12_m./D_m;
y21_m=-1/z0*2*s21_m./D_m;
y22_m=1/z0*((1+s11_m).*(1-s22_m)+s12_m.*s21_m)./D_m;
D_o=(1+s11_o).*(1+s22_o)-s12_o.*s21_o;
y11_o=1/z0*((1-s11_o).*(1+s22_o)+s12_o.*s21_o)./D_o;
y12_o=-1/z0*2*s12_o./D_o;
y21_o=-1/z0*2*s21_o./D_o;
y22_o=1/z0*((1+s11_o).*(1-s22_o)+s12_o.*s21_o)./D_o;
D_s=(1+s11_s).*(1+s22_s)-s12_s.*s21_s;
y11_s=1/z0*((1-s11_s).*(1+s22_s)+s12_s.*s21_s)./D_s;
y12_s=-1/z0*2*s12_s./D_s;
y21_s=-1/z0*2*s21_s./D_s;
y22_s=1/z0*((1+s11_s).*(1-s22_s)+s12_s.*s21_s)./D_s;
%Subtract open response in Y-parameters
y11_mp=y11_m-y11_o;
y12_mp=y12_m-y12_o;
y21_mp=y21_m-y21_o;
y22_mp=y22_m-y22_o;
y11_sp=y11_s-y11_o;
y12_sp=y12_s-y12_o;
y21_sp=y21_s-y21_o;
y22_sp=y22_s-y22_o;
%Transform 2-port Y-parameters to 2-port Z-parameters
D_mp=y11_mp.*y22_mp-y12_mp.*y21_mp;
z11_mp=y22_mp./D_mp;
z12_mp=-y12_mp./D_mp;
z21_mp=-y21_mp./D_mp;
z22_mp=y11_mp./D_mp;
D_sp=y11_sp.*y22_sp-y12_sp.*y21_sp;
z11_sp=y22_sp./D_sp;
z12_sp=-y12_sp./D_sp;
Appendix A: Electrical Characterization
163
z21_sp=-y21_sp./D_sp;
z22_sp=y11_sp./D_sp;
%Subtract short response in Z-parameters
z11=z11_mp-z11_sp;
z12=z12_mp-z12_sp;
z21=z21_mp-z21_sp;
z22=z22_mp-z22_sp;
%Transform 2-port Z-parameters to 2-port Y-parameters
D=z11.*z22-z12.*z21;
y11=z22./D;
y12=-z12./D;
y21=-z21./D;
y22=z11./D;
%Transform 2-port Y-parameters to lumped impedances
imp_g=(z21+z12)/2; %Shunt impedance to ground
imp_s1=z11-z12; %Series impedance 1
imp_s2=z22-z21; %Series impedance 2
%Convert frequency from Hz to rad/s
w=2*pi()*f;
Cg_vs_f=-1./(w.*(imag(imp_g)));
Cg=mean(Cg_vs_f(max(find(f<30e9)):max(find(f<35e9))))
Rg_vs_f=real(imp_g);
Rg=mean(Rg_vs_f(max(find(f<30e9)):max(find(f<35e9))))
Ls1_vs_f=imag(imp_s1)./w;
Ls1=mean(Ls1_vs_f(max(find(f<30e9)):max(find(f<35e9))))
Rs1_vs_f=real(imp_s1);
Rs1=mean(Rs1_vs_f(max(find(f<30e9)):max(find(f<35e9))))
Ls2_vs_f=imag(imp_s2)./w;
Ls2=mean(Ls2_vs_f(max(find(f<30e9)):max(find(f<35e9))))
Rs2_vs_f=real(imp_s2);
Rs2=mean(Rs2_vs_f(max(find(f<30e9)):max(find(f<35e9))))
f0=55e9;
Q1_vs_f=-imag(z11)./real(z11);
Q2_vs_f=-imag(z22)./real(z22);
Q1_1GHz=mean(Q1_vs_f(max(find(f<30e9)):max(find(f<35e9))).*f(max(find(f<30e9)):max(find(f<35e9)))./(f0f(max(find(f<30e9)):max(find(f<35e9)))).*f0)/30e9*(f0-30e9)/f0
Q2_1GHz=mean(Q2_vs_f(max(find(f<30e9)):max(find(f<35e9))).*f(max(find(f<30e9)):max(find(f<35e9)))./(f0f(max(find(f<30e9)):max(find(f<35e9)))).*f0)/30e9*(f0-30e9)/f0
%Calculate de-embedded 2-port S-parameters
s11=((1-z0.*y11).*(1+z0.*y22)+z0.*y12.*z0.*y21)./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
s12=-2*z0.*y12./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
s21=-2*z0.*y21./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
s22=((1+z0.*y11).*(1-z0.*y22)+z0.*y12.*z0.*y21)./((1+z0.*y11).*(1+z0.*y22)-z0.*y12.*z0.*y21);
%Calculate modeled lumped impedances
imp_gi=Rg+1./(j*w*Cg);
imp_s1i=Rs1+j*w*Ls1;
imp_s2i=Rs2+j*w*Ls2;
%Calculate modeled 2-port Z-parameters
z11i=imp_gi+imp_s1;
Appendix A: Electrical Characterization
164
z12i=imp_gi;
z21i=imp_gi;
z22i=imp_gi+imp_s2;
%Calculate modeled 2-port Y-parameters
Di=z11i.*z22i-z12i.*z21i;
y11i=z22i./Di;
y12i=-z12i./Di;
y21i=-z21i./Di;
y22i=z11i./Di;
%Calculate modeled 2-port S-parameters
s11i=((1-z0.*y11i).*(1+z0.*y22i)+z0.*y12i.*z0.*y21i)./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
s12i=-2*z0.*y12i./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
s21i=-2*z0.*y21i./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
s22i=((1+z0.*y11i).*(1-z0.*y22i)+z0.*y12i.*z0.*y21i)./((1+z0.*y11i).*(1+z0.*y22i)-z0.*y12i.*z0.*y21i);
Appendix A: Electrical Characterization
165
Appendix B. List of Cadence Layouts
Table B.1 lists the main Cadence layouts for all the CMOS-MEMS variable capacitors and
the CMOS-MEMS phase shifter presented in this work. Table B.2 lists all the Cadence libraries
with layouts that were created by the author.
Layout
Gap-Tuning Capacitor
Gap-Tuning Capacitor
with Updated Heating
Resistors
Initial Digital
Capacitor
Updated Digital
Capacitor
Phase Shifter Digital
Capacitor
Phase Shifter
Charge Pump
Design Contest GapTuning Capacitor
Table B.1: List of Cadence Layouts
Description
Cell Name
The gap-tuning capacitor presented in
cap5
Chapter 3.
The gap-tuning capacitor presented in
Chapter 3 with the heating resistors
cap6
sized to produce a uniform temperature.
The initial digital capacitor presented in
switch5
Chapter 4.
The updated digital capacitor with
reduced parasitic capacitance presented
switch7
in Section 4.5.5
The phase shifter digital capacitor
switch1
presented in Chapter 5.
The phase shifter presented in Chapter
phase_shifter2
5.
A CMOS charge pump capable of
charge_pump2
producing ≈ 9 V from a 3.3 V supply.
The gap-tuning capacitor used in the
cap2_test2
SRC/SIAA Design Contest.
Library
jz60_025
Process
Jazz 0.35 µm
BiCMOS
jz60_028
Jazz 0.35 µm
BiCMOS
jz60_031
Jazz 0.35 µm
BiCMOS
jz60_032
Jazz 0.35 µm
BiCMOS
jz60_032
jz60_032
jz60_031
jz18_001
Jazz 0.35 µm
BiCMOS
Jazz 0.35 µm
BiCMOS
Jazz 0.35 µm
BiCMOS
Jazz 0.18 µm
BiCMOS
Table B.2: List of Cadence Libraries
Library
Category
Process
jz60_024
John
Jazz 0.35 µm BiCMOS
jz60_025
John
Jazz 0.35 µm BiCMOS
jz60_026
John
Jazz 0.35 µm BiCMOS
jz60_027
John
Jazz 0.35 µm BiCMOS
jz60_028
John
Jazz 0.35 µm BiCMOS
jz60_031
John
Jazz 0.35 µm BiCMOS
jz60_032
John
Jazz 0.35 µm BiCMOS
jz60_033
John
Jazz 0.35 µm BiCMOS
jz18_001
John
Jazz 0.18 µm BiCMOS
ibm7rf_001
John
IBM 0.18 µm CMOS
ibm7rf_002
Everything
IBM 0.18 µm CMOS
ibm7rf_003
Everything
IBM 0.18 µm CMOS
tsmc035_001
John
TSMC 0.35 µm CMOS
tsmc018_001
John
TSMC 0.18 µm CMOS
tsmc018_004
John
TSMC 0.18 µm CMOS
st7rf_003
John
ST 0.25 µm BiCMOS
Appendix B: List of Cadence Layouts
166