TDA7429S TDA7429T

TDA7429S TDA7429T ® DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX 3 STEREO/4 STEREO INPUTS INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE MIDDLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE: - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES FOUR SPEAKERS ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS SDIP42 TQFP44 ORDERING NUMBERS: TDA7429S TDA7429T It reproduces surround sound by using programmable phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. DESCRIPTION The TDA7429 is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. July 1999 R_IN3 R_IN2 R_IN1 41 R_IN4 PS3 42 CREF PS2 43 PS4 PS1 44 VS LP PIN CONNECTION (TQFP44) 40 39 38 37 36 35 34 29 L_IN3 VAR_L 6 28 L_IN4 BASSO_L 7 27 AUXOUT_L VAR_R 8 26 AUXOUT_R BASSO_R 9 25 L_OUT BASS_LO 10 24 R_OUT BASS_LI 11 23 DIG_GND 12 13 14 15 16 17 18 19 20 21 22 SCL L_IN2 5 SDA 30 REARIN AGND REAROUT TREBLE_L L_IN1 4 TREBLE_R MONITOR_L 31 MIDDLE_RI 32 3 MIDDLE_RO HP1 HP2. MIDDLE_LI MONITOR_R MIDDLE_LO 33 2 BASS_RI 1 BASS_RO LP1 D96AU532 1/20 TDA7429S - TDA7429T PIN CONNECTION (SDIP42) PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VS CREF R_IN3 R_IN2 R_IN1 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI D97AU623 TEST CIRCUIT (TDA7429S) 2.2µF 2.2µF 2.2µF 0.47µF 0.47µF BASSO_R 22nF PS4 22nF PS3 4.7nF PS2 100nF PS1 1.2nF LP 5.6nF 5.6nF LP1 TREBLE_R 5.6nF TREBLE_L VAR_R 14 BASSO_L 13 REAROUT VAR_L 12 11 REARIN 9 R_IN2 R_IN3 40 10 39 1 38 36 2 35 3 34 4 33 5 6 22nF MIDDLE_LO MIDDLE_LI 18nF 2.7K MIDDLE_RI 24 41 L_IN2 L_IN3 CREF 0.47µF 0.47µF 0.47µF 100nF 22µF 220nF 37 100nF 15 19 BASS_LO 100nF 16 20 17 21 BASS_LI BASS_RO 5.6K 100nF 100nF 22 18 32 31 30 AUXOUT_L AUXOUT_R L_OUT 29 28 27 26 R_OUT DIG_GND SCL SDA 25 8 AGND HP2 7 HP1 D97AU626 680nF 2/20 L_IN1 10µF 22nF MIDDLE_RO MONITOR_L VS 18nF 2.7K 0.47µF 42 23 100nF MONITOR_R R_IN1 BASS_RI 5.6K TDA7429S - TDA7429T QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. 9 10.2 VS VCL Supply Voltage 7 Max. input signal handling 2 THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N SC Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz 106 90 Treble Control (2db step) Unit V Vrms 0.1 % dB dB -14 +14 dB Middle Control (2db step) -14 +14 dB Bass Control (2dB step) -14 -79 +14 0 dB dB 1dB step (LCH, RCH) Balance Control Mute Attenuation 100 dB TEST CIRCUIT (TDA7429T) 2.2µF BASSO-R 22nF PS4 22nF PS3 4.7nF PS2 100nF PS1 1.2nF LP 5.6nF LP1 5.6nF TREBLE-R 5.6nF TREBLE-L VAR-R BASSO-L 8 9 2.2µF 2.2µF REAROUT VAR-L 7 6 0.47µF 0.47µF R-IN4 R-IN3 REARIN 4 37 5 0.47µF R-IN2 36 35 40 34 32 41 31 42 30 43 29 44 28 1 22nF MIDDLE-LO MIDDLE-LI 18 2.7K MIDDLE-RO MIDDLE-RI L-IN1 L-IN2 L-IN3 L-IN4 0.47µF 0.47µF 0.47µF 0.47µF 10µF TDA7429 19 38 CREF 100nF 22µF 220nF 33 100nF 10 14 BASS-LO 100nF 11 15 22nF 18nF MONITOR_L VS 18nF 2.7K 0.47µF 39 100nF MONITOR_R R-IN1 12 16 BASS-LI BASS-RO 5.6K 100nF 100nF 17 13 27 26 25 24 23 22 21 AUXOUT-L AUXOUT-R L-OUT R-OUT DIG-GND SCL SDA 20 3 AGND HP2 2 BASS-RI 5.6K HP1 D96AU533 680nF 3/20 L-IN1 R-IN4 0.47µF R-IN3 0.47µF R-IN2 0.47µF R-IN1 0.47µF L-IN4 0.47µF L-IN3 0.47µF L-IN2 0.47µF 37 36 35 34 28 29 30 31 33 MONITOR R 31.5dB control 31.5dB 1 control 3 HP1 + 39 VS RLP1 RHP1 2 LP1 20 38 SUPPLY + - R6 R5 HP2 THE SWITCHES POSITION MATCHES THE RESET CONDITION 50K 50K 50K 50K 50K 50K 50K 50K 32 MONITOR L Vref L-R 22µF + - + - CREF 0.47µF AGND LP 44 MOVIE/ MUSIC SIM 1.2nF 5 2.2µF 4 MOVIE/SIM 50K MIXING AMP 5.6nF 18 MIDDLE TREBLE 5.6nF 2.7K 18nF 22nF 16 REAR SURR 3BAND FIX RB 5.6K 100nF REAR 100nF 12 SURR FIX 3BAND BASSO-R 79dB CONTROL MUTE REC ATT MUTE REC ATT 7 BASSO-L 79dB CONTROL I2C BUS DECODER + LATCHES BASS 13 RB 10 BASS-LO 100nF BASS-LI BASS 11 5.6K 22nF 100nF 14 RM MIDDLE 17 15 RM 2.7K 18nF TREBLE TREBLE-R SURR SURR 19 TREBLE-L OFF OFF 40 MIXING AMP PS4 400Hz PS4 PS3 400Hz 41 RPS4 PS3 22nF RPS3 MUSIC 42 EFFECT CONTROL OFF PS2 4KHz PS1 90Hz PS2 RPS2 LPF 9KHz 43 RPS1 PS1 22nF REAROUT 4.7nF REARIN MIDDLE-LI MIDDLE-RI 100nF BASS-RI MIDDLE-LO MIDDLE-RO 680nF BASS-RO 2.2µF 9 30K FIX VAR 30K VAR-L VAR-R 8 VAR FIX 6 2.2µF - 4/20 - + + 5.6nF 79dB CONTROL MUTE SPKR ATT MUTE SPKR ATT 79dB CONTROL AUXOUT-R R-OUT DIG GND SDA SCL L-OUT AUXOUT-L D96AU513 26 24 23 21 22 25 27 TDA7429S - TDA7429T BLOCK DIAGRAM (TDA7429T) R_IN3 0.47µF R_IN2 0.47µF R_IN1 0.47µF L_IN3 0.47µF L_IN2 0.47µF L_IN1 40 39 38 33 34 35 37 MONITOR_R 31.5dB control 31.5dB control 7 HP1 + 42 VS RLP1 RHP1 6 LP1 25 41 SUPPLY + - R6 R5 8 HP2 THE SWITCHES POSITION MATCHES THE RESET CONDITION 50K 50K 50K 50K 50K 50K 36 MONITOR_L Vref L-R 22µF + - + - CREF 0.47µF AGND LP 5 MOVIE/ MUSIC SIM 1.2nF 10 2.2µF 9 MOVIE/SIM 50K MIXING AMP MIXING AMP PS4 400Hz PS4 PS3 400Hz 2 RPS4 PS3 22nF RPS3 MUSIC 3 EFFECT CONTROL OFF PS2 4KHz PS1 90Hz PS2 RPS2 LPF 9KHz 4 RPS1 PS1 22nF REAROUT 4.7nF REARIN 23 MIDDLE TREBLE 5.6nF 2.7K 18nF 22nF 21 18 REAR SURR RB 15 BASS RB 5.6K 100nF REAR 100nF 17 SURR FIX 3BAND BASSO_R 79dB CONTROL MUTE REC ATT MUTE REC ATT 12 BASSO_L 79dB CONTROL I2C BUS DECODER + LATCHES 3BAND FIX BASS_LO 100nF BASS_LI BASS 16 5.6K 22nF 100nF 19 RM MIDDLE 22 20 RM 2.7K 18nF TREBLE TREBLE_R SURR SURR 24 TREBLE_L OFF OFF 1 5.6nF MIDDLE_LI MIDDLE_RI 100nF BASS_RI MIDDLE_LO MIDDLE_RO 680nF BASS_RO 2.2µF 14 VAR_R 30K FIX VAR 30K VAR_L 13 VAR FIX 11 2.2µF - + + 5.6nF 79dB CONTROL MUTE 31 29 28 26 27 30 AUXOUT_R R_OUT DIG GND SDA SCL L_OUT AUXOUT_L D97AU624A SPKR ATT MUTE SPKR ATT 79dB CONTROL 32 TDA7429S - TDA7429T BLOCK DIAGRAM (TDA7429S) 5/20 TDA7429S - TDA7429T THERMAL DATA Symbol Rth j-pins Description Thermal Resistance Junction-pins Value Unit 85 °C/W Max. ABSOLUTE MAXIMUM RATINGS Symbol VS Tamb Tstg Parameter Value Unit 11 V -10 to 85 °C -55 to +150 °C Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS IS Supply Voltage 7 9 10.2 V Supply Current 10 18 26 mA SVR Ripple Rejection 60 80 35 50 2 2.5 31.5 LCH / RCH out, Mode = OFF dB INPUT STAGE RIN Input Resistance VCL Clipping Level Control Range CRANGE THD = 0.3% 65 KΩ Vrms dB AVMIN AVMAX Min. Attenuation -1 0 1 dB Max. Attenuation 31 31.5 32 dB ASTEP Step Resolution 0.5 1 dB +14.0 +16.0 dB BASS CONTROL Gb Control Range BSTEP Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ +11.5 +14.0 +16.0 dB 1 17.5 2 25 3 32.5 dB KΩ +13.0 +14.0 +15.0 dB 1 2 3 dB - 21 0.5 1 -6 1.5 dB dB 15.2 18.3 KΩ KΩ RB Max. Boost/cut +11.5 MIDDLE CONTROL Gm MSTEP RM Control Range Max. Boost/cut Step Resolution Internal Feedback Resistance TREBLE CONTROL Gt Control Range TSTEP Step Resolution Max. Boost/cut EFFECT CONTROL CRANGE SSTEP Control Range Step Resolution SURROUND SOUND MATRIX PHASE RPS10 RPS11 Phase Shifter 1: D1 = 0, D0 = 0 Phase Shifter 1: D1 = 0, D0 = 1 8.3 10 11.8 14.1 RPS12 Phase Shifter 1: D1 = 1, D0 = 0 12.6 17.9 23.3 KΩ RPS13 Phase Shifter 1: D1 = 1, D0 = 1 Phase Shifter 2: D3 = 0, D2 = 0 26.4 4 37.3 5.6 48.85 7.2 KΩ KΩ RPS20 6/20 TDA7429S - TDA7429T ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 Symbol Parameter Min. Typ. Max. Unit RPS21 RPS22 Phase Shifter 2: D3 = 0, D2 = 1 Test Condition 4.8 6.8 8.7 KΩ Phase Shifter 2: D3 = 1, D2 = 0 6 8.4 10.9 KΩ RPS23 Phase Shifter 2: D3 = 1, D2 = 1 12.9 18.3 23.7 KΩ RPS30 Phase Shifter 3: D5 = 0, D4 = 0 8.5 12.1 15.6 KΩ RPS31 Phase Shifter 3: D5 = 0, D4 = 1 10.2 14.5 18.7 KΩ RPS32 RPS33 Phase Shifter 3: D5 = 1, D4 = 0 Phase Shifter 3: D5 = 1, D4 = 1 12.7 27.4 18.1 39.1 23.3 50.75 KΩ KΩ RPS40 Phase Shifter 4: D7 = 0, D6 = 0 8.5 12.1 15.6 KΩ RPS41 Phase Shifter 4: D7 = 0, D6 = 1 10.2 14.5 18.7 KΩ RPS42 RPS43 Phase Shifter 4: D7 = 1, D6 = 0 Phase Shifter 4: D7 = 1, D6 = 1 12.7 27.4 18.1 39.1 23.3 50.75 KΩ KΩ GOFF In-phase Gain (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout Lin → Lout -1 0 1 dB DGOFF LR In-phase Gain Difference (OFF) -1 0 1 dB GMOV In-phase Gain (Movie) Mode OFF, Input signal of 1kHz, 1.4 Vp-p Rin → Rout, Lin → Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p Rin → Rout, Lin → Lout DGMOV LR In-phase Gain Difference (Movie) GMUS In-phase Gain (Music) DGMUS 8 dB Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout), (Lin → Lout) 0 dB 7 dB LR In-phase Gain Difference (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) - (Lin → Lout) 0 dB LMON1 Simulated L Output 1 Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Lout 4.5 dB LMON2 Simulated L Output 2 –4.0 dB LMON3 Simulated L Output 3 Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Lout 7.0 dB RMON1 Simulated R Output 1 Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin →Rout – 4.5 dB RMON2 Simulated R Output 2 3.8 dB RMON3 Simulated R Output 3 Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin →Rout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Rout – 20 dB RLP1 RHPI Low Pass Filter Resistance High Pass Filter Resistance 7 42 10 60 13 78 KΩ KΩ RLPF LP Pin Impedance 7 10 13 KΩ 7/20 TDA7429S - TDA7429T ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit SPEAKER & AUX ATTENUATORS Crange Control Range SSTEP Step Resolution EA VDC AMUTE RVEA Attenuation set error 79 1 1.5 dB dB -1.5 0 1.5 Av = -20 to -79dB -3 0 2 dB adjacent att. steps -3 0 3 mV Output Mute Condition +70 100 Input Impedance 21 30 39 KΩ DC Steps Av = 0 to -20dB dB -0.5 dB AUDIO OUTPUTS 30 µVrms µVrms µVrms Mode = Music , BW = 20Hz to 20KHz, 30 mVrms Output Noise (Simulated) Mode = Simulated, BW = 20Hz to 20KHz 30 µVrms d SC Distorsion Channel Separation Av = 0 ; Vin = 1Vrms VOCL ROUT Clipping Level Output Resistance d = 0.3% VOUT DC Voltage Level NO(OFF) Output Noise (OFF) NO(MOV) Output Noise (Movie) NO(MUS) Output Noise (Music) NO(MON) Output Mute, Flat BW = 20Hz to 20KHz Mode =Movie , BW = 20Hz to 20KHz 4 5 0.01 70 90 2 25 2.5 50 0.1 % dB 85 3.8 Vrms Ω V MONITOR OUTPUTS d SC Distorsion Channel Separation Av = 0 ; Vin = 1Vrms VOCL ROUT Clipping Level Output Resistance d = 0.3% VOUT DC Voltage Level 70 0.01 90 2 25 2.5 50 0.1 85 4.5 % dB Vrms Ω V BUS INPUTS 8/20 VIL VIH Input Low Voltage Input High Voltage IIN VO Input Current Output Voltage SDA Acknowledge 1 V V +5 0.4 µA V 3 -5 IO = 1.6mA TDA7429S - TDA7429T 2 I C BUS INTERFACE Data transmission from microprocessor to the TDA7429 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 9/20 TDA7429S - TDA7429T address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7429 SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK DATA 1 to DATA n LSB B DATA MSB ACK LSB DATA ACK P D95AU226A ACK = Achnowledge S = Start P = Stop A = Address B = Auto Increment EXAMPLES No Incremental Bus The TDA7429 receives a start condition, the cor- CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 rect chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. A 0 MSB ACK 0 DATA LSB X X MSB X D3 D2 D1 D0 ACK LSB DATA ACK P D95AU306 Incremental Bus The TDA7429 receive s a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D95AU307 10/20 0 0 SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. A 0 MSB ACK 1 DATA 1 to DATA n LSB X X X D3 D2 D1 D0 ACK MSB LSB DATA ACK P TDA7429S - TDA7429T DATA BYTES Address = 80(HEX) FUNCTION SELECTION: The first byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 B X X X 0 0 0 0 INPUT ATTENUATION B X X X 0 0 0 1 SURROUND & OUT & EFFECT CONTROL B B X X X X X X 0 0 0 0 1 1 0 1 PHASE RESISTOR BASS & NATURAL BASE B X X X 0 1 0 0 MIDDLE & TREBLE B X X X 0 1 0 1 SPEAKER ATTENUATION "L" B X X X 0 1 1 0 SPEAKER ATTENUATION "R" B B X X X X X X 0 1 1 0 1 0 1 0 AUX ATTENUATION "L" AUX ATTENUATION"R" B X X X 1 0 0 1 INPUT MULTIPLEXER, & AUX OUT B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 INPUT ATTENUATION SELECTION MSB D7 X X X X X X X X D6 X X X X X X X X D5 D4 D3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LSB INPUT ATTENUATION D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS 0 -4 -8 -12 -16 -20 -24 -28 D2 D1 D0 REAR SWITCH REARIN, REAROUT PIN ACTIVE NO REARIN, REAROUT PIN INPUT ATTENUATION = 0 ∼ -31.5dB D7 X D6 0 X 1 D5 D4 D3 11/20 TDA7429S - TDA7429T SURROUND SELECTION MSB D7 X X X X LSB D6 D5 D4 D3 X X X X X X X X X X X X X X X X X X D2 D1 0 0 1 1 D0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 PHASE RESISTOR SELECTION MSB D7 LSB D6 D5 0 0 1 1 0 0 1 1 12/20 0 1 0 1 D4 0 1 0 1 D3 D2 0 0 1 1 0 1 0 1 D1 0 0 1 1 D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (KΩ) 12 14 18 37 PHASE SHIFT 2 (KΩ) 6 7 8 18 PHASE SHIFT 3 (KΩ) 12 14 18 39 PHASE SHIFT 4 (KΩ) 12 14 18 39 TDA7429S - TDA7429T BASS SELECTION MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB BASS D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 LSB SPEAKER/AUX ATT D0 0 1 0 1 0 1 0 1 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE SPEAKER/AUX ATT. R & L SELECTION MSB D7 X X X X X X X X D6 D5 D4 D3 X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 X X 1 1 0 1 1 X X X D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 X = INDIFFERENT 0,1 SPEAKER/AUX ATTENUATION = 0dB ∼ -79dB 13/20 TDA7429S - TDA7429T MIDDLE & TREBLE SELECTION MSB D7 D6 D5 D4 LSB MIDDLE D3 D2 D1 D0 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 0 1 1 0 1 0 -8 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 1 1 1 1 0 0 1 1 1 0 2 1 1 0 1 4 1 1 1 0 0 1 0 1 6 8 1 1 0 0 1 0 0 1 10 12 1 0 0 0 14 TREBLE 2 dB STEPS 0 0 0 0 0 0 0 0 1 0 1 0 -14 -12 -10 0 0 1 1 -8 0 0 0 1 1 1 0 0 1 0 1 0 -6 -4 -2 0 1 1 1 1 1 1 1 1 1 1 0 0 0 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 4 6 8 10 12 14 14/20 TDA7429S - TDA7429T INPUT/RECOUT L & R SELECTION MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 INPUT MULTIPLEXER X 0 0 0 IN2 X 0 1 0 IN3 X 1 0 0 IN4 X 1 1 0 IN1 AUX OUT "L" X 0 0 0 VER 1 (3BAND) X 0 1 0 VER 2 (SURR) X 1 0 0 VER 3 (REAR) X 1 1 0 FIX AUX OUT "R" X X 0 0 0 1 0 0 VER 1 (3BAND) VER 2 (SURR) X 1 0 0 VER 3 (REAR) X 1 1 0 FIX POWER ON RESET BASS & MIDDLE TREBLE 2dB 0dB SURROUND & OUT CONTROL+ EFFECT CONTROL OFF + FIX + MAX ATTENUATION SPEAKER/AUX ATTENUATION L &R INPUT ATTENUATION + REAR SWITCH MUTE MAX ATTENUATION + ON NATURAL BASE INPUT OFF IN1 PIN: TREBLE-L, TREBLE-R PIN: VOUT REF VS VS 20µA 20µA 25K GND GND D95AU233A 10K D95AU309 GND 15/20 TDA7429S - TDA7429T PIN: HP1 PIN: HP2 LP1 VS VS 10K 20µA 5.5K 60K 60K GND HP2 GND HP1 5.5K D94AU199 D94AU198 PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4, VS PIN: VAR-L, VAR-R, VS 20µA 20µA SW 50K GND VREF 30K D94AU200 PIN: CREF GND Vref D95AU227 PIN: LP1 VS VS 20K 20µA 20µA 42K 10K 20K GND D95AU336 GND 16/20 HP1 D94AU211 TDA7429S - TDA7429T PIN: SCL, SDA PIN: PS1, PS2, PS3, PS4, LP VS 20µA GND 20µA D94AU205 GND D95AU308 PIN: L-OUT, R-OUT, MONITOR-L, MONITOR-R REAROUT, BASSO-L, BASSO-R, AUXOUT_L, AUXOUT_R PIN: REARIN VS VS 20µA 20µA SW 50K GND Vref D95AU229 GND D95AU230 PIN: BASS-LI, BASS-RI, MIDDLE-LI, MIDDLE-RI, PIN: BASS-LO, BASS-RO, MIDDLE-LO, MIDDLE-RO, VS VS 20µA 20µA (*) GND BASS-LO GND 45K : Bass or 25K : MIDDLE BASS-RO,MIDDLE-LO,MIDDLE-RO BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI D95AU231A D95AU232 (*) 45K : Bass 25K : MIDDLE 17/20 TDA7429S - TDA7429T mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.014 0.018 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L 0.45 0.60 0.75 OUTLINE AND MECHANICAL DATA MAX. 0.018 0.024 L1 1.00 K 0°(min.), 3.5˚(typ.), 7°(max.) 0.030 0.039 TQFP44 (10 x 10) D D1 A A2 A1 33 23 34 22 0.10mm .004 B E B E1 Seating Plane 12 44 11 1 C L e K TQFP4410 18/20 TDA7429S - TDA7429T mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 5.08 0.20 A1 0.51 A2 3.05 3.81 4.57 0.120 B 0.38 0.46 0.56 0.0149 0.0181 0.0220 B1 0.89 1.02 1.14 0.035 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 36.58 36.83 37.08 1.440 E 15.24 16.00 0.60 E1 12.70 14.48 0.50 0.020 13.72 0.150 0.040 1.450 0.180 0.045 1.460 0.629 0.540 e 1.778 0.070 e1 15.24 0.60 0.570 e2 18.54 0.730 e3 1.52 0.060 L 2.54 OUTLINE AND MECHANICAL DATA MAX. 3.30 3.56 0.10 0.130 SDIP42 (0.600") 0.140 E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 Gage Plane 1 e3 21 e2 SDIP42 19/20 TDA7429S - TDA7429T Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 20/20 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.

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