MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Table of Contents
Chapter 1 DIP-IPM Product Outlines
1.1 DIP-IPM Series and Typical Applications
1.2 Functions and Features
1.2.1 Functions Outlines
1.2.2 Product Features
Chapter 2 Electrical Characteristics
2.1 Static Characteristics
2.2 Dynamic Characteristics
Chapter 3 Package
3.1 Package Outlines Drawing
3.2 Isolation
3.3 Laser Marking
3.4 List of Input / Output Terminals
3.4.1 Input / Output Terminals Description
3.4.2 Structure and Detailed Description of Input / Output Terminals
3.4.3 Description of Drive and Protection Functions
3.5 Installation Guidelines (Flatness / Mounting Strength / Screw Type /Grease)
Chapter 4 Applications
4.1 System Connection Diagram
4.2 Input circuit
4.3 Mono Drive-Voltage-Supply Scheme
4.3.1 Initial charging
4.3.2 Charging and Discharging of Bootstrap Capacitor During Inverter Operation
4.4 Interface Circuit Examples and Guidelines
4.4.1 Direct Input (without Opto-Coupler) Interface Example
4.4.2 Interface Example when a Fast Opto-Coupler is used
4.4.3 Interface Example when a Slow Opto-Coupler is used
4.4.4 Snubber Circuit
4.4.5 Parallel Connection
4.5 Short Circuit Protective Function
4.5.1 Timing Charts of Short Circuit Protection
4.5.2 Selecting the Current Sensing Shunt Resistance Value
4.5.3 Filter Circuit Setting (RC Time Constant) for Short-circuit Operation
4.5.4 SOA of the DIP-IPM (For short-circuit switching)
4.5.5 Series of Short Circuit protection
4.5.6 Fo Circuit
4.6 Guidelines for Control Supply
4.6.1 Timing Charts of Under-voltage Protection
4.6.2 Control Supply Starting-up and Shutting-down Sequence
4.6.3 Other Guidelines
4.7 Power Loss and Heat Dissipation Design
4.7.1 Power Loss Calculation (Example)
4.7.2 Temperature Rise Considerations and Calculation Example
4.8 Noise Withstand Capability
4.8.1 Example of Measurement Circuits
4.8.2 Countermeasures and Precautions
4.8.3 Surge resistance
Chapter 5 Additional Guidelines
5.1 Packaging Specification
5.2 Handling Notice
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Chapter1 DIP-IPM Product Outlines
1.1. DIP-IPM Series and Typical Applications
Table 1. The DIP-IPM Series and Some Typical Applications
Type
Name
IGBT Ratings
(IC /VCES)
PS20341-G
3A/500V
PS20351-G
PWM
Frequency
(Typ. )
Motor
Ratings
Typical
Applications
5kHz
0.1kW/AC220V
3A/500V
15kHz
0.1kW/AC220V
PS21342–G
5A/600V
5kHz
0.2kW/AC220V
PS21352–G
5A/600V
15kHz
0.2kW/AC220V
PS21353–G
PS21542–G
PS21552–G
10A/600V
5A/600V
5A/600V
15kHz
5kHz
15kHz
0.4kW/AC220V
0.2kW/AC220V
0.2kW/AC220V
PS21553–G
10A/600V
15kHz
0.4kW/AC220V
Refrigerator etc.
Refrigerator
Washing machine etc.
Refrigerator etc.
Refrigerator
Washing machine etc.
Washing machine etc.
Refrigerator, Industry etc.
Refrigerator, Industry etc.
Washing machine ,
Industry etc.
Note
Viso = 1500Vrms
(Sinusoidal, 1min)
Viso = 2500Vrms
(Sinusoidal, 1min)
1.2. Functions and Features
1.2.1. Functions Outlines
Figure-1(a) and Figure-1(b) show the photograph and internal functions block diagram of the DIP-IPM. The
DIP-IPM is the ultra-compact intelligent power module which integrates power parts, and drive and
protection circuit of AC 100-220V class inverter drive for small power motor control in dual-in-line
transfer-mold package.
Figure-1(a). Photograph of the DIP-IPM
Single Mold
Lead Frame
Control ICiHVICCLVICj
IGBTCFWDi
Figure-1(b). Structure
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
VUFS
VUFB
VP1
UP
+VCC
Input
Signal
Condition
Level
Shift
HVIC
VVFS
P
Gate
Drive
& UV
lock
out
VVFB
VP1
VP
+VCC
Input
Signal
Condition
HVIC
VWFS
5V Logic
Interface
to MCU
Level
Shift
Gate
Drive
& UV
lock
out
U
VWFB
VP1
WP
+VCC
Input
Signal
Condition
Level
Shift
HVIC
VN1
UN
VN
WN
Fo
CFO
CIN
V
Gate
Drive
& UV
lock
out
Motor
W
+VCC
Input Signal
Conditioning
Gate
Drive
Fault Logic &
UV lock out
Protection
Circuit
VNC
N
LV-ASIC
+
15V
Figure 1(c). Internal Functions Block Diagram of the DIP-IPM
1.2.2. Product Features
² Built-in IGBT inverter circuit for three
@ phase
@ AC@ output. ® Loss reduction by 4th gen. planar IGBT chip.
VCE(sat)(V)
PS21352-G saturation voltage characteristics
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Tj=25Ž
Tj=125Ž
0
1
2
3
Ic(A)
4
5
6
Figure2. Saturation voltage characteristics
Mono drive-power-supply.
Control and Protection Functions
- P-side : Control circuit Under-Voltage (UV) protection (without fault signaling).
- N-side : UV and Short-Circuit (SC) protection(Using External shunt resistor) (with Fault signaling).
² Small packaging using transfer mold materials realizes miniaturized inverter designs.
² By virtue of integrating an application specific type HVIC (High Voltage IC) inside the module, direct
coupling to CPU terminals without any opto-coupler or transformer isolation is possible. Thus, at least six
isolation circuits, which were required in the past, can be eliminated.
² By virtue of fast
@ and
@ high
@ voltage
@ elements,
@ and
@ built-in
@ peripheral
@ circuits,
@ mono
@ drive-power-supply
scheme is possible. Thus, three of the four external power supplies, which
@ were
@ required
@ in the past,
can be eliminated.
²
²
Ø
High integration of power parts, and built-in drive and protection functions miniaturize the overall
inverter set size and reduce design time.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Chapter 2 Electrical Characteristics
2.1. Static Characteristics
Table 2. Characteristics of DIP-IPM PS21352–G (5A/600V class)
Symbol
VCES
VCE(sat)
VEC
Parameter
Collector-emitter voltage
Collector-emitter saturation
voltage
FWDi forward voltage
Condition
Rating
600V Max.
VD=VDB=15V, VCIN=0V, IC=5A
Tj=25°C
-IC=5A, Tj=25°C, VCIN=5V
10% saturation voltage VCE(sat) reduction.
1.8V (Typ.)
2.2V (Typ.)
2.2. Dynamic Characteristics
Table 3. Characteristics of DIP-IPM PS21352–G (5A/600V class)
ton/toff
Switching times
VCC=300V, VD=15V, IC=5A
Tj=125°C, VCIN=0 Û 5V
0.6/1.1µs (Typ.)
tc(on)/tc(off)
Switching times
VCC=300V, VD=15V, IC=5A
Tj=125°C, VCIN=0 Û 5V
0.20/0.35µs
(Typ.)
Psw(on)/Psw(off)
Switching losses
VCC=300V, VD=15V, IC=5A
Tj=125°C, VCIN=0 Û 5V
0.15/0.30 mj/pulse
(Typ.)
Conditions : VCC=300V, VD=VDB=15V, Tj=125°C, Ic=5A Inductive Load Half-Bridge Circuit (L=10mH)
Tek Run: 250MS/s
Hi Res
Trig
Hi Res
Tek Run: 250MS/s
Mt
Trig
Mt
IC:2A/div
VCE:100V/div
t:200ns/div
ch1
100V
ch2
Math1
250 VV
VCE:100V/div
IC:2A/div
t:200ns/div
200mV
200ns
M 200ns ch2
628mV
ch1
100V
ch2
Math1
250 VV
200mV
200ns
M 200ns ch2
628mV
Figure 3. Switching Waveform of DIP-IPM PS21352–G (5A/600V class) (Typ.)
DC 5V
P-Side IGBT
VP1
VCIN(P)
IN
COM
P-Side Input Signal
VB
L
OUT
VS
A
VCC
B
VD
VCIN(N)
VN1
OUT
IN
VNC
V NO
CIN
L
N-Side IGBT
N-Side Input Signal
Figure 4. Half-Bridge Evaluation Circuit Diagram (Inductive Load)
*Note : B is connected during P-side switching, while A is connected during N-side switching.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Chapter-3 : Package
3.1. Package Outlines Drawing (Tentative)
×
φ
φ
×
Figure 5. Package Outlines
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
3.2. Isolation
Table 4. Isolation distance of Mini DIP-IPM
Standard
Clearance (mm)
UL 508
1.6
34.7
Table34.1-B
Mini DIP-IPM
Rating Volt. 51~300V
Between Power terminals
Under 2HP,
Between Control terminals
Less than 1440VA
Between Terminal and Fin
4.0
1.8
2.0
Creepage distance (mm)
3.2
Mini DIP-IPM
Between power terminals
4.0
Between control terminals
4.0
Between Terminal and Fin
4.0
(1) Clearance are designed that between Power terminals are 4.0mm, between Control terminals are 1.8mm,
between Terminal and Fin are 2.0mm. They are more than 1.6mm on UL 508 standard.
(2) Creepage distance are designed that between Power terminals are 4.0mm, between Control terminals
are 4.0mm, between Terminal and Fin are 4.0mm. They are more than 3.2mm on UL 508 standard.
3.3. Laser Marking
The laser marking range of Mini DIP is described in Fig.6. Mitsubishi mark, Type name(Point A), Lot
number(Point B), are marked in the range of 8´45mm. Type name, Lot number are marked from the position
of 21mm from left end of the laser marking range.
Marking Range
Figure 6. Marking
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
3.4. List of Input / Output Terminals
3.4.1. Input / Output Terminals Description
28 27 26 25 24 23 22 21 20 19 18 16
17
15 13
14
12 10
11
987
654
Type name , Lot No.
321
(φ3
.3)
(30.5)
29
30
35
34
33
32
31
(42)
(49)
Figure 7. Configuration of the DIP-IPM Terminals
Table 5. Description of the DIP-IPM Terminals
Description
Terminal Terminal
No.
Name
1
VUFS
U-phase P-Side drive supply GND terminal.
2
UPG
Dummy-pin
3
VUFB
U-phase P-Side drive supply terminal.
4
VP1
U-phase P-Side control supply terminal.
5
COM
Dummy-pin
6
UP
U-phase P-Side control input terminal.
7
VVFS
V-phase P-Side drive supply GND terminal.
8
VPG
Dummy-pin
9
VVFB
V-phase P-Side drive supply terminal.
10
VP1
V-phase P-Side control supply terminal.
11
COM
Dummy-pin
12
VP
V-phase P-Side control input terminal.
13
W WFS
W-phase P-Side drive supply GND terminal.
14
WPG
Dummy-pin
15
W WFB
W-phase P-Side drive supply terminal.
16
VP1
W-phase P-Side control supply terminal.
17
COM
Dummy-pin
18
WP
W-phase P-Side control input terminal.
19
UNG
Dummy-pin
20
VNO
NC
21
UN
U-phase N-Side control input terminal.
22
VN
V-phase N-Side control input terminal.
23
WN
W-phase N-Side control input terminal.
24
FO
Fault output terminal.
25
CFO
Fault output time setting terminal (connected to external capacitor).
26
CIN
Short-circuit trip voltage sensing terminal.
27
VNC
control GND terminal.
28
VN1
N-side control supply terminal.
29
VNG
Dummy-pin
30
WNG
Dummy-pin
31
P
Inverter DC-link positive terminal.
32
U
U-phase inverter output terminal.
33
V
V-phase inverter output terminal.
34
W
W-phase inverter output terminal.
35
N
Inverter DC-link negative (GND) terminal.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
3.4.2. Structure and Detailed Description of Input / Output Terminals
Table 6. Structure and Detailed Description of the DIP-IPM Input and Output Terminals
Item
Symbol
Description
P-side drive
VUFB-VUFS • These are drive supply terminals for the P-side IGBTs.
VVFB-VVFS • By virtue of the ability to use the boot-strap circuit scheme, no external
supply terminal
VWFB-VWFS power supplies are required for the DIP-IPM P-side IGBTs.
P-side drive
• Each boot-strap capacitor is generally charged from the N-side VD supply
during ON-state of the corresponding N-IGBT in the loop.
supply GND
• An abnormal operation may result if the VD supply is not aptly stabilized or
terminal
has insufficient loading capability. In order to prevent malfunction caused
by such unstability, or by noise and ripple in supply voltage, a smoothing
capacitor of favorable frequency and temperature characteristics should be
mounted very close to each pair of these terminals.
P-side control
VP1
• These are control supply terminals for the built-in ICs (LVIC & HVICs).
VN1
supply terminal
• VP1 and VN1 should be connected externally.
• In order to prevent malfunction caused by noise and ripple in the supply
voltage, a smoothing capacitor of favorable frequency characteristics
N-side control
should be mounted very close to these terminals.
supply terminal
• Careful design work is, however, necessary so that the voltage ripple
caused by noise or by system operation is kept below the maximum
specified values.
GND terminal
VNC
• This is control ground for the built-in ICs (LVIC & HVICs).
• Line current of the power circuit, however, should not be allowed to flow
through these terminals to avoid noise influences.
Control input
UP,VP,W P • Input terminals for controlling the DIP-IPM switching operation.
UN,VN,W N • Operate by voltage input signals. These terminals are internally connected
terminal
to Schmitt trigger circuit composed of 5V-class CMOS.
• Each signal line should be pulled up to plus side of the 5 V power supply
with approximately 4.7k9 resistance. (The value might change depending
on wiring patterns.)
• The wiring of each input should be as short as possible (less than 2 cm) to
protect the DIP-IPM against noise influences.
• To prevent signal oscillations, an RC coupling is reccomended.
Short-circuit trip CIN
• Current sensing resistance should be connected between this terminal and
voltage sensing
VNC to detect short-circuit situations (short-circuit voltage trip level). Input
terminal
impedance for CIN terminal is approximately 600k9.
• CR filter should be connected in order to eliminate noise.
Fault output
FO
• This is the terminal for fault output. Active low output is given from this
terminal
terminal indicating a faulty state of the DIP-IPM (SC and UV operation at
N-side).
• This output is open collecter type. FO signal line should be pulled up to the
5V power supply with approximately 5.1k9 resistance.
Fault pulse output CFO
• This is the terminal for setting the fault pulse output time.
time setting
• An external capacitor should be connected between this terminal andVNC to
set the fault pulse output time.
terminal
• A capacitor with the capacitance of 22nF is recommended (corresponding
to 1.8ms typical value of fault pulse output time).
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Item
Inverter positive
power supply
terminal
Description
• DC-link positive power supply terminal of the inverter.
• Internally connected to the collecters of the P-side IGBTs.
• In order to suppress surge voltage caused by DC-link wiring or PCB pattern
inductance, connect the smoothing capacitor very close to the P and N
terminals. It is also effective to add a small film capacitor of good frequency
characteristics.
Inverter GND
N
• DC-link negative power supply terminal (power ground) of the inverter.
Terminal
• This terminal is connected to the emitters of the N-side IGBTs.
Inverter power
U, V, W
• Inverter output terminals for connection to inverter load (e.g. AC motor).
output terminal
• Each terminal is internally connected to the intermidiate point of the
corresponding IGBT half bridge arm.
Note) The following pins are dummy pins and therefore should not be connected VNO, UPG, VPG, WPG,
COM, UNG, VNG, WNG.
P
Symbol
3.4.3. Description of Drive and Protection Functions
Table 7. Description of Drive and Protection Functions
Function
Symbol
Description
Normal drive —
• The drive logic is based on “active-low” input format.
• Off-level input signal (VCIN > Vth(off) ) drives IGBT off, and on-level input signal (VCIN
< Vth(on) ) drives IGBT on.
Short circuit
SC
• The external shunt resistance detects collector forward current of the DC-link.
protection
When the current exceeds a preset SC trip level, it is judged as a short circuit state,
and the N-side IGBTs are turned off immediately.
• A fault pulse signal is outputted from Fo terminal when this abnormal current flows
through the external shunt resistance and the pulse duration is determined by the
capacitance of the capacitor connected between CFO and VNC. After it is being
outputted continuounsly for a certain period of time (depends on the capacitor),
fault resetting takes place when the next input signal reaches the on-level.
Control circuit UVD
• An internal logic monitors the N-side control supply voltage. If the voltage falls
under voltage
below the UVD trip level for a given period of time, input signals to the N-side
IGBTs are blocked.
protection(UV)
• The state of control circuit under-voltage protection remains until the voltage
exceeds the UVDr reset level.
• UVD fault pulse signal output period is determined by the capacitance of the
external capacitor (CFO-VNC). After fault signal is being outputted for a certain
period of time (depends on the capacitor and the voltage level), the fault resetting
takes place at the next input signal if control supply voltage is over the reset level.
UVDB
• An internal logic monitors the P-side floating voltage supplies. If the voltage level
drops below the UVDB trip level for a given period of time, input signals for the Pside IGBTs concerned are not accepted.
• The state of control circuit under-voltage protection remains until the voltage
exceeds the UVDBr reset level.
• Fault signal is not outputted for the P-side UV state.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
3.5. Installation Guidelines (Flatness / Mounting Strength / Screw Type / Grease)
Fastening with excessive uneven stress when installing a module to a heat sink might cause devices to be
damaged or to be degraded because the silicon chips inside the module will be stressed. An example of
recommended fastening order is shown in Figure 8.
Temporary fastening
®‚
Permanent fastening
®‚
2
1
Figure 8. Recommended Fastening Order of Mounting Screws
* As a standard rule, set the temporary fastening torque to 20~30 % of the maximum rating.
Table 8. Mounting Torque and Heat Sink Flatness Specifications
Item
Condition
Mounting torque
Mounting screw : Reccomended 0.78 N·m
M3
Reccomended 8kg·cm
Heat sink flatness
—
<
Min.
0.59
6
-50
Typ.
0.78
8
—
Max.
0.98
10
+100
Unit
N·m
kg·cm
µm
B
DIP-IPM
Thickness gauge
Tightening torque is confirmed more than
0.98N·m (10kg·cm), and also confirmed it in
the worst flatness condition.
Heat-sink
@@@@@@@
Figure 9. Tightening torque test
DIP-IPM
{|
Measurement range
Surface applied grease
3mm
Base plate edge
DIP-IPM
{
|
Heat-sink
|
{
@@@@
Heat-sink flatness range
Heat-sink
Figure 10. Measurement Point of Heat Sink Flatness
Heat sink flatness is prescribed as seen in Figure 10.
For most effective heat-radiation it is necessary to enlarge, as much as possible, the contact area between
the module and the heat sink while minimizing the contact thermal resistance. Regarding the heat sink
flatness (warp/concavity and convexity) on the module installation surface (refer to Fig. 10). Also, the surface
finishing-treatment should be 12s or less.
Evenly apply 100µm~200µm of thermally-conductive grease over the contact surface between a module and
a heat sink. It is also useful for preventing the contact surface from being corroded. Further, use a grease
type of stable quality within the operating temperature range and have long endurance. Use a torque wrench
to fasten up to the specified recommended torque. Exceeding the Max. torque limit might cause the modules
to be damaged or to be degraded as the above-mentioned fastening with uneven stress. Pay attention not to
put any foreign matter onto the contact surface between a module and a heat sink.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Chapter 4 Applications
4.1. System Connection Diagram
CBW-
CBW+
CBU+
Protection
circuit ( UV)
CBV+
CBV-
Input signal Input signal
conditioning conditioning
Level shifter
C4
C3
Input signal
conditioning
Level shifter Level shifter
Protection
circuit (UV)
Drive circuit Drive circuit
Inrush current
limiter circuit
CBU-
High-side input (PWM)
(5V line)
Note 1,2)
C3: Tight tolerance, temp-compensated electrolytic type
(Note: The capacitance value depends on the PWM control scheme used in the
applied system.)
C4: 0.22<2mF R-category ceramic capacitor for noise filtering
Note 6)
Protection
circuit (UV)
DIP-IPM
Drive circuit
P
AC input
H-side IGBTs
U
Note 4)
V
W
C
M
AC line output
Z
N1
VNC
Z: Surge absorber.
C: AC filter (Ceramic capacitor 2.2<6.5nF)
(Protection against common-mode noise)
N
L-side IGBTs
CIN
Drive circuit
Input signal conditioning
(((((((((
Low-side
input (PWM)
(5V line) Note 1,2)
Fo logic
SC protection
Control supply
under-voltage
protection
Fo CFO
Fo output (5V line)
Note 3,5)
VNC
VD
(15V line)
Figure 11. System Block Diagram of the DIP-IPM
Note 1) To prevent the input signals oscillation, an RC coupling at each input is recommended.
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to
CPU terminals without any opto-coupler or transformer isolation is possible.
Note 3) This output is open collector type. The signal line should be pulled up to the positive side of the
5V power supply with approximately 5.1kW resistance.
Note 4) The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as
possible to protect the DIP-IPM against catastrophic high surge voltage. For extra precaution, a
small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be
mounted close to these P and N1 DC power input terminals.
Note 5) Fo output pulse width (tFO) should be decided by connecting external capacitor between CFO
and VNC terminals. (Example : CFO = 22nF ® tFO = 1.8ms (Typ.)).
Note 6) High voltage diodes (600V or more) should be used for the bootstrap circuit.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.2. Input circuit
Structure of Control Input Terminals and Application Examples
5V
Pull-up Resistor R1
(
D I P- I PM
A
*
Vreg(6.2Vtyp.)
RCIN
)
CPU
Rreg=57k¶(typ.)
ICIN
Input wiring
+
CCIN
RIN=1k¶(typ.)
Drive circuit
UP,VP,WP,UN,VN,WN
VNC(GND)
Figure12. Structure of DIP-IPM Control Input Terminals
The structure of the DIP-IPM control input terminals is described in Fig.12, and Input currentThreshold
voltage ratings is in table 9.
Table9. Input current·Threshold voltage ratings (VD=15V, Tj=25°C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
1. L level input current
ICINL
UP, VP, W P terminals (VCIN=0V)
-150
-100
-50
mA
(Turn on signal)
UN, VN, W N terminals (VCIN=0V)
-200
-100
-50
mA
2. H level input current
ICINH
UP, VP, W P terminals (VCIN=5V)
-50
-20
-7
mA
(Turn off signal)
UN, VN, W N terminals (VCIN=5V)
-50
-20
-7
mA
3. Turn-on threshold voltage Vth(on) UP, VP, W P-VPC terminals
0.8
1.4
2.0
V
4. Turn-off threshold voltage Vth(off)
2.5
3.0
4.0
5. Turn-on threshold voltage Vth(on) UN, VN, W N-VNC terminals
0.8
1.4
2.0
V
6. Turn-off threshold voltage Vth(off)
2.5
3.0
4.0
* : DIP-IPM is driven by L level signal.
Input On signal (CPU output L level)
The current of R,Sflow to a CPU from DIP-IPM inside power supply Vreg and the input 5V power supply. The value of
current R is on Table 9 item1, and current S are decided with input pull-up resistance. (I CINL)
For instance, when input pull-up resistance R1 is 4.7k W, the total current of R and S become below;
200´10-6 (Min.)+5/4.7´10-3=1.26mA.
Please pay attention so that the voltage level (the potential of the A point) at the time of CPU low level output is not over
Min. in Table 9 item 3,5. (Vth(on) min.) Also, in the case that the input wiring (the thick line) is long, wiring impedance is
not able to disregard so make the input wiring of short as much as possible.
Input Off signal (CPU output H level)
The current of Q flows to 5V power supply from DIP-IPM inside power supply Vreg. The current of Q is the value on
Table 9 item2. (I CINH)
For instance, when input pull-up resistance R1 is 4.7kW, the potential of an A point is 5+[1.2´ (R1)/(R1+R2+R3)]=5.09V.
The maximum ratings of input voltage is 5.5V(Max.), please set R1 to less than 4.7kW. The input part of DIP-IPM is high
impedance due to CMOS structure. Accordingly, the impedance of a signal line needs to make it low , noise is hardly
imposed on line. We recommend to set the value of R1 as small as possible, because the impedance of a signal line is
decided with the value of R1.
It is effective to insert a RC filter into a signal line for a noise measure. Please insert a RC filter near DIP-IPM.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Input Voltage
The structure of the DIP-IPM control input terminals is described in Figure 13. FO output and input signals of
the DIP-IPM should be 5V-class interface, in order to interface directly with CPU. Signal input terminals are
internally connected to 5V-class Schmitt trigger circuits. Therefore, if an opto-coupler is used, its supply
voltage should be 5V. Maximum ratings for input and FO output voltages are shown in the following table.
As FO is open collector type and its rating is VD+0.5, 15V-class supply is possible. However, 5V-class supply
is recommended for Fo output same as the input signals.
Table 10. Maximum Ratings for Input Voltage and Fault Output Voltage ( Tj=25°C, unless otherwise noted)
Item
Symbol
Input voltage
VCIN
Fault output supply voltage
VFO
Condition
Applied between UP,VP,W PVNC, UN,VN,W N-VNC
Applied between Fo-VNC
L level input current
ICINL
+
15V
A
Unit
-0.5~+5.5
V
-0.5~VD+0.5
V
H level input current
VP1 ,VN1
UP ,VP ,WP ,
UN ,VN ,WN
Ratings
ICINH
15V
A
5V
VNC
+
VP1 ,VN1
UP ,VP ,WP ,
UN ,VN ,WN
VNC
Figure 13. Diagram of Input Current Measurement Circuit
Minimized input pulse width
Table11. Minimized input pulse width Ratings
Item
Minimized input pulse width
Min.
300
Ratings
Typ.
-
Max.
Unit ; ns
* : Control IC of DIP-IPM disregards input signals whose pulse width is less than 300ns. and also does not
make malfunction by such pulse.
Mar. 2001
13
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.3. Mono Drive-Voltage-Supply Scheme
4.3.1. Initial Charging
:
Charging current loop
P(VCC)
Bootstrap capacitor
+
HVIC
VDB
High voltage fast
recovery diode
LVIC
VD
P-side IGBT
U,V,W
N-side IGBT
VCIN(n)
N(GND)
Bootstrap circuit
VCC
PWM Start
0V
VD
VDB
0V
0V
VCIN(n)
on
Timing chart of bootstrap operation
Figure 14. Charging Current Loop and Timing Chart of Bootstrap Circuit
Charging
In order for the DIP-IPM to start, initial bootstrap charging signals are required. By turning on the N-side
IGBT, as shown in Figure 14, the bootstrap capacitor should be charged. Enough pulse width to fully
charge the bootstrap capacitor should be applied.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.3.2. Charging and Discharging of the Bootstrap Capacitor During Inverter Operation
High-side IC
R1
D1
VB
P
C1
ID
IGBT1
M1
R2
Q1
VCC
FWDi1
VS
M
IGBT2
FWDi2
N
VCE(sat) of IGBT2 is Vsat2, VEC of FWDi2 is VEC2, and VF of D1 is V F1.
Figure 15. Illustrative Inverter Circuit Diagram
(1) Charging Timing Chart of Bootstrap Capacitor (C1)
Case 1-1 : IGBT2 ON (Figure 16)
When IGBT2 is in the ON state, charging voltage at C1 (VC1) is calculated by the equations :
VC1(1) = VCC–VF1–Vsat2–ID·R2 (Transient state)
VC1(1) = VCC (Steady state)
Following this, IGBT2 is turned OFF. While both arms are OFF (the dead time of IGBT1 and IGBT2),
regenerative mode conducted by FWDi1 generally starts. As the electric potential of VS rises close to that
of P, C1 is not charged.
When IGBT1 is turned ON, the voltage at C1 gradually declines from the potential VC1(1) due to the current
consumed by drive circuit.
OFF
IGBT1
ON
OFF
IGBT2
Spontaneous discharge of C1
ON
Declining due to current
consumed by drive circuit
VC1
Potential of C1
VC1(1)
VS
Figure 16. Timing Chart for Case 1-1
Mar. 2001
15
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Case 1-2 : IGBT2 OFF and FWDi2 ON (Figure 17)
When IGBT2 is OFF and FWDi2 is ON, the supply voltage across C1 (VC1) is calculated by the equation:
VC1(2)=VCC–VF1+VEC2
While both IGBT2 and IGBT1 are OFF, regenerative mode conducted by FWDi2 is maintained. Thus the
potential of VS drops to -VEC2, C1 is charged to restore the declined potential and its voltage starts to rise.
Then, when IGBT1 is turned ON, the potential of VS rises to that of P, hence charging stops and the
voltage across C1 gradually declines from the potential V C1(2) due to the current consumed by the drive
circuit.
OFF
IGBT1
ON
OFF
IGBT2
ON
VC1
VC1(2)
Potential of C1
Declining due to current
consumed by drive circuit
VS
Figure 17. Timing Chart for Case 1-2
(2)
Guidelines for Selecting the Bootstrap Capacitor (C1) and Resistance (R2)
The capacitance of bootstrap capacitor can be selected by this equation:
C1=IBS×T1/DV
where T1 is the maximum ON pulse width of IGBT1 and IBS is the drive current of the IC (depends on
temperature and frequency characteristics), and DV is the allowable discharge voltage. Additional margin
value should also be added to the calculated capacitance.
Resistance R2 should be basically selected such that the time constant C1·R2 will enable the discharged
voltage (DV) being charged again into C1 within the minimum ON pulse width (T2) of IGBT2.
However, if only IGBT1 has an ON–OFF–ON control mode (Figure 18), the time constant should be set so
that the consumed charge during the ON period can be charged during the OFF period.
OFF
IGBT1
ON
OFF
Declining due to curren
consumed by drive circuit
IGBT2
ON
Vc1
Potential of C1
Charging area
VS
Figure 18. Timing Chart of ON–OFF–ON Control Mode
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Setting example Bootstrap circuit
Selecting bootstrap capacitor
Condition: DVDB(discharge voltage by drive circuit)=1V, The maximum ON pulse width T1 of Upper-side IGBT is
5ms, IDB is 1mA(Max. rating).
C=IDB×T1/DVDB=5.0×10-6
The calculated value of bootstrap capacitor is 5mF.
Taking consideration on dispersion and reliability, it is general that the capacitance is selected in 2~3 times of
calculated capacitance.
Selecting bootstrap resistor
Condition: The value of bootstrap capacitor is 5mF, VD=15V, VDB=14V. If the minimum ON pulse width t0 of
Lower-side IGBT or the minimum OFF pulse width t0 of Lower-side IGBT is 20ms, bootstrap capacitor needed to
be charged
DVDB=1V for this term.
R={(VD–VDB) ×t0}/(C×DVDB)=4
The bootstrap resistor is selected 4W.
In the case of the control for DCBLM or 2 phase modulation for IM, long ON term on Upper-side IGBT should be
occurred, therefore please design it with paying attention about this.
This setting example is only calculation, so you should be design with taking into consideration your control
pattern and lifetime of components.
Selecting bootstrap diode
The bootstrap diode whose endurance voltage is more than 600V is selected. In DIP-IPM, supply voltage(Vcc)
is 450V guaranteed, so it is added 500V included surge voltage. therefore we recommend endurance voltage is
more than 600V as considering margin. and also characteristics is high speed recovery type (recovery time is
less than 100ns recommended).
Noise filter of control supply
We recommend noise filters which is film capacitor or ceramic capacitor 0.22~2mF is inserted to control supply
terminal(VP1–VNC,VN1–VNC,VUFB–VUFS,VVFB–VVFS,VWFB–VWFS). Noise filter capacitor is selected smaller one by
reducing supply wiring impedance. The supply circuit should be designed such that the noise fluctuation is
softer than ±1V/ms, and the ripple voltage is less than 2V.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
(3) Current characteristics of P-side floating supply (V*- V5) are described in Fig.19 to 21 (typical for PS21352-G):
Conditions. V,=V,*= 15V, Tj =–20, 25, 125°C, DUTY = 10, 30, 50, 70, 90%, fc = 3, 7, 15kHz
Carrier frequency vs. Circuit current characteristics
Circuit current (µA)
1000
DUTY=10%
DUTY=30%
DUTY=50%
DUTY=70%
DUTY=90%
900
800
700
600
500
1
10
100
Carrier frequency(kHz)
Figure 19. Characteristics under the Condition of Tj=–20°C (typical for PS21352-G)
Circuit current (µA)
Carrier frequency vs. Circuit current characteristics
900
DUTY=10%
DUTY=30%
DUTY=50%
DUTY=70%
DUTY=90%
800
700
600
500
1
10
Carrier frequency(kHz)
100
Figure 20. Characteristics under the Condition of Tj=25°C (typical for PS21352-G)
Circuit current (µA)
Carrier frequency vs. Circuit current characteristics
700
DUTY=10%
DUTY=30%
DUTY=50%
DUTY=70%
DUTY=90%
600
500
400
300
1
10
100
Carrier frequency(kHz)
Figure 21. Characteristics under the Condition of Tj=125°C (typical for PS21352-G)
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Table 12. Example of the Circuit Current Value for Each Parameter (typical for PS21352–G; Unit:µA)
DUTY(%)
Tj(°C)
Carrier Frequency
10
30
50
70
90
fc(kHz)
–20
3
572
596
620
642
666
7
653
676
699
722
745
15
811
835
859
882
905
25
3
501
519
536
554
571
7
585
599
618
635
653
15
745
763
780
798
814
125
3
388
400
410
419
432
7
472
484
494
504
515
15
638
649
659
670
682
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.4. Interface Circuit Examples and Guidelines
4.4.1. Direct Input (without Opto-Coupler) Interface Example
Figure 22 shows a typical application circuit interface example, when signals are inputted directly from a microcomputer.
C1.Electrolytic capacitor of good temperature characteristics
C2,C3.0.22<2ÊF R-category ceramic capacitor for noise filtering
5V line
C2
VUFB
C1
VUFS
VP1
C3
UP
C2
VVFB
C1
VVFS
VP1
C3
VP
C2
VWFB
C1
Controller
P
VCC
VB
IN
HO
COM
VS
VCC
VB
IN
HO
COM
VS
VCC
VB
IN
HO
U
V
M
VWFS
VP1
C3
DIP-IPM
WP
COM
W
VS
+
-
UOUT
VN1
C3
VCC
5V line
VOUT
UN
VN
WN
Fo
VNC
UN
VN
WN
Fo
GND
WOUT
If this wiring is too long, it
might cause short circuit.
VNO
CIN
N
CFO
C
CFO
15V line
C4(CFO)
A
CIN
B
R1
C5
Long wiring of GND might generate noise If this wiring is too long, SC level
on input signals and cause the IGBT drive fluctuation might be large and cause
to malfunction.
SC malfunction.
Shunt
Resistor
N1
Figure 22. Typical Application Circuit Interface Example with Direct Input (without Opto-Coupler).
Note 1) To prevent the input signals oscillation, an RC coupling at each input is recommended, and the
wiring of each input should be as short as possible. (Less than 2cm)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU
terminals without any opto-coupler or transformer isolation is possible.
Note 3) Fo output is open collector type. This signal line should be pulled up to the positive side of the 5V
power supply with approximately 5.1kW resistance.
Note 4) Fo output pulse width should be decided by connecting an external capacitor between CFO and Vnc
terminals (CFO). (Example : CFO=22nF®tFO=1.8ms(Typ.))
Note 5) Each input signal line should be pulled up to the 5V power supply with approximately 4.7kW
resistance (other RC coupling circuits at each input may be needed depending on the PWM control
scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a
0.22~2µF by-pass capacitor should be used across each power supply connection terminal.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Note 6) To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
Note 7) In the recommended protection circuit, please select the R1C5 time constant in the range 1.5~2µs.
SC intercept time might change depending on the wiring patterns.
Note 8) Each capacitor should be put as nearby the terminals of the DIP-IPM as possible.
Note 9) To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals
should be as short as possible. Approximately a 0.1~0.22µF snubber between the P&N1 terminals
is recommended.
4.4.2. Interface Example when a Fast Opto-Coupler is used
Figure 23 shows a typical application circuit interface example, when a fast opto-coupler is used.
VUFB
DIP-IPM
VUFS
C1 C2
VP1
C3
DC 5V
UP
DC 5V
VVFB
HVIC1
VCC
VB
IIN
HO
COM
VS
VVFS
C1 C2
C3
VP1
VP
VWFB
CONTROLLER
C3
VP1
WP
U
HVIC2
VCC
VB
IN
HO
COM
VS
VWFS
C1 C2
P
V
M
{
|
HVIC3
VCC
VB
IN
HO
COM
VS
W
LVIC
UOUT
VN1
VCC
C3
VOUT
UN
VN
WN
Fo
VNC
UN
VN
WN
Fo
GND
WOUT
VNO
CIN
N
CFO
CFO
CIN
Control Power Supply
DC 15V
C4
R1
C5
Shunt Resistor
N1
Figure 23. Typical Application Circuit Interface Example when a Fast Opto-coupler is used.
Note: 5V should be applied to the secondary side of the opto-coupler. The 5V supply line should be referenced to
the same ground as the 15V supply line (VNC). For other precautions, please refer to the data sheets.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.4.3. Interface Example when a Slow Opto-Coupler is used
Figure 24 shows a typical application circuit interface example, when a slow opto-coupler is used.
VUFB
DIP-IPM
VUFS
C1 C2
VP1
C3
DC 5V
UP
DC 5V
VVFB
HVIC1
VCC
VB
IN
HO
COM
VS
VVFS
C1 C2
C3
VP1
VP
VWFB
CONTROLLER
C3
VP1
WP
U
HVIC2
VCC
VB
IN
HO
COM
VS
VWFS
C1 C2
P
V
M
{
|
HVIC3
VCC
VB
IN
HO
COM
VS
W
LVIC
UOUT
VN1
VCC
C3
VOUT
UN
VN
WN
FO
VNC
UN
VN
WN
FO
GND
WOUT
VNO
CIN
N
CFO
CFO
CIN
Control Power Supply
DC 15V
C4
R1
C5
Shunt Resistor
N1
Figure 24. Typical Application Circuit Interface Example when a Slow Opto-coupler is used.
Note
• Wiring between opto-coupler and DIP-IPM terminals should be as short as possible and a pattern layout
that suppresses stray capascitance should be adopted.
• Slow opto-coupler with the capacity of CTR 100~200% should be used. The input current should be set
to 8~10mA in order to achieve active region operation.
• Transient voltage change should be as small as possible by mouting capacitors of low impedence
characteristics, etc. close to each control supply terminal.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.4.4. Snubber circuit
There are Q and R as insertion point of snubber capacitor shown in figure 25.
Snubber capacitor is needed to install in a position of R in order to reduce surge voltage in the maximum,
but charging and discharging current (wiring inductance and resonance current of snubber capacitor)
flows in shunt resistance through snubber capacitor. When wiring inductance is large, there is the case
that short circuit protection might be worked with this charging and discharging current.
When putting a snubber capacitor in outside of shunt resistance (position of Q), wiring of A is as short as
possible and please examine that it is installed just like S.
DIP-IPM
Wiring Inductance
P
{
)
(
*
|
N
A
Figure 25. Snubber Circuit
4.4.5. Parallel Connection
Figure 26 shows the circuit of parallel connected two DIP-IPMs.
Gate charging of Lower-arm IGBT is routeQ in DIP-IPM No.1, routeR in DIP-IPM No.2. When this route is
long, gate voltage is not enough to be added by wiring impedance which gives annoying effect to switching
action. (Charging of bootstrap capacitor of upper arm is the similar, too.) Noise can be easily imposed on
wiring impedance. If there are many numbers of DIP-IPM parallel connected, GND pattern becomes long
and the influence to the another circuit(power supply, protection circuit etc.) by the fluctuation of GND
potential is conceivable, therefore parallel connection is not recommended.
DIP-IPM No.1
VP1
P
VP1
DC15V
VP1
U,V,W
M
AC100/200V
VN1
N
VNC
Shunt resistor
(
DIP-IPM No.2
VP1
VP1
P
VP1
U,V,W
VN1
VNC
N
M
Shunt resistor
)
Figure 26. Parallel Connection
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.5. Short Circuit Protective Function
4.5.1. Timing Charts of Short Circuit Protection (Figure 27)
A. Short-Circuit protection (Lower-arms only) : Protection by external shunt resistor and CR time constant circuit
a1. Normal operation: IGBT ON and carrying current
a2. Short circuit current detection (SC trigger). The optimum setting for the CR circuit time constant is 1.5~2.0µs.
a3. Hard IGBT gate interrupt
a4. IGBT turns OFF
a5. Fo timer operation starts: The pulse width of the Fo signal is set by the external capacitor CFO.
a6. Input “H”= IGBT OFF state
a7. Input “L”= IGBT ON state
a8. IGBT OFF state
N-side control input
a6
Protection circuit state
a7
SET
Internal IGBT gate
RESET
a3
a2
SC
a4
a1
Output current Ic(A)
a8
SC reference voltage
Sense voltage of the
Shunt resistance
CR circuit time constant DELAY
Error output Fo
a5
Figure 27. Timing Chart of SC Operation
* If the protection is reset at LOW state (active) of N-side control input, IGBT is turned ON at the next
HIGH-to-LOW input signal.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.5.2. Selecting the Current Sensing Shunt Resistor Value
Short-circuit Protection
Figure 28 shows the example of external SC protection circuit. When the line current on N-side DC-link is
detected, protective operation starts through the RC filter. If the current exceeds the SC reference voltage, all
the gates of the N-side three-phase IGBTs are interrupted and the fault signal is outputted. As short–circuit
protection is non-repetitive, operation should be stopped immediately after the fault output.
DIP-IPM
Ic(A)
Drive circuit
P
H-side IGBTs
SC protection level
U
V
W
L-side IGBTs
SC Protection External Parts
N1
External shunt resistance A
Note1)
C
N
VNC
R
B
C
Collector current
waveform
Drive circuit
0
CIN
Note2)
SC protection
2
tw(Ês)
Figure 28. Example of External Protection Circuit
Setting of RC Time Constant
When the RC filter circuit is connected, SC protection malfunction caused by noise on shunt resistor can be
prevented. Moreover, the RC filter circuit immediately interrupts short-circuit currents due to its
characteristics (shown in Figure 28). It also allows the conduction of the FWDi reverse recovery current. In
order to set the time constant, the IGBT ability (shown in Figure 30) should be considered. Figure 30 shows
example of an IGBT with Min. ON threshold voltage value (thus having high saturation current). For example,
when the drive-voltage is the Max. 16.5V of the recommended range, 8.5 times of the rating collector current
(maximum current at VD=16.5V) conduct under the above conditions. In this case, if the ON period of the
IGBT (pulse width) is less than 4ms, it indicates that the IGBT has the ability to safely turn off. As for the
DIP-IPM, the recommended RC time constant is 2ms or less in consideration of margins.
Note : In order to avoid SC protection malfunction caused by wiring inductance influences, wiring between A,
B, and C should be as short as possible.
The DIP-IPM short circuit protection accepts the voltage value across the external current sensing
resistance into the control IC as SC trip level (reference voltage) and operates by internally interrupting the
output. The scheme for setting the value of external current sensing resistance is shownbelow :
Selecting shunt resistance
The current sensing resistance value is calculated using this expression :
Current sensing resistance value R= VSC(ref)/SC
where VSC(ref) is the SC reference voltage (trip level) of the control IC.
SC trip level Max value need to be set to below the Min value of IGBT saturation current which is 1.7 times
of rating current.
Calculation example for PS21352-G when SC trip level is set to 8.5A:
Table13 shows the dispersion of SC reference voltage.
Table13 Specification for VSC(ref) (Unit:[V])
Specification for ALL Conditions
including Temperature variations
Min
Typ
Max
0.42
0.50
0.57
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Shunt resistance is also dispersion, in order to consider it, SC trip level shows below;
SCmax.= VSC(ref)max./Shunt resistance value min.···Q
SCtyp.= VSC(ref)typ./ Shunt resistance value typ.
SCmin.= VSC(ref)min./ Shunt resistance value max.
When shunt resistance dispersion is ±5%, operative of SC level is table 14.
Table14. Operative of SC level Unit:A(Shunt resistance value min.67mW, typ.70mW, max.73mW)
min.
typ.
max.
Operative of SC level for ALL Conditions
5.8
7.1
8.5
including Temperature variations
There are situations when resonant signals caused by parasitic inductance and parasitic capacity falsely
start the short –circuit protection. In that case, appropriate filter circuit would be necessary. Finally, the
sensing resistance value should be evaluated on the actual design.
4.5.3. Filter Circuit Setting (RC Time Constant) for Short-circuit Operation
When the RC filter circuit is connected, SC protection malfunction caused by noise on shunt resistance can be
prevented. Moreover, the RC filter circuit immediately interrupts short-circuit currents due to its characteristics
(shown in Figure 28). It also allows the conduction of the FWDi reverse recovery current. In order to set the
time constant, the IGBT ability (shown in Figure 30) should be considered.
Time t1 that the voltage is added to a CIN terminal through a RC filter, after the voltage that exceeds SC level
to shunt resistance occurred is calculated using this expression:
V=R · I · (1-e-t1/ J)
t1=- t · ln(1-(V/R · I))
V : SC reference voltage VSC(ref)
R : Shunt resistance
I : Peak current
t : RC time constant
t1 : interrupt time
Time t2 (the delay time inside IC) when the gate of IGBT is interrupted after voltage being input to a CIN
terminal s is shown in Table 15.
Table15. SC circuit delay time
Item
min
typ
max
Unit
SC interrupted time
0.3
0.5
1.0
ms
Time tTOTAL when the gate of IGBT is interrupted after the voltage that exceeds SC level to shunt resistance
occurred is calculated using this expression:
tTOTAL=t1+t2
Example)
In the case that the maximum value of a SC level is set up to 1.7 times (8.5A) of a rating current in
PS21352-G, from expressionQ shunt resistance consists with 67mW. At this time, the interrupted time
characteristic of in the case that RC time constant set to 2ms is shown in Figure 29.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Interrupted Time Characteristics(RC Time Constnt)
30.0
Ic(Short circuit current)-Pulse width characteristics
80
25.0
VD=18V
Saturation current max value(VD=16.5V)
20.0
VD=16.5V
VD=15V
60
15.0
Ic(peak)(A)
Peak CurrentiAj
70
10.0
SC operation range of 4th gen. IGBT
50
40
30
Saturation current max value(V D=16.5V)
20
5.0
10
0.0
0
5
10
15
Interrupted TimeiÊsj
20
0
25
Figure 29. Interrupted time characteristics
SC operation range of 3rd gen. IGBT
0
1
2
3
4
Pulse width(Ês)
5
6
7
.ECKHA30. SC-SOA (PS21312&PS21352-G)
Figure.30 shows short-circuit conduction capability of the IGBTs incorporated into the DIP-IPM (Example of
PS21352-G). It shows example of an IGBT with Min. ON threshold voltage value (thus having high saturation
current). In this case, if the ON period of the IGBT (pulse width) is less than 4.5ms, it indicates that the IGBT
has the ability to safely turn off.
Conditions: VCC=400V, Tj=125°C (initially), non-repetitive, VCES £ 600V, VCC(surge)=500V (including surge
voltage), 2m load short-circuit.
From Figure.30, the thermal capability of IGBT on PS21352-G is 0.122J (Vcc´Ic (peak) ´pulse width),
therefore action at slanted line part in Figure.30 is in an enough Short circuit SOA curve and it has no problem.
The wiring of Protection circuit guidelines
Drive circuit
H-side IGBTs
DIP-IPM
P
U
V
W
SC protection External Parts
DC-bus current route
L-side IGBTs
B
N
Drive circuit
A
C
R2
CIN
C1
Shunt resistance
SC protection
VNC
D
N1
Figure 31. External protection circuit
Influence of an A part wiring pattern
The ground of L-side IGBT is VNC. If A part wiring pattern in figure 31 is long, voltage fluctuation is occur by A
part wiring inductance, and Emitter electric potential of IGBT change in switching of IGBT, and it is an anomaly
working factor.
Please install shunt resistance in a N terminal as nearly as possible.
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Influence of a B part wiring pattern
B part wiring gives influence to a short circuit protection level. Short circuit protection works by voltage to occur
between CIN-VNC(typ,0.5V). If B part wiring is long, by surge voltage to occur by this wiring inductance, a short
circuit
protection level deteriorates. CIN and VNC don't include B part wiring, and please be connected to both ends
of shunt resistance.
Influence of a C part wiring pattern
C1R2 filter is connected for removing noise occurring in shunt resistance, but filter effect becomes small and is
easy to come to receive induction noise in order to if C part wiring is long. Please install a C1R2 filter near CIN,
VNC terminal.
Influence of a D wiring pattern
D wiring pattern gives influence all the item to 2-1~3. GND wiring should be as short as possible.
4.5.4. SOA of the DIP-IPM (For short-circuit switching)
· SOA of the DIP-IPM is described below. (It is not recommended to operate the DIP-IPM under these conditions.)
VCES : MAX rating of IGBT collector-emitter voltage inside DIP-IPM
VCC : P-N supply voltage
VCC(surge) : Calculated by adding to VCC the surge voltage, which is generated by the wiring inductance
between the DIP-IPM and the DC-link capacitor.
VCC(PROT) : Indicates the P-N supply voltage value up to which the DIP-IPM can protect itself.
Collector current Ic
VCE=0C IC=0
£ VCES
£ VCES
£ VCC(PROT)
£ VCC(PROT)
Short-circuit current
VCE=0C IC=0
Figure 32. SOA for Switching and Short-circuit
£ 2Ês
Turn-off switching
VCES represents the 600V voltage rating of the IGBTs incorporated into the DIP-IPM. Subtracting the
surge voltage (100V or less), generated by wiring inductance inside the DIP-IPM, from VCES is VCC(surge),
that is, 500V. Moreover, subtracting from VCC(surge) the surge voltage (50V or less) generated by the wiring
inductance between the DIP-IPM and the DC-link capacitor is VCC, that is, 450V.
For short-circuit operation
VCES represents the 600V voltage rating of the IGBTs incorporated into the DIP-IPM. Subtracting the
surge voltage (100V or less) generated by wiring inductance inside the DIP-IPM from VCES is VCC(surge), that
is, 500V. Moreover, subtracting from VCC(surge) the surge voltage (100V or less) generated by the wiring
inductance between the DIP-IPM and the electrolytic capacitor is VCC, that is, 400V.
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.5.5. Series of Short Circuit protection
When Short Circuit protection works and repeated protection®re-start®protection®re-start, it influences
life expectancy of device so that a temperature change of IGBT (DTj) occurs repeatedly.
Figure 33 shows Power Cycle curve.
Short circuit protection of DIP-IPM protects DIP-IPM oneself for short circuit status of non-repetition.
Accordingly you should stop with control signal and action when there was Fo output.
10000000
1%
10%
0.1%
Number of Cycles
1000000
100000
10000
1000
((
10
100
Junction Temperature DifferencecTj(Ž)1
1000
Figure 33. Power Cycle
It was the data which it measured by 3 points of DTj=46, 88, 98°C and expressed each failure rate 0.1, 1,
10% in regression line.
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.5.6. Fo Circuit
5V
DIP-IPM
R4
Protection
signal circuit
Fo terminal
((((
Figure 34. Fo circuit
Table16. Maximum Ratings
Item
Symbol
Condition
Fault output supply voltage
VFO
Applied between Fo-VNC
Fault output current
IFO
Sink current of Fo terminal
Table17. Electrical characteristics
Item
Symbol
VFOH
Fault output voltage
VFOL
VFOsat
Ratings
-0.5~VD+0.5
15
Condition
VSC=0VCFo=10kW 5V@
pull-upped
VSC=1VCFo=10kW 5V@
pull-upped
VSC=1VCIFO=15mA
Min.
4.9
–
0.8
Unit
V
mA
Typ.
–
0.8
1.2
Max.
–
1.2
1.8
Unit
V
V
V
Figure 34. shows internal Fo circuit. Fo output is open collector type. This signal line should be pulled up to
the positive side of the 5V or 15V power supply. Please set pull-up resistor satisfied above ratings.
Figure 35. shows V-I characteristics of Fo terminal.
1.2
1
VFO(V)
0.8
0.6
0.4
0.2
0
0
5
10
IFO(mA)
15
20
Figure 35. V-I characteristics of Fo terminal.
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.6. Guidelines for Control Supply
4.6.1. Timing Charts of Under-Voltage Protection (Figure 36,37)
B. Under-Voltage Protection (N-side, VD)
b1. Normal operation : IGBT ON and carrying current
b2. Under-voltage trip (UVDt)
b3. IGBT turns OFF inspite of control input condition.
b4. Fo timer operation starts
b5. Under-voltage reset (UVDr)
b6. Normal operation : IGBT ON and carrying current
Control input
Protection circuit state
SET
Control supply voltage V D
UV Dr
RESET
b5
UV Dt
b2
b1
b3
b6
Output current Ic(A)
b4
Error output Fo
Figure 36. Timing Chart for N-side UV Operation
C. Under-Voltage Protection (P-side, VDB)
c1. Control supply voltage rises : After the voltage level reaches UVDBr, the circuits start to operate when the
next input is applied.
c2. Normal operation : IGBT ON and carrying current
c3. Under-voltage trip (UVDBt)
c4. IGBT OFF inspite of control input condition, but there is no Fo signal output.
c5. Under-voltage reset (UVDBr)
c6. Normal operation : IGBT ON and carrying current
Control input
Protection circuit state
RESET
UVDB r
Control supply voltage VDB
c1
RESET
SET
UVDB t
c2
c5
c3
c4
c6
Output current Ic(A)
High-level output (no fault output)
Error output Fo
Figure 37. Timing Chart for P-side UV Operation
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.6.2. Control Supply Starting up and Shutting Down Sequence
Control supply VD should be started up prior to the main supply (P-N supply).
Control supply VD should be shut down after the main supply (P-N supply).
5V-class power supply for input pull-up is required for the DIP-IPM, which is driven by 5V input. This 5Vclass power supply should be started up when the control supply VD reaches the reset level of undervoltage protection (UVDr).
If the main supply had been started up before the control supply becomes stable, or if the main supply
remains after control supply was shut down, external noise might cause the DIP-IPM to malfunction.
Control supply starting up
UVDr
Control supply VD
5V Power supply
Input off threshold voltage Vth(off)
Control supply shutting down
UVDt
Control supply VD
5V Power supply
Input on threshold voltage Vth(on)
Figure 38. Timing chart of Control Supply Sequence
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.6.3. Other Guidelines
DIP-IPM state in each range of control supply voltage
The voltage range including ripples should meet the specification.
Table 18. DIP-IPM State in Each Range of Control Supply Voltage
Range of control supply
State
voltage(VD, VDB)
It is almost same as no power supply.
0~4.0
External noise may cause the DIP-IPM to malfunction (turns ON).
Supply under-voltage protection is not operated and no Fo signals
are outputted.
Even if control input signals are applied, switching operation
4.0~12.5
remains stopped.
Supply under-voltage protection starts operation and outputs Fo
signals.
Switching operation starts. This range of control supply voltage,
12.5~13.5
however, is below the recommended one. Thus, both VCE(sat) and
switching time become against the DIP-IPM specification values, it
might cause collector dissipation increase and junction temperature
rise.
13.5~16.5
Normal operation starts. This range is recommended.
Switching operation starts. This range, however, is over the
16.5~20.0
recommended one. Thus, too fast switching time might cause the
chips to be damaged, because they fall short of capabilities for
short-circuit operation.
20.0~
The control circuit of the DIP-IPM might be damaged.
Note) UV fault signals are outputted for VD supply only.
Specifications for Ripple Noise
High frequency noise is super imposed on the control IC supply line, IC malfunction might be caused
and fault signals might be outputted. Finally IC might stop (interrupt gates). To avoid such a malfunction,
the supply circuit should be designed such that the noise fluctuation is softer than ±1V/ms, and the ripple
voltage is less than 2 V.
Specification : dV/dt £ ±1V/ms, Vripple £ 2Vp-p
UV filter
When control supply voltage fell down , and IGBT does OFF which is not concerned with input signal.
However for about 10msec intervals input signals are communicated after control supply voltage fell to
UV trip voltage (UVDBt, UVDt) because it is built-in a filter about 10msec (standard value).
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.7. Power Loss and Heat Dissipation Design
4.7.1. Power Loss Calculation (Example)
Simple expressions for calculating average power loss
¨ Scope
In preparation for applying the DIP-IPM in VVVF inverter, it is possible to calculate overall loss in
normal operation in order to select (or compare) power modules. This calculation, however, cannot be
applied to thermal design under extreme conditions.
¨
Assumptions
 Sine waveform current output PWM control VVVF inverter
‚ PWM signals generated by the comparison of sine waveform and triangular waveform.
ƒ Duty amplitude of PWM signals varies within the range:
1- D 1+ D
(%/100)
~
2
2
„ Output current is given by Icp · sinx and it does not have ripple.
Load power factor for output current is cosq, while ideal inductive load is assumed for switching.
† IGBT saturation voltage VCE(sat) is in proportion to the collector current Ic.
‡ Forward voltage drop of free-wheeling diode VEC is in proportion to the forward current I EC.
ˆ Switching losses PSW(on) and PSW(off) are in proportion to the collector current.
‰ Reverse current of free-wheeling diode is constant regardless of the forward current I EC.
¨
Expressions
 Static loss of IGBT
1 D
Icp ´ Vce( sat )(@ Icp ) ´ ( +
cosG )
8 3F
‚ Dynamic loss of IGBT
( Psw(on) + Psw(off )) ´ fc ´
1
F
ƒ Static loss of free-wheeling diode
1 D
Iecp ´ Vec(@ Ifp = Icp) ´ ( cos G )
8 3F
„ Dynamic loss of free-wheeling diode
1
´ ( Irr ´ Vcc ´ trr ´ fc )
8
¨
Expressions Derivation
For the time t, duty ratio of PWM signals is presented by
1 + D ´ sin t
. This corresponds to the
2
change of output voltage. Thus, with the power factor cosq indicating the relationship between output
current and voltage, the expressions to calculate output current and PWM duty will be derived as
follows:
Output(current = Icp ´ sin x
1 + D ´ sin(t + G )
PWM(Duty =
2
Thus, VCE(sat) and VEC at the phase x for linear approximation is calculated by:
Vce( sat ) = Vce( sat )(@ Icp) ´ sin x)
Vec = Vec(@ Iecp = Icp)(-1) ´ sin x)
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Thus, the static loss of transistor is calculated by:
1 + D sin( x + G )
-dx
2
1 + D sin( x + G )
1 F
( Icp ´ sin 2 x) ´
-dx
= Icp ´ Vce( sat )(@ Icp) ´
ò
2F 0
2
1 D
= Icp ´ Vce( sat )(@ Icp) ´ +
cos G
8 3F
1
2F
ò
F
( Icp ´ sin x ) ´ (Vce( sat )(@ Icp ) ´
0
Similarly, the static loss of free-wheeling diode is calculated by:
1
2F
ò
2F
F
((-1) ´ Icp ´ sin x) ´ ((-1) ´ Vec(@ Icp) ´ sin x) ´
1 D
= Icp ´ Vec(@ Icp) ´ ( cos G )
8 3F
1 + D sin( x + G )
-dx
2
On the other hand, the dynamic loss of transistor, which does not depend on PWM duty, is calculated
by:
1
2F
F
ò
0
( Psw(on)(@ Icp) + Psw(off )(@ Icp)) ´ sin x) ´ fc-dx
= ( Psw(on)(@ Icp) + Psw(off )(@ Icp)) ´ fc ´
1
F
If dynamic loss of free-wheeling diode is idealized as shown in Figure 39, it is calculated by:
JHH
1-+
8 -+
J
1HH
8??
Figure 39.
Psw =
FWDi Dynamic Loss
Irr ´ Vcc ´ trr
(
(const.)
4
Recovery occurs in the middle of output current period. Thus, the dynamic loss is calculated by:
Irr ´ Vcc ´ trr
1
´ fc ´
4
2
1
´ ( Irr ´ Vcc ´ trr ´ fc )
8
¨
Guidelines for applying the power-loss expressions in inverter designs
Divide the output current period into fine-steps and calculate the losses at each step based on the
actual values of : PWM duty; output current; the values of VCE(sat), VEC, Psw corresponding to the
output current.
• PWM duty depends on the way of generating signals.
• The relationship between output current waveform or output current and PWM duty changes
depending on the way of generating signals, load, and other various factors. Thus, calculation
should be performed based on actual waveforms.
• The value of VCE(sat). (@Tj=125°C) should be used.
• The value of half bridge operation switching loss (Psw) at 125°C should be used.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.7.2. Temperature Rise Considerations and Calculation Example
• The result of loss calculation performed using the typical characteristics of PS21352 -G (5A/600V)
PS21353-G (10A/600V) are is given in Figure 40 as “Effective current Io vs carrier frequency characteristics”.
Conditions; VCC=300V, VD=VDB=15V, VCE(sat)=Typ., Switching loss=Typ. Value, Tj=125°C, Tf=100°C
Rth(j-f)=Max. specification, Simulation model 3-phase modulation 60Hz sine waveform output
Effective output current Io(Arms)
10
PS21353-G
PS21352-G
1
1
10
Carrier Frequency fc(kHz)
100
Figure 40. Carrier Frequency – Effective Current Characteristics
Note; The characteristics above may vary depending on the control schemes and the motor drive types.
Ø
Figure 40 indicates an example of an inverter operated under the condition of Tf=100 °C. It presents
the effective current Io rms which can be outputted when the junction temperature Tj rises to the
average junction temperature of 125°C (up to which the DIP-IPM operates safely).
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
4.8. Noise Withstand Capability
4.8.1. Examples of Measurement Circuits
Noise withstand capability
Note: For noise test of DIP-IPM, ±2.0kV or more withstand capability has been confirmed under the
conditions given in Figure 41. However, noise withstand capability heavily depends on the test
conditions, the wiring patterns of control substrate, parts layout, and other factors; therefore the
actual system test should be performed.
Measuring circuit
Heat sink
C1
R
Breaker
3-phase 200V
S
U
V
W
DIP-IPM
T
M
FO
Voltage slider
I/F
Control supply
(15V single power-source)
Isolation
transformer
Noise simulator
Inverter
DC supply
AC100V
Figure 41. Noise Test Circuit
C1: AC line common-mode filter 4700pF
PWM signals have been inputted from microcomputer both directly and through opto-coupler.
15V single power-source drive
Test is performed for both IM and DCBLM motors.
Measurement conditions
V++=300V, V,=15V, Ta=25°C, no load
The scheme for applying noise : From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05~1µs,
RANDOM input.
4.8.2. Countermeasures and Precautions
Noise countermeasures implemented within the DIP-IPM
The DIP-IPM improves noise withstand capabilities by reducing parts count, lowering inductance by the
internal wiring optimization, and reducing leakage current by the isolation structure optimization.
Noise countermeasures outside the DIP-IPM
For malfunction caused by external noise overcurrent
• Improving power supply filtering (close to DIP-IPM terminals)
• Lowering impedance of input parts (reducing pull-up resistance)
• Connecting filter between input parts and GND (bypassing noise)
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Example of overcurrent operation caused by DIP-IPM noise
Malfunction example when the input signal wiring of DIP-IPM is long:
• The evaluation circuit and conditions are given below.
Conditions: Vcc=280V, VD=15V (external supply), VDB=15V (External supply), Opto-coupler 5V supply
(external supply), Ta=25°C
Evaluation circuit
Input wiring
DC5V
VDB
VP1
VCIN(P)
IN
P-side IGBT
VB
L
OUT
VS
VPC
N-side IGBT
VCIN(N)
VCC
VN1
VD
OUT
IN
VNC
VNO
CIN
25m¶
Figure 42. Half Bridge Evaluation Circuit (Inductive Load)
• When the DIP-IPM input wiring is long, noise can be easily imposed on the wiring inductance. As a result,
the opto-coupler output voltage drops and arm short occurs. The wiring of the DIP-IPM output and input
might also cause inductive coupling. Noise caused by current fluctuation of the DIP-IPM and bus
inductance might cause cross talk on the wiring between the opto-coupler and the DIP-IPM as shown in
Figure 43.
Inductive coupling
Load
Load
Load
IPM input-side
IPM output-side
Figure 43. Cross Talk Model
• When an input signal changes from Low to High, the transistor on the light receiving parts of the optocoupler is OFF. The DIP-IPM input wiring is connected to the +5V supply through the load resistance of the
opto-coupler. Thus, if the transistor on the light receiving parts of the opto-coupler is OFF, the signal lines
impedance looking from the DIP-IPM becomes high and inductive noise can easily affect the DIP-IPM. The
longer the wiring between the opto-coupler output and the DIP-IPM input is, the more it tends to receive
inductive noise.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
• Four countermeasures are described below.
5V
R
C1
IPM input
C2
Light-receiving parts of
opto-coupler
GND
Figure 44. DIP-IPM Input Parts Circuit Example
1. Signal wiring impedance can be lowered by reducing the load resistance.
2. Signal wiring impedance can be lowered by connecting a capacitor in parallel with the load resistance.
3. Noise can be bypassed by connecting C2 between the DIP-IPM input terminals and GND. And insert
resistance to signal line for controlling charge/discharge current.
4. Inductive coupling factors of both output and input sides should be minimized by shortening wiring
lengths (reducing inductance).
4.8.3. Surge Withstand Capability
LVIC
R=0¶
C=200pF
Vm P
UN
VN
WN
Vm b
Figure 45.Surge Test circuit(VN1terminal)
HVIC
R=0¶
VP1
C=200pF
VUFB
VG
UP
VPb
VUFS
Figure 46.Surge Test circuit(VP1terminal)
For surge test of DIP-IPM, ±1.0kV or more withstand capability has been confirmed under the conditions given in
Figure 45,46.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Chapter 5 Additional Guidelines
5.1. Packaging Specification
(55)
(17)
Plastic tube
Per tube
(520)
DIP-IPM
10 pieces of DIP-IPM
4 columns
of tube
Per package box(Max.)
8 rows of Total number of tubes is 32.
(4 columns~8rows)
tube
Total number of DIP-IPMs is 320.
(32 tubes~10pieces)
Partition
-
-
(250)
Weight
(180)
Approximately 20g/DIP-IPM
Approximately 310g/Tube
Approximately 12kg/Packagebox
The above weights are ones when the
maximum number of DIP-IPM are
package.
(600)
Package box
Figure 47. DIP-IPM Packaging Specification
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
5.2. Handling Notice
Transportation
• Put package boxes in the correct direction. Putting them upside down, leaning them or
giving them uneven stress might cause electrode terminals to be deformed or resin case
to be damaged.
• Throwing or dropping the packaging boxes might cause the devices to be damaged.
• Wetting the packaging boxes might cause the breakdown of devices when operating.
Pay attention not to wet them when transporting on a rainy or a snowy day.
Storage
• We suggest room temperature and humidity in the ranges 5~35°C and 45~75%,
respectively, for the storage of modules. The quality or reliability of the modules might
decline if the storage conditions are quite different from the above.
Long storage
• When storing modules for a long time (more than one year), keep them dry. Also, when
using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on
their exterior.
Surroundings
• Keep modules away from places where water or organic solvent may attach to them
directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They
might cause serious problems.
Disposal
• The epoxy resin and the case materials are made of approved products in the UL
standard 94-V0, still they are incombustible.
Static electricity
• Exclusive ICs of MOS gate structure are used for the DIP-IPM power modules. Please
keep the following notices to prevent modules from being damaged by static electricity.
(1)Notice of breakdown by static electricity
Excessively high voltage (over the Max. rated input terminal voltage) resulting from the
static electricity of human bodies and packaging materials, might cause the modules to
be damaged if applied on the control terminals. For countermeasures against static
breakdown, it is important to control the static electricity as much as possible and when
it exists, discharge it as soon as possible.
* Do not use containers which are easy to be electrostaticly charged during transportation.
* Be sure to short the control terminals with carbon cloth, etc. just before using the
module. Also, do not touch between the terminals with bare hands.
* During assembly (after removing the carbon cloth, etc.), earth machines used and
human bodies. We suggest putting a conductive mat on the surface of the operating
table and the surrounding floor.
* When the terminals on the printed circuit board with mounted modules are open, the
modules might be damaged by static electricity on the printed circuit board.
* When using a soldering iron, earth its tip.
(2)Notice when the control terminals are open
* When the control terminals are open, do not apply voltage between the collector and
emitter.
* Short the terminals before taking a module off.
Mar. 2001
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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MINI DIP-IPM APPLICATION NOTE
Notice for Safe Designs
• We are making every effort to improve the quality and reliability of our products. However, there are
possibilities that semiconductor products be damaged or malfunctioned. Pay much attention to take
safety into consideration and to adopt redundant, fireproof and malfunction-proof designs, so that the
breakdown or malfunction of these products would not cause accidents including human life, fire, and
social damages.
Notes When Using This Specification
• This specification is intended as reference materials when customers use semiconductor products of
Mitsubishi Electric. Thus, we disclaim any warranty for exercise or use of our intellectual property rights
and other proprietary rights regarding the product information described in this specification.
• We assume absolutely no liability in the event of any damage and any infringement of third party’s rights
arising from the use of product data, diagrams, tables, and application circuit examples described in
this specification.
• All data including product data, diagrams, and tables described in this specification are correct as of the
day it was issued, and they are subject to change without notice. Always verify the latest information of
these products with Mitsubishi Electric and its agents before purchase.
• The products listed in this specification are not designed to be used with devices or systems, which
would directly endanger human life. Should you intend to use these products for special purposes such
as transportation equipment, medical instruments, aerospace machinery, nuclear-reactor controllers,
fuel controllers, or submarine repeaters, please contact Mitsubishi Electric and its agents.
• Regarding transmission or reproduction of this specification, prior written approval of Mitsubishi Electric
is required.
• Please contact Mitsubishi Electric and its agents if you have any questions about this specification.
Mar. 2001
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