Vol. 34, No. 4 Journal of Semiconductors April 2013 A 23 GHz low power VCO in SiGe BiCMOS technology Huang Yinkun(黄银坤)1; 2 , Wu Danyu(吴旦昱)1; 2 , Zhou Lei(周磊)1; 2 , Jiang Fan(江帆)1; 2 , Wu Jin(武锦)1; 2 , and Jin Zhi(金智)1; 2; 1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China 2 Key Abstract: A 23 GHz voltage controlled oscillator (VCO) with very low power consumption is presented. This paper presents the design and measurement of an integrated millimeter wave VCO. This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator. The VCO RFIC was implemented in a 0.18 m 120 GHz ft SiGe hetero-junction bipolar transistor (HBT) BiCMOS technology. The VCO oscillation frequency is around 23 GHz, targeting at the ultra wideband (UWB) and short range radar applications. The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around –94 dBc/Hz at a 1 MHz frequency offset. The FOM of the VCO is –177 dBc/Hz. Key words: VCO; low power; SiGe BiCMOS DOI: 10.1088/1674-4926/34/4/045003 EEACC: 2560J per presents the design of an integrated millimeter wave VCO which has a low power consumption. 1. Introduction In the last few years, the fast growth of wireless applications has driven an intense effort to design highly-integrated, high-performance, low-cost and low power radio-frequency integrated circuits (RFICs). In particular, with a new ISM band, from 22 to 29 GHz, to be authorized by the Federal Communication Commission to industry applications which need a wide frequency band to implement a high speed data communication and signal detection, the design of RFICs using this new ISM band is more urgent. As commercial communication systems operating in the new ISM band are mostly handheld devices, which are both cost sensitive and power consumption limited, increasing the integration and decreasing the power consumption are very important in order to make the new ISM band applicable. The VCO is a critical component of RF circuits in modern communication systems as a source of frequency. Traditionally, such circuits have been the exclusive domain of III– V compound semiconductors such as GaAs or InP. However, over the past several years, silicon and silicon germanium have emerged as low cost alternatives that deliver the performance of III–V compound semiconductors. A number of K band VCO have been reported using SiGe BiCMOS, SOI and CMOS process technologyŒ1 4 . Reference [1] gives out a K band CMOS VCO design which achieves a wide tuning range of 24.8% and a phase noise of –88 dBc/Hz at 100 kHz offset from a 23.32 GHz carrier. In Ref. [2], a K band SOI VCO is presented which has a tuning range of 23% and a phase noise of –130 dBc/Hz at 10 MHz offset from a 22 GHz carrier. Reference [3] presents a low power VCO which has a power consumption of 22 mW fabricated in SiGe BiCMOS technology. In summary, the VCO which is highly integrated, has a low phase noise, low power and wide band is the trend for the future. So this pa- 2. Circuit design 2.1. Design for low power A general LC-tuned VCO can be symbolized as in Fig. 1. The oscillator consists of an inductor L and a capacitor C , building a parallel resonance tank, and an active element –R, compensating the losses of the inductor represented by resistor RL in Fig. 1, and the losses of the capacitor represented by the resistor RC . This circuit results into an oscillator with angular center frequency: r 1 !C D : (1) LC The general LC-tuned VCO of Fig. 1 can be redrawn in Fig. 2, neglecting the capacitor losses, as the series resistance of integrated inductors largely dominates the tank losses. Using the energy conservation theorem, the maximal energy in the inductor must equal the maximal energy stored in the capacitor: 2 C Vpeak D 2 LIpeak : (2) 2 2 Vpeak is the peak amplitude voltage of the sine wave voltage across the capacitor and Ipeak is the peak amplitude current of the sine wave current through the inductor. This current is flowing to the resistor RS , so the effective loss in the tank can be calculated as: 2 Ploss D R C Vpeak R 2 Ipeak D ; 2 2 L (3) or with Eq. (1), * Project supported by the State Key Development Program for Basic Research of China (No. 2010CB327502). † Corresponding author. Email: jinzhi@ime.ac.cn Received 28 August 2012, revised manuscript received 29 October 2012 © 2013 Chinese Institute of Electronics 045003-1 J. Semicond. 2013, 34(4) Huang Yinkun et al. Fig. 1. Basic LC-VCO. Fig. 3. Schematic of VCO. Fig. 2. Basic LC-resonator tank. Ploss D R R 2 C2 !C2 Vpeak D V2 : 2 2L2 !C2 peak (4) This loss must be compensated by the active part of the VCO to sustain the oscillation. Ploss in the above equations is the fundamental minimum for the power consumption of a LCVCO. The equations lead to some significant conclusions for the design of low power consumption of any LC-VCO: (1) Power consumption decreases linearly with the series resistances in the resonance; (2) Power consumption decreases quadratically when the tank inductance is increased so that the oscillator frequency is assumed to be a constant; (3) Power consumption decreases quadratically when the tank capacitance is decreased so that the oscillator frequency is assumed fixed; (4) Power consumption decreases quadratically with the oscillation frequency when the tank inductance is a constant. Power consumption increases quadratically with the oscillation frequency when the tank capacitance is a constant. 2.2. Design for low phase noise From Leeson’s empirical phase noise theoriesŒ5 , the phase noise of a resonator-based VCO can be expressed as: 2F T L.!C ; f / D 10 lg Psig " 1C !1=f 3 ; 1C j!j !C 2QL ! Table 1. Low-power low phase noise design strategy. Parameter Low power Low phase noise L Maximize Maximize C Minimize Minimize RS Minimize Minimize Amplitude Minimize Maximize 2 # " F T L.!C ; f / D 10 lg 2 2Psig Rs L! 2 # " # F TRs 1 D 10 lg : 2 LC! 2 Vsig (6) Equation (6) shows that the way to reduce phase noise, is 2 to increase Vpeak and use a LC-tank with a higher Q or higher L=Rs ratio. 2.3. Design for low power low phase noise VCO As already stated in Sections 2.1 and 2.2, the critical factor for the design of low power low phase noise VCO is to provide a high Q resonator. From Eq. (6), for the lowest phase noise at minimal power consumption Q D !c L=Rs must be maximized. So the resulting guidelines for low power low phase noise VCO are summarized in Table 1, !c is assumed fixed. 3. Implementation and measurement results (5) where QL is the loaded quality factor of the tank, ! D 2f is the angular frequency offset, and F is called the device 3 noise excess factor or simply the noise factor. !1=f describes the flicker noise corner frequency and is not equal to the device flick noise corner frequency. Neglecting the flicker-noise portion and with Qtank D !c L=Rs , !c ! and Psig D 2 2 2 Vsig /(2Rp / D Vsig /(2Qtank Rs / Leeson’s equation simplifies to: In order that the VCO could be used in the new ISM band, the output frequency is set to 24 GHz and the phase noise at 1 MHz offset is 95 dBc/Hz. Figure 3 shows a simplified schematic of the complete VCO circuit implementation. The VCO is mainly composed of an active core formed by two cross-coupled transistors Q1 and Q2, a resonance tank consisting of a pair of single-end inductors and MOS varactors, and a tail current source. Directly coupled is applied in this design in order to ensure the reliable operation under a breakdown voltage between the collector and emitter (BVCEO /. 045003-2 J. Semicond. 2013, 34(4) Parameter Technology RF frequency (GHz) Phase noise (dBc/Hz) Die size (core) (mm2 / Tuning range Power dissipation (mW) FOM (dBc/Hz) Huang Yinkun et al. Table 2. Comparison of VCO performance. Ref. [7] Ref. [8] Ref. [9] 0.13 m SiGe BiCMOS 0.18 m CMOS 0.13 m CMOS 25 24.27 23 82:5 @ 500 kHz 100 @ 1 MHz 100 @ 1 MHz 0.115 0.42 0.32 10% 2.2% 2% 22 7.8 10 162 179 181 This work 0.18 m SiGe BiCMOS 22.5 94 @ 1 MHz 0.12 5% 2.5 177 Table 3. Simulated versus measured. Parameter Simulated Measured Output frequency (GHz) 23.7–24.9 22.5–23.7 Phase noise @ 1 MHz (dBc/Hz) 95 94 Power consumption (mW) 2.25 2.5 Fig. 4. Photo of the oscillator. According to the analysis of Section 2, the tank design goals can be recapitulated as (1) maximize L=C the ratio of inductance to capacitance, and (2) maximize L=R, the ratio of inductance to resistance. The minimal channel length and multi-finger are preferred for MOS-varactor to provide high quality factors. An octagonal inductor and minimal line space are applied to achieve high quality values. The optimized width and inductance of the inductor are 15 m and 350 pH respectively. The total capacitance of the resonator is 120 fF which consists of the parasitic capacitance of the Q1, Q2 and the following buffer. The amplitude of the oscillation core is 800 mV (Vp p /. The layout is also a key part of the K band VCO. The most critical nodes are the positive and negative oscillation nodes which have to be carefully designed to prevent capacitive and resistive parasitic effects. The connections of these nodes are designed using the top metal layer and a sufficient number of vias to reduce the parasitic capacitor and resistance. The proposed LC VCO shown in Fig. 3 is fabricated in HHNEC 0.18 m SiGe BiCMOS technology. The chip micrograph is shown in Fig. 4 and the active area is about 750 600 m2 . The measured output frequency of this design is 23 GHz. The oscillator core only consumes 1 mA current from a 2.5 V supply. The measured phase noise is around 94 dBc/Hz at 1 MHz offset from a 22.5 GHz carrier frequency as shown in Fig. 5. The simulated and measured results are summarized in Table 3. A figure-of-merit (FOM) is employed to evaluate the three performance parameters of the VCO: frequency, phase noise and power consumptionŒ6 , which are Fig. 5. Measured output spectrum and phase noise. FOM D 10 lg ! 0 2 1 ; ! Lf!gP (7) where L {!} is the total single-sideband phase noise spectral density at an offset frequency ! from the carrier frequency !0 . P valued in mW is the power dissipated by the oscillator core. The higher value of the FOM implies that the oscillator has achieved a better performance. Performance is summarized in Table 2. 4. Conclusion In this paper a ultra low power VCO is designed in HHNEC 0.18 m SiGe BiCMOS technology. The VCO core consumes a 1 mA current from 2.5 V supply and achieves a phase noise of 94 dBc/Hz at 1 MHz offset from a carrier frequency of 22.5 GHz. The value of FOM for this design achieves 177 dBc/Hz. Acknowledgment The authors genuinely appreciate the help of all the members of the IMECAS compound semiconductor device department and acknowledge HHNEC for providing the opportunity for chip fabrication. 045003-3 J. Semicond. 2013, 34(4) Huang Yinkun et al. References [1] Osorio J, Vaucher C S, Huff B, et al. A 21.7-to-27.8 GHz 2.6degrees-RMS 40 mW frequency systhesizer in 45 nm CMOS for mm-wave communication applications. IEEE ISSCC, 2011: 278 [2] Sadhu B, Ferriss M A, Plouchart J O, et al. A 21.8–27.5 GHz PLL in 32 nm SOI using Gm linearization to achieve –130 dBc/Hz phase noise at 10 MHz offset from a 22 GHz carrier. IEEE Radio Frequency Integrated Circuits Symposium, 2012: 75 [3] Nagarajan M, Ma K, Seng Y K, et al. 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