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All Theses and Dissertations
2004-07-01
Dynamic Element Matching Techniques For
Delta-Sigma ADCs With Large Internal Quantizers
Brent C. Nordick
Brigham Young University - Provo
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DYNAMIC ELEMENT MATCHING TECHNIQUES FOR
DELTA-SIGMA ADCS WITH LARGE INTERNAL QUANTIZERS
by
Brent C. Nordick
A thesis submitted to the faculty of
Brigham Young University
in partial fulfillment of the requirements for the degree of
Master of Science
Department of Electrical and Computer Engineering
Brigham Young University
August 2004
c 2004 Brent C. Nordick
Copyright All Rights Reserved
ABSTRACT
DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DELTA-SIGMA ADCS WITH
LARGE INTERNAL QUANTIZERS
Brent C. Nordick
Department of Electrical and Computer Engineering
Master of Science
This thesis presents two methods that enable high internal quantizer resolution in
delta-sigma analog-to-digital converters. Increasing the quantizer resolution in a delta-sigma
modulator can increase SNR, improve stability and reduce integrator power consumption.
However, each added bit of quantizer resolution also causes an exponential increase in the
power dissipation, required area and complexity of the dynamic element matching (DEM)
circuit required to attenuate digital-to-analog converter (DAC) mismatch errors. One way
to overcome these drawbacks is to segment the feedback signal, creating a “coarse” signal
and a “fine” signal. This reduces the DEM circuit complexity, power dissipation, and size.
However, it also creates additional problems. The negative consequences of segmentation are
presented, along with two potential solutions: one that uses calibration to cancel mismatch
between the “coarse” DAC and the “fine” DAC, and another that frequency-shapes this
mismatch error. Mathematical analysis and behavioral simulation results are presented. A
potential circuit design for the frequency-shaping method is presented in detail. Circuit
simulations for one of the proposed implementations show that the delay through the digital
path is under 7 ns, thus permitting a 50 MHz clock frequency for the overall ADC.
ACKNOWLEDGMENTS
I would like to gratefully acknowledge the support and encouragement from my wife,
Andrea. To her go the official titles of “Tech Writer” and “Hyphenation-Queen” for all the
proofreading and grammar checking. (Any mistakes still present in this text are most likely
because I made some changes and didn’t ask her to check them over.)
Special thanks to my wonderful parents for their support, and for providing a roof
over our heads for a bit when it was needed. Thanks as well to my brothers and sisters for
their examples in striving for advanced degrees.
I would like to acknowledge Dr. Craig Petrie for the time he has taken to proofread
and suggest improvements for the various drafts of this thesis. I also acknowledge the other
two members of my graduate committee, Dr. Michael Rice and Dr. Brent Nelson, for their
help with my thesis. Special thanks to all three for the instruction and mentoring they have
provided during my time as a student at BYU.
I would like to thank the Electrical Engineering Department of BYU: the combination
of wonderful professors, staff, and laboratory facilities made all the difference. (Additional
thanks for the LATEX thesis style package they provided.)
Special thanks to the Intel Research Council for funding this research.
Contents
Acknowledgments
vi
List of Tables
x
List of Figures
xii
1 Introduction
1.1
1
Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Delta-Sigma ADCs
2
3
2.1
Introduction to Delta-Sigma ADCs . . . . . . . . . . . . . . . . . . . . . . .
3
2.2
Obtaining High Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.3
Multi-Bit Internal Quantization . . . . . . . . . . . . . . . . . . . . . . . . .
9
2.4
High Internal Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3 Segmentation
14
3.1
Segmenting the Digital Word . . . . . . . . . . . . . . . . . . . . . . . . . .
14
3.2
Analysis of the Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
3.3
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
4 Calibration
19
4.1
The Motivation For Calibration . . . . . . . . . . . . . . . . . . . . . . . . .
19
4.2
The Calibration Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
4.3
Drawbacks and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
4.4
Behavioral Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . .
22
vii
4.5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Requantization
23
25
5.1
The Noise-Shaped Requantization (ReQ) Method . . . . . . . . . . . . . . .
25
5.2
Drawbacks and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
5.3
Behavioral Circuit Simulation Results . . . . . . . . . . . . . . . . . . . . . .
31
5.4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
6 Circuit Design
6.1
33
Circuit Overviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
6.1.1
Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
6.1.2
ReQ Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
6.1.3
Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
6.1.4
DEM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
6.2
Circuit Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
6.3
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
7 Conclusion
53
7.1
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
7.2
Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
7.3
Areas for Potential Future Research . . . . . . . . . . . . . . . . . . . . . . .
54
A Complete Circuit Schematics
57
A.1 Top Level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
A.2 Bubble Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
A.2.1 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
A.2.2 3 Input Nor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
A.3 2’s Complement Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
A.4 Unsigned Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
A.5 ReQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
A.5.1 8-bit Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
A.5.2 Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
viii
A.5.3 5-bit Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
A.5.4 D-Register Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
A.5.5 D-Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
A.5.6 D-Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
A.6 4-bit Decoder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
A.7 5-bit Decoder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
A.8 DEM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
A.8.1 16-line Rotate-1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . .
73
A.8.2 31-line Rotate-1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . .
74
A.8.3 2-to-1 Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
B MATLAB Code
76
B.1 Reference Case Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
B.2 Calibration Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
B.3 ReQ Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
B.4 Manual Calibration Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
B.5 Additional Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
B.5.1 mypsd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
B.5.2 mysnr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Bibliography
104
ix
List of Tables
2.1
Different Types of DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2.2
Example Operation of Different Types of DACs . . . . . . . . . . . . . . . .
11
4.1
Simulated SNR Results for Segmented ∆Σ ADC (in dB) . . . . . . . . . . .
20
6.1
Logic Table for 4-Bit Binary-to-Thermometer Code Conversion . . . . . . . .
44
6.2
Timing Results for the Critical Path . . . . . . . . . . . . . . . . . . . . . .
47
x
List of Figures
2.1
Comparison Between a Nyquist One-Bit ADC and a One-Bit ∆Σ ADC . . .
4
2.2
Circuit Level Block Diagram of a First-Order One-Bit ∆Σ ADC . . . . . . .
5
2.3
Z-Domain Model of a First-Order One-Bit ∆Σ ADC . . . . . . . . . . . . . .
5
2.4
Frequency Plot Showing SQ (ejw ) and SN (ejw ) for a ∆Σ ADC . . . . . . . . .
8
2.5
Basic First-Order ∆Σ ADC Block Diagram . . . . . . . . . . . . . . . . . . .
10
2.6
Graphical Explanation of DEM Operation . . . . . . . . . . . . . . . . . . .
12
3.1
Block Diagram: ∆Σ ADC With a Segmented DAC/DEM Structure . . . . .
15
3.2
Mathematical Block Diagram of a Segmented ∆Σ ADC . . . . . . . . . . . .
15
3.3
Simulation Results: 2nd-Order ∆Σ ADC With Segmented Feedback . . . . .
16
4.1
Block Diagram of Calibration Method . . . . . . . . . . . . . . . . . . . . . .
21
4.2
Simulated Results for Calibrated System . . . . . . . . . . . . . . . . . . . .
23
5.1
Mathematical Block Diagram of ReQ Architecture . . . . . . . . . . . . . . .
26
5.2
Power Spectra Showing DC Offset in Ideal ReQ Simulation . . . . . . . . . .
27
5.3
Simulated Results for ReQ System . . . . . . . . . . . . . . . . . . . . . . .
32
6.1
Overall Block Diagram of the Feedback Path for the ReQ Method . . . . . .
34
6.2
Bubble Decode Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
6.3
Encoder Circuit for the MSBs . . . . . . . . . . . . . . . . . . . . . . . . . .
36
6.4
Encoder Circuit for the LSBs . . . . . . . . . . . . . . . . . . . . . . . . . .
37
6.5
ReQ Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
6.6
Full Adder Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
6.7
D-Latch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
6.8
D-Register Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
6.9
4-Bit Binary-to-Thermometer Decoder Circuit . . . . . . . . . . . . . . . . .
42
6.10 5-Bit Binary-to-Thermometer Decoder Circuit . . . . . . . . . . . . . . . . .
43
xi
6.11 Block Diagram of DEM Circuitry . . . . . . . . . . . . . . . . . . . . . . . .
45
6.12 DEM Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
6.13 Timing Simulation for ReQ Bubble Decode Block . . . . . . . . . . . . . . .
48
6.14 Timing Simulation for ReQ Encoder Block . . . . . . . . . . . . . . . . . . .
49
6.15 Timing Simulation for ReQ 8-bit Subtractor Block . . . . . . . . . . . . . . .
50
6.16 Timing Simulation for ReQ 5-bit Subtractor Block . . . . . . . . . . . . . . .
51
6.17 Timing Simulation for ReQ Decoder Block . . . . . . . . . . . . . . . . . . .
52
A.1 Overall Schematic for Digital Feedback Path . . . . . . . . . . . . . . . . . .
57
A.2 Bubble Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
A.3 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
A.4 Nor Gate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
A.5 2’s Complement Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
A.6 Unsigned Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
A.7 Requantization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
A.8 8-bit Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
A.9 Full Adder Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
A.10 5-bit Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
A.11 D-Register Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
A.12 D-Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
A.13 D-Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
A.14 4-bit Binary-to-Thermometer Code Decoder . . . . . . . . . . . . . . . . . .
70
A.15 5-bit Binary-to-Thermometer Code Decoder . . . . . . . . . . . . . . . . . .
71
A.16 Dynamic Element Matching Logic . . . . . . . . . . . . . . . . . . . . . . . .
72
A.17 16-Input Rotate-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
A.18 31-Input Rotate-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
A.19 2-to-1 Mux
75
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
Chapter 1
Introduction
The analog-to-digital converter (ADC) is the essential link between “real world” analog signals and digital electronics. In the current digital age, they are nearly everywhere:
car sensors, home thermostats, DVD and CD players, televisions, personal computers, cell
phones, and many other common devices. As consumers expect more and more from digital
electronic devices, faster ADCs with higher resolution are needed. At the same time, cell
phones and other “mobile” technologies are demanding lower power alternatives. As such,
improving present ADC architectures is an active field of research.
The delta-sigma (∆Σ) ADC is one architecture that is being examined for use in lowpower, high-resolution, moderate-speed applications. Conventionally, ∆Σ ADCs are used
for low-frequency applications (< 100 kHz) requiring high resolution (> 14 bits), such as
digital audio or high-precision instrumentation [1, 2, 3]. Recent work, however, is extending
the signal bandwidths of ∆Σ ADCs into the MHz range while maintaining high resolution
[4, 5].
One method of extending the signal bandwidth of a ∆Σ ADC without decreasing the
resolution is to appropriately trade off internal quantization and oversampling ratio. As the
oversampling ratio is reduced, the signal bandwidth increases, but the signal-to-noise ratio
(resolution) is decreased. This can be recovered by increasing the number of bits in the
internal quantization path. Several problems arise from this approach. This thesis presents
an analysis of these problems and two potential solutions. Simulations show that near-ideal
resolution can be maintained for practical implementations.
1
1.1
Thesis Overview
The thesis begins with a short introduction of ∆Σ ADCs (Chapter 2). Some of the
issues involved in designing high-speed, high-resolution ADCs are presented. Increasing the
resolution of the internal quantization is shown to be a desirable step for higher bandwidth
design, and accompanying problems for quantization levels above one bit are discussed.
Problems that occur when internal quantization levels are increased too far are covered, and
a potential solution is presented: segmentation.
In Chapter 3, the proposed method of segmentation is described, along with its inherent drawbacks. The method is analyzed, and the source of the main drawback is identified.
In Chapter 4, calibration is presented as a potential solution to the problems associated with segmentation. A mathematical analysis is provided. An in-depth description
of how to implement the calibration solution is presented, along with the potential benefits
and drawbacks. Behavioral simulations are provided to demonstrate the performance of this
solution.
In Chapter 5, another potential solution is presented, this one adapting a method of
selecting the coarse and fine bits developed for ∆Σ DACs [6]. Again, a mathematical analysis
of this solution is presented. A description of the required hardware and its operation is
provided, again with the potential benefits and drawbacks. Simulation results are shown to
demonstrate this solution’s performance.
In Chapter 6, circuits implementing the ReQ method are presented, with schematics
and explanations. SPICE simulations are presented showing the worst-case timing of the
design, verifying that it is fast enough to meet the design constraints.
As a conclusion, Chapter 7 reviews the research presented and then compares the
results of the two potential solutions and their respective strengths and weaknesses. Contributions of this project are presented, and areas for continued research are proposed.
2
Chapter 2
Delta-Sigma ADCs
As a starting point for discussion, this chapter presents the key operating principles of
∆Σ ADCs. The design parameters which can be adjusted to increase the output resolution
are presented, as well as the practical limits of their application.
2.1
Introduction to Delta-Sigma ADCs
This is not meant to be a full tutorial on ∆Σ ADCs, but a basic summary of key
concepts to provide a common basis for further discussion. As presented in [1], a ∆Σ ADC
achieves high resolution by trading resolution in time for resolution in amplitude. The
internal circuitry of the ADC is clocked at some multiple of the required external data
rate (the oversampling ratio), providing multiple internal data points that can be digitally
processed to provide an output of much higher resolution than could be otherwise obtained.
The effective bandwidth is limited, however, to a fraction of the achievable internal frequency.
Three of the key design parameters that affect the resolution of a ∆Σ ADC are:
The oversampling ratio (OSR), the modulator order (L in the following equations), and the
number of bits of internal quantization (N ). Each of these will be discussed in more depth
in Section 2.2.
Figure 2.1 shows how a ∆Σ ADC works in comparison with a “standard” (nonoversampling or “Nyquist”) ADC architecture. Simple one-bit ADCs are used for the comparison, meaning that each ADC output is quantized to a single bit. The first part of the
picture shows the operation of a Nyquist ADC. The dashed line is the input to the ADC, and
the circles represent ADC outputs. The one-bit ADC is very inaccurate in its representation
of the input signal, since there are only two possible levels for the outputs: low and high.
3
One−bit Nyquist ADC
Amplitude
1
0.5
0
−0.5
−1
0
Input
Digital Output
10
20
30
40
50
60
70
80
70
80
One−bit delta−sigma ADC
Amplitude
1
0.5
0
−0.5
−1
0
Input
Intermediate Values
Digital Output
10
20
30
40
50
60
Time
Figure 2.1: Comparison Between a Nyquist One-Bit ADC and a One-Bit ∆Σ ADC
The lower portion of the figure shows the operation of a one-bit ∆Σ converter. The input
signal is the same, but the ∆Σ device generates ten intermediate values for each output.
These intermediate values are filtered to give more precise outputs. From the plot we can
see seven distinct output levels, suggesting that the one-bit ADC could have an output that
has at least three bits of accuracy.
Figure 2.2 shows the circuit-level block diagram of a basic, first-order ∆Σ ADC, and
Figure 2.3 shows its equivalent z-domain model. From these it can be shown that:
Y (z) = z −1 X(z) + 1 − z −1 Q(z).
(2.1)
It can also be shown that the noise transfer function from Q(z) to the output is:
Y (z) = 1 − z −1 .
Q(z)
(2.2)
Given that q(n) (the time domain representation of the signal Q(z)) is the quantization noise inserted by the internal quantizer, it is limited in magnitude to one-half an LSB
4
x(n)
+
Integrator
y(n)
ADC
-
2N
DAC
Figure 2.2: Circuit Level Block Diagram of a First-Order One-Bit ∆Σ ADC
Q(z)
X(z)
+
+
z-1
1-z-1
-
+
Y(z)
Figure 2.3: Z-Domain Model of a First-Order One-Bit ∆Σ ADC
step size (the range [− ∆2 ,
∆
]).
2
In the case of one-bit quantization where the output is set to
±Vref , ∆ is given by the following equation:
∆=
2 · Vref
= Vref .
2
(2.3)
If the input signal is sufficiently random, q(n) can be assumed to be uniformly distributed within [− ∆2 ,
∆
].
2
Following this assumption, the probability density function (pdf)
of q(n) can be described as follows:
Pq (u) =



1
∆
− ∆2 ≤ u ≤

 0
∆
2
.
(2.4)
elsewhere
The pdf of q(n) can be shown to be zero-mean by the following method:
µ = E{Q} =
Z
∞
−∞
=
Z
∆
2
−∆
2
u · Pq (u)du
u·
1 u2
=
∆ 2
"
= 0.
5
1
du
∆
#∆
2
−∆
2
(2.5)
Following a similar process, the variance of q(n) can be shown to be a constant:
2
Z
2
σ = E{Q } =
∞
−∞
Z
=
∆
2
−∆
2
u2 · Pq (u)du
u2 ·
1 u3
=
∆ 3
"
1
du
∆
#∆
2
−∆
2
∆2
.
12
=
(2.6)
The quantization noise sequence is usually modeled as a “wide-sense stationary”
(WSS) random process [7]. The power spectral density (PSD) of a WSS random process
is defined as the discrete-time Fourier transform (DTFT) of the autocorrelation function.
Given that the signal is zero-mean, this is equal to the covariance:
SQ (ejω ) = σ 2 .
(2.7)
Notice that the power is not a function of frequency; it is equal at all frequencies. This PSD
characterizes the quantization noise added to the samples by the ∆Σ ADC, and the noise
defines the accuracy, or SNR (signal-to-noise ratio), of the internal quantizer.
However, in the case of a ∆Σ ADC, the quantization error is not directly transmitted
to the output, but is shaped by the (1 − z −1 ) term in Equation (2.2). The modulation noise,
or the quantization noise’s effect on the output, can be shown to be:
N (z) = 1 − z −1 Q(z).
(2.8)
The PSD of the shaped noise is then:
1 − ejω
SN (ejω ) = 1 − ejω σ 2
=
1 + ejω σ 2
= [2 − 2 cos(ω)] σ 2 .
(2.9)
The modulation noise power is a function of frequency, as shown by Equation (2.9).
A ∆Σ ADC is only interested in a small portion of the signal band, so the modulation noise
power in the band of interest is given by:
1 Z ω0
S∆Σ (e ) =
SN (ejω )dω
2π −ω0
jω
6
=
=
≈
≈
σ 2 Z ω0
[2 − 2 cos(ω)]dω
2π −ω0
2σ 2
[ω0 − sin(ω0 )]
π "
#
ω3
2σ 2
ω0 − ω0 +
π
6
2 3
σ ω
3π
(2.10)
Given that ω0 = ωs /(2 · OSR) and that ωs = 2π, Equation (2.10) can be rewritten as
follows:
S∆Σ (ejω ) ≈ σ 2 ·
1
· ω3
3π 0
!2
≈
V
√ref
12
!2
≈
V
√ref
12
·
π3
1
·
3π OSR3
·
1
π2
·
3 OSR3
(2.11)
Figure 2.4 is a graphical comparison between the signals Q(ω) and N (ω) for a ∆Σ
ADC with an oversampling ratio (OSR) of 16. Notice how little power of N (ω) exists in the
signal band, which is all that will remain after low-pass filtering.
2.2
Obtaining High Resolution
The resolution of a ∆Σ ADC is measured by its signal-to-noise ratio (SNR). As shown
in Equation (2.12), SNR is calculated by taking the root-mean-square (RMS) signal power,
S, and dividing it by the RMS noise power in the band of interest:
SNRideal = 10 · log10
S
.
n0
(2.12)
In order to maximize the SNR, and thus the possible resolution, of the ADC, the noise power,
n0 , should be minimized.
The basic modulator of Figure 2.2 can be modified in several ways to increase the
resolution. The first would be to simply run the internal clock faster relative to the output
clock rate (in other words, increase the oversampling ratio). A second way is to increase the
aggressiveness of the noise shaping by adding additional integration stages (this increases
7
5
Quantization Error
0
SQ(ejω)
Noise Power (dB)
−5
Signal Band
SN(ejω)
−10
Modulation Noise
−15
−20
−25
−30
−1
0
10
10
Frequency
Figure 2.4: Frequency Plot Showing SQ (ejw ) and SN (ejw ) for a First-Order ∆Σ ADC With
an OSR of 16.
the modulator order). A third method is to increase the number of bits used in the feedback
path, N .
Equation (2.11) can be generalized to give an approximation of the ideal quantization
noise in a ∆Σ ADC:
n0 ≈
2 · Vref
πL
1
√ ·√
·
.
(L+0.5)
2L + 1 OSR
2N 12
(2.13)
(It should be noted that this derivation assumes that the ∆Σ ADC is using (1 − z −1 )L noise
shaping. Other noise transfer functions are possible.) This equation is comprised of the
three aforementioned parameters: oversampling ratio (OSR); modulator order, L; and the
number of bits of internal quantization, N . As each is increased, the ideal resolution of the
ADC is increased because the overall noise signal is reduced. However, an increase in any of
the three can also adversely affect power dissipation, design complexity, area required, and
system stability.
8
The OSR is the ratio of how fast the internal digital circuitry must run (sampling
frequency, fs ) compared to the Nyquist rate (2fo ):
OSR =
fs
1
=
.
2fo
2fo T
(2.14)
The higher the OSR, the more aggressive the digital filtering (lower cutoff frequency) that
can be done to remove more of the noise, and thus the higher the potential output resolution.
However, increasing the OSR can only be done by either increasing the internal modulator
frequency (which is limited by realizable device speeds), or decreasing the output bandwidth.
For designs requiring high bandwidths, the OSR is limited to relatively small numbers.
The modulator order is generally the number of integration stages in the analog forward path of the ∆Σ ADC. Increasing the modulator order will increase the ADC resolution,
but at the cost of more circuitry. This leads to a more complex design that requires more
power and more chip area. Higher-order modulators are also more difficult to make stable,
which sacrifices some of the aggressiveness of the noise shaping.
The internal quantization level is the number of bits of resolution the internal quantizer uses. The previous discussions in Section 2.1 used one-bit internal quantization. More
internal quantization levels provide an increased resolution to the internal data points, resulting in higher overall resolution. It can also improve the overall system stability. However,
this causes the internal quantizer to become more complex, increasing the chip area and required power. Perhaps more importantly, any quantization above one bit requires a DAC
which must be as accurate as the overall ADC, as discussed in Section 2.3. For this reason,
traditional ∆Σ modulators have used strictly two-level (one-bit) internal quantization.
2.3
Multi-Bit Internal Quantization
The problem with internal quantization greater than one bit is caused by the digital-
to-analog conversion required in the ∆Σ modulator feedback path. As shown in Figure 2.5,
the ADC output code passes through a DAC and then is summed into the analog forward
path of the modulator. Any errors introduced by this DAC are added directly to the input
signal and are then transmitted directly to the output along with the input. Because of this,
the feedback DAC must have a resolution equal to the overall required ADC resolution. This
9
Input
+
Integrator
Digital
Low Pass
Filter
ADC
-
Output
2N
DAC
Figure 2.5: Basic First-Order ∆Σ ADC Block Diagram
is easily done for one-bit DACs, which have inherently perfect linearity. However, multi-bit
DACs have various internal element mismatches which prevent them from realizing such high
resolutions given achievable matching in typical VLSI fabrication processes.
This problem is overcome by various noise-shaping algorithms generally known as
“dynamic element matching” (DEM) techniques. DEM algorithms operate on the signal at
the input to the DAC, and take advantage of the oversampling inherent in ∆Σ devices and
attempt to shape the noise generated by the DAC, shifting the noise to frequencies that are
out of the band of interest. The low-pass filter present at the output of the ∆Σ modulator
will then remove this error. DEM noise shaping is similar to ∆Σ noise shaping. However,
DEM is done digitally where the ∆Σ noise shaping discussed earlier is analog, and DEM
operates on noise generated from DAC element mismatches, while ∆Σ noise shaping operates
on the quantization noise.
To understand DEM, the various DAC architectures must be described. Table 2.1
shows the three main categories of interest for this discussion. “Binary-weighted” DACs
have one element for each of the input bits. A 4-bit DAC would have exactly four elements,
each weighted according to the binary place value of each bit: 1:2:4:8. A “unit-element”
or “thermometer-coded” DAC has as many elements as it has input codes (minus one): a
4-bit unit-element DAC would have 24 − 1 = 15 elements, all weighted equally. “Segmented”
DACs are a split between binary-weighted and unit-element DACs. A 4-bit segmented DAC
may have the two least significant bits realized by 22 − 1 = 3 elements, of weight “1”, and the
two most significant bits realized by 3 elements of weight “4”. Table 2.2 shows how various
input codes would be realized by a 4-bit DAC from each category.
10
Table 2.1: Different Types of DACs
Thermometer-Coded or
Unit-Element DAC
Segmented DAC
Binary-Weighted DAC
2N − 1 elements
2 Groups:
2k − 1 MSB elements
2l − 1 LSB elements
k+l =N
N elements
all elements
identically weighted
weighting of MSB to LSB
2N −k : 1
binary weighting
2N −1 : · · · : 21 : 20
Table 2.2: Example Operation of Different Types of DACs
Input Code
3
5
Unit-Element DAC
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
2-2 Segmented DAC
1 1 1
4
4
4
11
1
2
4
8
1 1 1
4
4
Binary-Weighted DAC
4
1
2
4
8
Input Code = 2
Input Code = 3
Input Code = 5
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
Figure 2.6: Graphical Explanation of DEM Operation
DEM algorithms generally use unit-element DACs. Each element of the DAC is
designed to be exactly the same size, but there is always some mismatch present. Standard
unit-element DACs have a fixed error for a given input code because the same unit elements
are used each time to form that code. A code of “1” will be formed with the first unit
element, while a code of “4” would use the first four unit elements. DEM changes the
element selection process, using different unit elements to form the same code in order to
create a time-varying error.
There are several different DEM algorithms, varying mostly in how they choose which
unit elements to use. The method chosen for this research is a data-weighted averaging
(DWA) method, also referred to as barrel-shifting. This method keeps track of the last
element used in the previous code, and uses the next group of elements sequentially. Figure
2.6 demonstrates how this works. For a code of “2” followed by a code of “3” and a code
of “5”, the algorithm would use the first two unit elements in the DAC for the first code,
followed by elements three through five for the second code. The subsequent code would
then begin at the sixth element. This selection method turns each element on and off rapidly.
The end result is that the DAC error is first-order noise shaped with most of the noise power
at higher frequencies, as shown in [8, 9].
2.4
High Internal Quantization
While such DEM algorithms work well for relatively low quantization levels (two to
five bits), they begin to present significant problems when internal quantization levels are
extended farther. Each additional bit of internal quantization causes an exponential increase
in the complexity, size, and power dissipation of the DEM logic and DAC. This is because
DEM algorithms work with unit-element DACs. The DAC must have 2N −1 elements (where
12
N is the number of bits of internal quantization), and the DEM logic must deal with the
control signals feeding those 2N − 1 unit elements.
Increasing the internal quantization level also increases the size, complexity, and
power usage of the internal quantizer. Fortunately, there are some architectures available
that will reduce these effects, two of which are folding and two-step ADC architectures. These
both generate the digital word in two parts, a “coarse” resolution and a “fine” resolution,
allowing the internal quantizer to be smaller and use less power. The drawback of these
architectures is that the time required to perform the quantization increases, potentially
destabilizing the ∆Σ modulator. A folding ADC, with its lower latency, would be the first
obvious choice. Recent research has also shown that it is possible to incorporate two-step
ADCs within a single-loop modulator, potentially maintaining loop stability [10, 11].
Efficient DEM algorithms are needed to accommodate the high level of quantization
achieved with folding, two-step, or other coarse/fine quantizers. Research has shown that
DEM algorithms based on a tree structure can be adapted for use with a segmented DAC
structure [12]. An approach was desired, however, that utilizes the DWA (barrel-shifting)
DEM method in search of a potentially simpler solution.
2.5
Conclusion
The tradeoffs involved in achieving high resolution in ∆Σ ADCs usually lead to low
internal quantization levels and high oversampling rates. In order to achieve higher bandwidths, the OSR needs to be lowered and the internal quantization level increased. New
DEM algorithms are needed to enable internal quantization levels over 5 or 6 bits while
keeping chip size and power dissipation within reasonable bounds.
13
Chapter 3
Segmentation
Technological advancement is always calling for faster, higher resolution ADCs. In
order to have both high bandwidth and high resolution in ∆Σ ADCs, an efficient DEM
algorithm is required to insure the accuracy of the ADC feedback path. This chapter presents
one potential method of achieving such an efficient DEM application.
3.1
Segmenting the Digital Word
As mentioned in Section 2.4, a folding or two-step architecture for the internal quan-
tizer can solve some of the problems arising from increasing the internal quantization level
beyond 5 bits. Since these architectures provide the digital data in two sections, “coarse
bits” and “fine bits”, a logical way to interface with the DEM is to simply perform DEM
independently on the coarse and fine DAC banks, as illustrated in Figure 3.1. With this
method there is no need to encode and recombine the coarse and fine thermometer-coded
signals generated by the quantizer, resulting in simple and fast feedback path circuitry.
(Thermometer code is a method of encoding N binary bits using 2N signal lines. To create
an output code of k, the first k lines are set high and the rest are set low, similar to mercury
in a thermometer.) The quantizer produces NC bits as the coarse signal and NF bits as the
fine signal, for a total of N bits (N = NC + NF ).
Figure 3.2 shows a mathematical representation of the segmented architecture from
Figure 3.1. The two-step quantizer resolves the NC coarse bits, and then subtracts this value
from the input and generates the NF fine bits from this signal. The gain of 2−(N −NC ) inside
the quantizer represents a binary right shift to insure the correct place value of the bits,
since the coarse bits are the NC most significant bits of an N -bit signal.
14
Coarse
Thermometer
Code
Input
+
Two Step
ADC
Integrator
-Coarse
DAC
Fine
DAC
2NC
2NF
Encoder
Fine
Thermometer
Code
Output
N=NC+NF
2NC
2NF
DEM
DEM
Figure 3.1: Block Diagram of a ∆Σ ADC With a Segmented DAC/DEM Structure
Coarse/Fine ADC
QC
X
+
H(z)
2-(N-NC)
+
+
QF
-+
+
+
Coarse DAC
(1-e)2(N-NC)
DEM
1
1
1
Fine DAC
DEM
YC
2(N-NC)
Y
+
+
YF
Figure 3.2: Mathematical Block Diagram of a ∆Σ ADC With a Segmented DAC/DEM
Structure
15
SNR vs Element Mismatch
102
100
98
SNR (dB)
96
94
92
90
88
86
84
82
0
Reference
Uncalibrated
0.2
0.4
0.6
0.8
1
% Fine Element Mismatch (Coarse is ~1/4 this value)
Figure 3.3: Simulation Results For a Second-Order ∆Σ ADC With a Segmented Feedback
Path
The coarse and fine outputs are each applied to separate DACs using smaller, independent DEM circuits, significantly reducing DEM complexity. Since DEM does not change
the digital signal, but only operates on the error within each DAC, the DEM blocks can be
represented as a simple gain of unity, as seen in Figure 3.2. The coarse DAC transfer function is weighted 2N −NC times that of the fine DAC to represent the place value of the coarse
bits relative to the fine. In practice, this is done by making the elements of the coarse DAC
2N −NC times larger than those of the fine DAC. The quantization noise, QC , present in both
signals YC and YF , ideally will cancel when the coarse and fine signals are summed together
at the modulator input. This result should be the same as if a single DEM circuit with a
single DAC had been in the feedback path. With perfect DACs (0% mismatch), MATLAB
behavioral simulations indicate that this system operates well, as shown in Figure 3.3. But,
as shown in the same Figure, with the addition of unit-element mismatch, the overall SNR
of the system drops much faster than the full 256-element reference case.
16
Unless otherwise noted, all simulations performed for comparison in this thesis use a
second-order ∆Σ ADC architecture with an OSR of 20 and 8 bits of internal quantization.
The reference case is a non-segmented (single-path) architecture, and the others use some
variation of the segmented architecture, splitting the feedback signal into 4 bits for each
of the coarse and fine paths. The percent mismatch of the coarse unit elements is scaled
assuming they are 2N −NC times larger than the fine unit elements, which is typically the
case in a practical application. Random element sizes are generated using the MATLAB
“rand” function. To account for the randomness of the element mismatch, the average of 21
different simulations is taken, with new element values generated for each run.
3.2
Analysis of the Problem
The previous explanation of the system’s operation neglected an important point.
The weighting of the coarse DAC as compared to the fine DAC depends on the relative sizes
of the unit elements. Since the unit elements vary in actual size, the weight of the coarse
DAC will not be exactly 2N −NC , but will be off by the factor 1 − , as shown in Figure 3.2.
Because of this gain mismatch between the coarse and fine DAC banks, the quantization
noise, QC , will not completely cancel when the coarse and fine signals are summed together,
as they would in the ideal case. The non-canceled portion of the quantization noise will be
added directly to the input signal, and thus be transmitted to the output of the ADC.
The output, Y , of the ADC in Figure 3.2 can be derived as follows:
h
YC (z) =
i
2−(N −NC ) QC (z) + (X(z) − YF (z)) H(z)
h
YF (z) =
(3.1)
1 + (1 − )H(z)
i
(−QC (z) + QF (z)) 1 + (1 − )H(z)
(3.2)
1 + (1 − )H(z)
N −NC
Y (z) = YC (z) · 2
+ YF (z)
X(z) · H(z)
QF (z)
=
+
1 + (1 − )H(z) 1 + (1 − )H(z)
|
{z
Desired Signal
}
|
{z
Expected Noise
+
}
· (QC (z) − QF (z))H(z)
.
1 + (1 − )H(z)
|
17
(3.3)
{z
Extra Noise Term
}
(3.4)
For comparison, a non-segmented (single-path) approach would lead to:
Y (z) =
X(z) · H(z)
Q(z)
+
.
1 + H(z)
1 + H(z)
|
{z
}
Desired Signal
|
{z
(3.5)
}
Expected Noise
A comparison of Equations (3.4) and (3.5) shows that the coarse/fine system has the error
term “ · (QC − QF )” present in addition to normal quantization noise. The values of QC
and QF are dependent on the number of bits used in the coarse and fine signals (NC and NF
respectively) and the current input signal. In normal implementations, QC >> QF because
the LSB step size of the coarse bits is much larger than the LSB step size of the fine bits, so
QC − QF ≈ QC . The value of the mismatch term, , changes with each clock cycle due to
the operation of the DEM. Its magnitude depends on the mismatch between coarse and fine
DACs, which is a function of mismatch between unit elements. For realistic unit-element
mismatch values, is small, but still large enough to significantly affect the SNR of the
system. Simulations show that a segmented ∆Σ ADC, as described in this section, with a
unit-element mismatch of 1.0% has an SNR of 84 dB as compared to almost 99 dB for the
reference case (see Figure 3.3).
3.3
Conclusion
Handling the coarse and fine data separately is an appealing option. It requires very
little hardware, can be very fast, and is simple and intuitive. However, simulations and
mathematical analysis show that this method has some serious problems and will degrade
the overall SNR of the system. The problem lies in the mismatch between the coarse and fine
DACs. Because the unit elements in each DAC will each have an element of random error in
their size, the ratio of the coarse DAC weighting to that of the fine will not be the desired
value, and will even vary with time due to the DEM circuitry’s operation. This results in
coarse quantization noise leaking to the output, which degrades SNR substantially.
18
Chapter 4
Calibration
Using a segmented feedback DAC with separate DEM is a potential method to simplify the DEM block and allow it to operate on highly-quantized signals. However, error is
introduced by another mismatch problem, namely, the mismatch between the coarse and fine
DAC banks. As the title suggests, this chapter presents a method to remove that mismatch
using calibration.
4.1
The Motivation For Calibration
The mismatch term, , from Equation (3.4) represents the deviation from the desired
gain ratio of the coarse and fine DACs. As mentioned in the previous section, each DAC’s
gain changes with every cycle due to the DEM operation. However, since ∆Σ ADCs use
oversampling, the average gain of the DAC over time is more important than any instantaneous value. For an N -bit, fully-differential DAC with M = 2N − 1 unit elements, each of
value Di , the output corresponding to an input code of “n” in the range [0, N ] is equal to:
FD (n) =
n
X
Di −
i=1
M
X
Di .
(4.1)
i=n+1
In words: the output is equal to the sum of the first n elements minus the sum of the
remaining elements. The difference between two successive input codes is then given by:
FD (k) − FD (k − 1) = 2 · Dk .
(4.2)
Since the DAC gain is equal to the average slope of the transfer function, the average gain
of the DAC (A) can be written as:
A=
FD (k) − FD (k − 1)
Di
=
,
2Dref
Dref
19
(4.3)
Table 4.1: Simulated SNR Results for Segmented ∆Σ ADC (in dB)
Unit-Element % Mismatch
Reference
Segmented
Segmented with
Adjusted DAC Gain
0.0
0.5
1.0
100.8
100.8
99.6
89.5
98.4
83.8
100.8
99.5
98.0
where 2Dref represents the ideal output step size (corresponding to an input LSB change)
and Di is the average unit-element value.
Equation (4.3) states that the average gain of the coarse or fine DAC is equal to the
normalized average element size. So the mismatch, , from Equation (3.4) can be reduced
by matching the average element values between DACs with the ratio of 2N −NC : 1. The
individual DAC element values are not important, as long as the average element values
meet this ratio. The (1 − ) factor will be zero on average and the coarse quantization noise
will not leak to the output. Simulated results shown in Table 4.1 demonstrate this. The
first row is the SNR of the reference ∆Σ ADC at various unit-element mismatch values.
The second row shows the standard segmented case. The third row is the same segmented
case, with a single fine unit element adjusted such that the average unit-element value in
the coarse DAC is exactly 16 times larger than the average unit-element value in the fine
DAC (28−4 : 1 = 16 : 1). At 1% mismatch, the segmented ADC without equalized DAC
gains has an SNR 14.6 dB lower than the reference (non-segmented) case. In comparison,
the ADC with adjusted DAC gains has an SNR only 0.4 dB lower than the reference case.
Such adjustment of the DAC gains can be acheived through calibration.
4.2
The Calibration Method
Figure 4.1 is a block diagram of a proposed calibration architecture. This method
performs the calibration as an initialization step. During calibration, the connections from
the coarse/fine ADC to the feedback path are broken and a single-bit path provides the
20
Additional
Stages
CAL
+
-- -
One-Bit
ADC
Coarse
DAC
CAL
DEM
Calibration
Signal
Fine
DAC
CAL0
CAL
CAL1
1-bit Cal
DAC
Output
Coarse/
Fine ADC
DEM
CAL
Input
Synck
Filter
and
Calibration
Logic
CAL
CAL
Test
Signal
Figure 4.1: Block Diagram of Calibration Method
modulator feedback. A one-bit quantizer is used because it is immune to the mismatch that
plagues multi-bit quantizers. The modulator input is grounded and a fixed, DC test signal
is presented to the coarse and fine DACs through the DEM circuitry. The output is sent
to an averaging synck filter, and then measured for each DAC individually, with the other
DACs disconnected from the circuit. The relative measurement between coarse and fine
DAC banks can then be used to make the necessary adjustment to match the ratio of the
average DAC element values. Simulations show that the calibration routine must measure
coarse and fine average capacitor values to within 2.5% of their nominal values to keep SNR
penalties below 2 dB. This means that the one-bit modulator must measure the calibration
signal to within 0.0098% of full scale (13 to 14-bit accuracy); this is feasible for a one-bit
modulator with high oversampling.
Correction must be applied to one of the DACs to complete the calibration. Due
to the averaging effect of the DEM algorithm, the required adjustment does not have to
be added to all the unit elements in the bank. Simulations show that it is sufficient to
manipulate a single fine unit element to achieve the required average unit-element ratio.
21
Similarly adjusting a coarse bank element is not effective; two possible explanations for this
are as follows: 1) the mismatch between individual coarse bank elements may be increased,
reducing the effectiveness of coarse-bank DEM, and 2) the coarse DAC input data is more
strongly patterned than the fine DAC input data, therefore DEM averaging is performed
less efficiently in the coarse DAC.
4.3
Drawbacks and Benefits
A distinct advantage of the calibration method is the low complexity of the feedback
path. For an 8-bit quantizer, two independent, 4-bit DEM implementations are required.
These DEM algorithms can be constructed so that only a four-stage pass-gate structure is
required in the signal path to shuffle the thermometer-coded ADC outputs [13]. Thus both
the complexity and the timing delay of the digital feedback path are minimal.
The necessity of having a separate calibration mode is a significant drawback. The
device is not ready for immediate use, and cannot track changes in circuit behavior relating
to temperature and other time-varying effects. A possible solution is to use a background
calibration routine, such as one that uses an out-of-band DAC test sequence as proposed
in [14]. Another drawback is that the calibration circuitry can be quite complex and large,
requiring a lot of control circuitry and memory to compute and apply the required calibration
adjustment. Also, as separate DACs are generally used for each integration stage in ∆Σ
modulators, each set of DAC banks must be calibrated individually, which adds to the time
required to calibrate high-order modulators. Exactly how to apply the calibration adjustment
in such a way that does not add additional error is also a non-trivial problem.
4.4
Behavioral Simulation Results
Figure 4.2 shows simulation results for both calibrated and uncalibrated systems com-
pared to the reference case for various unit-element mismatch percentages. In the calibration
simulation, a “calibration mode” is simulated using a 1-bit ADC and feedback path, and
alternately applying a test signal to the coarse and fine DAC to measure their individual
effects on the output. These individual measurements are then compared and used to calculate how much a single fine element must be adjusted to insure an average element size
22
SNR vs Element Mismatch
102
100
98
SNR (dB)
96
94
92
90
88
86
84
82
0
Reference
Calibration
Uncalibrated
0.2
0.4
0.6
0.8
1
% Fine Element Mismatch (Coarse is ~1/4 this value)
Figure 4.2: Simulated Results for Calibrated System
ratio of 16:1. The simulation then continues normal operation with this calibration amount
in place.
For the uncalibrated system and 1% mismatch, using independent coarse/fine DEM
results in a 14.5 dB degradation in SNR from the ideal case. For the calibrated simulation,
one of the fine DAC elements was adjusted to correct the gain ratio between the coarse and
fine DACs. This small adjustment achieved an SNR within 0.5 dB of the reference case.
(Note that this does not take into account errors in applying the calibration adjustment.)
4.5
Conclusion
Calibration can significantly improve the SNR of the subdivided system, and can be
done in a way to minimally affect the overall operation of the ADC. The method proposed
adds a one-bit calibration path and extra circuitry that are active during an initialization
step to perform the calibration, and a small bit of logic to vary one of the fine unit elements.
It does not add extra logic to the feedback path, and does not change the normal operation of
the ADC. As such, it is fairly simple, and can be quite accurate. However, it is unable to track
changes in the unit-element values that can occur over time, and the calibration measurement
and adjustment circuitry can be complex. Also, the calibration must be performed for
23
each group of DAC banks, meaning that increasing the order of the ∆Σ modulator will
significantly increase the time required to fully calibrate the ADC.
24
Chapter 5
Requantization
The previous chapter showed that calibration is a viable option for eliminating the
error added by the segmented DEM approach. However, the operation of the DEM blocks
themselves suggests another solution. The DEM blocks function not by removing the error
in the DAC elements, but by shifting the noise caused by that error away from the band of
interest. This chapter presents a noise-shaping method that attempts to do the same with
the noise caused by the coarse and fine DAC bank mismatch.
5.1
The Noise-Shaped Requantization (ReQ) Method
This method was initially proposed in [6] for a ∆Σ DAC; this work extends this
concept to ∆Σ ADCs. The basic idea is to generate a new coarse signal with a digital ∆Σ
modulator and use this coarse signal to generate a new fine signal. This insures that both
the coarse and fine signals are individually noise shaped, which is performed in a way that
causes the quantization error leakage to be noise shaped as well. Even though it does not
completely cancel errors due to DAC mismatch, the quantization error noise power will be
outside the signal band. The process is explained below, and is modeled in Figure 5.1.
First, the coarse and fine signals from the ADC internal quantizer are encoded into
binary and concatenated to form a 2’s complement N -bit signal, Y 0 . This signal is then
requantized to NC bits to form a new coarse signal using a digital first-order ∆Σ modulator.
This coarse signal is subtracted from the original N -bit signal to form the new fine signal,
comprised of NF +1 bits. After requantization, the new coarse and fine signals are:
h
YC0 (z) = 2−(N −NC ) Y 0 (z) + Q0C (z) 1 − z −1
25
i
(5.1)
Coarse/Fine ADC
X
+
QC
+
+
H(z)
2(N-NC)
2-(N-NC) NC
YC
QF
-+
+
+
Y'
+
+
NF
YF
N
Coarse DAC DEM
Y'C NC
(1-e)2(N-NC)
1
(N-NC)
NC 2
+
2(N-NC)
NF+1
1
1
Fine DAC
DEM
-
Digital First Order Modulator
Q'C
-(N-N
)
C
2
+
N
+
-+
Z
+
-1
Y'F
Figure 5.1: Mathematical Block Diagram of ReQ Architecture
YF0 (z) = −Q0C (z) · (1 − z −1 ).
(5.2)
Signals YC0 (z) and YF0 (z) then pass through independent DEM blocks and DACs and are
summed at the input of the modulator. With first-order requantization (ReQ), the quantization error that is not completely cancelled due to coarse/fine DAC mismatch (as in
Equation (3.4)) is noise-shaped away from the signal band. The output of the system with
ReQ as in Figure 5.1 is derived as follows:
h
i
YC (z) = 2−(N −NC ) QC (z) + X(z) − (1 − )2N −NC · YC0 (z) − YF0 (z) H(z)
YF (z) = −QC (z) + QF (z)
Y 0 (z) = YC (z) · 2N −NC + YF (z)
h
i
= X(z) · H(z) − (1 − )Q0C (z) − Q0C (z)
1 − z −1
+ QF (z) − (1 − )H(z) · Y 0 (z)
X(z) · H(z)
QF (z)
+
=
1 + (1 − )H(z) 1 + (1 − )H(z)
|
{z
Desired Signal
}
|
{z
Expected Noise
26
}
Power
Power Spectra
100
100
50
50
0
0
−50
−50
−100
−100
−150 0
10
2
10
4
10
−150 0
10
Frequency
2
10
4
10
Frequency
Figure 5.2: Comparison of an Ideal Segmented ∆Σ ADC (as in Figure 3.2) and an Ideal ∆Σ
ADC Using the ReQ Block Showing DC Offset
( · Q0C (z)) (1 − z −1 ) H(z)
.
+
1 + (1 − )H(z)
|
{z
Extra Noise Term
(5.3)
}
A comparison of Equation (5.3) and Equation (3.4) shows that the desired signal and expected noise terms are almost the same, but the extra noise term in Equation (5.3) is
now multiplied by (1 − z −1 ), which causes first-order noise shaping. Simulations show that
higher-order ReQ is not necessary; first-order ReQ sufficiently suppresses coarse/fine mismatch errors below the noise shaped by the DEM within each DAC.
5.2
Drawbacks and Benefits
Although the need for calibration is eliminated, the ReQ method contains several
minor drawbacks. An extra fine bit is required because of the final addition operation before
the DEM blocks in Figure 5.1, requiring slightly larger DEM and DAC implementations.
The total number of bits of information is still the same (N bits); the coarse and fine signals
YC0 and YF0 overlap by one bit. Another potential drawback is a slight reduction in signal
range due to the possibility of overflow in the ReQ circuitry. Simulations show that the SNR
is not adversely affected by potential overflow if the input is limited to about 90% of full
scale.
27
A third drawback comes in the form of a DC error that occurs when using the ReQ
method. Even when simulations are performed using ideal unit elements, some DC offset is
present. Figure 5.2 demonstrates this. The left half of the picture shows the power spectrum
for a segmented ∆Σ ADC with ideal elements. The right half shows the same signal, this
time from a ∆Σ ADC with ReQ operating in the feedback path. The ReQ signal shows
first-order noise shaping of the quantization noise leakage, but it also has a DC component.
This DC offset arises due to the difference between YF and YF0 . The signal YF is an unsigned
number (the lower bits of a 2’s complement number), while YF0 is a 2’s complement number,
which can be either positive or negative. An analysis of the source of this DC error follows.
In a system using unsigned numbers (positive integers), a fully-differential DAC can
be modeled by the following equation:
D(Y ) =
i
Vref Vref h N
Y
−
2
−
1
− Y .
2N − 1
2N − 1
(5.4)
(A fully-differential DAC is one that always uses all of the elements, each in either the
“positive” or the “negative” sense.) In a 2’s complement DAC, the equation for D(Y ) is
slightly different:
D(Y ) =
i
Vref Vref h N
N −1
N −1
Y
+
2
2
−
1
−
Y
+
2
−
.
2N − 1
2N − 1
(5.5)
The first term represents the elements that are “on,” or added, and the second term represents the elements that are “off,” or subtracted. In these equations, Vref is the reference
voltage for the DAC, and 2N − 1 is representative of how many individual levels the DAC
can represent. The term Y + 2N −1 in Equation (5.5) results from the need to convert the
2’s complement number “Y ” to a positive number representing how many unit elements to
use in the “positive” sense (the rest are “negative”, as shown by the second term in the
equation). Through some simplification it is easy to show that the 2’s complement DAC
equation reduces to:
D(Y ) =
Vref
(2 · Y + 1) .
2N − 1
28
(5.6)
For a basic coarse/fine system with no ReQ step inserted, as in Figure 3.2, since YC is
a 2’s complement number, and YF is an unsigned number, the following equations describe
the output of the DACs:
Vref · 2N −NC NC −1
Y
+
2
C
2N − 1
i
Vref · 2N −NC h NC
NC −1
−
2
−
1
−
Y
+
2
C
2N − 1
i
Vref h NF
Vref
(YF ) − N
2 − 1 − (YF ) .
DF (YF ) = N
2 −1
2 −1
DC (YC ) =
(5.7)
(5.8)
The sum of the output of these two DACs with the input of YC and YF should be the same
as the output of a single DAC with the input of Y (see Equation (5.6)):
DC (YC ) + DF (YF ) =
Vref h
N −NC
NC −1
2
·
2
Y
+
2
+ 2 (YF )
C
2N − 1
i
−2N −NC 2NC − 1 − 2NF − 1
=
Vref h N −NC
N −NC
NC −1
2
2
·
Y
+
Y
+
2
·
2
C
F
2N − 1
− 2N − 1 − −2N −NC + 2NF
i
i
Vref h N −1
N
2
Y
+
2
−
2
−
1
2N − 1
Vref
= N
(2 · Y + 1) .
2 −1
=
(5.9)
This shows that the two separate DACs together perform exactly the same function that a
single DAC (as in the reference design) would do: D(Y ) = DC (YC ) + DF (YF ).
When this same analysis is applied to the ReQ system (as in Figure 5.1), a slightly
different result is obtained. Both YC0 and YF0 are 2’s complement numbers, and YF0 has one
more bit than YF . So the DAC equations are:
Vref · 2N −NC 0
NC −1
Y
+
2
C
2N − 1
i
Vref · 2N −NC h NC
0
NC −1
−
2
−
1
−
Y
+
2
C
2N − 1
Vref 0
DF0 (YF0 ) = N
YF + 2NF
2 −1
i
Vref h NF +1
− N
2
− 1 − YF0 + 2NF .
2 −1
DC0 (YC0 ) =
29
(5.10)
(5.11)
The sum of DC0 (YC0 ) and DF0 (YF0 ) should be the same as a single DAC with an input of Y 0 .
However, it is not. The sum is instead given by:
DC0 (YC0 ) + DF0 (YF0 ) =
Vref h
N −NC
0
NC −1
0
NF
2
·
2
Y
+
2
+
2
Y
+
2
C
F
2N − 1
i
−2N −NC 2NC − 1 − 2NF +1 − 1
=
Vref h N −NC
0
0
N −NC
NC −1
2
2
·
Y
+
Y
+
2
·
2
C
F
2N − 1
− 2N − 1 + 2 · 2NF + 2N −NC − 2NF +1
=
i
Vref h N −NC
0
0
N −1
2
2
·
Y
+
Y
+
2
C
F
2N − 1
− 2N − 1 + 2NF +1 − 2NF
i
i
Vref h N −1
N
NF
2
Y
+
2
−
2
−
1
+
2
2N − 1
Vref
Vref NF (2 · Y + 1) + N
2
= N
.
2 − 1 {z
2 − 1{z
|
} |
}
=
Desired Signal
(5.12)
Offset
The offset term is added to the input node of the ∆Σ ADC, causing a DC offset in the output.
It is caused by the fact that YF0 is a signed number, whereas before, YF was unsigned. (The
examples given were for a 2’s complement number representation. It can be shown that
the same DC offset is present for other signed numbering systems, such as offset or signmagnitude notation.)
The DC offset is the same magnitude as the step caused by one coarse unit element.
To counter this offset, one extra unit element was added to the coarse DAC. Given the fullydifferential nature of the system, the additional unit element will effectively be subtracted
from the DAC output signal, removing the DC bias. With unit-element mismatch present, it
does not fully remove the DC offset, but does so accurately enough to not noticeably affect
the overall SNR of the ADC.
Since the ReQ method adds significant logic to the feedback path, it can potentially
limit the maximum possible clock speed of the device. If a folding ADC quantizer is used,
one-half clock cycle (less the ADC comparator latching time) is available for this digital
computation. As an example, the design presented later in this work has a target clock rate
of 50 MHz, permitting about 10 ns for the computation. Recent developments show that a
30
two-step ADC architecture can be used while still allowing this same amount of propagation
time for the logic [10, 11]. With careful design, the delay through this path should be small
enough, and as CMOS technology scales, the delay will continue to decrease, permitting
faster clock rates.
The benefits to offset these drawbacks are few, but significant. First, there is no
startup mode required, providing “instant-on” functionality. Second, since this method of
removing the DAC mismatch error is completely digital, the actual chip should operate very
close to the simulation. In the case of calibration, there are additional inaccuracies that
will be present in physical silicon (such as the circuits to apply the calibration change and a
limited number of bits to represent the measurements) that were not taken into account in
the simulations. So the ReQ method is potentially easier to implement and easier to achieve
functionality in silicon.
5.3
Behavioral Circuit Simulation Results
Figure 5.3 compares the performance of the calibration and ReQ methods against the
ideal (full DEM) case. For the case of 1% fine element mismatch, the ReQ method achieves
an average SNR of 96.5 dB, which is only 2 dB less than the full 8-bit DEM reference case.
The calibration method acheives slighty superior performance in simulation, but would be
much harder to effectively implement in silicon.
5.4
Conclusion
The ReQ method applies techniques developed for ∆Σ DACs to the ADC feedback
path. The coarse and fine signals are reassigned using a first-order digital modulator, and
then applied to the DEM and DAC circuits. The resulting system has slightly worse SNR
performance than the calibration method previously discussed, but it does not require any
special initialization or setup in order to work, and is potentially easier to implement.
This method adds significant delay to the feedback path, and adds some area and
power consumption for the required circuitry. However, operation very near the reference
case is achieved, and no additional steps or circuitry are required to use this method with
higher-order ∆Σ modulators.
31
SNR vs Element Mismatch
101.5
101
100.5
SNR (dB)
100
99.5
99
98.5
98
97.5
97
96.5
0
Reference
REQ
Calibration
0.2
0.4
0.6
0.8
% Fine Element Mismatch (Coarse is ~1/4 this value)
Figure 5.3: Simulated Results for ReQ System
32
1
Chapter 6
Circuit Design
Both the calibration and requantization methods previously discussed are successful
and efficient methods to implement a segmented DEM architecture. The physical realization
of the calibration method depends on analog circuits to apply the calibration. The ReQ
method, however, is completely digital in its implementation. As such, the physical operation
of the ReQ method should be closer to its simulated performance than that of the calibration
method. For this reason, the ReQ method was chosen as the solution for the current research
application. This chapter presents the circuit designs to implement the ReQ method in
silicon.
6.1
Circuit Overviews
The ReQ circuits presented in this chapter are designed to meet the following system
specifications in a TSMC 0.25 µm process: fourth-order ∆Σ ADC, 50 MHz clock rate,
NC = 4, and NF = 4. Straight-forward designs were used (circuits without many speed
optimizations) to see if standard circuits could be used to meet the time delay constraints.
Due to the lack of available synthesis tools, the designs were done by hand, instead of using
RTC. The overall block diagram of the feedback path is shown in Figure 6.1. Each block
will be explained in turn, and full schematics for each can be found in Appendix A.
6.1.1
Encoder
The first blocks in the feedback path are the two encoders. These identical blocks
first convert the thermometer code output of the ADC quantizer into a “one-hot” signal (a
signal in which only one wire is asserted at any given time). In order to do this, the circuitry
33
Additional
Stages
Input
+
- -
Fine
DAC
Output
Coarse/
Fine ADC
2NC
Coarse
DAC
Encoders
2NC
2NF+1
2NF
Decoders
DEM
DEM
2NC
NC
NC
NF
ReQ
Block
2NF+1
NF+1
Figure 6.1: Overall Block Diagram of the Feedback Path for the ReQ Method
looks for the edge of the thermometer code - a sequence of “0 0 1”. A three-input detection
allows the circuit to eliminate a spurious code of “1 0 1” (referred to as a “bubble”). The
circuit is comprised of 3-input nor gates and inverters. Figure 6.2 shows this part of the
design.
After this, the encoders convert the “one-hot” signals to binary. Since the output
of these two blocks represent, respectively, the four most significant bits and four least
significant bits of the 2’s complement binary number, the circuits are slightly different: the
encoder block for the most significant bits has an extra inverter on the MSB to make it
output 2’s complement signed numbers. Figure 6.3 shows the circuit design for the encoder
handling the most significant bits, and Figure 6.4 shows the circuit design for the encoder
handling the least significant bits. The circuits were designed using weak p-type pull-up
devices to hold the outputs high, unless pulled low by strong n-type devices controlled by
the input signals.
6.1.2
ReQ Block
The ReQ circuit (see Figure 6.5) is comprised of two 8-bit subtractors, a 5-bit sub-
tractor, and an 8-bit register. The lower right part of Figure 5.1 shows a block diagram view
34
out
vdd
vdd
one_high<15:1>
I11
vdd
in
out
NOR3
B
inverter_1b
vdd
out
vdd
TC<7>
vdd
TC<15>
vdd
I31
out
inverter_1b
NOR3
one_high<14>
Q
vdd
out
TC<6>
vdd
I19
in
TC<7>
out
I6
vdd
A
NOR3
B
one_high<6>
Q
C
gnd
A
NOR3
B
one_high<13>
Q
TC<5>
C
gnd
vdd
I20
in
one_high<12>
Q
TC<4>
C
gnd
vdd
I21
in
one_high<11>
TC<3>
C
gnd
out
vdd
I18
in
vdd
one_high<10>
Q
TC<2>
C
gnd
vdd
I17
in
vdd
gnd
gnd
gnd
vdd
NOR3
B
gnd
TC<4>
TC<3>
out
gnd
I1
vdd
A
NOR3
B
gnd
gnd
vdd
one_high<2>
Q
C
inverter_1b
gnd
I15
vdd
A
B
one_high<3>
Q
C
gnd
NOR3
one_high<9>
Q
TC<1>
C
inverter_1b
vdd
vdd
gnd
out
out
I3
vdd
A
gnd
gnd
NOR3
B
gnd
vdd
I16
in
TC<3>
TC<2>
out
I0
vdd
A
B
NOR3
C
inverter_1b
gnd
gnd
gnd
gnd
gnd
gnd
in
vdd
I24
TC<4>
I14
vdd
A
inverter_1b
TC<10>
TC<5>
gnd
gnd
TC<11>
gnd
inverter_1b
vdd
gnd
vdd
in
TC<11>
one_high<4>
Q
C
gnd
gnd
NOR3
Q
gnd
vdd
I27
NOR3
B
I12
vdd
A
B
inverter_1b
TC<12>
out
I2
vdd
A
vdd
out
TC<5>
gnd
vdd
TC<12>
TC<6>
inverter_1b
vdd
gnd
vdd
in
TC<13>
vdd
gnd
gnd
NOR3
inverter_1b
vdd
I26
gnd
I13
vdd
A
B
one_high<5>
Q
C
gnd
out
NOR3
B
gnd
vdd
TC<13>
TC<6>
out
I7
vdd
A
inverter_1b
vdd
gnd
vdd
in
vdd
I25
TC<14>
TC<7>
vdd
out
I8
vdd
vdd
TC<14>
gnd
TC<9>
TC<8>
gnd
vdd
vdd
in
vdd
I28
TC<15>
inverter_1b
TC<10>
gnd
gnd
gnd
TC<11>
one_high<7>
Q
C
inverter_1b
gnd
TC<12>
NOR3
B
C
inverter_1b
TC<13>
out
I4
vdd
A
gnd
gnd
in
TC<8>
gnd
gnd
TC<13>
TC<9>
inverter_1b
I9
vdd
B
vdd
I22
in
A
gnd
vdd
gnd
vdd
I29
gnd
gnd
gnd
in
one_high<8>
Q
C
gnd
inverter_1b
gnd
TC<14>
NOR3
B
inverter_1b
Q
gnd
gnd
vdd
I32
out
I5
vdd
A
gnd
in
vdd
I23
in
C
gnd
vdd
TC<13>
one_high<15>
TC<8>
TC<9>
gnd
TC<14>
A
vdd
I33
TC<10>
gnd
gnd
TC<15:1>
vdd
inverter_1b
gnd
vdd
gnd
gnd
vdd
I34
Figure 6.2: Bubble Decode Circuitry
35
gnd
in
vdd
TC<15>
vdd
vdd
vdd
one_high<1>
Q
PM32
PM33
"pch"
"pch"
"pch"
l:240.0n
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
m:1
vdd
PM1
PM37
"pch"
"pch"
l:240.0n
l: 240.0n
w=1.74u
w=1.74u
fingers=3
fingers=3
m:1
m:1
NM1
NM97
"nch"
"nch"
l:240.0n
gnd
w=1.16u
gnd
fingers:1
l:240.0n
w=1.16u
gnd
PM31
"pch"
vdd
one_high<15:1>
PM30
vdd
vdd
vdd
gnd
m:1
PM34
fingers:1
m:1
"pch"
l:240.0n
bit<3:0>
one_high<15>
w=1.74u
fingers=3
m:1
bit<2>
NM30
NM34
NM33
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
m:1
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fi ngers:1
fingers:1
m:1
"nch"
: 40.0n
l2
w=1.16u
PM36
"pch"
gnd
NM35
"nch"
vdd
NM36
fingers:1
m:1
l:240.0n
one_high<14>
w=1.74u
fingers=3
m:1
NM37
NM38
NM39
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
: 40.0n
l2
bit<1>
NM32
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
m:1
l:240.0n
w=1.16u
gnd
w=580.0n
fingers:1
fingers:1
vdd
"nch"
m:1
PM35
one_high<13>
"pch"
l:240.0n
w=1.74u
NM45
NM46
NM48
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
fingers=3
m:1
bit<0>
NM31
"nch"
l:240.0n
gnd
w=1.16u
one_high<12>
NM44
NM43
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
fingers:1
m:1
one_high<11>
NM61
NM63
NM64
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
one_high<10>
NM60
NM58
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
Both N and P type devices in
array are w/l=540n/240n.
Inverters are
P:w/l=1.74u/240n
N:w/l=1.16u/240n.
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<9>
NM52
NM49
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<8>
NM53
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<7>
NM94
"nch"
l:240.0n
NM95
NM96
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
one_high<6>
NM91
"nch"
NM90
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<5>
NM87
NM85
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<4>
NM82
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<3>
NM78
NM77
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<2>
NM75
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<1>
NM72
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
Figure 6.3: Encoder Circuit for the MSBs
36
bit<3>
vdd
vdd
gnd
PM1
"pch"
PM31
PM32
PM33
"pch"
"pch"
"pch"
"pch"
l:240.0n
l:240.0n
l:240.0n
l:240.0n
l:240.0n
w=1.74u
fingers=3
one_high<15:1>
w=580.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
m:1
m:1
"nch"
vdd
l:240.0n
gnd
w=1.16u
gnd
bit<3>
NM1
fingers:1
vdd
PM30
m:1
PM34
"pch"
l:240.0n
bit<3:0>
one_high<15>
w=1.74u
fingers=3
m:1
bit<2>
NM30
NM34
NM33
"nch"
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
m:1
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fi ngers:1
fingers:1
m:1
"nch"
: 40.0n
l2
w=1.16u
PM36
"pch"
gnd
NM35
vdd
NM36
fingers:1
m:1
l:240.0n
one_high<14>
w=1.74u
fingers=3
m:1
NM37
NM38
NM39
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
: 40.0n
l2
bit<1>
NM32
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
m:1
l:240.0n
w=1.16u
gnd
w=580.0n
fingers:1
fingers:1
vdd
"nch"
m:1
PM35
one_high<13>
"pch"
l:240.0n
w=1.74u
NM45
NM46
NM48
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
fingers=3
m:1
bit<0>
NM31
"nch"
l:240.0n
gnd
w=1.16u
one_high<12>
NM44
NM43
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
fingers:1
m:1
one_high<11>
NM61
NM63
NM64
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
one_high<10>
NM60
NM58
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
Both N and P type devices in
array are w/l=540n/240n.
Inverters are
P:w/l=1.74u/240n
N:w/l=1.16u/240n.
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<9>
NM52
NM49
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<8>
NM53
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<7>
NM94
"nch"
l:240.0n
NM95
NM96
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
one_high<6>
NM91
"nch"
NM90
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<5>
NM87
NM85
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<4>
NM82
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<3>
NM78
NM77
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<2>
NM75
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<1>
NM72
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
Figure 6.4: Encoder Circuit for the LSBs
37
of the ReQ. The path including the register and the two 8-bit subtractors makes up a firstorder digital modulator to form a new noise-shaped coarse signal, and the 5-bit subtractor
is used to form the new noise-shaped fine signal.
The subtractors are a simple ripple-carry design. Since they are only 8 or 5 bits wide,
the potential speedup of carry lookahead circuits is small, and does not seem to offset the
drawback of the increased size and power requirements. The basic full adder circuit is shown
in Figure 6.6.
The D-flip-flops are a standard design, such as can be found in textbooks and web
tutorials. Each flip-flop is made up of two anti-parallel inverters connected in a loop, with
pass gates to break the feedback and connect the input signal when the controlling clock
is high. Register setup and hold times are difficult to simulate without accurate transistor
models, so care was taken to allow a generous amount of time for setup and hold. The circuit
used in this design is shown in Figures 6.7 and 6.8.
6.1.3
Decode Logic
The decode logic is a collection of complex gates to realize the conversion from 4-
or 5-bit binary to thermometer code. The logic was generated by hand using standard
logic tables and k-maps. As an example, Table 6.1 shows the desired operation of the 4-bit
binary-to-thermometer code conversion. The table for the 5-bit binary-to-thermometer code
conversion follows the same pattern.
Since larger devices require more power, the transistors in the complex gates are
all minimum size. This slows down the logic somewhat, but it is still fast enough for this
application. Figures 6.9 and 6.10 show the schematics of the two decoder blocks.
6.1.4
DEM Logic
The DEM logic was designed using the methods presented in [13]. Figure 6.11 shows
the basic operational blocks of the DEM logic for the coarse path: the rotate block and the
rotate control. The rotate control logic takes the binary output signal from the ReQ logic
and adds it to the current value stored in the pointer register. Since the current input code
38
39
gnd
vdd
in<7:0>
B<7:0>
A<7:0>
I9
gnd
GND
sub_8b
V DD
vdd
gnd
clk2
clk1
D<7:0>
I 11
clk2
clk1
B<4:0>
A<4:0>
I8
Sum<7:0>
Overflow
coarse<4>,gnd,gnd,gnd,gnd
<4:0>
coarse<7:4>,coarse<3:0>
d-register_8b
Q<7:0>
Sum<7:0>
Overflow
vdd
vdd
gnd
Figure 6.5: ReQ Circuit
gnd
GND
sub_8b
V DD
vdd
gnd
GND
sub_5b
V DD
vdd
I 12
B<7:0>
A<7:0>
coarse<7:4>,gnd,gnd,gnd,gnd
Sum<4:0>
Overflow
<7:0>
coarse<7:4>
coarse<7:4>
fine<4:0>
Figure 6.6: Full Adder Circuit
40
B
B
A
Cin
NM1
NM0
PM1
PM0
B
NM2
PM2
A
B
B
A
NM3
NM4
PM4
PM3
GND
A
A
NM5
NM6
PM6
PM5
B
B
PM7
Cin
NM7
Cin
All N-type devices:
l=240n
w=580n
A
Cin
Cin
A
VDD
All P-type devices:
l=240n
w=1.74u
NM8
PM8
A
B
Cin
Cin
B
A
NM9
NM10
NM11
PM11
PM10
PM9
NM12
PM12
NM13
PM13
Cout
Sum
Cout
Sum
Q_bar
All devices:
l=240n
w=580n
clk
gnd
vdd
vdd
vdd
Q
gnd
gnd
gnd
D
vdd
inverter_1b
gnd
gnd
gnd
vdd
clk
in
vdd
out
clk
vdd
clk
D
D
vdd
vdd
vdd
Figure 6.7: D-Latch Circuit
D
Q_bar
d-latch
clk
Q
d-latch
clk
Q
gnd
Q
gnd
clk2
gnd
clk1
Q_bar
Figure 6.8: D-Register Circuit
41
Q_bar
vdd
vdd
vdd
vdd
gnd
b<3:0>
b<2>
vdd
b3_NOT
vdd
b<0>
vdd
b<1>
b3_NOT
TC_bar<14:0>
inverter_1b
gnd
b<2>
gnd
gnd
b<2>
gnd
b3_NOT
gnd
gnd
All devices:
l=240n
w=580n
vdd
vdd
vdd
vdd
vdd b<2>
TC_bar<11> b3_NOT
vdd
b3_NOT
vdd
b<1>
vdd
vdd
b<2>
vdd
TC_bar<10>
gnd
b<2>
gnd
b<0>
gnd
vdd
b<2>
vdd
TC_bar<12>
gnd
b<1>
b<2>
b3_NOT
vdd b<0>
b<1>
vdd
b3_NOT
b<1>
vdd
gnd
gnd
gnd
vdd
TC_bar<13>
b<1>
b3_NOT
gnd
b<1>
b<0>
vdd
gnd
out b3_NOT
vdd
vdd b<2>
gnd
vdd
in
gnd
b<1>
vdd
vdd
TC_bar<14>
b<0>
b<3>
b3_NOT
b<2>
b<2>
gnd b<0>
gnd
b<1>
gnd
b<0>
vdd
b<1>
vdd
b<2>
vdd
TC_bar<9>
gnd
b<2>
gnd
b<1>
vdd
b3_NOT
TC_bar<8>
gnd
gnd b<0>
b<1>
gnd
gnd
gnd
gnd
b3_NOT
vdd
b3_NOT
in
b<2>
vdd b<1>
vdd
vdd b<0>
b<2>
vdd
vdd
b<1>
vdd
vdd
vdd
gnd
gnd
b3_NOT
gnd
b<2>
gnd
b3_NOT
gnd
b3_NOT
vdd
out TC_bar<7>
b<2>
inverter_1b
b3_NOT
gnd
gnd
vdd
vdd
b3_NOT
gnd
gnd b<0>
vdd
b<1>
vdd
TC_bar<5>
TC_bar<6>
b3_NOT
b<0>
vdd
b3_NOT
b<1>
gnd
b<2>
gnd
gnd
vdd
b3_NOT
TC_bar<4>
gnd
b<2>
gnd
b3_NOT
gnd
b<1>
gnd b<0>
gnd
vdd
gnd b<2>
vdd b<0>
b<2>
gnd
b3_NOT
vdd
vdd
vdd
vdd
b<2>
b<1>
vdd
vdd
vdd
vdd
TC_bar<3>
b<1>
vdd
b<2>
vdd
b3_NOT
vdd
b3_NOT
gnd b<2>
gnd b3_NOT
gnd b<0>
b<0>
vdd
b<1>
vdd
b<2>
vdd
TC_bar<1>
TC_bar<2>
gnd
b<1>
gnd
gnd b<2>
b3_NOT
vdd
gnd
TC_bar<0>
gnd
b<1>
b3_NOT
gnd
b<2>
gnd
b<1>
gnd b<0>
gnd
gnd
gnd
gnd
b3_NOT
gnd
gnd
b<2>
b3_NOT
gnd
gnd
b<1>
Figure 6.9: 4-Bit Binary-to-Thermometer Decoder Circuit
42
b4_bar
gnd
vdd
b<3>
vdd
gnd
TC_bar<7>
inverter_1b
gnd
out b4_bar
inverter_1b
vdd
TC_bar<23>
vdd
gnd
vdd
TC_bar<30:0>
out TC_bar<15>
gnd
gnd
b<3>
vdd
gnd
b<3>
b4_bar
gnd
vdd
b4_bar
b<3>
vdd
b4_bar in
b4_bar
b<4> in
vdd
gnd
b<3>
vdd
b4_bar
vdd
gnd
b<3>
b<2>
b<1>
b<0>
b<2>
b<2>
b<1>
b<0>
b<1>
vdd
gnd
gnd
b4_bar
b<3>
b<1>
gnd
gnd
gnd
vdd
gnd
b<1>
gnd
gnd
b<2>
vdd
TC_bar<6>
b<0>
gnd
gnd
b<0>
vdd
vdd
vdd
b<3>
b<2>
gnd
TC_bar<14>
b<0>
b<0>
vdd
TC_bar<22>
vdd
vdd
b<0>
vdd
b<3>
b<1>
vdd
gnd
gnd
gnd
gnd
vdd
gnd
gnd
b<1>
b<1>
vdd
gnd
b<0>
b4_bar
vdd
b4_bar
vdd
b4_bar
b<2>
b<2>
b<3>
b<3>
vdd
b<2>
b<3>
b4_bar
b4_bar
vdd
vdd
gnd
vdd
gnd
b4_bar
vdd
b4_bar
b4_bar
gnd
b<3>
b<2>
b<3>
b<2>
b<1>
b<2>
b<1>
b<3>
b<1>
b<3>
b<2>
b<1>
vdd
vdd
b<2>
b<1>
vdd
vdd
b<1>
gnd
gnd
gnd
b<1>
vdd
gnd
gnd
TC_bar<5>
vdd
gnd
gnd
gnd
b<1>
TC_bar<21>
vdd
vdd
gnd
gnd
gnd
gnd
vdd
TC_bar<13>
b4_bar
vdd
b<3>
gnd
b<2>
b4_bar
vdd
b4_bar
vdd
gnd
b4_bar
vdd
gnd
b<2>
b<2>
b<3>
b<3>
vdd
vdd
b4_bar
b<3>
b4_bar
TC_bar<30>
vdd
vdd
gnd
vdd
gnd
b4_bar
b4_bar
gnd
vdd
b<3>
vdd
gnd
vdd
b<1>
gnd
b<1>
vdd
vdd
vdd
b<0>
b<2>
gnd
b<0>
vdd
gnd
b<1>
gnd
TC_bar<20>
gnd
TC_bar<4>
TC_bar<12>
vdd
b<1>
b<1>
vdd
vdd
b<0>
b<3>
vdd
b<1>
vdd
gnd
vdd
b4_bar
b4_bar
gnd
gnd
b<3>
b4_bar
vdd
b<2>
b<3>
gnd
gnd
vdd
gnd
gnd
vdd
b<3>
gnd
b<2>
vdd
vdd
b<2>
b4_bar
b<3>
b<2>
TC_bar<3>
gnd
b4_bar
b4_bar
b4_bar
b<3>
b<3>
b4_bar
TC_bar<27>
vdd
TC_bar<19>
vdd
vdd
gnd
gnd
gnd
vdd
vdd
TC_bar<11>
b<2>
b<2>
b<2>
gnd
vdd
b4_bar
b<3>
b<3>
b4_bar
gnd
gnd
b<3>
b<3>
b4_bar
vdd
gnd
vdd
gnd
b4_bar
TC_bar<28>
vdd
vdd
b<2>
gnd
b<1>
b<0>
gnd
vdd
b<0>
gnd
gnd
b<3>
gnd
b<3>
b<2>
b<1>
b<2>
b4_bar
vdd
b4_bar
b<3>
b<2>
b<0>
vdd
gnd
b<2>
b<0>
b<2>
b4_bar
b<2>
gnd
vdd
gnd
b<3>
b<0>
vdd
b4_bar
b<2>
b4_bar
b<3>
b<3>
b4_bar
TC_bar<29>
vdd
vdd
gnd
vdd
gnd
vdd
vdd
gnd
gnd
gnd
gnd
vdd
gnd
gnd
vdd
gnd
b<2>
b<3>
gnd
gnd
b<2>
gnd
vdd
vdd
b<3>
b4_bar
vdd
b<2>
b<1>
b<0>
gnd
gnd
gnd
gnd
b4_bar
b4_bar
b4_bar
b<3>
b<3>
b4_bar
TC_bar<26>
vdd
vdd
TC_bar<2>
TC_bar<10>
vdd
vdd
gnd
b<1>
b<0>
b<0>
TC_bar<18>
gnd
gnd
vdd
vdd
b<2>
b<3>
b<1>
b<0>
gnd
gnd
gnd
b<2>
b<0>
vdd
vdd
gnd
b<1>
b<0>
vdd
b<3>
vdd
vdd
gnd
gnd
b<3>
b<1>
b<0>
b4_bar
vdd
vdd
vdd
b<2>
b<1>
gnd
b4_bar
b<2>
b<1>
b4_bar
vdd
gnd
vdd
b<0>
gnd
b<3>
b<2>
vdd
b<1>
vdd
gnd
b<3>
b4_bar
b<2>
gnd
vdd
b<3>
b<1>
b<1>
gnd
gnd
vdd
vdd
gnd
vdd
vdd
b<2>
gnd
vdd
b<2>
b<3>
vdd
b<1>
b<1>
TC_bar<17>
b<1>
gnd
TC_bar<9>
gnd
gnd
vdd
vdd
b<2>
vdd
gnd
TC_bar<1>
gnd
gnd
vdd
b4_bar
gnd
b<3>
b<2>
b<2>
b<3>
b<2>
b<3>
vdd
vdd
b<2>
b<3>
b4_bar
gnd
vdd
vdd
vdd
b<1>
b<0>
b<1>
gnd
vdd
vdd
b<1>
gnd
gnd
gnd
gnd
b<0>
TC_bar<8>
TC_bar<16>
b<1>
b<0>
b<3>
vdd
vdd
b<0>
gnd
gnd
TC_bar<24>
b<2>
gnd
gnd
vdd
vdd
vdd
gnd
gnd
b<0>
b<2>
vdd
vdd
vdd
gnd
gnd
b<1>
b<0>
b4_bar
b<1>
vdd
b4_bar
b4_bar
b<3>
b<0>
b4_bar
b<1>
b<0>
gnd
b4_bar
vdd
gnd
b<3>
b<2>
vdd
b<3>
b<3>
b<1>
b4_bar
b<2>
b<1>
gnd
gnd
vdd
gnd
vdd
vdd
TC_bar<25>
b<1>
b4_bar
vdd
b4_bar
b<3>
b<3>
gnd
gnd
b<2>
b<2>
b<1>
b4_bar
vdd
gnd
vdd
b<2>
vdd
b<2>
vdd
gnd
b<4:0>
gnd
vdd
gnd
vdd
vdd
gnd
vdd
vdd
gnd
gnd
vdd
gnd
vdd
gnd
gnd
vdd
vdd
gnd
vdd
gnd
gnd
vdd
vdd
gnd
vdd
gnd
vdd
gnd
vdd
gnd
gnd
vdd
43
gnd
Figure 6.10: 5-Bit Binary-to-Thermometer Decoder Circuit
gnd
TC_bar<0>
Table 6.1: Logic Table for 4-Bit Binary-to-Thermometer Code Conversion
b3 b2 b1
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
b0 14 13 12
1
1 1 1
0
0 1 1
1
0 0 1
0
0 0 0
1
0 0 0
0
0 0 0
1
0 0 0
0
0 0 0
1
0 0 0
0
0 0 0
1
0 0 0
0
0 0 0
1
0 0 0
0
0 0 0
1
0 0 0
0
0 0 0
11
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
10
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
9
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
8
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
5
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
4
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
3
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
2
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
is used to calculate the control signal for the following cycle, this computation is performed
outside the loop of the modulator and has no bearing on the critical path of the overall ADC.
The current value in the pointer register is used as the control signal to the rotate
block, which rotates the thermometer-coded output from the decoder a fixed number of digit
positions in response to the pointer control value. The rotate block is made up of 4 separate
rotate cells that each conditionally rotate by a fixed amount, depending on the pointer value.
For example, the “rotate 2” block passes the input unchanged to its output if bit 1 of the
pointer control signal is not asserted, or rotates the input signal by 2 positions if the control
bit is asserted. In other words, the “rotate 2” cell passes bit 0 of its input to bit 2 of its
output, bit 1 of its input to bit 3 of its output, and so on, as illustrated on the right hand
side of Figure 6.11. Each rotate cell is designed with transmission gates. The Figure actually
shows the block diagram for the 4-bit coarse case. The 5-bit fine DEM has a 5-bit pointer
and an extra rotate cell that rotates by 16. Figure 6.12 shows the DEM schematics.
44
From Decoder
In Position Out Position
15
From ReQ
4
Adder
P0
P1
P2
4
Ptr Reg
P3
Rotate 1
Rotate 2
P1=0
P1=1
0
1
2
3
0
1
2
3
2
3
4
5
13
14
15
13
14
15
15
0
1
Rotate 4
Rotate 8
To DAC
Figure 6.11: Block Diagram of DEM Circuitry
6.2
Circuit Simulations
The target clock rate for this design is 50 MHz. Due to the design used for the two-
step quantizer and integrators, the computations in the digital feedback must be completed
during one-half clock cycle. This requires a worst-case delay of less than 10 ns. The “feedback
path” includes the encoder blocks, the ReQ, the decode blocks, and the DEM logic. (A small
amount of extra time must be allotted for the comparators in the internal quantizer at the
beginning and the DACs at the end, so the actual time available is less than 10 ns.) The
critical path for the digital feedback involves the following: a 4-bit bubble decode, a 4-bit
thermometer code-to-binary encoder, an 8-bit adder and a 5-bit adder in the ReQ block,
a 5-bit binary-to-thermometer decoder, and a 31-line DEM consisting of 5 stages of pass
gates. Achieving a transistor-level simulation in which all of these elements operated in the
worst-case condition proved to be very difficult, as the resulting output from a worst-case
simulation of some blocks did not allow for the worst-case simulation of connected blocks.
To simulate an absolute maximum delay, simulations were run on each block separately,
carefully loading each block to mimic its connected operation. Figures 6.13, 6.14, 6.15, 6.16,
and 6.17 show timing diagrams for each of the blocks in the critical path, and Table 6.2
shows the overall results of these simulations. The overall delay should be acceptable; more
45
fine_bin<4:0>
fine_th<30:0>
coarse_bin<3:0>
gnd
vdd
clk2
clk1
rot_31_cont_bar<4>
rot_31_cont<4>
sel_bar
sel
in<30:0>
rot_16_cont_bar<3>
rot_16_cont<3:0>
rot_16_31_bit
rot_31_cont<4:0>
rot_8_16_bit
adder_4b
B<4:0>
A<4:0>
out<30:0>
B<3:0>
A<3:0>
Sum<4:0>
Overflow
rot_31_cont_bar<3>
adder_5b
rot_16_cont<2>
sel_bar
sel
in<30:0>
rot_16_cont_bar<2>
rot_31_cont<3>
Sum<3:0>
Overflow
out<15:0>
clk2
clk1
clk2
clk1
D<3:0>
clk2
clk2
clk1
D<4:0>
Q<4:0>
rot_16_cont<1>
rot_31_cont_bar<4:0>
rot_31_cont<4:0>
rot_31_cont_bar<2>
rot_31_cont<2>
sel_bar
sel
in<30:0>
rot_16_cont_bar<1>
rot_16_cont_bar<3:0>
rot_16_cont<3:0>
out<15:0>
Q_bar<4:0>
d-register_5b
out<30:0>
Q_bar<3:0>
Q<3:0>
rot_4_16_bit
d-register_4b
rot_8_31_bit
clk1
sel_bar
sel
in<15:0>
vdd
vdd
vdd
vdd
gnd
gnd
sel
sel_bar
vdd
vdd
gnd
gnd
vdd
VDD
gnd
in<15:0>
gnd
rot_16_cont<3>
gnd
GND
vdd
VDD
GND
gnd
vdd
vdd
vdd
vdd
gnd
gnd
gnd
gnd
vdd
vdd
vdd, coarse_th<14:0>
gnd
gnd
sel_bar
sel
rot_4_31_bit
in<15:0>
vdd
vdd
vdd
out<30:0>
rot_2_16_bit
vdd
gnd
gnd
rot_16_cont<0>
rot_31_cont_bar<1>
sel_bar
sel
in<30:0>
rot_16_cont_bar<0>
rot_31_cont<1>
out<15:0>
sel_bar
sel
rot_2_31_bit
in<15:0>
vdd
out<30:0>
rot_1_16_bit
vdd
gnd
gnd
coarse_th<14:0>
gnd
gnd
gnd
vdd
vdd
gnd
rot_31_cont_bar<0>
rot_31_cont<0>
out<15:0>
sel_bar
sel
in<30:1>
coarse_out<15:0>
vdd
rot_1_31_bit
vdd
gnd
46
gnd
Figure 6.12: DEM Circuitry
out<30:0>
fine_out<30:0>
Table 6.2: Timing Results for the Critical Path
Block
Equivalent
Name
Fan Out
1) Bubble Decode
1 inverter
2) Therm-to-Bin Encoder
8 inverters
3) 8-bit Subtractor
25 inverters
4) 5-bit Subtractor
35 inverters
5) Bin-to-Therm Decoder 5 layers of muxes
and 31-line DEM and 2 inverters
TOTAL:
WorstCase Delay
0.15 ns
0.23 ns
1.94 ns
1.46 ns
2.50
∼ 6.28
ns
ns
simulations that take into account delays of the analog components involved are needed to
thoroughly verify this.
6.3
Conclusion
The circuits presented in this chapter are basic circuit designs such as one could find
in basic textbooks. A few blocks, such as the decoders, were done as complex logic gates
using basic design methods. The design has an overall worst-case delay of under 7 ns, which
is less than the maximum allowable delay of 10 ns.
47
Figure 6.13: Timing Simulation for ReQ Bubble Decode Block
V )
(
- 1. 0
0. 0
1. 0
2. 0
3. 0
0. 0
1. 0
2. 0
3. 0
160. 0n
:
:
:
:
bi t =" 14"
bi t =" 6" ;
bi t =" 14"
bi t =" 6" ;
A: ( 160. 104n 1. 25015)
B: ( 160. 249n 1. 24973)
( V )
48
bi t =" 13"
bi t =" 5" ;
bi t =" 13"
bi t =" 5" ;
160. 1n
:
:
A
:
:
bi t =" 12"
bi t =" 4" ;
bi t =" 12"
bi t =" 4" ;
del t a: ( 144. 834p - 417. 415u)
s l ope: - 2. 88204M
:
:
:
:
:
:
:
:
:
:
:
:
bi t =" 10"
bi t =" 2" ;
bi t =" 10"
bi t =" 2" ;
160. 2n
t i me ( s )
bi t =" 11"
bi t =" 3" ;
bi t =" 11"
bi t =" 3" ;
T r a ns i ent Res pons e
B
:
:
:
:
bi t =" 9" ;
bi t =" 1" ;
bi t =" 9" ;
bi t =" 1" ;
16: 07: 32 2003
ADC_l i b bubbl e_dec ode_4b_t i mi ng s c hemat i c : Oc t 30
160. 3n
:
:
:
:
bi t =" 8" ;
bi t =" 0" ;
bi t =" 8" ;
bi t =" 0" ;
:
:
bi t =" 7" ;
bi t =" 7" ;
160. 4n
Figure 6.14: Timing Simulation for ReQ Encoder Block
V )
(
- 1. 0
0. 0
1. 0
2. 0
3. 0
- 1. 0
0. 0
1. 0
2. 0
3. 0
9. 90n
:
:
:
:
:
:
bi t =" 1
bi t =" 5
A
bi t =" 1
bi t =" 4
del t a: ( 225. 826p 70. 0478u)
s l ope: 310. 184K
10. 0n
:
:
:
:
t i me ( s
bi t =" 1
bi t =" 3
10. 1n
:
:
)
:
:
:
:
bi t =" 9
bi t =" 1
10. 2n
B
bi t =" 2" ; / out put <3: 0>
bi t =" 0" ; / out put <3: 0>
bi t =" 1
bi t =" 2
Tr ans i ent Res pons e
:
:
10. 3n
bi t =" 8
bi t =" 0
: Oc t 30 16: 20: 55 2003
ADC_l i b enc _t her m_t o_bi n_4_bi t _2s _t i mi ng s c hemat i c
bi t =" 3" ; / out put <3: 0>
bi t =" 1" ; / out put <3: 0>
bi t =" 1
bi t =" 6
A: ( 10. 0493n 1. 25699)
B: ( 10. 2751n 1. 25706)
( V )
49
:
bi t =" 7
10. 4n
Figure 6.15: Timing Simulation for ReQ 8-bit Subtractor Block
V)
(
- 1. 0
0. 0
1. 0
2. 0
3. 0
- 1. 0
0. 0
1. 0
2. 0
3. 0
9. 50n
:
:
:
:
A
10. 2n
bi t =" 7" ; / net 2<0: 7
bi t =" 3" ; / net 2<0: 7
bi t =" 7" ; / t o_l oad<
bi t =" 3" ; / t o_l oad<
A: (10.1011n 1.25106) delta: (1.9399n 645.227u)
slope: 332.609K
B: (12.041n 1.2517)
( V)
50
:
:
:
:
10. 9n
bi t =" 6" ; / net 2<0: 7
bi t =" 2" ; / net 2<0: 7
bi t =" 6" ; / t o_l oad<
bi t =" 2" ; / t o_l oad<
t i me ( ) s
:
:
:
:
Tr ans i ent Res pons e
11. 6n
bi t =" 5" ; / net 2<0: 7
bi t =" 1" ; / net 2<0: 7
bi t =" 5" ; / t o_l oad<
bi t =" 1" ; / t o_l oad<
B
:
:
:
:
12. 3n
2003
ADC_l i b s ub_8b_1 _t i mi ng s c hemat i c : Oc t 30 16: 49: 50
bi t =" 4" ; / net 2<0: 7
bi t =" 0" ; / net 2<0: 7
bi t =" 4" ; / t o_l oad<
bi t =" 0" ; / t o_l oad<
13. 0n
Figure 6.16: Timing Simulation for ReQ 5-bit Subtractor Block
V)
(
- 1. 0
0. 0
1. 0
2. 0
3. 0
- 1. 0
0. 0
1. 0
2. 0
3. 0
9. 50n
:
:
:
:
A: (10.101n 1.2501)
B: (11.5829n 1.25002)
( V)
51
A
:
:
delta: (1.48183n -80.9507u)
slope: -54.6287K
10. 2n
bi t =" 4" ; / t o_l oad<4: 0>
bi t =" 1" ; / t o_l oad<4: 0>
bi t =" 4" ; / net 1
bi t =" 4" ; / net 1
bi t =" 3" ; / net 1
bi t =" 3" ; / net 1
:
:
10. 9n
t i me ( ) s
B
11. 6n
bi t =" 2" ; / net 1
bi t =" 2" ; / net 1
bi t =" 3" ; / t o_l oad<4: 0>
bi t =" 0" ; / t o_l oad<4: 0>
:
:
Tr ans i ent Res pons e
ADC_l i b s ub_8b_2 _t i mi ng s c hemat i c : Feb
:
:
:
:
:
12. 3n
13. 0n
bi t =" 0" ; / net 1
bi t =" 0" ; / net 1
bi t =" 2" ; / t o_l oad<4: 0>
bi t =" 1" ; / net 1
bi t =" 1" ; / net 1
8 20: 38: 11 2004
Figure 6.17: Timing Simulation for ReQ Decoder Block
V)
(
- 1. 0
0. 0
1. 0
2. 0
3. 0
- 1. 0
0. 0
1. 0
2. 0
3. 0
111n
A: (111.855n 1.25)
B: (114.35n 1.25001)
( V)
52
bi t =" 1
bi t =" 6
:
:
bi t =" 1
bi t =" 5
bi t =" 2
bi t =" 2
112n
:
:
:
:
delta: (2.49489n 10.1035u)
slope: 4.04969K
bi t =" 3
bi t =" 2
:
A
bi t =" 4" ; / net 18<0: 4>
bi t =" 1" ; / net 18<0: 4>
:
:
:
:
:
:
:
113n
bi t =" 1
bi t =" 4
bi t =" 2
bi t =" 2
:
:
:
:
:
:
:
:
:
:
114n
t i me ( ) s
bi t =" 1
bi t =" 3
bi t =" 2
bi t =" 1
B
bi t =" 1
bi t =" 2
bi t =" 2
bi t =" 1
bi t =" 3" ; / net 18<0: 4>
bi t =" 0" ; / net 18<0: 4>
Tr ans i ent Res pons e
:
bi t =" 9
bi t =" 1
:
:
:
:
116n
bi t =" 8
bi t =" 0
bi t =" 2
bi t =" 1
bi t =" 2" ; / net 18<0: 4>
8 21: 00: 30 2004
bi t =" 2
bi t =" 1
115n
:
:
:
:
ADC_l i b t her mo_c ode_5b_ t i mi ng s c hemat i c : Feb
:
:
:
117n
bi t =" 7
bi t =" 2
bi t =" 1
Chapter 7
Conclusion
7.1
Contributions
The intended contributions of this research are as follows:
• A new presentation and mathematical analysis of the problems involved with segmenting the digital word in a ∆Σ ADC feedback path.
• Design of two potential methods to overcome these problems: a calibration method
and a requantization method.
• Simulations for these two potential solutions, along with an analysis and comparison.
• Designs for the circuits of the ReQ method to be used with a 50 MHz ∆Σ ADC design
with 8-bit internal quantization and a desired output resolution of over 15 bits, along
with timing and functional simulations.
A paper presenting this work has been accepted for publication at the 2004 IEEE
International Symposium on Circuits and Systems [15].
7.2
Summary of Results
Chapter 3 presented that segmentation of the DAC structures in the feedback path
of ∆Σ ADCs is desirable. It simplifies circuitry and allows for higher levels of internal
quantization. However, the mismatch between the two DAC banks adds an additional source
of error to the system, significantly reducing the effective SNR of the overall modulator. Two
potential solutions were proposed: one to calibrate the DAC banks and remove the mismatch,
53
and the other to requantize the segmented signals and frequency shape the error resulting
from the mismatch away from the band of interest.
The calibration method described in Chapter 4 adds no extra logic to the feedback
path of the ∆Σ ADC, insuring that the feedback path does not limit the overall clock speed.
It does, however, add an initialization routine to set the calibration values, which must be
run before regular operation can occur. This calibration routine must calibrate the DACs
for each stage of the ∆Σ modulator, increasing the time required to perform calibration for
high-order modulators. In the test case of a second-order modulator with an OSR of 20,
an internal quantization of (4+4)-bit, and the coarse and fine percent mismatches scaled
assuming a 16:1 size ratio between coarse and fine elements, the calibration method achieves
an average SNR of 98dB at a mismatch of 1%. This is only 0.5dB less than the SNR of the
full 8-bit DEM reference case.
The ReQ method described in Chapter 5 does add logic to the feedback path, but it
requires no initialization or startup routine. The critical path through the required logic is
fairly short, and can be optimized to limit the effect of the feedback path logic on the overall
clock speed. The DC offset inserted by the ReQ logic can be removed by a small change in
the DAC structure, and the overall SNR of this method is acceptable, if a little worse than
that of the calibration method. In the standard test case at 1% fine element mismatch, the
ReQ method achieves an average SNR of about 96dB, which is only 2dB less than the SNR
of the full 8-bit DEM reference case.
The ReQ method scales better for use with higher-order modulators. It also has fewer
implementation-related random factors to influence its actual operation in silicon, as it is
completely digital. For these reasons, it is the chosen method to use for the specific ∆Σ
design. The circuits were designed (discussed in Chapter 6, and shown in full in Appendix
A) to minimize power consumption while still meeting the timing goals. The total delay
achieved through the feedback path was about 7 ns.
7.3
Areas for Potential Future Research
Some areas of suggested research on the material presented in this thesis are:
54
• Further develop and verify the analysis of the DC offset introduced by the ReQ method.
More specifically identify its source and how to avoid or more completely remove it,
preferably using a digital method.
• Adapt a higher-order DEM algorithm that does not introduce significant additionally
delay for use in the ADC. This would permit the use of a higher-order ReQ circuit and
provide higher output resolution.
• Expand existing background calibration methods that calibrate DAC elements into one
which will provide background calibration between the coarse and fine banks [14].
• Further optimize the digital circuitry of the ∆Σ feedback path. This includes higherorder or more efficient methods of performing the ReQ modulation, as well as more
efficient circuits to implement all functions.
55
Appendix
56
Appendix A
Complete Circuit Schematics
I7
vdd
bubble_decode_4b
TC<15:1>
one_high<15:1>
I5
vdd
one_high<15:1>
gnd
I6
vdd
bubble_decode_4b
TC<15:1>
one_high<15:1>
I4
vdd
bit<3:0>
_bi
t
enc_therm_to_bin_4
one_high<15:1>
yf<3:0>
gnd
gnd
gnd
gnd
vdd
zf<4:0>
gnd
coarse_out<15:0>
fine_out<30:0>
clk1 clk2
I3
TC_bar<30:0>
gnd
b<4:0>
DEM
fine_bin<4:0>
fine_th<30:0>
thermo_code_convert_5b
zf<4:0>
vdd
clk2
clk2
coarse_bin<3:0>
coarse_th<14:0>
vdd
fine<4:0>
clk1
vdd
clk2
I1
zc<3:0>
coarse<7:4>
in<7:0>
ReQ
clk1
TC_bar<14:0>
clk1
vdd
yc<7:4>,yf<3:0>
gnd
b<3:0>
I0
gnd
vdd
vdd
I2
thermo_code_convert_4b
zc<3:0>
gnd
fine<15:1>
gnd
clk2
yc<7:4>
gnd
vdd
vdd
clk1
bit<3:0>
enc_therm_to_bin_4_bit_2s
gnd
fine<15:1>
gnd
coarse<15:1>
coarse<15:1>
gnd
gnd
vdd
vdd
vdd
vdd
Top Level Schematic
gnd
A.1
Figure A.1: Overall Schematic for Digital Feedback Path
57
coarse_DAC_bar<15:0>
fine_DAC_bar<30:0>
out
vdd
vdd
A
vdd
I33
in
out
NOR3
B
inverter_1b
vdd
out
vdd
TC<7>
vdd
TC<15>
vdd
I31
out
inverter_1b
gnd
Q
vdd
out
TC<6>
in
vdd
I19
NOR3
B
one_high<7>
Q
C
gnd
TC<8>
TC<7>
out
I6
vdd
A
NOR3
B
one_high<6>
Q
C
inverter_1b
gnd
NOR3
B
one_high<13>
Q
TC<5>
C
gnd
in
vdd
I20
one_high<12>
Q
TC<4>
C
gnd
in
vdd
I21
out
one_high<11>
Q
TC<3>
C
gnd
in
in
out
vdd
I18
vdd
one_high<10>
Q
TC<2>
C
gnd
out
in
vdd
I17
vdd
gnd
gnd
gnd
vdd
NOR3
B
gnd
TC<4>
TC<3>
out
I1
vdd
A
NOR3
B
one_high<2>
Q
C
gnd
gnd
gnd
I15
vdd
NOR3
one_high<9>
Q
TC<1>
C
inverter_1b
vdd
A
B
one_high<3>
Q
C
gnd
gnd
in
vdd
I16
TC<3>
TC<2>
out
I0
vdd
A
B
NOR3
C
inverter_1b
gnd
gnd
gnd
gnd
gnd
out
I3
vdd
A
inverter_1b
vdd
gnd
vdd
in
TC<10>
TC<4>
gnd
gnd
NOR3
gnd
TC<11>
TC<5>
I14
vdd
inverter_1b
vdd
I24
gnd
gnd
A
B
one_high<4>
Q
C
inverter_1b
vdd
gnd
vdd
vdd
I27
NOR3
B
gnd
gnd
NOR3
gnd
TC<11>
out
I2
vdd
A
I12
vdd
A
B
inverter_1b
TC<12>
TC<5>
gnd
vdd
TC<12>
TC<6>
inverter_1b
vdd
gnd
vdd
in
TC<13>
gnd
gnd
gnd
NOR3
gnd
vdd
I26
C
I13
vdd
A
B
one_high<5>
Q
gnd
out
NOR3
B
vdd
TC<13>
out
I7
vdd
A
gnd
vdd
TC<14>
TC<6>
inverter_1b
vdd
gnd
vdd
in
vdd
I25
TC<7>
gnd
out
I8
vdd
A
vdd
TC<14>
vdd
TC<15>
vdd
gnd
vdd
vdd
in
vdd
I28
inverter_1b
TC<9>
out
I4
vdd
A
gnd
gnd
TC<10>
TC<8>
gnd
inverter_1b
TC<11>
TC<9>
C
gnd
TC<12>
gnd
inverter_1b
one_high<14>
inverter_1b
TC<13>
one_high<8>
Q
C
gnd
NOR3
B
vdd
I22
I9
vdd
gnd
in
vdd
I29
in
A
gnd
vdd
TC<13>
NOR3
B
gnd
gnd
in
out
inverter_1b
inverter_1b
gnd
TC<14>
vdd
I23
gnd
gnd
gnd
vdd
I32
in
I5
vdd
A
gnd
in
TC<8>
Q
C
gnd
vdd
TC<13>
one_high<15>
TC<9>
gnd
TC<14>
TC<10>
gnd
one_high<15:1>
I11
vdd
gnd
vdd
TC<15:1>
vdd
inverter_1b
gnd
gnd
vdd
I34
Figure A.2: Bubble Decode Logic
58
gnd
in
vdd
TC<15>
gnd
gnd
vdd
vdd
vdd
Bubble Decode
gnd
A.2
one_high<1>
Q
A.2.1
Inverter
vdd
PM0
"pch"
l:240.0n
w=1.74u
fingers= 3
m:1
out
in
NM0
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
gnd
Figure A.3: Inverter
59
vdd
3 Input Nor
A
B
P-type devices:
l=240n
w=5.22u
C
N-type devices:
l=240n
w=580n
C
vdd
B
vdd
A
vdd
B
gnd
vdd
gnd
Q
Q
A
gnd
gnd
A.2.2
Figure A.4: Nor Gate
60
C
gnd
vdd
vdd
PM32
PM33
"pch"
"pch"
"pch"
l:240.0n
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
m:1
vdd
PM1
PM37
"pch"
"pch"
l:240.0n
l: 240.0n
w=1.74u
w=1.74u
fingers=3
fingers=3
m:1
m:1
NM1
NM97
"nch"
"nch"
l:240.0n
l:240.0n
gnd
w=1.16u
gnd
fingers:1
bit<3>
w=1.16u
gnd
one_high<15:1>
PM31
"pch"
vdd
gnd
PM30
vdd
2’s Complement Encoder
m:1
PM34
fingers:1
m:1
"pch"
l:240.0n
bit<3:0>
one_high<15>
w=1.74u
fingers=3
m:1
bit<2>
NM30
NM34
NM33
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fi ngers:1
fingers:1
m:1
m:1
m:1
"nch"
vdd
NM35
"nch"
: 40.0n
l2
w=1.16u
PM36
"pch"
m:1
gnd
NM36
fingers:1
m:1
l:240.0n
one_high<14>
w=1.74u
fingers=3
m:1
NM37
NM38
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
bit<1>
NM39
NM32
"nch"
"nch"
l:240.0n
gnd
w=1.16u
fingers:1
vdd
: 40.0n
l2
m:1
PM35
one_high<13>
"pch"
l:240.0n
w=1.74u
NM45
NM46
NM48
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
fingers=3
m:1
bit<0>
NM31
"nch"
l:240.0n
w=1.16u
gnd
A.3
one_high<12>
NM44
NM43
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
fingers:1
m:1
one_high<11>
NM61
NM63
NM64
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
one_high<10>
NM60
NM58
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
Both N and P type devices in
array are w/l=540n/240n.
Inverters are
P:w/l=1.74u/240n
N:w/l=1.16u/240n.
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<9>
NM52
NM49
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<8>
NM53
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<7>
NM94
"nch"
l:240.0n
NM95
NM96
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
NM91
NM90
"nch"
"nch"
one_high<6>
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<5>
NM87
NM85
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<4>
NM82
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<3>
NM78
NM77
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<2>
NM75
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<1>
NM72
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
Figure A.5: 2’s Complement Encoder
61
Unsigned Encoder
vdd
vdd
gnd
PM1
"pch"
PM31
PM32
PM33
"pch"
"pch"
"pch"
"pch"
l:240.0n
l:240.0n
l:240.0n
l:240.0n
l:240.0n
w=1.74u
fingers=3
one_high<15:1>
w=580.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
m:1
m:1
"nch"
vdd
l:240.0n
gnd
w=1.16u
gnd
bit<3>
NM1
fingers:1
vdd
PM30
m:1
PM34
"pch"
l:240.0n
bit<3:0>
one_high<15>
w=1.74u
fingers=3
m:1
bit<2>
NM30
NM34
NM33
"nch"
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fi ngers:1
fingers:1
m:1
m:1
m:1
m:1
"nch"
vdd
NM35
: 40.0n
l2
w=1.16u
PM36
"pch"
gnd
NM36
fingers:1
m:1
l:240.0n
one_high<14>
w=1.74u
fingers=3
m:1
NM37
NM38
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
bit<1>
NM39
NM32
"nch"
"nch"
l:240.0n
gnd
w=1.16u
fingers:1
vdd
: 40.0n
l2
m:1
PM35
one_high<13>
"pch"
l:240.0n
w=1.74u
NM45
NM46
NM48
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
fingers=3
m:1
bit<0>
NM31
"nch"
l:240.0n
w=1.16u
gnd
A.4
one_high<12>
NM44
NM43
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
fingers:1
m:1
one_high<11>
NM61
NM63
NM64
"nch"
"nch"
"nch"
l:240.0n
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
one_high<10>
NM60
NM58
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
Both N and P type devices in
array are w/l=540n/240n.
Inverters are
P:w/l=1.74u/240n
N:w/l=1.16u/240n.
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<9>
NM52
NM49
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<8>
NM53
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<7>
NM94
"nch"
l:240.0n
NM95
NM96
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
fingers:1
m:1
m:1
m:1
NM91
NM90
"nch"
"nch"
one_high<6>
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<5>
NM87
NM85
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<4>
NM82
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<3>
NM78
NM77
"nch"
"nch"
l:240.0n
l:240.0n
w=580.0n
w=580.0n
fingers:1
fingers:1
m:1
m:1
one_high<2>
NM75
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
one_high<1>
NM72
"nch"
l:240.0n
w=580.0n
fingers:1
m:1
Figure A.6: Unsigned Encoder
62
Figure A.7: Requantization Logic
63
gnd
vdd
in<7:0>
B<7:0>
A<7:0>
I9
gnd
GND
sub_8b
V DD
vdd
gnd
clk2
clk1
D<7:0>
I 11
clk1
clk2
B<4:0>
A<4:0>
Sum<7:0>
Overflow
coarse<4>,gnd,gnd,gnd,gnd
<4:0>
coarse<7:4>,coarse<3:0>
d-register_8b
Q<7:0>
Sum<7:0>
Overflow
vdd
vdd
gnd
I8
gnd
GND
sub_8b
V DD
vdd
gnd
GND
sub_5b
V DD
vdd
I 12
B<7:0>
A<7:0>
coarse<7:4>,gnd,gnd,gnd,gnd
Sum<4:0>
Overflow
<7:0>
coarse<7:4>
coarse<7:4>
fine<4:0>
A.5
ReQ
64
Figure A.8: 8-bit Subtractor
Overflow
out
gnd
vdd
xor2
GND
VDD
Sum <7:0>
B
A
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<7>
A
A<7>
gnd
inverter_1b
Sum
B<7>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<6>
A
A<6>
gnd
inverter_1b
Sum
B<6>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<5>
A
A<5>
gnd
inverter_1b
Sum
B<5>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<4>
A
A<4>
gnd
inverter_1b
Sum
B<4>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<3>
A
A<3>
gnd
inverter_1b
Sum
B<3>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<2>
A
A<2>
gnd
inverter_1b
Sum
B<2>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<1>
A
A<1>
gnd
inverter_1b
Sum
B<1>
B
out
in
Cin
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<0>
A
A<0>
gnd
inverter_1b
Sum
B<0>
B
out
in
Cin
VDD
vdd
VDD
A<7:0>
B<7:0>
GND
VDD
A.5.1
8-bit Subtractor
65
Figure A.9: Full Adder Design
B
B
NM1
NM2
A
B
B
A
NM3
NM4
PM4
PM3
GND
A
A
VDD
NM5
NM6
PM6
PM5
B
B
PM7
Cin
NM7
Cin
All N-type devices:
l=240n
w=580n
A
Cin
NM0
PM1
B
PM2
All P-type devices:
l=240n
w=1.74u
A
Cin
Cin
A
PM0
NM8
PM8
A
B
Cin
Cin
B
A
NM9
NM10
NM11
PM11
PM10
PM9
NM12
PM12
NM13
PM13
Cout
Sum
Cout
Sum
A.5.2
Full Adder
66
Figure A.10: 5-bit Subtractor
Sum<4:0>
Overflow
out
gnd
xor2
vdd
GND
VDD
B
A
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<4>
Sum
A
A<4>
gnd
inverter_1b
B<4>
B
out
Cin
in
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<3>
Sum
A
A<3>
gnd
inverter_1b
B<3>
B
out
Cin
in
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<2>
Sum
A
A<2>
gnd
inverter_1b
B<2>
B
out
Cin
in
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<1>
Sum
A
A<1>
gnd
inverter_1b
B<1>
B
out
Cin
in
VDD
vdd
Cout
GND
GND
VDD
VDD
GND
Full Adder
Sum<0>
Sum
A
A<0>
gnd
inverter_1b
B<0>
B
out
in
Cin
VDD
vdd
VDD
A<4:0>
B<4:0>
GND
VDD
A.5.3
5-bit Subtractor
gnd
vdd
D-Register Bank
Q<7:0>
D<4>
clk1
clk2
D<3>
clk1
clk2
D<2>
clk1
clk2
D<1>
clk1
clk2
D<0>
clk1
clk2
gnd
vdd
vdd
gnd
Q<6>
D
Q
Q<5>
d-register
Q_bar
clk1
clk2
gnd
clk2
clk2
vdd
clk1
Q
d-register
Q_bar
D
Q
Q<4>
d-register
clk1
Q_bar
clk2
gnd
D<5>
D
clk1
vdd
clk2
Q_bar
clk2
D
Q
d-register
clk1
Q_bar
clk2
D
Q<3>
gnd
clk1
d-register
clk1
vdd
D<6>
Q<7>
d-register
clk1
clk2
D
Q
Q
d-register
clk1
Q_bar
clk2
D
clk1
Q<2>
Q_bar
gnd
clk2
vdd
clk2
clk1
Q
Q<1>
gnd
clk1
D
vdd
D<7>
vdd
D<7:0>
Q
Q<0>
d-register
clk2
Q_bar
gnd
A.5.4
Figure A.11: D-Register Bank
67
D-Register
D
D
vdd
vdd
vdd
A.5.5
D
Q_bar
d-latch
clk
Q
d-latch
clk
Q
gnd
Q
gnd
clk2
gnd
clk1
Q_bar
Figure A.12: D-Register
68
Q_bar
A.5.6
D-Latch
Q_bar
clk
vdd
All devices:
l=240n
w=580n
gnd
vdd
vdd
Q
gnd
gnd
gnd
D
vdd
inverter_1b
gnd
clk
in
gnd
gnd
vdd
vdd
out
clk
vdd
clk
Figure A.13: D-Latch
69
vdd
gnd
b<3:0>
b<2>
vdd
b<0>
vdd
b<1>
b3_NOT
gnd
b<1>
b<2>
b3_NOT
gnd
gnd
gnd
b3_NOT
gnd
gnd
vdd
vdd b<2>
TC_bar<11> b3_NOT
gnd
b3_NOT
gnd
All devices:
l=240n
w=580n
vdd
vdd
vdd
vdd b<0>
vdd
b<1>
vdd
b<2>
vdd
vdd
b<2>
gnd
b<0>
b<2>
gnd
gnd
gnd
b<1>
b<2>
gnd
TC_bar<12>
gnd
b<1>
b3_NOT
b<2>
vdd
vdd
gnd
out b3_NOT
b<1>
vdd
b3_NOT
vdd
TC_bar<13>
gnd
b<1>
inverter_1b
gnd
vdd
vdd b<2>
gnd
vdd
in
vdd
TC_bar<14>
b<0>
b<3>
b3_NOT
b<2>
b<1>
vdd
b3_NOT
TC_bar<14:0>
vdd
vdd
b<0>
vdd
vdd
vdd
4-bit Decoder Logic
b3_NOT
vdd
vdd
TC_bar<10>
b<2>
gnd b<0>
gnd
b<1>
gnd
b<0>
vdd
b<1>
vdd
b<2>
vdd
TC_bar<9>
gnd
b<2>
gnd
b<1>
vdd
b3_NOT
TC_bar<8>
gnd b<0>
b<1>
gnd
gnd
gnd
gnd
b<2>
gnd
b3_NOT
gnd
gnd
b3_NOT
vdd
b3_NOT
in
b<2>
vdd b<1>
vdd
vdd b<0>
b<2>
vdd
vdd
b<1>
vdd
vdd
vdd
gnd
gnd
b3_NOT
vdd
out TC_bar<7>
b<2>
inverter_1b
gnd
b3_NOT
gnd
vdd
b3_NOT
gnd
gnd b<0>
b<0>
vdd
b<1>
vdd
vdd
vdd
b3_NOT
TC_bar<5>
TC_bar<6>
b3_NOT
b<1>
gnd
b<2>
gnd
gnd
vdd
b3_NOT
TC_bar<4>
gnd
b<2>
gnd
b3_NOT
gnd
b<1>
gnd b<0>
gnd
vdd
gnd b<2>
vdd b<0>
b<2>
gnd
b3_NOT
vdd
vdd
vdd
vdd
b<2>
b<1>
vdd
vdd
TC_bar<3>
b<1>
vdd
b<2>
vdd
b3_NOT
vdd
b3_NOT
gnd b<2>
gnd b3_NOT
gnd b<0>
b<0>
vdd
b<1>
vdd
b<2>
vdd
TC_bar<1>
TC_bar<2>
gnd
b<1>
gnd
gnd b<2>
b3_NOT
vdd
gnd
TC_bar<0>
gnd
b<1>
b3_NOT
gnd
b<2>
gnd
b<1>
gnd b<0>
gnd
gnd
gnd
b3_NOT
gnd
gnd
vdd
vdd
b3_NOT
gnd
gnd
b<1>
b<2>
gnd
A.6
Figure A.14: 4-bit Binary-to-Thermometer Code Decoder
70
Figure A.15: 5-bit Binary-to-Thermometer Code Decoder
b4_bar
gnd
vdd
b<3>
vdd
gnd
TC_bar<7>
inverter_1b
gnd
out b4_bar
inverter_1b
vdd
TC_bar<30:0>
TC_bar<23>
vdd
gnd
vdd
out TC_bar<15>
gnd
gnd
b<3>
vdd
gnd
b<3>
b4_bar
gnd
vdd
b4_bar
b<3>
vdd
b4_bar in
b4_bar
b<4> in
vdd
gnd
b<3>
vdd
b4_bar
vdd
gnd
b<3>
b<2>
b<1>
b<0>
b<2>
b<2>
b<1>
b<0>
b<1>
vdd
gnd
gnd
b4_bar
b<3>
b<1>
gnd
gnd
gnd
vdd
b<2>
gnd
gnd
b<1>
gnd
gnd
b<2>
vdd
TC_bar<6>
b<0>
gnd
b<0>
vdd
vdd
vdd
b<3>
gnd
TC_bar<14>
b<0>
b<0>
vdd
TC_bar<22>
vdd
vdd
b<0>
vdd
b<3>
b<1>
vdd
gnd
gnd
gnd
gnd
vdd
gnd
gnd
b<1>
b<1>
vdd
gnd
b<0>
b4_bar
vdd
b4_bar
vdd
b4_bar
b<2>
b<2>
b<3>
vdd
b<2>
b<3>
b4_bar
b4_bar
b<3>
vdd
gnd
vdd
gnd
vdd
vdd
b4_bar
b4_bar
gnd
b<3>
b<2>
b<3>
b<2>
b<1>
b<2>
b<1>
b<3>
b<1>
b<3>
b<2>
b<1>
vdd
vdd
b<2>
b<1>
vdd
vdd
b<1>
gnd
gnd
gnd
b<1>
gnd
vdd
gnd
gnd
TC_bar<5>
vdd
gnd
gnd
b<1>
TC_bar<21>
vdd
vdd
gnd
gnd
gnd
gnd
vdd
TC_bar<13>
b4_bar
vdd
b<3>
gnd
b<2>
b4_bar
vdd
b4_bar
vdd
gnd
b4_bar
vdd
gnd
b<2>
b<2>
b<3>
b<3>
vdd
vdd
b4_bar
b<3>
b4_bar
TC_bar<30>
vdd
b4_bar
gnd
vdd
b<3>
vdd
gnd
vdd
b<1>
gnd
b<1>
vdd
vdd
vdd
b<0>
b<2>
gnd
b<0>
vdd
gnd
b<1>
gnd
TC_bar<20>
gnd
TC_bar<4>
TC_bar<12>
vdd
b<1>
b<1>
vdd
vdd
b<0>
b<3>
vdd
b<1>
vdd
gnd
vdd
b4_bar
b4_bar
gnd
gnd
b<3>
b4_bar
vdd
b<2>
b<3>
gnd
gnd
vdd
gnd
gnd
vdd
b<3>
gnd
b<2>
vdd
vdd
b<2>
b4_bar
b<3>
b<2>
TC_bar<3>
gnd
b4_bar
b4_bar
b4_bar
b<3>
b<3>
b4_bar
TC_bar<27>
vdd
TC_bar<19>
vdd
vdd
gnd
gnd
gnd
vdd
vdd
TC_bar<11>
b<2>
b<2>
b<2>
gnd
vdd
b4_bar
b<3>
b<3>
b4_bar
gnd
gnd
b<3>
b<3>
b4_bar
vdd
gnd
vdd
gnd
b4_bar
TC_bar<28>
vdd
vdd
b<2>
gnd
b<1>
b<0>
gnd
vdd
b<0>
gnd
gnd
b<3>
gnd
b<3>
b<2>
b<1>
b<2>
b4_bar
vdd
b4_bar
b<3>
b<2>
b<0>
vdd
gnd
b<2>
b<0>
b<2>
b4_bar
b<2>
gnd
vdd
gnd
b<3>
b<0>
vdd
b4_bar
b<2>
b4_bar
b<3>
b<3>
b4_bar
TC_bar<29>
vdd
b4_bar
gnd
b<2>
b<3>
gnd
b<2>
gnd
vdd
vdd
b<3>
b4_bar
vdd
b<2>
b<1>
b<0>
gnd
gnd
gnd
gnd
TC_bar<2>
TC_bar<10>
vdd
vdd
gnd
b<1>
b<0>
b<0>
TC_bar<18>
gnd
gnd
vdd
vdd
b<2>
b<3>
b<1>
b<0>
gnd
gnd
gnd
vdd
b<2>
b4_bar
b4_bar
b4_bar
b<3>
b<3>
b4_bar
TC_bar<26>
vdd
b<0>
vdd
vdd
gnd
b<1>
b<0>
vdd
b<3>
gnd
vdd
vdd
gnd
gnd
b<3>
b<1>
b<0>
b<1>
b4_bar
vdd
vdd
vdd
b<2>
b<1>
gnd
b4_bar
b<2>
b<1>
b4_bar
vdd
gnd
vdd
b<0>
gnd
b<3>
b<2>
vdd
vdd
gnd
vdd
gnd
vdd
gnd
vdd
gnd
b4_bar
gnd
vdd
vdd
gnd
gnd
vdd
gnd
vdd
gnd
b<3>
b4_bar
b<2>
gnd
vdd
b<3>
b<1>
b<1>
b<2>
gnd
gnd
vdd
vdd
gnd
vdd
vdd
b<2>
gnd
vdd
b<2>
b<3>
vdd
b<1>
b<1>
b<1>
TC_bar<17>
b<1>
gnd
TC_bar<9>
gnd
gnd
vdd
vdd
b<2>
b<3>
gnd
TC_bar<1>
gnd
gnd
b<3>
b<2>
vdd
b4_bar
gnd
b<2>
b<3>
b<2>
b<3>
vdd
vdd
b<2>
b<3>
b4_bar
gnd
vdd
vdd
vdd
b<1>
b<0>
b<1>
gnd
vdd
vdd
b<1>
gnd
gnd
gnd
gnd
b<0>
TC_bar<8>
TC_bar<16>
b<1>
b<0>
b<3>
vdd
vdd
b<0>
gnd
gnd
TC_bar<24>
b<2>
gnd
gnd
vdd
vdd
vdd
gnd
gnd
b<0>
b<2>
vdd
vdd
vdd
gnd
gnd
b<1>
b<0>
b4_bar
b<1>
vdd
b4_bar
b4_bar
b<3>
b<0>
b4_bar
b<1>
b<0>
gnd
vdd
b<2>
b<1>
b<3>
b4_bar
vdd
gnd
b<3>
b<2>
vdd
gnd
vdd
gnd
b4_bar
TC_bar<25>
vdd
vdd
gnd
b<1>
b4_bar
vdd
b4_bar
b<3>
b<3>
gnd
gnd
b<2>
b<2>
b<1>
b4_bar
vdd
gnd
vdd
b<2>
vdd
vdd
gnd
b<4:0>
vdd
gnd
vdd
gnd
vdd
gnd
gnd
vdd
gnd
vdd
gnd
vdd
gnd
vdd
gnd
gnd
vdd
vdd
gnd
gnd
vdd
vdd
gnd
gnd
vdd
vdd
gnd
vdd
gnd
vdd
gnd
vdd
gnd
gnd
vdd
71
gnd
gnd
TC_bar<0>
A.7
5-bit Decoder Logic
fine_bin<4:0>
fine_th<30:0>
coarse_bin<3:0>
gnd
vdd
clk2
clk1
rot_31_cont_bar<4>
rot_31_cont<4>
sel_bar
sel
in<30:0>
rot_16_cont_bar<3>
sel
rot_16_cont<3:0>
sel_bar
rot_16_31_bit
rot_31_cont<4:0>
gnd
vdd
rot_8_16_bit
vdd
gnd
adder_4b
B<4:0>
A<4:0>
out<30:0>
B<3:0>
A<3:0>
gnd
Sum<4:0>
Overflow
rot_31_cont_bar<3>
adder_5b
rot_16_cont<2>
sel_bar
sel
in<30:0>
rot_16_cont_bar<2>
rot_31_cont<3>
Sum<3:0>
Overflow
out<15:0>
clk2
clk1
clk2
clk1
D<3:0>
clk2
clk2
clk1
D<4:0>
Q<4:0>
rot_16_cont<1>
rot_31_cont<2>
rot_31_cont_bar<4:0>
rot_31_cont<4:0>
rot_31_cont_bar<2>
sel_bar
sel
in<30:0>
rot_16_cont_bar<1>
rot_16_cont_bar<3:0>
rot_16_cont<3:0>
out<15:0>
Q_bar<4:0>
d-register_5b
out<30:0>
Q_bar<3:0>
Q<3:0>
rot_4_16_bit
d-register_4b
rot_8_31_bit
clk1
sel_bar
sel
in<15:0>
vdd
vdd
gnd
gnd
in<15:0>
vdd
vdd
gnd
vdd
VDD
gnd
vdd
vdd
rot_16_cont<3>
gnd
GND
vdd
VDD
GND
gnd
vdd
vdd
gnd
gnd
gnd
vdd
vdd
vdd, coarse_th<14:0>
sel_bar
sel
rot_4_31_bit
in<15:0>
gnd
vdd
out<30:0>
rot_2_16_bit
vdd
gnd
gnd
rot_16_cont<0>
rot_31_cont_bar<1>
sel_bar
sel
in<30:0>
rot_16_cont_bar<0>
rot_31_cont<1>
out<15:0>
sel_bar
sel
rot_2_31_bit
in<15:0>
vdd
out<30:0>
rot_1_16_bit
vdd
gnd
gnd
coarse_th<14:0>
gnd
gnd
vdd
vdd
gnd
vdd
vdd
gnd
gnd
rot_31_cont_bar<0>
rot_31_cont<0>
out<15:0>
sel_bar
sel
in<30:1>
coarse_out<15:0>
vdd
rot_1_31_bit
vdd
gnd
72
gnd
out<30:0>
fine_out<30:0>
A.8
DEM Logic
Figure A.16: Dynamic Element Matching Logic
sel_bar
sel
in<15:0>
gnd
out<15:0>
in<11>
in<12>
in<12>
in<13>
in<13>
in<14>
in<14>
in<15>
vdd
in1
in0
in1
in0
in1
in0
in1
in0
gnd
gnd
Mux_2to1
out
vdd
sel
Mux_2to1
out
vdd
sel
Mux_2to1
out
vdd
vdd
sel_bar
sel_bar
Mux_2to1
out
sel_bar
out<12>
out<13>
out<14>
out<15>
in<7>
in<8>
in<8>
in<9>
in<9>
in<10>
in<10>
in<11>
vdd
in1
in0
in1
in0
gnd
Mux_2to1
out
vdd
sel
Mux_2to1
out
vdd
sel
gnd
gnd
gnd
s el
sel
vdd
sel
sel
sel_bar
sel_bar
in1
in0
in1
in0
sel_bar
out<9>
out<8>
Mux_2to1
out
out<10>
out<11>
Mux_2to1
out
sel_bar
sel_bar
in<3>
in<4>
in<4>
in<5>
in<5>
in<6>
in<6>
in<7>
vdd
in1
in0
Mux_2to1
out
vdd
sel
gnd
gnd
gnd
gnd
in1
in0
Mux_2to1
out
in1
in0
in1
in0
sel_bar
out<5>
out<4>
Mux_2to1
out
out<6>
out<7>
Mux_2to1
out
sel_bar
sel_bar
vdd
sel
vdd
sel
sel
sel_bar
sel_bar
gnd
gnd
gnd
gnd
gnd
in<15>
in<0>
in<0>
in<1>
in<1>
in<2>
in<2>
in<3>
vdd
in1
in0
Mux_2to1
out
in1
in0
in1
in0
in1
in0
gnd
Mux_2to1
out
gnd
out<1>
out<0>
Mux_2to1
out
out<3>
out<3>
Mux_2to1
out
gnd
vdd
sel
vdd
sel
vdd
sel
sel
sel_bar
sel_bar
sel_bar
sel_bar
sel_bar
vdd
vdd
gnd
sel
vdd
sel
vdd
sel
sel
gnd
sel_bar
73
sel
Figure A.17: 16-Input Rotate-1
sel_bar
A.8.1
16-line Rotate-1 Logic
Figure A.18: 31-Input Rotate-1
sel_bar
sel
out<30:0>
in<27>
in<28>
in<28>
in<29>
in<29>
in<30>
vdd
in1
in0
Mux_2to1
out
vdd
sel
gnd
in1
in0
Mux_2to1
out
sel_bar
in1
in0
Mux_2to1
out
sel_bar
out<28>
out<29>
out<30>
in<23>
in<24>
in<24>
in<25>
in<25>
in<26>
in<26>
in<27>
gnd
in1
in0
Mux_2to1
out
gnd
in1
in0
Mux_2to1
out
gnd
in<30:0>
gnd
gnd
gnd
gnd
vdd
vdd
sel
vdd
sel
in1
in0
Mux_2to1
out
vdd
sel
vdd
sel
vdd
sel
sel
sel_bar
sel_bar
sel_bar
sel_bar
in1
in0
Mux_2to1
out
sel_bar
out<24>
out<25>
out<26>
out<27>
in<19>
in<20>
in<20>
in<21>
in<21>
in<22>
in<22>
in<23>
vdd
in1
in0
Mux_2to1
out
vdd
sel
in1
in0
Mux_2to1
out
vdd
sel
vdd
in1
in0
Mux_2to1
out
in1
in0
Mux_2to1
out
out<20>
out<21>
out<22>
out<23>
in<15>
in<16>
in<16>
in<17>
in<17>
in<18>
in<18>
in<19>
in1
in0
Mux_2to1
out
in1
in0
Mux_2to1
out
in1
in0
Mux_2to1
out
in1
in0
Mux_2to1
out
sel_bar
gnd
gnd
sel_bar
sel_bar
sel_bar
vdd
sel_bar
vdd
sel
sel
sel_bar
sel_bar
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
vdd
sel
vdd
sel
sel
vdd
sel
vdd
sel
vdd
sel
vdd
sel
sel
out<16>
out<17>
out<18>
out<19>
in<11>
in<12>
in<12>
in<13>
in<13>
in<14>
in<14>
in<15>
gnd
in1
in0
Mux_2to1
out
vdd
sel
vdd
in1
in0
Mux_2to1
out
vdd
sel
sel_bar
sel_bar
sel_bar
sel_bar
sel_bar
sel_bar
in1
in0
Mux_2to1
out
sel_bar
in1
in0
Mux_2to1
out
sel_bar
out<12>
out<13>
out<14>
out<15>
in<7>
in<8>
in<8>
in<9>
in<9>
in<10>
in<10>
in<11>
vdd
in1
in0
Mux_2to1
out
vdd
sel
in1
in0
Mux_2to1
out
vdd
sel
gnd
gnd
gnd
gnd
sel_bar
in1
in0
Mux_2to1
out
sel_bar
in1
in0
Mux_2to1
out
sel_bar
vdd
sel
vdd
sel
sel
sel_bar
sel_bar
gnd
gnd
gnd
gnd
gnd
out<8>
out<9>
out<10>
out<11>
in<3>
in<4>
in<4>
in<5>
in<5>
in<6>
in<6>
in<7>
vdd
gnd
gnd
in1
in0
Mux_2to1
out
vdd
sel
in1
in0
Mux_2to1
out
vdd
sel
in1
in0
Mux_2to1
out
vdd
sel
vdd
sel
vdd
sel
sel
sel_bar
sel_bar
sel_bar
sel_bar
in1
in0
Mux_2to1
out
sel_bar
out<4>
out<5>
out<6>
out<7>
in<3>
in<30>
in<0>
in<0>
in<1>
in<1>
in<2>
in<2>
gnd
in1
in0
Mux_2to1
out
gnd
in1
in0
Mux_2to1
out
gnd
in1
in0
Mux_2to1
out
gnd
in1
in0
Mux_2to1
out
gnd
gnd
gnd
gnd
sel_bar
sel_bar
sel_bar
sel_bar
vdd
sel
sel
sel_bar
sel_bar
vdd
vdd
sel
vdd
sel
vdd
sel
vdd
sel
sel
74
sel_bar
out<0>
out<1>
out<2>
out<3>
A.8.2
31-line Rotate-1 Logic
2-to-1 Mux
gnd
in0
sel_bar
in1
fingers:1
w=580.0n
l:240.0n
vdd
in0
vdd
in1
fingers:1
w=580.0n
l:240.0n
gnd
"pch"
PM0
sel
vdd
gnd
fingers:1
w=580.0n
l:240.0n
"pch"
"nch"
NM3
PM1
NM4
sel
sel_bar
out
Figure A.19: 2-to-1 Mux
75
fingers:1
w =580.0n
l:240.0n
"nch"
out
A.8.3
sel_bar
Appendix B
MATLAB Code
B.1
Reference Case Code
function out = second_order_reference(mismatch, iterate)
% 2nd order 8-bit sigma-delta model and noise analysis
% include DAC mismatch and regular, barrel-shifting DEM
% Craig Petrie 6/24/2002
% Modified by Brent Nordick
start_time = clock;
format long g
% model parameters
bin = 13;
% number of sine wave cycles to capture (i.e., fft bin number)
ptspc = 1040;
% number of points per cycle to plot
amp = 0.8;
% sine wave amplitude
ref = 1.0;
% reference voltage (full-scale analog input, positive side)
levels = 256;
% number of internal quantizer levels
init = 4;
% initialization points
OSR = 20;
% oversampling ratio
dacmm = 0;
% percent mismatch (in %) of dac elements
sigbins = 1;
% bins on either side of signal to lump with signal
NODEM = 0;
% set to 1 to turn off DEM
loop_iterate = 1;
%set up to run this many times for averaging
showme = 1;
%variable to control display of values and plots
%startup as function necessary stuff
if nargin > 0
dacmm = mismatch;
end
if nargin > 1
loop_iterate = iterate;
end
if nargout > 0
showme = 0;
end
% Initial calculations
pts = bin*ptspc;
norm_factor = ptspc/(2*OSR);
76
% calculate parameters for internal adc function
lm1 = levels - 1;
m = lm1/2/ref;
% slope
b = lm1/2;
% offset
%set up loop for averaging purposes
for lop = 1:loop_iterate
x = amp*sin(2*pi*bin*[0:pts-1+init]/pts);
% exactly ’bin’ cycles of
% ’pts’-point sine wave x=A*sin(2*pi*w*t)
%x = -1*ones(1,length(x));
%DC input for testing purposes
elm1 = getdac(levels,ref,dacmm);
% retrieve dac element values for dac #1
elm2 = getdac(levels,ref,0);
% retrieve dac element values for dac #2
% main delta-sigma loop
u = 0; v = 0;
% initialize integrator outputs
demptr = 0;
% initialize DEM pointer
y = zeros(1,pts+init);
% allocate and initialize output vector
oneelm = zeros(1,pts+init);
% examine frequency content of a single
% element signal
for i = 1:pts+init
[z,y(i)] = idealq(v,m,b,lm1);
% quantize using second
% integrator output before 2nd
% integration
if (NODEM)
demptr = 0;
end
% remove DEM pointer memory to turn off DEM
[dacvec,demptr] = dem(z,lm1,demptr);
% call DEM (Dynamic Element
% Matching) algorithm
oneelm(i) = dacvec(1);
% look at first element
v = v + 2*(u - sum(dacvec.*elm2));
% 2nd integration, use 1st
% integrator output before 1st integration
u = u + 0.5*(x(i) - sum(dacvec.*elm1)); % 1st integration
end
% plot waveforms, spectrum
x = x(init+1:pts+init);
y = y(init+1:pts+init);
ptsv = 1:pts;
yspec = mypsd(y);
% grab last part of data - ignore init portion
% grab last part of data - ignore init portion
% calculate snr
sigtonoise = mysnr(yspec,bin,OSR);
sig_to_noise(lop) = sigtonoise;
%vector of values to average
% compare with ideal snr of 2nd-order modulator
sigi = amp/sqrt(2);
% rms voltage of sine wave
noisei = 2*ref/levels/sqrt(12)*(pi)^2/sqrt(5)/(OSR)^2.5;
% theoretical rms quantization noise voltage
sigtonoisei = 20*log10(sigi/noisei);
% calculate sfdr
sigv = yspec(max([1,(bin-sigbins)]):bin+sigbins); % signal plus spectral bleed
noisev = [yspec(1:bin-sigbins-1) yspec(bin+sigbins+1:pts/2/OSR)]; % vector of
% bins used to calculate noise
77
sfdr = 10*log10(max(sigv)/max(noisev));
avg_sfdr(lop) = sfdr;
end
%calculate values for looping
if (loop_iterate ~= 1)
sig_to_noise = sort(sig_to_noise);
out_sig_to_noise(1) = sig_to_noise(1);
out_sig_to_noise(2) = mean(sig_to_noise);
out_sig_to_noise(3) = sig_to_noise(loop_iterate);
avg_sfdr = sort(avg_sfdr);
out_sfdr(1) = avg_sfdr(1);
out_sfdr(2) = mean(avg_sfdr);
out_sfdr(3) = avg_sfdr(loop_iterate);
else
out_sig_to_noise = sigtonoise;
out_sfdr = sfdr;
end
if (showme)
%Plot
figure(2);
%subplot(2,2,1);
plot(ptsv,x,ptsv,y);
title(’Time domain waves - sampled and quantized’);
legend(’sampled wave’,’quantized wave’);
xlabel(’time’);
ylabel(’voltage’);
figure(3);
subplot(2,1,1);
semilogx(10*log10(yspec));
title(’Power Spectrum’);
xlabel(’Frequency’);
ylabel(’Power’);
% look at spectra of single elements
oneelm = oneelm(init+1:pts+init);
subplot(2,1,2);
ospec = mypsd(oneelm);
semilogx(10*log10(ospec));
title(’Single Element Power Spectrum’);
xlabel(’Frequency’);
ylabel(’Power’);
figure(1);
%subplot(2,1,1)
semilogx(10*log10(yspec));
title(’Power Spectrum’);
xlabel(’Frequency’);
ylabel(’Power’);
78
% display avg/max/min on looping, or just the output when not
sigtonoisei
out_sig_to_noise
out_sfdr
else
%output of the function
out = out_sig_to_noise;
end
elapsed_time = etime(clock, start_time)
function elmvec = getdac(levs,fs,mm)
% calculate random element values for the dac; each element either added or
% subtracted
%
levs
output levels generated by the dac; there are (levs-1) elements
%
fs
full scale output value, positive side
%
mm
desired dac element mismatch, in percent
%
elmvec output vector containing (levs-1) dac element values
nom = fs/(levs-1);
% ideal dac element value (mean
% of output array)
elmvec = nom*(1 + 0.01*mm*randn(1,levs-1));
% 1-by-(levs-1) array of random
% element values
function [intout,dubout] = idealq(in,m,b,maxin)
% ideal quantization using pre-calculate slope and intercept values
%
in
value to be quantized
%
m
input multiplier before rounding
%
b
input offset before rounding
%
maxin
output code forced to be in range [0,maxin]
%
codout output integer quantized value
%
dubout output double quantized value (with same input range as ’in’)
intout = round(m*in + b);
intout = max([intout,0]);
intout = min([intout,maxin]);
dubout = (intout - b)/m;
function [vecout,ptrout] = dem(code,lm1,ptrin)
% perform barrel-shifing dem algorithm
%
code
input integer code
%
lm1
(# dac output levels) - 1; number of dac elements
%
ptrin
position where elements start getting used this time, in range
% [0,levs-1]
%
vecout boolean output vector (+1 or -1) corresp to ’on’ elements in the DAC
%
ptrout position where elements start getting used next time, in range
% [0,levs-1]
ptrout = mod(ptrin+code,lm1);
if ((ptrout > ptrin) | (code == 0))
vecout = [repmat(-1,1,ptrin),repmat(1,1,code),repmat(-1,1,lm1-code-ptrin)];
else
% (ptrout < ptrin) | (code == lm1)
vecout =
[repmat(1,1,code+ptrin-lm1),repmat(-1,1,lm1-code),repmat(1,1,lm1-ptrin)];
end
79
B.2
Calibration Code
function out = second_order_calibrate(mm_fine, iterate)
% 2nd order sigma-delta model and noise analysis
% include DAC mismatch and course/fine DEM
% Craig Petrie 6/24/2002
% Brent Nordick 12-10-03
start_time = clock;
format long g
% model parameters
bin = 13;
% number of sine wave cycles to capture (i.e., fft bin number)
ptspc = 1040;
% number of points per cycle
amp = 0.8;
% sine wave amplitude
ref = 1.0;
% reference voltage (full-scale analog input, positive side)
clevs = 16;
% number of course levels (output codes) in two-step internal
% quantizer
flevs = 16;
% number of fine levels in internal quantizer
init = 4;
% initialization points
OSR = 20;
% oversampling ratio
dacmmc = 0;
% percent mismatch (in %) of course dac elements
dacmmf = 0;
% percent mismatch (in %) of fine dac elements
sigbins = 1;
% bins on either side of signal to lump with signal
NODEM = 0;
% set to 1 to turn off DEM
loop_iterate = 1; %Make it loop to get average StoN
showme = 1;
%variale to control display of values and plots
%startup as function necessary stuff
if nargin > 0
dacmmf = mm_fine;
end
if nargin > 1
loop_iterate = iterate;
end
if nargout > 0
showme = 0;
end
% Initial calculations
pts = bin*ptspc;
norm_factor = ptspc/(2*OSR);
% calculate parameters for internal two-step adc function
% for fine quantization, input signal is in the range [-ref/clevs,+ref/clevs]
olevs = clevs*flevs;
% number of overall levels in internal quantizer
olm1 = olevs - 1;
clm1 = clevs - 1;
flm1 = flevs - 1;
mc = olm1/2/flevs/ref; % slope for course quantization
bc = clm1/2;
% offset for course quantization
mf = olm1/2/ref;
% slope for fine quantization
bf = flm1/2;
% offset for fine quantization
80
%set up loop for averaging purposes
for lop = 1:loop_iterate
x = amp*sin(2*pi*bin*[0:pts-1+init]/pts);
% exactly ’bin’ cycles of
% ’pts’-point sine wave
[elm1c,elm1f] = getdac2(clevs,flevs,ref,dacmmc,dacmmf);
% retrieve dac
% element values for dac #1
[elm2c,elm2f] = getdac2(clevs,flevs,ref,0,0);
% retrieve dac
% element values for dac #2
%compute averages and adjust fine values so that the average is the same
%this translates to same average gain
avgc = sum(elm1c)/size(elm1c,2);
avgf = sum(elm1f)/size(elm1f,2);
deltaf = (avgc/16-avgf);
deltac = (avgf*16-avgc);
avg_cap_calculated = [avgc avgf];
%save for analysis
delta_list(lop)=deltaf;
avgc_list(lop) = avgc;
avgf_list(lop) = avgf;
% main delta-sigma loop
u = 0; v = 0;
% initialize integrator outputs
demptrc = 0; demptrf = 0;
% initialize DEM pointers
y = zeros(1,pts+init);
% allocate and initialize output vector
mydisp = 1;
corselm = zeros(1,pts+init);
% examine frequency content of a single
% course element signal
fineelm = zeros(1,pts+init);
% examine frequency content of a single fine
% element signal
yc = zeros(1,pts+init);
% examine course adc output signal
yf = zeros(1,pts+init);
% examine fine adc output signal
%cal length
% 868
% 2170
% 4123
% 8680
%16492
and M for third order sync
289
723
1374
2893
5497
%Calibration routine
figure(2);
subplot(2,1,1);
cal_length = 16492;
for lop1 = 1:2
for lop2 = 1:cal_length
%[zc,zf,y(lop2),yc(lop2),yf(lop2)] =
idealq2(v,mc,bc,mf,bf,clm1,flm1);
if (lop1 == 1)
zc = 1;
zf = 1;
end
81
% two-step quantization; use
% second integrator output 1st
if (lop1 == 2);
zc = 1;
zf = 1;
end
zcal(lop2) = idealq_1b(v);
if (lop1 ==1)
[dacvecc,demptrc] = dem(zc,clm1,demptrc);
v = v + 2*(u - sum(dacvecc.*elm2c) - zcal(lop2));
% 2nd
u = u + 0.5*(0 - sum(dacvecc.*elm1c) - zcal(lop2));
% 1st
else
[dacvecf,demptrf] = dem(zf,flm1,demptrf);
v = v + 2*(u - sum(dacvecf.*elm2f) - zcal(lop2));
% 2nd
u = u + 0.5*(0 - sum(dacvecf.*elm1f) - zcal(lop2));
% 1st
end
integration
integration
integration
integration
end
plot([1:cal_length],zcal)
axis([0,cal_length,-1.1,1.1]);
output_cal(lop1,:) = zcal(1:cal_length);
title(’Coarse Calibration Routine’);
subplot(2,1,2);
end
title(’Fine Calibration Routine’);
%Calibration values
M = 5497;
b = [1 zeros(1,M-1) -3 zeros(1,M-1) 3 zeros(1,M-1) -1];
% 3rd order sinc filter
a = (M^3)*[1 -3 3 -1];
yprime(1,:) = filter(b, a, output_cal(1,:));
yprime(2,:) = filter(b, a, output_cal(2,:));
figure(3)
plot(yprime(1,:))
hold on
plot(yprime(2,:),’r’)
hold off
legend(’coarse’,’fine’)
avg_y(1) = yprime(1,cal_length);
avg_y(2) = yprime(2,cal_length);
%avg_filtered = avg_y
%remove ; for displaying
avg_cap = ((avg_y ./ 13)) *[[1/1 0]; [0 1/1]];
error(lop,:) = avg_cap - avg_cap_calculated;
delta_cap =[ (avg_cap(2)*flevs - avg_cap(1)) (avg_cap(1)/(flevs) avg_cap(2))];
%elm1c(1) = elm1c(1) + (clevs-1)*delta_cap(1);
elm1f(1) = elm1f(1) + (flevs-1)*delta_cap(2);
%elm1c = elm1c + delta_cap(1);
%elm1f = elm1f + delta_cap(2);
82
%Standard operation
u = 0; v = 0;
% initialize integrator outputs
demptrc = 0; demptrf = 0;
% initialize DEM pointers
y = zeros(1,pts+init);
% allocate and initialize output vector
for i = 1:pts+init
[zc,zf,y(i),yc(i),yf(i)] = idealq2(v,mc,bc,mf,bf,clm1,flm1);
% two-step
% quantization; use second integrator output 1st
if (NODEM)
% remove DEM pointer memory to turn off DEM
demptrc = 0; demptrf = 0;
end
[dacvecc,demptrc] = dem(zc,clm1,demptrc);
% call DEM (Dynamic
% Element Matching) algorithm for course dac
[dacvecf,demptrf] = dem(zf,flm1,demptrf);
% call DEM (Dynamic
% Element Matching) algorithm for fine dac
corselm(i) = dacvecc(1);
% look at first element
fineelm(i) = dacvecf(1);
% look at first element
v = v + 2*(u - sum(dacvecc.*elm2c) - sum(dacvecf.*elm2f));
% 2nd integration
u = u + 0.5*(x(i) - sum(dacvecc.*elm1c) - sum(dacvecf.*elm1f));
% 1st integration
end
% plot waveforms, spectrum
x = x(init+1:pts+init);
y = y(init+1:pts+init);
ptsv = 1:pts;
yspec = mypsd(y);
% grab last part of data
% grab last part of data
% calculate snr
sigv = yspec(max([1,(bin-sigbins)]):bin+sigbins);
% signal plus spectral bleed
noisev = [yspec(1:bin-sigbins-1) yspec(bin+sigbins+1:pts/2/OSR)];
% vector of bins used to calculate noise
sig = sum(sigv); noise = sum(noisev);
sigtonoise = 10*log10(sig/noise);
sig_to_noise(lop) = sigtonoise;
%vector of values to average
% compare with ideal snr of 2nd-order modulator
sigi = amp/sqrt(2);
% rms voltage of sine wave
noisei = 2*ref/clevs/flevs/sqrt(12)*(pi)^2/sqrt(5)/(OSR)^2.5;
% theoretical rms quantization noise voltage
sigtonoisei = 20*log10(sigi/noisei);
% calculate sfdr
sfdr = 10*log10(max(sigv)/max(noisev));
avg_sfdr(lop) = sfdr;
end
%calculate values for looping
if (loop_iterate ~= 1)
83
sig_to_noise = sort(sig_to_noise);
out_sig_to_noise(1) = sig_to_noise(1);
out_sig_to_noise(2) = mean(sig_to_noise);
out_sig_to_noise(3) = sig_to_noise(loop_iterate);
avg_sfdr = sort(avg_sfdr);
out_sfdr(1) = avg_sfdr(1);
out_sfdr(2) = mean(avg_sfdr);
out_sfdr(3) = avg_sfdr(loop_iterate);
%delta results
avgc_list = sort(avgc_list);
out_avgc(1) = avgc_list(1);
out_avgc(2) = mean(avgc_list);
out_avgc(3) = avgc_list(loop_iterate);
avgf_list =
out_avgf(1)
out_avgf(2)
out_avgf(3)
delta_list =
out_delta(1)
out_delta(2)
out_delta(3)
sort(avgf_list);
= avgf_list(1);
= mean(avgf_list);
= avgf_list(loop_iterate);
sort(abs(delta_list));
= delta_list(1);
= mean(delta_list);
= delta_list(loop_iterate);
out = out_sig_to_noise;
else
out_sig_to_noise = sigtonoise;
out_sfdr = sfdr;
%delta results
out_avgc = avgc;
out_avgf = avgf;
out_delta = deltaf;
end
if (showme)
%Plots
figure(22);
plot(ptsv,x,ptsv,y);
title(’Time domain waves - sampled and quantized’);
legend(’sampled wave’,’ideal quantized wave’);
xlabel(’time’);
ylabel(’voltage’);
figure(1);
%subplot(2,1,2);
semilogx(10*log10(yspec));
% plot it
title(’Power Spectrum of output signal (using FFT) (y) - Dual DEM with
Gain Equalization’);
xlabel(’Frequency’);
ylabel(’Power’);
axis([10^0 10^4 -150 100])
84
% look at spectra of course and fine elements and signals
corselm = corselm(init+1:pts+init);
fineelm = fineelm(init+1:pts+init);
yc = yc(init+1:pts+init);
yf = yf(init+1:pts+init);
figure(23);
subplot(2,2,1);
cspec = (abs(fft(corselm))).^2;
% power spectrum using fft
cspec = cspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(cspec));
% plot it
title(’Single Element Course Power Spectra (corselm)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,3);
fspec = (abs(fft(fineelm))).^2;
% power spectrum using fft
fspec = fspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(fspec));
% plot it
title(’Single Element Fine Power Spectra (fineelm)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,2);
cspec = (abs(fft(yc))).^2;
% power spectrum using fft
cspec = cspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(cspec));
% plot it
title(’Course Output Power Spectra (yc)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,4);
fspec = (abs(fft(yf))).^2;
% power spectrum using fft
fspec = fspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(fspec));
% plot it
title(’Fine Output Power Spectra (yf)’);
xlabel(’Frequency’);
ylabel(’Power’);
% display avg/max/min on looping, or just the output when not
norm_factor
sigtonoisei
out_sig_to_noise
out_sfdr
out_avgc
out_avgf
out_delta
else
%output of the function
out = out_sig_to_noise;
end
elapsed_time = etime(clock, start_time)
function [out] = idealq_1b(in)
85
%ideal 1 bit quantization for calibrate routine
%
in
value to be quantized
% Simple comparator
if (in > 0)
out = 1;
else
out = -1;
end
function [elmc,elmf] = getdac2(clevs,flevs,fs,mmc,mmf)
% calculate random element values course and fine dac arrays; each element
% either added or subtracted
%
clevs
course output levels generated by the dac; there are (clevs-1)
% course elements
%
flevs
fine output levels generated by the dac; there are (flevs-1) fine
% elements
%
fs
full scale output value, positive side
%
mmc
desired course dac element mismatch, in percent
%
mmf
desired fine dac element mismatch, in percent
%
elmc
output vector containing (clevs-1) course dac element values
%
elmf
output vector containing (flevs-1) fine dac element values
%randn(’state’,sum(100*clock));
%randomly reset random number seed
nomc = fs*flevs/(clevs*flevs - 1);
% ideal course dac element value
% (mean of output array)
nomf = fs/(clevs*flevs - 1);
% ideal fine dac element value
% (mean of output array)
%elmc = nomc*(1 + 0.01*mmc*randn(1,clevs-1));
% 1-by-(clevs-1) array of
% random element values
elmf = nomf*(1 + 0.01*mmf*randn(1,flevs-1));
% 1-by-(clevs-1) array of
% random element values
for lop = 1:clevs-1
elmc(lop) = sum(nomf*(1 + 0.01*mmf*randn(1,flevs)));
end
%stdev_f = std(elmf)/nomf
%stdev_c = std(elmc)/nomc
%calc_stdv = sqrt(sum((elmc-nomc).^2)/16) / nomc
function [outc,outf,dubout,dubc,dubf] = idealq2(in,mc,bc,mf,bf,maxc,maxf)
% ideal 2-step (course,fine) quantization using pre-calculated slope and
% intercept values
%
in
value to be quantized
%
mc
course input multiplier before rounding
%
mf
fine input multiplier before rounding
%
bc
course input offset before rounding
%
bf
fine input offset before rounding
%
maxc
course output code is forced to be in range [0,maxc]
%
maxf
fine output code is forced to be in range [0,maxf]
%
outc
course output integer quantized value
%
outf
fine output integer quantized value
%
dubout output double quantized value (with same input range as ’in’)
%
dubc
course quantized value (with same input range as ’in’)
%
dubf
fine quantized value (with same input range as ’in’, but scaled
% to be fine)
outc = round(mc*in + bc);
% 1st (course) quantization step
86
outc =
outc =
dubc =
outf =
outf =
outf =
dubf =
dubout
max([outc,0]);
min([outc,maxc]);
(outc - bc)/mc;
round(mf*(in - dubc) + bf);
max([outf,0]);
min([outf,maxf]);
(outf - bf)/mf;
= dubc + dubf;
% 2nd (fine) quantization step
function [vecout,ptrout] = dem(code,lm1,ptrin)
% perform barrel-shifing dem algorithm
%
code
input integer code
%
lm1
(# dac output levels) - 1; number of dac elements
%
ptrin
position where elements start getting used this time, in range
% [0,levs-1]
%
vecout boolean output vector (+1 or -1) corresp to ’on’ elements in the
% DAC
%
ptrout position where elements start getting used next time, in range
% [0,levs-1]
ptrout = mod(ptrin+code,lm1);
if ((ptrout > ptrin) | (code == 0))
vecout =
[repmat(-1,1,ptrin),repmat(1,1,code),repmat(-1,1,lm1-code-ptrin)];
else
% (ptrout < ptrin) | (code == lm1)
vecout =
[repmat(1,1,code+ptrin-lm1),repmat(-1,1,lm1-code),repmat(1,1,lm1-ptrin)];
end
87
B.3
ReQ Code
function out = second_order_ReQ(mm_caps, iterate)
% 2nd order 8-bit sigma-delta model and noise analysis
% include DAC mismatch and coarse/fine DEM
% Craig Petrie 6/24/2002
% Modified by Brent Nordick
start_time = clock;
format long g
% model parameters
bin = 13;
% number of sine wave cycles to capture (i.e., fft bin number)
ptspc = 1040;
% number of points per cycle
amp = 0.8;
% sine wave amplitude
ref = 1.0;
% reference voltage (full-scale analog input, positive side)
clevs = 16;
% number of coarse levels (output codes) in two-step internal
% quantizer
flevs = 16;
% number of fine levels in internal quantizer
clevs_ReQ = 16; % number of coarse levels (output codes) in ReQ circuitry % flevs_ReQ is automatically calculated
%flevs_ReQ = 32; % number of fine levels in ReQ circuitry (total of the ReQ bits
% should be 1 extra for the overlap)
init = 4;
% initialization points
OSR = 20;
% oversampling ratio
dacmmc = 0;
% percent mismatch (in %) of coarse dac elements
dacmmf = 0;
% percent mismatch (in %) of fine dac elements
sigbins = 1;
% bins on either side of signal to lump with signal
NODEM = 0;
% set to 1 to turn off DEM
loop_iterate = 1; %Make it loop to get average StoN
showme = 1;
%variable to control display of values and plots
%startup as function necessary stuff
if nargin > 0
dacmmf = mm_caps;
end
if nargin > 1
loop_iterate = iterate;
end
if nargout > 0
showme = 0;
end
% Initial calculations
pts = bin*ptspc;
norm_factor = ptspc/(2*OSR);
flevs_ReQ = 2*clevs*flevs/clevs_ReQ;
% calculate parameters for internal two-step adc function
% for fine quantization, input signal is in the range [-ref/clevs,+ref/clevs]
olevs = clevs*flevs;
% number of overall levels in internal quantizer
olm1 = olevs - 1;
clm1 = clevs - 1;
flm1 = flevs - 1;
88
mc
bc
mf
bf
=
=
=
=
olm1/2/flevs/ref;
clm1/2;
olm1/2/ref;
flm1/2;
%
%
%
%
slope for coarse quantization
offset for coarse quantization
slope for fine quantization
offset for fine quantization
%set up loop for averaging purposes
for lop = 1:loop_iterate
x = amp*sin(2*pi*bin*[0:pts-1+init]/pts);
% exactly ’bin’ cycles of
% ’pts’-point sine wave
[elm1c,elm1f] = getdac2(clevs,flevs,clevs_ReQ,flevs_ReQ,ref,dacmmc,dacmmf);
% retrieve dac element values for dac #1
[elm2c,elm2f] = getdac2(clevs,flevs,clevs_ReQ,flevs_ReQ,ref,0,0);
% retrieve dac element values for dac #2
% main delta-sigma loop
u = 0; v = 0;
% initialize integrator outputs
demptrc = 0; demptrf = 0;
% initialize DEM pointers
y = zeros(1,pts+init);
% allocate and initialize output vector
mydisp = 1;
corselm = zeros(1,pts+init);
% examine frequency content of a single
% coarse element signal
fineelm = zeros(1,pts+init);
% examine frequency content of a single fine
% element signal
yc = zeros(1,pts+init);
% examine coarse adc output signal
yf = zeros(1,pts+init);
% examine fine adc output signal
zerr = 0;
dub_err = 0;
maxf = 0;
minf = 0;
for i = 1:pts+init
[zc,zf,y(i),yc(i),yf(i)] = idealq2(v,mc,bc,mf,bf,clm1,flm1);
% two-step
% quantization; use second integrator output 1st
if (NODEM)
% remove DEM pointer memory to turn off DEM
demptrc = 0; demptrf = 0;
end
%noise shape gain error between DAC’s
dub_mod = y(i)-dub_err;
%dub_mod(i)=min([max([dub_mod(i),-1]),1]);
%limit to allowable range
z_mod_8_b = min([max([round((olm1)/2*(dub_mod) + (olm1)/2),0]),olm1]);
z_mod_4_b = floor(z_mod_8_b/(flevs_ReQ/2));
zc = z_mod_4_b;
zc = max([zc 0]);
zc = min([zc 15]);
z_mod_4_b_ls = z_mod_4_b * (flevs_ReQ/2);
dub_4_b_ls = (z_mod_4_b_ls - ((olm1)/2))/((olm1)/2);
dub_err = dub_4_b_ls-dub_mod;
%dub_err=min([max([dub_err,-1]),1]); %limit to allowable range
dub_fine = y(i) - dub_4_b_ls;
z_fine_8b = min([max([round((olm1)/2*dub_fine+(olm1)/2),0]),olm1]);
89
zf = z_fine_8b-(olevs-flevs_ReQ)/2;
%this converts from 8 bit to 5 bit bias number
zf = max([zf 0]);
zf = min([zf 31]);
yc(i) = (zc * (flevs_ReQ/2) - ((olm1)/2))/((olm1)/2);
yf(i) = (zf + (olevs-flevs_ReQ)/2 - ((olm1)/2))/((olm1)/2);
%end noise shape stuff
[dacvecc,demptrc] = dem(zc,clevs_ReQ-1+1,demptrc);
% call DEM (Dynamic
% Element Matching) algorithm for coarse dac
[dacvecf,demptrf] = dem(zf,flevs_ReQ-1,demptrf);
% call DEM (Dynamic
% Element Matching) algorithm for fine dac
corselm(i) = dacvecc(1);
% look at first element
fineelm(i) = dacvecf(1);
% look at first element
v = v + 2*(u - sum(dacvecc.*elm2c) - sum(dacvecf.*elm2f) );
% 2nd integration
u = u + 0.5*(x(i) - sum(dacvecc.*elm1c) - sum(dacvecf.*elm1f) );
% 1st integration
end
% plot waveforms, spectrum
x = x(init+1:pts+init);
y = y(init+1:pts+init);
ptsv = 1:pts;
yspec = mypsd(y);
% grab last part of data
% grab last part of data
% calculate snr
sigv = yspec(max([1,(bin-sigbins)]):bin+sigbins); % signal plus spectral bleed
noisev = [yspec(1:bin-sigbins-1) yspec(bin+sigbins+1:pts/2/OSR)];
% vector of bins used to calculate noise
sig = sum(sigv);
noise = sum(noisev);
sigtonoise = 10*log10(sig/noise);
sig_to_noise(lop) = sigtonoise;
%vector of values to average
% compare with ideal snr of 2nd-order modulator
sigi = amp/sqrt(2);
% rms voltage of sine wave
noisei = 2*ref/clevs/flevs/sqrt(12)*(pi)^2/sqrt(5)/(OSR)^2.5;
% theoretical rms quantization noise voltage
sigtonoisei = 20*log10(sigi/noisei);
% calculate sfdr
sfdr = 10*log10(max(sigv)/max(noisev));
avg_sfdr(lop) = sfdr;
end
%calculate values for looping
if (loop_iterate ~= 1)
sig_to_noise = sort(sig_to_noise);
out_sig_to_noise(1) = sig_to_noise(1);
out_sig_to_noise(2) = mean(sig_to_noise);
out_sig_to_noise(3) = sig_to_noise(loop_iterate);
90
avg_sfdr = sort(avg_sfdr);
out_sfdr(1) = avg_sfdr(1);
out_sfdr(2) = mean(avg_sfdr);
out_sfdr(3) = avg_sfdr(loop_iterate);
else
out_sig_to_noise = sigtonoise;
out_sfdr = sfdr;
end
%Output
if (showme)
% Plots
figure(22);
plot(ptsv,x,ptsv,y);
title(’Time domain waves - sampled and quantized’);
legend(’sampled wave’,’ideal quantized wave’);
xlabel(’time’);
ylabel(’voltage’);
figure(1);
%subplot(2,1,2);
semilogx(10*log10(yspec));
% plot it
title(’Power Spectrum (using FFT) (y) - Dual DEM with segmented noise
shaping’);
xlabel(’Frequency’);
ylabel(’Power’);
axis([10^0 10^4 -150 100])
% look at spectra of coarse and fine elements and signals
corselm = corselm(init+1:pts+init);
fineelm = fineelm(init+1:pts+init);
yc = yc(init+1:pts+init);
yf = yf(init+1:pts+init);
figure(23);
subplot(2,2,1);
cspec = mypsd(corselm);
semilogx(10*log10(cspec));
% plot it
title(’Single Element Coarse Power Spectra (corselm)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,3);
fspec = mypsd(fineelm);
semilogx(10*log10(fspec));
% plot it
title(’Single Element Fine Power Spectra (fineelm)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,2);
cspec = mypsd(yc);
semilogx(10*log10(cspec));
% plot it
title(’Coarse Output Power Spectra (yc)’);
91
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,4);
fspec = mypsd(fspec);
semilogx(10*log10(fspec));
% plot it
title(’Fine Output Power Spectra (yf)’);
xlabel(’Frequency’);
ylabel(’Power’);
% display avg/max/min on looping, or just the output when not
norm_factor
sigtonoisei
out_sig_to_noise
out_sfdr
else
%output of the function
out = out_sig_to_noise;
end
time_elapsed = etime(clock, start_time)
function [elmc,elmf] = getdac2(clevs,flevs,clevs_ReQ,flevs_ReQ,fs,mmc,mmf)
% calculate random element values coarse and fine dac arrays; each element
% either added or subtracted
%
clevs
coarse output levels generated by the dac;
%
flevs
fine output levels generated by the dac;
%
clevs_ReQ
Coarse output levels from the ReQ circuitry; there are
% (clevs_ReQ-1) coarse elements (plus one for offset)
%
flevs_ReQ
Fine output levels from the ReQ circuitry; there are
% (flevs_ReQ-1) fine elements
%
fs
full scale output value, positive side
%
mmc
desired coarse dac element mismatch, in percent
%
mmf
desired fine dac element mismatch, in percent
%
elmc
output vector containing (clevs-1) coarse dac element values
%
elmf
output vector containing (flevs-1) fine dac element values
%randn(’state’,sum(100*clock));
%randomly reset random number seed
nomc = fs*(flevs_ReQ/2)/(clevs*flevs - 1);
% ideal coarse dac element value
% (mean of output array)
nomf = fs/(clevs*flevs - 1);
% ideal fine dac element value
% (mean of output array)
%elmc = nomc*(1 + 0.01*mmc*randn(1,clevs_ReQ-1+1));
% 1-by-(clevs-1) array
% of random element values
elmf = nomf*(1 + 0.01*mmf*randn(1,flevs_ReQ-1));
% 1-by-(clevs-1) array of
% random element values
for lop = 1:clevs_ReQ-1+1
elmc(lop) = sum(nomf*(1 + 0.01*mmf*randn(1,flevs_ReQ/2)));
end
%stdev_f = std(elmf)/nomf
%stdev_c = std(elmc)/nomc
%calc_stdv = sqrt(sum((elmc-nomc).^2)/16) / nomc
function [outc,outf,dubout,dubc,dubf] = idealq2(in,mc,bc,mf,bf,maxc,maxf)
% ideal 2-step (coarse,fine) quantization using pre-calculated slope and
% intercept values
92
%
%
%
%
%
%
%
%
%
%
%
%
in
mc
mf
bc
bf
maxc
maxf
outc
outf
dubout
dubc
dubf
outc =
outc =
outc =
dubc =
outf =
outf =
outf =
dubf =
dubout
value to be quantized
coarse input multiplier before rounding
fine input multiplier before rounding
coarse input offset before rounding
fine input offset before rounding
coarse output code is forced to be in range [0,maxc]
fine output code is forced to be in range [0,maxf]
coarse output integer quantized value
fine output integer quantized value
output double quantized value (with same input range as ’in’)
coarse quantized value (with same input range as ’in’)
fine quantized value (with same input range as ’in’, but scaled
% to be fine)
round(mc*in + bc);
% 1st (coarse) quantization step
max([outc,0]);
min([outc,maxc]);
(outc - bc)/mc;
round(mf*(in - dubc) + bf);
% 2nd (fine) quantization step
max([outf,0]);
min([outf,maxf]);
(outf - bf)/mf;
= dubc + dubf;
function [vecout,ptrout] = dem(code,lm1,ptrin)
% perform barrel-shifing dem algorithm
%
code
input integer code
%
lm1
(# dac output levels) - 1; number of dac elements
%
ptrin
position where elements start getting used this time, in range
% [0,levs-1]
%
vecout boolean output vector (+1 or -1) corresp to ’on’ elements in the
% DAC
%
ptrout position where elements start getting used next time, in range
% [0,levs-1]
ptrout = mod(ptrin+code,lm1);
if ((ptrout > ptrin) | (code == 0))
vecout =
[repmat(-1,1,ptrin),repmat(1,1,code),repmat(-1,1,lm1-code-ptrin)];
else
% (ptrout < ptrin) | (code == lm1)
vecout =
[repmat(1,1,code+ptrin-lm1),repmat(-1,1,lm1-code),repmat(1,1,lm1-ptrin)];
end
93
B.4
Manual Calibration Code
function out = second_order_man_calibrate(mm_fine, iterate)
% 2nd order 8-bit sigma-delta model and noise analysis
% include DAC mismatch and course/fine DEM
% Craig Petrie 6/24/2002
% Modified by Brent Nordick
start_time = clock;
format long g
% model parameters
bin = 13;
% number of sine wave cycles to capture (i.e., fft bin number)
ptspc = 1040;
% number of points per cycle
amp = 0.8;
% sine wave amplitude
ref = 1.0;
% reference voltage (full-scale analog input, positive side)
clevs = 16;
% number of course levels (output codes) in two-step internal
% quantizer
flevs = 16;
% number of fine levels in internal quantizer
init = 4;
% initialization points
OSR = 20;
% oversampling ratio
dacmmc = 0;
% percent mismatch (in %) of course dac elements
dacmmf = 0;
% percent mismatch (in %) of fine dac elements
sigbins = 1;
% bins on either side of signal to lump with signal
NODEM = 0;
% set to 1 to turn off DEM
loop_iterate = 1; %Make it loop to get average StoN
showme = 1;
%variale to control display of values and plots
%startup as function necessary stuff
if nargin > 0
dacmmf = mm_fine;
end
if nargin > 1
loop_iterate = iterate;
end
if nargout > 0
showme = 0;
end
% Initial calculations
pts = bin*ptspc;
norm_factor = ptspc/(2*OSR);
% calculate parameters for internal two-step adc function
% for fine quantization, input signal is in the range [-ref/clevs,+ref/clevs]
olevs = clevs*flevs;
% number of overall levels in internal quantizer
olm1 = olevs - 1;
clm1 = clevs - 1;
flm1 = flevs - 1;
mc = olm1/2/flevs/ref; % slope for course quantization
bc = clm1/2;
% offset for course quantization
mf = olm1/2/ref;
% slope for fine quantization
bf = flm1/2;
% offset for fine quantization
94
%set up loop for averaging purposes
for lop = 1:loop_iterate
x = amp*sin(2*pi*bin*[0:pts-1+init]/pts);
% exactly ’bin’ cycles of
% ’pts’-point sine wave
[elm1c,elm1f] = getdac2(clevs,flevs,ref,dacmmc,dacmmf);
% retrieve dac
% element values for dac #1
[elm2c,elm2f] = getdac2(clevs,flevs,ref,0,0);
% retrieve dac
% element values for dac #2
%compute averages and adjust fine values so that the average is the same
%this translates to same average gain
avgc = sum(elm1c)/size(elm1c,2);
avgf = sum(elm1f)/size(elm1f,2);
deltaf = (avgc/16-avgf);
deltac = (avgf*16-avgc);
%make adjustments
%elm1f = elm1f + deltaf;
%add some to each cap
%elm1c = elm1c + deltac;
elm1f(1) = elm1f(1) + (flevs-1)*deltaf;
% Add all adjustment to one
% fine cap
%elm1c(1) = elm1c(1) + (clevs-1)*deltac;
% Add all adjustment to one
% coarse cap
%elm1f = elm1f * (1 + 0.01/100);
% create mismatch in ideal
% gain-match - fine
%elm1c = elm1c * (1 + 0.05/100);
% create mismatch in ideal
% gain-match - coarse
%elm1f = elm1f - (ref/(clevs*flevs-1)) *(0.01/100);
%mismatch by
% constant value - all - fine
%elm1f(1) = elm1f(1) * (1 + .08/100);
%mismatch by
% constant value - one - fine
%save for analysis
delta_list(lop)=deltaf;
avgc_list(lop) = avgc;
avgf_list(lop) = avgf;
%recalculate averages to verify that it worked
%avgc = sum(elm1c)/size(elm1c,2)
%avgf = sum(elm1f)/size(elm1f,2)
%delta = (avgc/16 - avgf)
% main delta-sigma loop
u = 0; v = 0;
% initialize integrator outputs
demptrc = 0; demptrf = 0;
% initialize DEM pointers
y = zeros(1,pts+init);
% allocate and initialize output vector
mydisp = 1;
corselm = zeros(1,pts+init);
% examine frequency content of a single
% course element signal
fineelm = zeros(1,pts+init);
% examine frequency content of a single fine
% element signal
yc = zeros(1,pts+init);
% examine course adc output signal
yf = zeros(1,pts+init);
% examine fine adc output signal
for i = 1:pts+init
95
[zc,zf,y(i),yc(i),yf(i)] = idealq2(v,mc,bc,mf,bf,clm1,flm1);
% two-step
% quantization; use second integrator output 1st
if (NODEM)
% remove DEM pointer memory to turn off DEM
demptrc = 0; demptrf = 0;
end
[dacvecc,demptrc] = dem(zc,clm1,demptrc);
% call DEM (Dynamic Element
% Matching) algorithm for course dac
[dacvecf,demptrf] = dem(zf,flm1,demptrf);
% call DEM (Dynamic Element
% Matching) algorithm for fine dac
corselm(i) = dacvecc(1);
% look at first element
fineelm(i) = dacvecf(1);
% look at first element
v = v + 2*(u - sum(dacvecc.*elm2c) - sum(dacvecf.*elm2f));
% 2nd integration
u = u + 0.5*(x(i) - sum(dacvecc.*elm1c) - sum(dacvecf.*elm1f));
% 1st integration
end
% plot waveforms, spectrum
x = x(init+1:pts+init);
y = y(init+1:pts+init);
ptsv = 1:pts;
yspec = mypsd(y);
% grab last part of data
% grab last part of data
% calculate snr
sigv = yspec(max([1,(bin-sigbins)]):bin+sigbins); % signal plus spectral bleed
noisev = [yspec(1:bin-sigbins-1) yspec(bin+sigbins+1:pts/2/OSR)];
% vector of bins used to calculate noise
sig = sum(sigv); noise = sum(noisev);
sigtonoise = 10*log10(sig/noise);
sig_to_noise(lop) = sigtonoise;
%vector of values to average
% compare with ideal snr of 2nd-order modulator
sigi = amp/sqrt(2);
% rms voltage of sine wave
noisei = 2*ref/clevs/flevs/sqrt(12)*(pi)^2/sqrt(5)/(OSR)^2.5;
% theoretical rms quantization noise voltage
sigtonoisei = 20*log10(sigi/noisei);
% calculate sfdr
sfdr = 10*log10(max(sigv)/max(noisev));
avg_sfdr(lop) = sfdr;
end
%calculate values for looping
if (loop_iterate ~= 1)
sig_to_noise = sort(sig_to_noise);
out_sig_to_noise(1) = sig_to_noise(1);
out_sig_to_noise(2) = mean(sig_to_noise);
out_sig_to_noise(3) = sig_to_noise(loop_iterate);
avg_sfdr = sort(avg_sfdr);
out_sfdr(1) = avg_sfdr(1);
out_sfdr(2) = mean(avg_sfdr);
96
out_sfdr(3) = avg_sfdr(loop_iterate);
%delta results
avgc_list = sort(avgc_list);
out_avgc(1) = avgc_list(1);
out_avgc(2) = mean(avgc_list);
out_avgc(3) = avgc_list(loop_iterate);
avgf_list =
out_avgf(1)
out_avgf(2)
out_avgf(3)
delta_list =
out_delta(1)
out_delta(2)
out_delta(3)
sort(avgf_list);
= avgf_list(1);
= mean(avgf_list);
= avgf_list(loop_iterate);
sort(abs(delta_list));
= delta_list(1);
= mean(delta_list);
= delta_list(loop_iterate);
out = out_sig_to_noise;
else
out_sig_to_noise = sigtonoise;
out_sfdr = sfdr;
%delta results
out_avgc = avgc;
out_avgf = avgf;
out_delta = deltaf;
end
if (showme)
%Plots
figure(22);
plot(ptsv,x,ptsv,y);
title(’Time domain waves - sampled and quantized’);
legend(’sampled wave’,’ideal quantized wave’);
xlabel(’time’);
ylabel(’voltage’);
figure(1);
%subplot(2,1,2);
semilogx(10*log10(yspec));
% plot it
title(’Power Spectrum of output signal (using FFT) (y) - Dual DEM with
Gain Equalization’);
xlabel(’Frequency’);
ylabel(’Power’);
axis([10^0 10^4 -150 100])
% look at spectra of course and fine elements and signals
corselm = corselm(init+1:pts+init);
fineelm = fineelm(init+1:pts+init);
yc = yc(init+1:pts+init);
yf = yf(init+1:pts+init);
figure(23);
subplot(2,2,1);
97
cspec = (abs(fft(corselm))).^2;
% power spectrum using fft
cspec = cspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(cspec));
% plot it
title(’Single Element Course Power Spectra (corselm)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,3);
fspec = (abs(fft(fineelm))).^2;
% power spectrum using fft
fspec = fspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(fspec));
% plot it
title(’Single Element Fine Power Spectra (fineelm)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,2);
cspec = (abs(fft(yc))).^2;
% power spectrum using fft
cspec = cspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(cspec));
% plot it
title(’Course Output Power Spectra (yc)’);
xlabel(’Frequency’);
ylabel(’Power’);
subplot(2,2,4);
fspec = (abs(fft(yf))).^2;
% power spectrum using fft
fspec = fspec(2:pts/2+1);
% only interested one side, forget dc
semilogx(10*log10(fspec));
% plot it
title(’Fine Output Power Spectra (yf)’);
xlabel(’Frequency’);
ylabel(’Power’);
% display avg/max/min on looping, or just the output when not
norm_factor
sigtonoisei
out_sig_to_noise
out_sfdr
out_avgc
out_avgf
out_delta
else
%output of the function
out = out_sig_to_noise;
end
elapsed_time = etime(clock, start_time)
function [elmc,elmf] = getdac2(clevs,flevs,fs,mmc,mmf)
% calculate random element values course and fine dac arrays; each element
% either added or subtracted
%
clevs
course output levels generated by the dac; there are (clevs-1)
% course elements
%
flevs
fine output levels generated by the dac; there are (flevs-1) fine
% elements
%
fs
full scale output value, positive side
%
mmc
desired course dac element mismatch, in percent
%
mmf
desired fine dac element mismatch, in percent
98
%
elmc
output vector containing (clevs-1) course dac element values
%
elmf
output vector containing (flevs-1) fine dac element values
%randn(’state’,sum(100*clock));
%randomly reset random number seed
nomc = fs*flevs/(clevs*flevs - 1);
% ideal course dac element value
% (mean of output array)
nomf = fs/(clevs*flevs - 1);
% ideal fine dac element value
% (mean of output array)
%elmc = nomc*(1 + 0.01*mmc*randn(1,clevs-1));
% 1-by-(clevs-1) array of
% random element values
elmf = nomf*(1 + 0.01*mmf*randn(1,flevs-1));
% 1-by-(clevs-1) array of
% random element values
for lop = 1:clevs-1
elmc(lop) = sum(nomf*(1 + 0.01*mmf*randn(1,flevs)));
end
%stdev_f = std(elmf)/nomf
%stdev_c = std(elmc)/nomc
%calc_stdv = sqrt(sum((elmc-nomc).^2)/16) / nomc
function [outc,outf,dubout,dubc,dubf] = idealq2(in,mc,bc,mf,bf,maxc,maxf)
% ideal 2-step (course,fine) quantization using pre-calculated slope and
% intercept values
%
in
value to be quantized
%
mc
course input multiplier before rounding
%
mf
fine input multiplier before rounding
%
bc
course input offset before rounding
%
bf
fine input offset before rounding
%
maxc
course output code is forced to be in range [0,maxc]
%
maxf
fine output code is forced to be in range [0,maxf]
%
outc
course output integer quantized value
%
outf
fine output integer quantized value
%
dubout output double quantized value (with same input range as ’in’)
%
dubc
course quantized value (with same input range as ’in’)
%
dubf
fine quantized value (with same input range as ’in’, but scaled
% to be fine)
outc = round(mc*in + bc);
% 1st (course) quantization step
outc = max([outc,0]);
outc = min([outc,maxc]);
dubc = (outc - bc)/mc;
outf = round(mf*(in - dubc) + bf);
% 2nd (fine) quantization step
outf = max([outf,0]);
outf = min([outf,maxf]);
dubf = (outf - bf)/mf;
dubout = dubc + dubf;
function [vecout,ptrout] = dem(code,lm1,ptrin)
% perform barrel-shifing dem algorithm
%
code
input integer code
%
lm1
(# dac output levels) - 1; number of dac elements
%
ptrin
position where elements start getting used this time, in range
% [0,levs-1]
%
vecout boolean output vector (+1 or -1) corresp to ’on’ elements in the
% DAC
%
ptrout position where elements start getting used next time, in range
% [0,levs-1]
99
ptrout = mod(ptrin+code,lm1);
if ((ptrout > ptrin) | (code == 0))
vecout =
[repmat(-1,1,ptrin),repmat(1,1,code),repmat(-1,1,lm1-code-ptrin)];
else
% (ptrout < ptrin) | (code == lm1)
vecout =
[repmat(1,1,code+ptrin-lm1),repmat(-1,1,lm1-code),repmat(1,1,lm1-ptrin)];
end
100
B.5
B.5.1
Additional Functions
mypsd
function out = mypsd(signal)
% Attempt to create a "mypsd" function
% Brent Nordick 01/17/03
pts = length(signal);
hann = 0.5*(1 - cos(2*pi*(0:pts-1)/pts) );
%hann window
spec = abs(fft(signal.*hann)).^2;
%/(pts/4);
%windowed FFT
spec = spec(2:pts/2+1);
%Choose only lower half (also omits DC?)
%Either output the value from the function or print to screen
if (nargout == 1),
out = spec;
elseif (nargout == 0),
figure;
semilogx(10*log10(spec));
title(’Power Spectrum of signal’);
xlabel(’Frequency’);
ylabel(’Power’);
%
hold on;
%compare w/ the PSD function - for now
%
[xspec,fvec] = psd(signal,pts,50e6,pts-1);
% power spectrum estimate
% using MATLAB’s psd, hanning window
%
xspec = xspec’;
%
semilogx(10*log10(xspec),’g’);
% plot it with frequency x-axis
end
101
B.5.2
mysnr
function out = mysnr(signal,bin,OSR)
% Attempt to create a "mysnr" function to calculate the signal-to-noise ratio
% of a given signal
% Brent Nordick 01/22/03
%signal:
%bin:
the signal to be analized
number of bins to divide the signal into
%temp or needed to pass?
sigbins = 1;
pts = size(signal);
sigv = signal(max([1,(bin-sigbins)]):bin+sigbins);
% signal plus spectral bleed
noisev = [signal(1:bin-sigbins-1) signal(bin+sigbins+1:pts(2)/OSR)];
% vector of bins used to calculate noise
%aparently wants pts/2/OSR to be an integer
sig = sum(sigv);
noise = sum(noisev);
sigtonoise = 10*log10(sig/noise);
%Either output the value from the function or print to screen
if (nargout == 1),
out = sigtonoise;
elseif (nargout == 0),
disp(’SNR’);
disp(sigtonoise);
end
102
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