10-bit 1-channel 100 MSPS ADC
SPECIFICATION
1. FEATURES
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TSMC CMOS 65 nm
Resolution 10 bit
1 channel
Different power supplies for digital (1.2 V) and analog parts (1.2 V)
Sampling rate up to 100 MSPS
Standby mode (current consumption <10 uA)
Low-power dissipation:
34 mW at 100 MSPS
21 mW at 50 MSPS
Differential full-scale input range peak-to-peak 1 V
Dynamic performance:
66.0 dB SFDR, 54.2 dB SINAD at 50 MSPS and fin = 10.7 MHz
66.3 dB SFDR, 53.0 dB SINAD at 100 MSPS and fin = 10.7 MHz
Differential nonlinearity 0.79 LSB
Integral nonlinearity 0.94 LSB
Compact die area 0.26 mm2
Supported foundries: TSMC, UMC, Global Foundries, SMIC
2. APPLICATION
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WiFi, WiMax
Mobile Communications
High quality imaging video systems
Data acquisition systems
Portable ultrasound and digital beam-forming systems
3. OVERVIEW
The 10-bit 100 MSPS ADC employs a high-performance front-end sample-and-hold with
differential multistage pipelined architecture and output error correction logic. The biasing circuit
and the clock generator are also included to provide a complete ADC. The ADC operates with
sampling rate up to 100 MSPS and a corresponding input clock up to 200 MHz (input clock is
divided by two). The ADC can be configured to achieve addition power saving at low sampling
rate, supports standby mode and features the excellent dynamic and static performance, wide
bandwidth inputs, low power consumption and compact die area.
The block is designed on TSMC CMOS 65 nm technology.
Ver. 1.2
January 2015
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
refp
adj_md<3:0>
adj_sh<3:0>
en
4. STRUCTURE
vdd_a
vdd_d
Configuration register
vcm
ip
Multi-stage pipelined
ADC
S/H
in
Output error
correction logic
refn
dout<9:0>
clkout
clkp
Clock generator
Biasing circuit
clkn
iref_10u
gnd_a
gnd_d
Figure 1: 10-bit 100 MSPS ADC structure
Ver. 1.2
page 2 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
5. PIN DESCRIPTION
Name
iref_10u
ip
in
clkp
clkn
refp
vcm
vcm
Direction
I
I
Analog differential input (1V peak-to-peak)
I
200MHz differential clock input
I
I
I
Positive reference voltage (0.8V)
Common mode voltage (0.55V)
Negative reference voltage (0.3V)
ADC enable:
“0”
disabled
“1”
enabled
Register of adjust reference current the sample and
hold:
“0001”
5uA
“1111”
75uA
Register of adjust reference current the multi-stage
ADC:
“0001”
5uA
“1111”
75uA
Output data
100MHz output clock
Analog block supply voltage (1.2V)
Digital blocks supply voltage (1.2V)
Analog blocks ground
Digital blocks ground
en
I
adj_sh<3:0>
I
adj_md<3:0>
I
dout<9:0>
clkout
vdd_a
vdd_d
gnd_a
gnd_d
O
O
P
P
P
P
Ver. 1.2
Description
Reference current (10uA)
page 3 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
6. FUNCTIONAL DESCRIPTION
The input clock is divided by two and after td1 time analog input voltage is sampled by the
positive edge. The output data after the conversion latency of 8 clock cycles is latched.
clkn
clkp
clkdiv
ip
in
td1
N+7
N+5
N
Sample
N+2
N+9
N+3
N+1
N+4
N+10
N+8
N+6
clkout
dout
N-5
N-4
N-3
N-2
N-1
N
N+1
N+2
N+3
N+4
Latency ~8 clock cycles
Figure 2: Timing diagram for normal operation
7. CURRENT CONSUMPTION PROGRAMMABILITY
There is also ability to adjust reference current the sample-and-hold and multi-stage pipeline
ADC. The values of reference current determine current consumption. Adjustable reference
current allows configuring operation mode related to static, dynamic performance and sampling
rate.
IDC = 5uA ∙ 440 ∙ adj_sh + 5uA ∙ 440 ∙ adj_md,
where adj_sh – decimal representation register of adjust reference current the sample and hold;
adj_md – decimal representation register of adjust reference current the multi-stage pipeline
ADC.
8. LAYOUT DESCRIPTION
8.1 TECHNOLOGY OPTIONS
ADC is designed under TSMC 65nm LP CMOS technology process with following options:
- 4x1z1u metal option
- 1.2V standard Vt MOS
- 1.2V low Vt MOS
- 2.0fF/um2 MIM capacitor
- P+ polysilicon OP resistor
Ver. 1.2
page 4 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
8.2
PHYSICAL DIMENTIONS
ADC layout dimensions are given in the table 1.
Table 1: Block dimension
Dimension
Height
Width
Value
410
630
Unit
um
um
Figure 3: Layout ADC
1. Sample and hold
2. Multistage ADC
3. Output error correction logic
4. Clock generator
5. Biasing circuit
Ver. 1.2
page 5 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
9. INTEGRATION GUIDELINES
9.1
PLACE AND ROUTE GUIDELINES
1) ADC analog inputs ip and in signals should be connected to analog IO PADs or an
internal analog circuits (intermediate frequency amplifier, filter). IO PADs should not
have an internal resistor to increase bandwidth.
2) Wiring of analog inputs should be symmetrical and as short as possible.
3) Noisy, power and high-frequency circuits should not place near ADC.
4) Minimum space 40 um between ADC and other circuits should be kept.
5) Minimum metal wiring width is 50 um for vdd_a and gnd_a. Multiple layers of metal can
be used to reduce layout space.
6) Minimum metal wiring width is 10 um for vdd_d and gnd_d. Multiple layers of metal can
be used to reduce layout space.
7) Allowable total resistance of vdd_a and gnd_a are 0.5 Ohm. Blocking capacitors should
be added and placed as close as possible.
8) Allowable total resistance of vdd_a and gnd_a are 2 Ohm. Blocking capacitors should be
added and placed as close as possible.
Ver. 1.2
page 6 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
10. ELECTRICAL CHARACTERISTICS
10.1 TECHNICAL CHARACTERISTICS
Technology
Status
Area
TSMC CMOS 65nm
silicon proven
0.26 mm2
10.2 ELECTRICAL CHARACTERISTICS
The values of electrical characteristics are specified for Vdd_a=1.14÷1.26 V, Vdd_d=1.14÷1.26 V and T =-40÷+85°C, typical values
are at Vdd_a = 1.2 V, Vdd_d=1.2 V, T = +27°C, unless otherwise specified.
Parameter
Operating temperature
range
max
-40
+27
+85
°C
Power Supply Requirements
1.14
1.14
FS= 50MSPS
FS= 100MSPS
-
1.2
1.2
17
28
1.26
1.26
-
V
V
mA
mA
-
10
-
uA
-
21
34
-
mW
mW
-
10
±0.79
±0.94
±2.0
±0.11
-
bit
LSB
LSB
LSB
LSB
T
-
Vdd_a
Vdd_d
Resolution
Differential nonlinearity
Integral nonlinearity
Offset error
Gain error
N
DNL
INL
OE
GE
Icn
Is
Pcn
FS= 50MSPS
FS= 100MSPS
DC Accuracy
FS=50MSPS
FS=50MSPS
FS=50MSPS
FS=50MSPS
Analog Inputs
Unit
AIN p-p
-
-
1
-
V
Vcm_in
-
0.5
-
0.55
V
Ceff_in
Reff_in
Output logic coding
High input level voltage
Low input level voltage
VIH
VIL
Input clock
Sampling rare
Duty cycle
Latency
Fclk
Fs
S
L
Reference current
Positive reference voltage
Common mode voltage
Negative reference
voltage
Iref
Vrefp
Vcm
Ver. 1.2
Value
typ.
Conditions
Analog supply voltage
Digital supply voltage
Current consumption in
normal mode
Current consumption in
standby mode
Power consumption in
normal mode
Differential full-scale
input range
Input common-mode
voltage
Input capacitance
Input resistance
min
Symbol
Vrefn
4
100
Digital Inputs and Outputs
Offset binary
0.7 Vdd_d
0.3 Vdd_d
Timing Information
200
Fclk/2
100
45
50
55
8
External Reference Requirements
9.9
10
10.1
0.80
0.55
-
page 7 of 13
-
0.30
-
pF
KOhm
code
V
V
MHz
MSPS
%
clock cycles
uA
V
V
V
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
Table “Electrical characteristics” (continue)
Parameter
Signal-to-noise ratio
Signal-to-noise and
distortion ratio
Effective number of bits
Worst second or third
harmonic
Spurious-free dynamic
range
Two-tone spurious-freedynamic range
Intermodulation
distortion third-order
Full power bandwidth
Signal-to-noise ratio
Signal-to-noise and
distortion ratio
Effective number of bits
Worst second or third
harmonic
Spurious-free dynamic
range
Full power bandwidth
Ver. 1.2
Symbol
Conditions
min
Dynamic characteristic at FS=50MSPS
fin = 10.7MHz
fin = 21.4MHz
SNR
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
SINAD
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
ENOB
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
SFDR
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
Two-tone
fin = 21.4MHz
SFDR
fin = 30MHz
fin = 10.7MHz
IMD3 fin = 21.4MHz
fin = 30MHz
FB
Dynamic characteristic at FS=100MSPS
fin = 10.7MHz
fin = 21.4MHz
SNR
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
SINAD
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
ENOB
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
fin = 30MHz
fin = 70MHz
fin = 10.7MHz
fin = 21.4MHz
SFDR
fin = 30MHz
fin = 70MHz
FB
-
page 8 of 13
Value
typ
max
54.3
53.5
53.0
49.8
54.2
53.4
52.9
49.6
8.7
8.6
8.5
8.0
78
81
67
76
66.0
63.3
61.1
54.5
64
61
58
74
76
71
500
-
dB
dB
dB
dB
dB
dB
dB
dB
bit
bit
bit
bit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
53.1
52.4
52.0
48.7
53.0
52.2
51.8
48.5
8.5
8.4
8.3
7.8
72
67
67
59
66.3
63.7
60.5
52.1
400
-
dB
dB
dB
dB
dB
dB
dB
dB
bit
bit
bit
bit
dB
dB
dB
dB
dB
dB
dB
dB
MHz
Unit
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
11. TYPICAL CHARACTERISTICS
Figure 4: Spectrum with FS=50 MSPS and
fin=10.7 MHz
Figure 5: Spectrum with FS=50 MSPS and
fin=21.4 MHz
Figure 6: Spectrum with FS=50 MSPS and
fin=30 MHz
Figure 7: Spectrum with FS=50 MSPS and
fin=70 MHz
Figure 8: Spectrum with FS=100 MSPS and
fin=10.7 MHz
Figure 9: Spectrum with FS=100 MSPS and
fin=21.4 MHz
Ver. 1.2
page 9 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
Figure 10: Spectrum with FS=100 MSPS and
fin=30 MHz
Figure 11: Spectrum with FS=100 MSPS and
fin=70 MHz
Figure 12: SNR/SFDR vs. Input Amplitude
with FS=50 MSPS and fin=10.7 MHz
Figure 13: SNR/SFDR vs. Input Amplitude
with FS=100 MSPS and fin=10.7 MHz
Figure 14: DNL with FS=50 MSPS and
fin=10.7 MHz
Figure 15: INL with FS=50 MSPS and
fin=10.7 MHz
Ver. 1.2
page 10 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
Figure 16: DNL with FS=100 MSPS and
fin=10.7 MHz
Figure 17: INL with FS=100 MSPS and
fin=10.7 MHz
Figure 18: Spectrum with FS=50 MSPS,
fin1=10.2 MHz and fin2=11.2 MHz
Figure 19: IMD3/SFDR vs. Input Amplitude
with FS=50 MSPS, fin1=10.2 MHz and
fin2=11.2 MHz
Figure 20: Spectrum with FS=50 MSPS,
fin1=20.9 MHz and fin2=21.9 MHz
Figure 21: IMD3/SFDR vs. Input Amplitude
with FS=50 MSPS, fin1=20.9 MHz and
fin2=21.9 MHz
Ver. 1.2
page 11 of 13
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
Figure 22: Spectrum with FS=50 MSPS,
fin1=29 MHz and fin2=31 MHz
Figure 23: IMD3/SFDR vs. Input Amplitude
with FS=50 MSPS, fin1=29 MHz and
fin2=31 MHz
Figure 24: Input histogram FS=50 MSPS
12. DELIVERABLES
Depending on license type IP may include:
 Schematic or NetList
 Abstract view (.lef and .lib files)
 Layout (optional)
 Verilog behavior model
 Extracted view (optional)
 GDSII
 DRC, LVS, antenna report
 Test bench with saved configurations (optional)
 Documentation
Ver. 1.2
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065TSMC_ADC_08
10-bit 1-channel 100 MSPS ADC
REVISION HISTORY
1. From version 1.0:
 The section “Overview” was changed (refer to page 1)
 The section “Structure” was changed (refer to page 2)
 The section “Pin description” was changed (refer to page 3)
 The section “Electrical characteristics” was changed (refer to page 5)
2. From version 1.1:
 The section “Feature” was changed (refer to page 1)
 The section “Overview” was changed (refer to page 1)
 The section “Structure” was changed (refer to page 2)
 The section “Pin description” was changed (refer to page 3)
 The section “Functional Description” was added (refer to page 4)
 The section “Current consumption programmability” was added (refer to page 4)
 The section “Layout description” was changed (refer to page 4)
 The section “Integration guidelines “ was added (refer to page 6)
 The section “Electrical characteristics” was changed (refer to page 7)
Ver. 1.2
page 13 of 13
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