a
FEATURES
Dual 10-Bit, 40 MSPS, 65 MSPS, 80 MSPS, and
105 MSPS ADC
Low Power: 275 mW at 105 MSPS per Channel
On-Chip Reference and Track/Holds
300 MHz Analog Bandwidth Each Channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p Analog Input Range Each Channel
Single 3.0 V Supply Operation (2.7 V–3.6 V)
Power-Down Mode for Single Channel Operation
Two’s Complement or Offset Binary Output Mode
Output Data Alignment Mode
Pin-Compatible with 8-Bit AD9288
–75 dBc Crosstalk between Channels
APPLICATIONS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
Ultrasound Equipment
10-Bit, 40/65/80/105 MSPS
3 V Dual A/D Converter
AD9218
FUNCTIONAL BLOCK DIAGRAM
ENCODE A
AD9218
TIMING
AINA
T/H
ADC
10
AINA
OUTPUT
REGISTER
10
REFINA
USER
SELECT #2
REF
REFOUT
REFINB
DATA
FORMAT/
GAIN
AINB
T/H
ADC
10
AINB
ENCODE B
D9A–D0A
USER
SELECT #1
OUTPUT
REGISTER
10
D9B–D0B
TIMING
VD
GND
VDD
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9218 is a dual 10-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
Low Power—Just 275 mW power dissipation per channel at
105 MSPS. Other speed grade proportionally scaled down while
maintaining high ac performance.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full operation. No external
reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible and a
separate output power supply pin supports interfacing with
3.3 V or 2.5 V logic.
Pin Compatibility Upgrade—Allows easy migration from 8-bit
to 10-bit. Pin-compatible with the 8-bit AD9288 dual ADC.
Ease of Use—On-chip reference and user controls provide flexibility in system design.
High Performance—Maintain 54 dB SNR at 105 MSPS with a
Nyquist input.
Channel Crosstalk—Very low at –75 dBc.
The clock input is TTL/CMOS-compatible and the 10-bit
digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combination of power-down modes, digital data formats and digital
data timing schemes. In power-down mode, the digital outputs
are driven to a high-impedance state.
Fabricated on an advanced CMOS process, the AD9218 is
available in a 48-lead surface-mount plastic package (7 × 7 mm
LQFP) specified over the industrial temperature range (–40°C
to +85°C).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9218–SPECIFICATIONS
DC SPECIFICATIONS (V
DD
Parameter
= 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
Temp
Test
Level
Min
RESOLUTION
ACCURACY
No Missing Codes1
Offset Error2
Gain Error2
Differential Nonlinearity
(DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error2
Reference
REFERENCE
Internal Reference Voltage
(REFOUT)
Input Resistance (REFIN A, B)
ANALOG INPUTS
Differential Input Voltage
Range (AIN, AIN)3
Common-Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY
VD
VDD
Supply Currents
IVD (VD = 3.0 V)4
IVDD (VDD = 3.0 V)4
Power Dissipation DC5
IVD Power-Down Current6
Power Supply Rejection Ratio
AD9218BST-40/-65
Typ
Max
Min
10
AD9218BST-80/-105
Typ
Max
10
GNT
2
18
3
8
± 0.3/± 0.6 1/1.3
Bits
Full
25°C
25°C
25°C
VI
I
I
I
–18
–2
–1
Full
25°C
Full
VI
I
VI
± 0.8
–1/–1.6 ± 0.3/± 1
±1
Full
Full
Full
V
V
V
25°C
I
1.18
1.24
1.28
1.18
1.24
1.28
V
Full
V
9
11
13
9
11
13
kΩ
Full
V
Full
Full
25°C
V
VI
V
8
VD/3
10
3
14
8
VD/3
10
3
14
V
kΩ
pF
Full
Full
IV
IV
2.7
2.7
3
3
3.6
3.6
2.7
2.7
3
3
3.6
3.6
V
V
Full
25°C
Full
Full
25°C
VI
V
VI
VI
I
108/117
7/11
325/350
20
±1
113/122
172/183
13/17
515/550
22
±1
175/188
mA
mA
mW
mA
mV/V
1/1.6
–18
–2
–1
GNT
2
3.5
± 0.5/± 0.8
Unit
± 0.6/± 0.9
–1.35/–2.7 ± 0.75/± 2
± 1/± 2.3
10
80
40
18
8
1.2/1.7
LSB
% FS
LSB
1.35/2.7
LSB
LSB
LSB
4
100
40
1 or 2
ppm/°C
ppm/°C
ppm/°C
1
340/365
V
525/565
NOTES
1
No Missing Codes across industrial temperature range guaranteed for -40 MSPS, -65 MSPS, and -80 MSPS grades. No missing codes at room temperature guaranteed for -105 grade.
2
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) -65 Grade in 2 V p-p range, -40, -85, -105 Grades in
1 V p-p range.
3
(AIN – AIN) = ± 0.5 V in 1 V range (full scale), (AIN – AIN) = ± 1 V in 2 V range (full scale).
4
AC Power Dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, C LOAD = 5 pF.
5
DC Power Dissipation measured with rated encode and a dc analog input (Outputs Static, IV DD = 0)
6
In power-down state IV DD = ± 10 µA typical (all grades).
Specifications subject to change without notice.
–2–
REV. 0
AD9218
DIGITAL SPECIFICATIONS
(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
Parameter
Test
Temp Level
DIGITAL INPUTS
Encode Input Common Mode
Encode “1” Voltage
Encode “0” Voltage
Encode Input Resistance
Logic “1” Voltage—S1, S2, DFS
Logic “0” Voltage—S1, S2, DFS
Logic “1” Current—S1
Logic “0” Current—S1
Logic “1” Current—S2
Logic “0” Current—S2
Logic “1” Current—DFS
Logic “0” Current—DFS
Input Capacitance—S1, S2, Encode Inputs
Input Capacitance DFS
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
V
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
V
V
Full
Full
VI
VI
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
AD9218BST-40/-65
Min
Typ
Max
Min
AD9218BST-80/-105
Typ
Max
VD/2
VD/2
2
2
0.8
2.3
1.8
2
2.0
–50
–400
50
–50
30
–400
± 10
–230
230
± 10
100
–230
2
4.5
0.8
+50
–50
400
+50
200
–50
2.45
1.8
2
2.0
–50
–400
50
–50
30
–400
± 10
–230
230
± 10
100
–230
2
4.5
0.8
2.3
0.8
+50
–50
400
+50
200
–50
2.45
0.05
Two’s Comp. or Offset Binary
0.05
Two’s Comp. or Offset Binary
Unit
V
V
V
kΩ
V
V
µA
µA
µA
µA
µA
µA
pF
pF
V
V
Specifications subject to change without notice.
AC SPECIFICATIONS
(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
Parameter
Temp
Test
Level
AD9218BST-40/-65
Min
Typ
Max
AD9218BST-80/-105
Min
Typ
Max
Unit
25°C
25°C
I
I
58/55
-/54
59/57
59/56
57/53
55/52
58/55
57/54
dB
dB
25°C
25°C
I
I
58/54
-/53
59/56
59/55
56/52
55/51
58/53
57/53
dB
dB
25°C
25°C
I
I
9.4/8.8
-/8.6
9.6/9.1
9.6/8.9
9.1/8.4
9/8.3
9.4/8.6
9.3/8.6
Bits
Bits
25°C
25°C
I
I
–72/–66
-/–63
–89/–77
–89/–72
–69/–60
–65/–57
–77/–68
–76/–66
dBc
dBc
25°C
25°C
I
I
–68/–62
-/–60
–79/–68
–78/–64
–62/–57
–63/–57
–71/–63
–73/–69
dBc
dBc
25°C
25°C
I
I
–68/–62
-/–60
–79/–67
–78/–64
–62/–57
–63/–57
–69/–62
–70/–63
dBc
dBc
25°C
V
–74/–73
25°C
V
–73/–73
–77/–67
dBc
25°C
25°C
V
V
300
–75
300
–75
MHz
dBc
1
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = Nyquist2
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = Nyquist2
Effective Number of Bits
fIN = 10.3 MHz
fIN = Nyquist2
Second Harmonic Distortion
fIN = 10.3 MHz
fIN = Nyquist2
Third Harmonic Distortion
fIN = 10.3 MHz
fIN = Nyquist2
Spurious Free Dynamic Range SFDR
fIN = 10.3 MHz
fIN = Nyquist2
Two-Tone Intermod Distortion (IMD)
fIN1 = 10 MHz, fIN2 = 11 MHz
at –7 dBFS
fIN1 = 30 MHz, fIN2 = 31 MHz
at –7 dBFS
Analog Bandwidth, Full Power
Crosstalk
dBc
NOTES
1
AC specs based on an analog input voltage of –0.5 dBFS at 10.3 MHz unless otherwise noted. AC specs for -40, -80, -105 grades are tested in 1 V p-p range and
driven differentially. AC specs for -65 grade are tested in 2 V p-p range and driven differentially.
2
The -65, -80, and -105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the -65, -80, and -105 grades respectively.
Specifications subject to change without notice.
REV. 0
–3–
AD9218–SPECIFICATIONS
SWITCHING SPECIFICATIONS (V
DD
= 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
Parameter
Temp
Test
Level
AD9218BST-40/-65
Min
Typ
Max
AD9218BST-80/-105
Min
Typ
Max
ENCODE INPUT PARAMETERS
Maximum Encode Rate
Minimum Encode Rate
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Full
Full
Full
Full
25°C
25°C
VI
IV
IV
IV
V
V
40/65
80/105
DIGITAL OUTPUT PARAMETERS
Output Valid Time (tV)*
Output Propagation Delay (tPD)*
Output Rise Time (tR)
Output Fall Time (tF)
Out of Range Recovery Time
Transient Response Time
Recovery Time from Power-Down
Pipeline Delay
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
VI
VI
V
V
V
V
V
IV
20/20
20/20
7/6
7/6
5/3.8
5/3.8
2
3
2
3
3
3
4.5
1
1.2
5
5
10
5
7
4.5
1.0
1.2
5
5
10
5
Unit
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
6
NOTES
*tV and t PD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 5 pF or a dc current of ± 40 µA. Rise and fall times measured from 10% to 90%.
Specifications subject to change without notice.
SAMPLE
N+5
SAMPLE
N+1
SAMPLE N
SAMPLE
N+6
AINA,
AINB
tA
t EH
t EL
SAMPLE
N+2
SAMPLE
N+3
SAMPLE
N+4
1/fS
ENCODE
A&B
tV
t PD
D9A–D0A
DATA N–5
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
D9B–D0B
DATA N–5
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
–4–
REV. 0
AD9218
SAMPLE
N
SAMPLE SAMPLE
N+2
N+1
SAMPLE
SAMPLE
N+7
N+8
AINA,
AINB
tA
t EH
SAMPLE SAMPLE SAMPLE SAMPLE
N+3
N+4
N+5
N+6
t EL
1/fS
ENCODE A
tV
t PD
ENCODE B
D9A–D0A
DATA N–10
D9B–D0B
DATA N–8
DATA N–9
DATA N–6
DATA N–7
DATA N–4
DATA N–5
DATA N–2
DATA N–3
DATA N
DATA N–1
DATA N+2
DATA N+1
Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
SAMPLE
N
SAMPLE SAMPLE
N+2
N+1
SAMPLE
SAMPLE
N+7
N+8
AINA,
AINB
tA
t EH
t EL
SAMPLE SAMPLE SAMPLE SAMPLE
N+3
N+4
N+5
N+6
1/fS
ENCODE A
tV
t PD
ENCODE B
D9A–D0A
DATA N–10
DATA N–8
DATA N–6
DATA N–4
DATA N–2
DATA N
DATA N+2
D9B–D0B
DATA N–11
DATA N–9
DATA N–7
DATA N–5
DATA N–3
DATA N–1
DATA N+1
Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
REV. 0
–5–
AD9218
ABSOLUTE MAXIMUM RATINGS 1
EXPLANATION OF TEST LEVELS
Test Level
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
REFIN Inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
θJA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
I
100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2
Measured on a four-layer board with solid ground plane.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9218 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature
Range
Package Description
AD9218BST-40, -65, -80, -105
AD9218-65PCB
AD9218-105PCB
–40°C to +85°C
25°C
25°C
Metric Quad Flat Pack (1.4 mm thick: LQFP)
Evaluation Board (Supports -40/-65 Grade)
Evaluation Board (Supports -80/-105 Grade)
Package
Option
ST-48
Table I. User Select Modes
S1
S2
User Select Options
0
0
1
1
0
1
0
1
Power-Down Both Channel A and B.
Power-Down Channel B Only.
Normal Operation (Data Align Disabled).
Data Align Enabled (data from both channels
available on rising edge of Clock A. Channel B
data is delayed by a 1/2 clock cycle.)
–6–
REV. 0
AD9218
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1, 12, 16, 27, 29, 32, 34, 45
GND
Ground
2
AINA
Analog Input for Channel A
3
4
AINA
DFS/GAIN
5
6
7
8
9
10
11
13, 30, 31, 48
14
15, 28, 33, 46
17–26
35–44
47
REFINA
REFOUT
REFINB
S1
S2
AINB
AINB
VD
ENCB
VDD
D9B–D0B
D0A–D9A
ENCA
Analog Input for Channel A (Complementary)
Data Format Select and Analog Input Gain Mode. (Low = offset binary output available, 1 V p-p supported; high = two’s complement output available,
1 V p-p supported; floating = offset binary output available, 2 V p-p supported;
Set to VREF = two’s complement output available, 2 V p-p supported.)
Reference Voltage Input for Channel A
Internal Reference Voltage
Reference Voltage Input for Channel B
User Select #1 (Refer to Table I)
User Select #2 (Refer to Table I)
Analog Input for Channel B (Complementary)
Analog Input for Channel B
Analog Supply (3 V)
Clock Input for Channel B
Digital Supply (2.5 V to 3.6 V)
Digital Output for Channel B (D9B = MSB)
Digital Output for Channel A (D9A = MSB)
Clock Input for Channel A
D2A
D3A
D4A
D5A
D6A
D8A
D7A
GND
D9A (MSB)
VDD
ENCA
VD
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
GND 1
AINA 2
PIN 1
IDENTIFIER
AINA 3
DFS/GAIN 4
REFINA 5
REFOUT 6
AD9218
TOP VIEW
(Not to Scale)
REFINB 7
S1 8
D1A
35
D0A
34
33
GND
VDD
32
GND
31
VD
VD
30
S2 9
AINB 10
28
GND
VDD
27
GND
AINB 11
26
GND 12
25
D0B
D1B
29
–7–
D2B
D3B
D4B
D5B
D6B
D7B
D8B
GND
(MSB) D9B
VDD
VD
ENCB
13 14 15 16 17 18 19 20 21 22 23 24
REV. 0
36
AD9218
TERMINOLOGY
Analog Bandwidth
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Integral Nonlinearity
Aperture Uncertainty (Jitter)
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
The sample-to-sample variation in aperture delay.
Minimum Conversion Rate
Crosstalk
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a
full-scale signal.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a
network analyzer.
Noise (for Any Range within the ADC)
Differential Analog Input Voltage Range
 FSdBm −SNRdBc −Signal dBFS 



10
Z × 0.001 × 10
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the inputs phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Where Z is the input impedance, FS is the full scale of the
device for the frequency in question, SNR is the value for the
particular input level, and Signal is the signal level within the
ADC reported in dB below full scale. This value includes both
thermal and quantization noise.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Effective Number of Bits
Signal-to-Noise-and-Distortion (SINAD)
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
ENOB =
VNOISE =
Power Supply Rejection Ratio
SNRMEASURED – 1.76 dB
6.02
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
ENCODE Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a given clock rate, these specifications define an acceptable ENCODE duty cycle.
Spurious-Free Dynamic Range (SFDR)
Full-Scale Input Power
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Expressed in dBm. Computed using the following equation:
Two-Tone Intermodulation Distortion Rejection
PowerFull −Scale
 V 2 Full −Scale rms
 Z INPUT
= 10 log 
0.001


The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.





Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
–8–
REV. 0
AD9218
Worst Other Spur
VD
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
REF
Transient Response Time
Transient response is defined as the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
10k⍀
Out-of-Range Recovery Time
Figure 8. Reference Inputs
Out of range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
VD
EQUIVALENT CIRCUITS
S2
VD
10k⍀
30k⍀
AIN
30k⍀
40⍀
40⍀
Figure 9. S2 Input
AIN
15k⍀
15k⍀
VD
Figure 4. Analog Input Stage
10k⍀
S1
VD
2.6k⍀
ENCODE
600⍀
Figure 10. S1 Input
2.6k⍀
VD
Figure 5. Encode Inputs
15k⍀
DFS/GAIN
VD
15k⍀
VREF
OUT
Figure 11. DFS/Gain Input
Figure 6. Reference Output Stage
VDD
40⍀
DX
Figure 7. Digital Output Stage
REV. 0
–9–
AD9218 –Typical Performance Characteristics
0
0
ENCODE = 105MSPS
AIN = 50.1MHz AT –0.5dBFS
SNR = 53.8dB
SINAD = 53.4dB
H2 = –69dB
H3 = –65.8dB
–10
–20
–30
–20
–30
–40
dB
dB
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
52.5
20
0
0
ENCODE = 80MSPS
AIN = 39MHz AT –0.5dBFS
SNR = 56.1dB
SINAD = 55.5dB
H2 = –71.8dB
H3 = –66.2dB
–10
–20
–30
ENCODE = 105MSPS
AIN = 70MHz AT –0.5dBFS
SNR = 51.9dB
SINAD = 51.8dB
H2 = –70.5dB
H3 = –76.3dB
–10
–20
–30
–40
dB
–40
dB
0
TPC 4. FFT: FS = 40 MSPS, AIN = 19.7 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range
TPC 1. FFT: FS = 105 MSPS, AIN = 50.1 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
0
40
TPC 2. FFT: FS = 80 MSPS, AIN = 39 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range
40
TPC 5. FFT: FS = 105 MSPS, AIN = 70 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range
0
0
ENCODE = 65MSPS
AIN = 30.3MHz AT –0.5dBFS
SNR = 56.1dB
SINAD = 55.9dB
SFDR = 72dB
H2 = –83.2dB
H3 = –79dB
–10
–20
–30
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
ENCODE = 65MSPS
AIN = 15MHz AT –0.5dBFS
SNR = 56.4dB
SINAD = 55.9dB
H2 = –73.9dB
H3 = –71.7dB
–10
dB
–40
dB
ENCODE = 40MSPS
AIN = 19.75 MHz AT –0.5dBFS
SNR = 58.4dB
SINAD = 58.3dB
H2 = –87dB
H3 = –81dB
–10
32.5
0
32.5
TPC 6. FFT: FS = 65 MSPS, AIN = 15 MHz @ –0.5 dBFS;
with AD8138 Driving ADC Inputs, 1 V p-p Input Range
TPC 3. FFT: FS = 65 MSPS, AIN = 30.3 MHz @ –0.5 dBFS,
Differential, 2 V p-p Input Range
–10–
REV. 0
AD9218
0
0
ENCODE = 31MSPS
AIN = 8MHz AT –0.5dBFS
SNR = 59.23dB
SINAD = 59.1dB
H2 = –87dB
H3 = –81dB
–10
–20
–30
–20
–30
–40
dB
dB
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
0
15.5
80
0
75
2ND
70
–20
65
–30
–40
dB
SFDR
dB
ENCODE = 105MSPS
AIN1 = 30.1MHz AT –7dBFS
AIN 2 = 31.1MHz AT –7dBFS
SFDR = –67dBFS
–10
3RD
60
55
–50
50
–60
45
–70
40
–80
35
–90
–100
0
100
150
AIN FREQUENCY – MHz
50
200
0
250
TPC 8. Harmonic Distortion (Second and Third) and SFDR
vs. AIN Frequency (1 V p-p, FS = 105 MSPS)
52.5
TPC 11. Two–Tone Intermodulation Distortion (30 MHz
and 31 MHz; 1 V p-p, FS = 105 MSPS)
80
0
3RD
75
70
–20
65
–30
–40
dB
SFDR
55
–50
50
–60
45
–70
40
–80
35
–90
30
–100
0
50
ENCODE = 80MSPS
AIN1 = 29.3MHz AT –7dBFS
AIN 2 = 30.3MHz AT –7dBFS
SFDR = –77dBFS
–10
2ND
60
dB
15.5
TPC 10. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS;
with AD8138 Driving ADC Inputs, 1 V p-p Input Range
TPC 7. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range
100
150
AIN FREQUENCY – MHz
200
0
250
TPC 9. Harmonic Distortion (Second and Third) and SFDR
vs. AIN Frequency (1 V p-p, FS = 80 MSPS)
REV. 0
–50
–60
30
ENCODE = 31MSPS
AIN = 8MHz AT –0.5dBFS
SNR = 59dB
SINAD = 58.8dB
H2 = –78.7dB
H3 = –72.9dB
–10
40
TPC 12. Two–Tone Intermodulation Distortion (29.3 MHz,
30.3 MHz; 1 V p-p, FS = 80 MSPS)
–11–
AD9218
0
90
H2 1V
ENCODE = 65MSPS
AIN1 = 28.1MHz AT –7dBFS
AIN 2 = 29.1MHz AT –7dBFS
SFDR = –72.9dBFS
–10
1V DIFFERENTIAL DRIVE
80 H3
1V
–20
70
–30
SFDR 1V
–40
H2 2V
dB
dB
60
50
–60
H3 2V
40
–50
–70
SFDR 2V
30
–80
20
10
2V SINGLE-ENDED DRIVE
–90
–100
0
20
40
60
80
100
120
140
160
180
0
32.5
AIN FREQUENCY – MHz
TPC 16. Two-Tone Intermodulation Distortion
(28 MHz, 29 MHz; 1 V p-p, FS = 65 MSPS)
TPC 13. Harmonic Distortion (Second and Third) and
SFDR vs. AIN Frequency (FS = 65 MSPS)
90
0
85
–10
2nd
80
–20
3rd
–30
SFDR
75
–40
dB
dB
ENCODE = 40MSPS
AIN1 = 10MHz AT –7dBFS
AIN2 = 11MHz AT –7dBFS
SFDR = 74dBc
70
–50
–60
65
–70
60
–80
55
–90
50
10
20
30
40
50
AIN FREQUENCY – MHz
60
–100
70
0
TPC 14. Harmonic Distortion (Second and Third) and
SFDR vs. AIN Frequency (1 V p-p, FS = 40 MSPS)
20
TPC 17. Two–Tone Intermodulation Distortion
(10 MHz, 11 MHz; 1 V p-p, FS = 40 MSPS)
80
75
SFDR
75
70
SFDR
70
65
dB
dB
65
60
60
SINAD
SNR
55
55
50
50
SINAD
45
45
0
20
40
60
80
ENCODE RATE – MSPS
100
0
120
10
20
30
40
50
60
70
80
ENCODE RATE – MHz
TPC 18. SINAD and SFDR vs. Encode Rate
(AIN = 10.3 MHz, 65 MSPS Grade) AIN = –0.5 dBFS
Differential, 1 V p-p Analog Input Range
TPC 15. SINAD and SFDR vs. Encode Rate
(fIN = 10.3 MHz, 105 MSPS Grade) AIN = –0.5 dBFS
Differential, 1 V p-p Analog Input Range
–12–
REV. 0
AD9218
75
75
SFDR
70
70
SFDR
65
65
60
60
dB
dB
55
SINAD
50
55
45
50
SINAD
40
45
35
40
30
0
1
2
3
4
5
6
ENCODE POSITIVE PULSEWIDTH – ns
7
8
0
TPC 19. SINAD and SFDR vs. Encode Pulsewidth High.
AIN = –0.5 dBFS Single-Ended, 1 V p-p Analog Input
Range 105 MSPS
200
2
4
6
8
10
12
ENCODE POSITIVE PULSEWIDTH – ns
14
TPC 22. SINAD and SFDR vs. Encode Pulsewidth High.
AIN = –0.5 dBFS Single Ended, 1 V p-p Analog Input
Range 65 MSPS
4.5
50
45
180
GAIN -105
35
140
25
3.5
%
30
IVDD mA
160
mA
4.0
40
IVD -105
3.0
20
GAIN -65
120
15
IVD -65
-65/-105 IVDD
2.5
10
100
5
80
0
20
40
60
80
100
ENCODE CLOCK RATE – MSPS
2.0
–40
0
140
120
TPC 20. IVD and IVDD vs. Encode Rate (AIN = 10.3 MHz,
@ –0.5 dBFS). -65/-105 MSPS Grade Cl = 5 pF
–20
0
20
40
TEMPERATURE – ⴗC
60
80
TPC 23. Gain Error vs. Temperature. AIN = 10.3 MHz,
-65 MSPS Grade, -105 MSPS Grade, 1 V p-p
68
1.231
66
1.229
64
1.227
62
SFDR -65
dB
V
SFDR -105
1.225
60
1.223
58
1.221
56
1.119
54
SNR -65
SINAD -65
SNR -105
SINAD -105
–40
–20
0
20
40
TEMPERATURE – ⴗC
60
52
–40
80
TPC 21. VREF Output Voltage vs. Temperature
(ILOAD = 300 µ A)
REV. 0
–20
0
20
40
TEMPERATURE – ⴗC
60
80
TPC 24. SNR, SINAD, SFDR vs. Temperature.
AIN = 10.3 MHz , -65 MSPS Grade, -105 MSPS Grade,
1 V p-p
–13–
AD9218
1.50
90
1.45
80
SFDR – dBFS
1.40
70
1.35
60
SFDR – dBc
1.30
dB
V
50
1.25
40
1.20
30
1.15
70 dB REF LINE
20
1.10
10
1.05
1.00
–1.0
–0.5
0
0.5
1.0
ILOAD – mA
1.5
2.0
2.5
TPC 25. VREF vs. ILOAD
SNR – dBc
0
–60
–50
–40
–30
–20
AIN INPUT LEVEL – dBFS
–10
0
TPC 27. SFDR vs. AIN Input Level. 10.3 MHz AIN @ 80 MSPS
1.0
2.0
0.8
1.5
0.6
1.0
0.4
0.2
LSB
LSB
0.5
0
0
–0.2
–0.5
–0.4
–1.0
–0.6
–1.5
–0.8
–1.0
–2.0
0
CODES
0
1024
TPC 26. Typical INL Plot. 10.3 MHz AIN @ 80 MSPS
CODES
1024
TPC 28. Typical DNL Plot. 10.3 MHz AIN @ 80 MSPS
–14–
REV. 0
AD9218
THEORY OF OPERATION
500⍀
The AD9218 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 7 MSBs and drive a 3-bit flash. Each stage provides
sufficient overlap and error correction allowing optimization of
comparator accuracy. The input buffers are differential, and both
sets of inputs are internally biased. This allows the most flexible
use of ac-coupled or dc-coupled and differential or single-ended
input modes. The output staging block aligns the data, carries
out the error correction, and feeds the data to output buffers.
The set of output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels.
USING THE AD9218
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/
Hold circuit is essentially a mixer. Any noise, distortion, or
timing jitter on the clock will be combined with the desired
signal at the A/D output. For that reason, considerable care has
been taken in the design of the ENCODE input of the AD9218,
and the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS-compatible.
Analog Input
The analog input to the AD9218 is a differential buffer. For
best dynamic performance, impedance at AIN and AIN should
match. Special care was taken in the design of the analog input
section of the AD9218 to prevent damage and corruption of
data when the input is overdriven. The nominal input range is
1.024 V p-p. Optimum performance is obtained when the part is
driven differentially where common mode noise is minimized
and even order harmonics are reduced. An example of driving
the AD9218 differentially via a wideband RF transformer for
ac-coupled applications is shown in Figure 12. Applications
that require dc-coupled differential drive can be accommodated using the AD8138 differential output op amp, shown
in Figure 13.
25⍀
1:1
0.1␮F
AD9218
25⍀
VOCM
AD8138
AIN
15pF
25⍀
10k⍀
AIN
500⍀
0.1␮F
5k⍀
525⍀
Figure 13. Using the AD8138 to Drive the AD9218
Voltage Reference
A stable and accurate 1.25 V voltage reference is built into the
AD9218 (VREF OUT). In normal operation, the internal reference is used by strapping Pin 5 (REFINA) and Pin 7 (REFINB)
to Pin 6 (REFOUT). The input range for each channel can be
adjusted independently by varying the reference voltage inputs
applied to the AD9218. No appreciable degradation in performance occurs when the reference is adjusted ± 5%. The
full-scale range of the ADC tracks reference voltage, which
changes linearly.
The minimum guaranteed conversion rate of the AD9218 is
20 MSPS. At clock rates below 20 MSPS, dynamic performance
will degrade.
User Select Options
Two pins are available for a combination of operational modes.
These options allow the user to power-down both channels,
excluding the reference, or just the B channel. Both modes place
the output buffers in a high impedance state. Recovery from a
power-down state is accomplished in 10 clock cycles following
power-on.
The other option allows the user to skew the B Channel output
data by one-half a clock cycle. In other words, if two clocks are
fed to the AD9218 and are 180 degrees out of phase, enabling
the data align will allow Channel B output data to be available
at the rising edge of Clock A. If the same encode clock is provided to both channels and the data align pin is enabled, output
data from Channel B will be 180 degrees out of phase with
respect to Channel A. If the same encode clock is provided to
both channels and the data align pin is disabled, both outputs are
delivered on the same rising edge of the clock.
AIN
Figure 12. Using a Wideband Transformer to Drive the
AD9218
REV. 0
AVDD
AD9218
25⍀
The AD9218 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Timing Diagram). The length of the output data lines and loads placed
on them should be minimized to reduce transients within the
AD9218. These transients can detract from the converter’s
dynamic performance.
The digital outputs are TTL/CMOS-compatible for lower
power consumption. During power-down, the output buffers
transition to a high impedance state. A data format selection
option supports either two’s complement (set high) or offset
binary output (set low) formats.
AIN
500⍀
Timing
Digital Outputs
50⍀
ANALOG
SIGNAL
SOURCE
50⍀
ANALOG
SIGNAL
SOURCE
–15–
AD9218
wideband RF transformer T1, T2, allowing the ADC performance
for differential inputs to be measured using a single-ended source.
In this mode resistors R35, R33, R39, and R32 should not be in
place. Each analog input is terminated on the board with 50 Ω to
ground. Each input is ac-coupled on the board through a 0.1 µF
capacitor to an on-chip resistor divider that provides dc bias.
Single-ended performance can be measured by bypassing the
transformers using connectors SMB J5 (Channel A) and J1
(Channel B). In this mode, place a 0 Ω resistor at R35 and R33
(A Channel) and place R39 and R32 (B Channel). Note that the
inverting analog inputs are terminated on the board with 25 Ω
(optimized for differential operation). When driving the board
single-ended these resistors (R1, R3) can be changed to 50 Ω to
provide balanced inputs. The operational amplifier can be
used by connecting to J5 (Channel A) and J1 (Channel B).
The ac-coupling capacitors on the top level should be removed
from the board to use the operational amplifier. The components to use the op amp should be placed on the bottom of the
board. See PCB Bill of Materials list for values.
APPLICATIONS
The wide analog bandwidth of the AD9218 makes it attractive
for a variety of high-performance receiver and encoder applications. Figure 14 shows the dual ADC in a typical low cost
I and Q demodulator implementation for cable, satellite, or
wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and
encode rates empowers users to employ direct IF sampling
techniques. IF sampling eliminates or simplifies analog mixer
and filter stages to reduce total system cost and power.
AD9218
IF IN
BPF
Q
ADC
BPF
I
ADC
90
VCO
VCO
Encode
Figure 14. Typical I/Q Demodulation Scheme
EVALUATION BOARD
The AD9218 evaluation board offers an easy way to test the
AD9218. It provides a means to drive the analog inputs singleendedly or differentially. Differential drive can be tested through
a wideband RF transformer or a differential output operational
amplifier, the AD8138. The two encode clocks are accessible via
on-board SMB connectors J2, J7. These clocks are buffered
on board to provide the clocks for an on-board DAC and latches.
The digital outputs and output clocks are available at two 40-pin
connectors, P3 and P4. The board has several different modes
of operation, and is shipped in the following configuration:
The encode clock for Channel A uses SMB connector J7.
Channel B encode uses SMB connector J2. Each clock input is
terminated on the board with 50 Ω to ground. The input clocks
are fed directly to the ADC and to buffers U5, U6, which drive
the DAC and latches. The clock inputs are TTL-compatible.
Voltage Reference
The AD9218 has an internal 1.25 V voltage reference. An external reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18–E1 and E17–E19). To use external references,
connect to VREFA and VREFB pins on the power connector P1
and use jumpers E20–E18 and E19–E21.
Normal Operation Mode
• Differential Analog Input (RF Transformer Mode)
Power Connector
In this mode both converters are clocked by the same encode
clock, latency is five clock cycles (see Timing Diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set with the jumpers labeled S1 and S2 (near the analog input).
Power is supplied to the board via a detachable 12-pin power strip.
Data Align Mode
+5 V – Optional Supply for Operational Amplifier
–5 V – Optional Supply for Operational Amplifier
VREFA – Optional External Reference Input
VREFB – Optional External Reference Input
VDL – Supply for Support Logic and DAC
VDD – Supply for ADC Outputs
VD – Supply for ADC Analog
In this mode channel B output is delayed an additional one-half
cycle. Signals S1 (Pin 8) and signal S2 (Pin 9) are both held
high. This is set with the jumpers labeled S1 and S2 (near the
analog input).
• Normal Operation Timing Mode
• Internal Voltage Reference
Data Format Select
Analog Inputs
The evaluation board accepts a 1 V analog input signal centered
at ground at each analog input. SMB connectors J4 and J6 are
used for AIN and BIN respectively. These signals each drive a
Data Format Select sets the output data format and the gain of
the ADC. Setting DFS (Pin 4) low sets the output format to be
offset binary and gain of 1; setting DFS high sets the output to
be two’s complement and gain of 1. Removing the jumper for
DFS sets the output data format to offset binary and a gain of 2;
setting DFS to the middle selection sets the output data format
to two’s complement and a gain of 2.
–16–
REV. 0
AD9218
PCB Bill of Materials
#
Qty
REFDES
Device
Package
Value
1
2
3
6
7
29
2
7
8
3
C1, C3–C15, C20–C25, C27–C35
C2, C36
C16, C17, C18, C19, C26, C37, C38
J1, J2, J3, J4, J5, J6, J7, J8
P1, P4, P11
Capacitor
Capacitor
Capacitor
Connector
4-Pin Power Connector
0603
0603
TAJD
SMB
TB4
0.1 µF
15 pF
10 µF
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
8
10
2
6
2
2
8
2
2
1
2
1
2
4
2
P2, P3
R1–R4, R22–R24, R30
R5–R12, R34, R37
R13, R14
R15, R17, R18, R26, R29, R31
R16, R25
R19, R27
R20, R32, R33, R35, R36, R38–R40
R21, R28
T1, T2
U1
U2, U3
U4
U5, U6
U7, U8, U9, U10
U11, U12
HEADER40
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Transformer
AD9218
74LCX821
AD9763
74LCX86
Resistor Array
AD8138
0603
0603
0603
0603
0603
0603
0603
0603
ADT-1-1WT
LQFP48
SO24M3
LQFP48
SO14
CTS20
SO8NB
25 Ω
50 Ω
2 kΩ
500 Ω
525 Ω
4 kΩ
0Ω
1 kΩ
Minicircuits
Wieland
25.531.3425.0
Z5.602.5453.0
22 Ω
NOTE
R22, R23, R24, R30, R32, R33, R35, R36, R38, R39, R40, C2, C36 not placed on board.
Data Outputs
DAC Outputs
The ADC digital outputs are latched on the board by two
LCX821s, the latch outputs are available at the two 40-pin
connectors at Pins 23–33 on P3 (Channel A) and Pins 23–33 on
P4 (Channel B). The latch output clocks (data ready) are available at Pin 4 on P3 (Channel A) and Pin 4 on P4 (Channel B).
The data ready signal on Channel B can be aligned with Clock
A input by connecting E43–E42 or aligned with Clock B input
by connecting E42–E33.
Each channel is reconstructed by an on-board dual channel DAC,
an AD9763. This DAC is intended to assist in debug only. It
should not be used to measure the performance of the ADC.
It is a current output DAC with on-board 50 Ω termination
resistors. Figure 16 is representative of the DAC output with a
full-scale analog input. The scope setting was low bandwidth,
50 Ω termination.
PIN 31 (DATA)
PIN 37 (CLOCK)
T
T
1
CH1
CH1 2.00V CH2 2.00V M 10.0ns
CH4
40mV
M 50.0ns
CH1
Figure 16. DAC Output
Figure 15. Data Output and Clock at 80-Pin Connector
REV. 0
500mV⍀
–17–
380mV
C19
10␮F
ENCODE A
GND
TIEA
VDL
1
E34
12 E3
VDL
E41
GND
CLKDACA
11
10
E39 E38
9
E37
8
GND
DRA
VDL
D2A
D3A
37
D2A
D4A
38
D3A
D5A
D6A
D7A
41
D6A
D8A
42
D7A
D9A
43
GND
D0B
VD
ENCB
36
35
34
D1A
D0A
GND
C4
0.1␮F
GND
33
32
VDD
GND
31
VD
30
29
C3
0.1␮F
GND
GND
28
27
26
D0B
D1B
GND
24
D2B
25
VDD
C1
0.1␮F
GND
D2B
23
D3B
C5
0.1␮F
D3B
D1B
GND
C11
0.1␮F
D8A
45
GND
VDD
OPTIONAL INPUT PATH FOR OPAMP OR SINGLE-ENDED
GND
46
47
ENCA
GND
D6B
R3
25⍀
VD
20
R32
0⍀
VD
U1
D6B
GND
AD9218
D7B
C12
0.1␮F
VDD
E18 6
VREFA
REFOUT
E17
VREFB
7
REFINB
E24
E21
E19
8
S1
E22
9
S2
AINBB
10
AINB
AINB
11
AINB
12
GND
GND
GND
R39
0⍀
3Y
GND
REFINA
19
4
GND
DFS/GAIN
D7B
3
R4
25⍀
E26
5
VDD
48
6
5
E29
E20 E1
D8B
AMPINB
AINB
R38
SINGLE-ENDED
0⍀
J1
R37
50⍀
GND
GND
1
2
3A
GND
18
GND
E28
T1
3B
2Y
AINAB
GND
GND
VD
4
GND
AINB
DIFFERENTIAL
C30
0.1␮F
GND
E23
4Y
2B
D0A
16
J6
E30
GND
VD
3
E25
E2 E27
C9
0.1␮F
C15
0.1␮F
R6
50⍀
VD
GND
4
U8
AINA
VDD
T2
REFOUT
4A
D1A
ENCB
3
6
5
AINAB
GND
15
C14
0.1␮F
AINA
DIFFERENTIAL
GND
R2
25⍀
1
GND
2
C10
0.1␮F
VD
J4
GND
AINA
GND
C31 GND
0.1␮F
1
GND
2
GND
VD
R1
25⍀
R36
0⍀
AMPINA
GND
AINA
SINGLE-ENDED
14
J5
R5
50⍀
GND
D8B
GND
R33
00⍀
13
R35
00⍀
1Y
13 E40
GND
VD
GND
C7
0.1␮F
GND
R34
50⍀
4B
C8
0.1␮F
44
–5V
OPTIONAL INPUT PATH FOR OPAMP OR SINGLE-ENDED
GND
VCC
1B
C25
0.1␮F
VDL
14
GND
+5V
GND
GND
VDD
ENCA
D9A
VDL
D9B
VDD
E31
17
E32
7
GND
D9B
VD
VDD
VREFB
E9
VREFA
GND
VDL
VD
GND
VDD
GND
E10
6
CLKLATA
1A
2A
5
39
3 2
4
P14
E36
E35
D4A
4
ENCA
3
D4B
1
P13
22
2
2
D4B
4 3
1
TIEA
40
1
GND
P11
P4
P1
E47
2
P12 P19
R11
GND 50⍀
GND
E45
VDL
3
74LCX86
J7
E46
4
GND
ENCA
C26
10␮F
D5A
C18
10␮F
D5B
C17
10␮F
VREFB
VREFA
VDL
VDD
C16
10␮F
21
C38
10␮F
DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED
D5B
C37
10␮F
VD
–5V
+5V
AD9218
GND
VDD
C6
0.1␮F
GND
DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED
C27
0.1␮F
REFINA
C24
0.1␮F
GND
ENCB
ENCODE B
REFINB
74LCX86
P20 P21
J2
E49
TIEB
E50
H4
MT HOLE6
H2
MT HOLE6
H1
MT HOLE6
H3
MT HOLE6
VDL
E48
GND
VDL
R7
GND 50⍀
GND
E13
TIEB
P23
ENCB
GND
2
3
P22
E16
E14
1
4
5
DRB
GND
6
7
1A
VCC
1B
4B
1Y
4A
2A
U5
4Y
2B
3B
2Y
3A
GND
3Y
14
13
E5
12 E4
11
C13
0.1␮F
VDL
E44
GND
CLKLATB
10
9
8
VDL
E11
E15
VDL
E12
GND
GND
CLKDACB
Figure 17a. PCB Schematic
–18–
REV. 0
REV. 0
–19–
Figure 17b. PCB Schematic
D9B
D8B
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
U8
CT520
VALUE = 22
U7
CT520
VALUE = 22
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
D9N
D8N
D7N
D6N
D5N
D4N
D3N
D2N
D1N
D0N
D0M
D1M
D2M
D3M
D4M
D5M
D6M
D7M
D8M
D9M
GND
D9N
D8N
D7N
D6N
D5N
D4N
D3N
D2N
D1N
D0N
GND
GND
D0M
D1M
D2M
D3M
D4M
D5M
D6M
D7M
D8M
D9M
GND
12
11
10
9
8
7
6
5
4
3
2
1
12
11
10
9
8
7
6
5
4
3
2
1
GND
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
OE
U2
CLK
U3
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VCC
CLK
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VCC
74LCX821
GND
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
GND
74LCX821
13
14
15
16
17
18
19
20
21
22
23
24
CLKLATA
D0X
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D8X
D9X
D9Y
D8Y
D7Y
D6Y
D5Y
D4Y
D3Y
D2Y
D1Y
D0Y
D0X
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D8X
D9X
CLKLATA
E43
E42 E33
D0Y
D0Y
D0Y
D0Y
D0Y
D0Y
D0Y
D0Y
D0Y
D0Y
C20
0.1␮F
VDL
GND
13
14
15
16
17
18
19
20
21
22
23
24
C21
0.1␮F
VDL
GND
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
CLKLATD
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
U10
CT520
VALUE = 22
U9
CT520
VALUE = 22
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
D0P
D1P
D2P
D3P
D4P
D5P
D6P
D7P
D8P
D9P
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
15
13
11
9
7
5
3
1
14
12
10
8
6
4
2
17
19
21
23
25
27
29
31
33
35
37
16
18
20
22
24
26
28
30
32
34
36
38
P2
1
2
39
3
4
40
5
9
10
6
11
12
7
13
14
8
15
16
19
21
23
25
27
29
31
17
HEADER40
P3
33
35
37
39
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
E7
E8
GND
GND
GND
GND
GND
GND
GND
D0Q
D1Q
D2Q
D3Q
D4Q
D5Q
D6Q
D7Q
D8Q
D9Q DRB
GND
GND
GND
GND
GND
GND
GND
GND
GND
D0P
D1P
D2P
D3P
D4P
D5P
D6P
D7P
D8P
D9P
GND
DRA
GND
E6
DRA
AD9218
AD9218
J3
GND
GND
GND
GND
40 R8, 50⍀
SLEEP
37
38
39
IB2IA2
ACOM
41 R14, 2k⍀
FSADJ2
42
REFLO
43
FSADJ1
REFIO
44 R13, 2k⍀
45 R12, 50⍀
IB1
46
IA2
DB6–P2
DB9–P2
24 DB8–
P2
DB7–P2
36
35
34
33
32
D0X
31
D1X
30
D2X
29
D3X
28
D4X
27
D5X
26
D6X
25
D7X
23
DCOM2
22
WRT2/IQSEL
CLK2/IQRESET
DB5–P2
21
20
CLK1/IQCLK
19
DVDD
WRT1/IQWRT
DB4–P2
18
13
NC = NO CONNECT
DB3–P2
DCOM1
D0Y
DB2–P2
17
D1Y
DB1–P2
9763
GND
D2Y
NC7
DB0–P2
16
D3Y
POWER-DOWN OPTION
NC4
15
48
D4Y
R20
00⍀
NC5
NC3
D5Y
NC2
D6Y
VDL
GND
NC6
14
D7Y
AVDD
MODE
47
GND
D8Y
(OPTIONAL)
R40
00⍀
R9
50⍀
GND
VDL
C22
0.1␮F
1 DB9
–P1
2
DB8–P1
3
DB7–P1
4
DB6–P1
5
DB5–P1
6
DB4–P1
7
DB3–P1
8
DB2–P1
9
DB1–P1
10
DB0–P1
11
NC
12
NC1
GND
GND
GND
D9Y
GND
J8
C23
0.1␮F
R10
50⍀
VDL
DAC OUTPUT A
GND
DAC OUTPUT B
GND
GND
CLKDACA
C28
0.1␮F
CLKDACA
GND
CLKDACB
CLKDACB
GND
U4
GND
GND
D8X
D9X
GND
C29
0.1␮F
VDL
VDL
R18
500⍀
R21
1k⍀
R27
4k⍀
GND
C32
0.1␮F
R22
25⍀
R25
525⍀
4
3
V+
+OUT
–IN
C36
15pF
R29
500⍀
AIINAB
V–
–OUT
R24
25⍀
5
NC = NO CONNECT
+IN
–OUT
V–
U12
AD8138
R23
25⍀
5
6
NC
+IN
7
8
R17
500⍀
2
1
4
3
V+
2
1
–IN
VOCM
+OUT
C2
15pF
AMPINA
R30
25⍀
AINBB
U11
AD8138
NC = NO CONNECT
GND
GND
AINA
6
GND
GND
VOCM
R16
525⍀
GND
C35
0.1␮F
+5V
NC
+5V
R28
1k⍀
5V
7
5V
8
R19
4k⍀
R26
500⍀
AMPINB
GND
AINB
GND
C33
0.1␮F
C34
0.1␮F
–5V
–5V
R15
500⍀
R31
500⍀
Figure 17c. PCB Schematic
–20–
REV. 0
AD9218
Figure 18. PCB Top Side Silkscreen
Figure 19. PCB Top Side Copper
REV. 0
–21–
AD9218
Figure 20. PCB Ground Layer
Figure 21. PCB Split Power Plane
–22–
REV. 0
AD9218
Figure 22. PCB Bottom Side Copper
Figure 23. Bottom Side Silkscreen
REV. 0
–23–
AD9218
Troubleshooting
• Verify power at IC pins.
The AD9218 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
• Check that all jumpers are in the correct position for the
desired mode of operation.
• Verify VREF is at 1.23 V.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C02001–1.5–7/01(0)
• Try running encode clock and analog inputs at low speeds
(20 MSPS/1 MHz) and monitor LCX821 outputs, DAC
outputs, and ADC outputs for toggling.
If the board does not seem to be working correctly, try the
following:
48-Lead LQFP
(ST-48)
0.063 (1.60)
MAX
0.030 (0.75)
0.018 (0.45)
0.354 (9.00) BSC SQ
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
0ⴗ
MIN
12
25
13
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
24
0.011 (0.27)
0.006 (0.17)
0.057 (1.45)
0.053 (1.35)
7ⴗ
0ⴗ
0.006 (0.15) SEATING
0.002 (0.05) PLANE
PRINTED IN U.S.A.
COPLANARITY
0.003 (0.08)
–24–
REV. 0