IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 8, AUGUST 2009
843
Abstract —In this letter, we demonstrated dopant-segregated
Schottky (DSS) p-MOSFET with gate-all-around silicon-nanowire
(SiNW) channel of 10 nm in diameter. The DSS transistor shows improved performance as compared to a reference Schottky barrier (SB) transistor without dopant segregation. The DSS transistor shows I
ON
−
0.6 V, high I
ON of 319
/I
OFF
μ A /μ m at a low gate overdrive of ratio (
∼
10
5
) , and short-channel performance with subthreshold slope
∼
90 mV/dec down to 100-nm gate length with relatively thick (6 nm) deposited gate oxide. The
DSS transistor also shows significant reduction (
∼
40
× lower) in the series resistance as compared to the SB transistor. The origin of the improved performance of the DSS is the thin dopant layer segregated at the nickel monosilicide/SiNW point contact which results in the enhanced hole injection at the source side and the suppressed electron injection at the drain side.
Index Terms —Dopant segregation (DS), gate-all-around (GAA),
Schottky barrier (SB) MOSFET, silicon nanowire (SiNW).
device [9]. However, most of the reported GAA devices suffer from “parasitic gate” formed during poly-Si etching, leaving behind a trail of poly-Si underneath the S/D extension, known as the polysilicon stringer [9]–[12]. This polysilicon stringer results in the underestimate of the effective gate length L
G and can contribute to the enhanced coupling between the gate and the effective SBH.
In this letter, SiNW dopant-segregated Schottky (DSS)
MOSFETs with a GAA structure free of polysilicon stringer are demonstrated for the first time. The devices are electrically characterized and exhibit excellent performance in terms of
I
ON
/I
OFF
, subthreshold swing (SS), as well as showing a much reduced series resistance as compared to SB MOSFETs.
I. I NTRODUCTION
S CHOTTKY barrier (SB) MOSFETs have been proposed to replace conventional MOSFETs due to their lower sheet resistance and abrupt junction usually formed by metal silicides
[1]. SB MOSFETs, however, suffer from high contact resistance which is related to the metal–semiconductor SB height (SBH) and the doping concentration at the SB interface [2]. Hence, two approaches have been proposed to reduce the contact resistance. First, by using noble or rare-earth metals such as
Pt [3], Er [4], Dy [5], or Yb [6], lower SBH can be achieved.
Second, metal silicide can be formed on an ultrashallow doped region to pile up the dopants at the SB interface or commonly known as dopant segregation (DS) [7], [8]. More recently, the effective SBH of silicon-nanowire (SiNW) SB MOSFETs has been shown to be more effectively modulated by the gate electrostatic field with smaller SiNW in a gate-all-around (GAA)
Manuscript received April 22, 2009; revised May 5, 2009. First published
June 23, 2009; current version published July 27, 2009. The review of this letter was arranged by Editor J. Cai.
Y. K. Chin is with the School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore 639798, and also with the
Institute of Microelectronics, A*STAR (Agency for Science, Technology and
Research), Singapore 117685 (e-mail: september_king@hotmail.com).
K.-L. Pey, K. H. Tan, and C.-Y. Ong are with the School of Electrical and
Electronic Engineering, Nanyang Technological University, Singapore 639798
(e-mail: eklpey@ntu.edu.sg; tank0106@ntu.edu.sg; ON0004IN@ntu.edu.sg).
N. Singh, G.-Q. Lo, and L. H. Tan are with the Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research),
Singapore 117685 (e-mail: navab@ime.a-star.edu.sg; logq@ime.a-star.edu.sg; tanlh@ime.a-star.edu.sg).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2009.2022851
II. D EVICE F ABRICATION
As starting substrates for the fabrication of DSS p-MOSFET,
200-mm p-type (100) SOI wafers with a resistivity of
5–10 Ω · cm and top silicon thickness of 70 nm on 145-nm buried oxide (BOX) were used. The top silicon was thinned down to 30 nm by oxidation. KrF lithography with alternating phase-shift mask was used to pattern the active areas of thin fin connected to source/drain regions. The photoresist was further trimmed to obtain a fin width of 30 nm. Si was etched to the
BOX to form the fin and source/drain mesa, followed by dry oxidation at 875
◦
C to further reduce the fin to nanowire with a diameter of 10 nm. Gate stack was defined by depositing
6 nm of LPCVD SiO
2 and 60-nm B-doped poly-Si followed by 20-nm-wide SiO
2
/ SiN spacer formation. Due to the nature of dry etching, conventional gate etching for GAA SiNW
MOSFETs will leave behind a trail of poly-Si underneath the SiNW extension from the S/D to the gate, commonly known as the polysilicon stringer. A new poly-Si etching is employed to remove the polysilicon stringer below the SiNW extension. Fig. 1(a) shows a twin SiNW MOSFET after poly-Si gate etching, and the inset on the top-right-hand corner shows the enlarged view of the SiNW extension without polysilicon stringer after gate etching while the inset on the bottomleft-hand corner shows a cross-sectional transmission electron micrograph (X-TEM) of the SiNW channel. Fig. 1(b) shows the GAA SiNW transistor with and without the polysilicon stringer. For SB MOSFETs, no implantation was done on the source/drain prior to silicidation. For DSS MOSFETs, a lowenergy BF
2
( 1
×
10
15 cm
− 2
/ 10 keV ) implantation was carried out prior to silicidation. The 10-nm Ni was then deposited followed by a two-step rapid thermal annealing (RTA) at 300
30 s and 450
◦
◦
C/
C/30 s while the unreacted Ni was etched back
0741-3106/$26.00 © 2009 IEEE
Authorized licensed use limited to: Nanyang Technological University. Downloaded on August 31, 2009 at 23:42 from IEEE Xplore. Restrictions apply.

844 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 8, AUGUST 2009
Fig. 2.
(a) I
D
– V
G and (b) I
D an SB MOSFET with L
G
– V
D characteristics of a DSS MOSFET versus
= 50 nm. The current of the SB MOSFET has been multiplied by ten in the I
D
– V
D plot for better comparison with the DSS
MOSFET. The current was normalized by using the diameter of the SiNW channel.
Fig. 1.
(a) Tilted SEM view of twin SiNWs channel MOSFET after poly-Si gate etch. The L
G is approximately 50 nm. The top-right-corner inset shows the enlarged view of the SiNW extension from the GAA channel free of the polysilicon stringer. Dotted lines show the original position of the polysilicon stringer before being etched away. The bottom-left-corner inset shows the
X-TEM of the 10-nm-diameter SiNW with 6-nm gate oxide. (b) Schematics of a GAA SiNW MOSFET (left) with and (right) without polysilicon stringer.
after the first RTA by immersing the samples in a sulfuric peroxide mixture ( H
2
SO
4
: H
2
O
2
= 4 : 1 ) for 5 min.
III. R ESULTS AND D ISCUSSION
Fig. 2(a) shows the I
D
– V
G of a DSS MOSFET and an SB
MOSFET with physical gate length, L
G
= 50 nm. It is clear that the DSS MOSFET shows improved transistor characteristics as compared to the SB MOSFET. The SB MOSFET I
D
– V
G curve indicates a typical ambipolar characteristic commonly seen in SB devices. This is due to the near-midgap SB at the
S/D, which has an electron barrier height of 0.67 eV and a hole barrier height of 0.45 eV for nickel monosilicide (NiSi). When the gate overdrive is negatively biased ( V
G
− V
T , sat
< 0 ) , the channel is in accumulation mode, and current is conducted by the transport of holes from the source side to the channel. When the gate overdrive is positively biased ( V
G
− V
T , sat
> 0 ) , the channel is inverted, and current is conducted by the transport of electrons from the source to the channel. As shown in Fig. 2(b), compared with the SB MOSFET, the DSS MOSFET achieves a higher I
ON of 319 μ A /μ m while the SB MOSFET, with exponential increase in the drain current lower I
ON
V
DS of 11.2
μ A /μ
=
−
1.0 V. The I
ON
I
DS
, shows a much m at a gate overdrive of
−
0.6 V and has been normalized to the SiNW diameter. Observation shows that the DSS MOSFET drive current I
ON is more than one order of magnitude higher, and also, its I
OFF
10
−
4 μ A /μ is about five orders of magnitude (approximately m for the DSS MOSFET versus 10 μ A /μ m for the
SB MOSFET) lower than that of the SB MOSFET at V
DS
=
1.0 V. The remarkable enhancement of DSS MOSFET over the
SB MOSFET is due to the existence of a thin layer of segregated
Fig. 3.
SS of the DSS MOSFETs extracted from various gate lengths ranging from 30 to 320 nm. The SS is observed to be constant down to L
G
= 100 nm.
boron at the NiSi–Si point contact on the SiNW at the S/D-tochannel side. It is believed that the fully depleted boron result in the distortion of the SB depletion region, thus giving rise to an enhanced hole carrier injection at the source side and a suppressed electron injection from the drain side as compared to the SB junction without DS. It is worth noting that the effect of the polysilicon stringer on the SB thinning in the SiNW has been removed in our GAA devices. Hence, the modulation of the SB depletion region is the result of the GAA electrostatic field modulation on the SB at the NiSi–Si point contact.
Fig. 3 shows the subthreshold slope (SS) of the DSS
MOSFETs as a function of L
G
. It can be observed that the
SS of the devices remain constant at approximately 90 mV/dec until L
G
= 100 nm, below which the SS starts to increase exponentially until 150 mV/dec at L
G
= 30 nm. Recently, the
SS achievable by conventional SiNW MOSFETs have been demonstrated to be close to the thermal limit at 60 mV/dec
[9]–[11], [13]. The lowest SS achieved in this letter is approximately 90 mV/dec, and this is attributed to the interface states and a lower oxide quality of LPCVD oxide that is used as the gate dielectric of the devices.
Authorized licensed use limited to: Nanyang Technological University. Downloaded on August 31, 2009 at 23:42 from IEEE Xplore. Restrictions apply.

CHIN et al.
: DOPANT-SEGREGATED SCHOTTKY SILICON-NANOWIRE MOSFETs 845 mally grown oxide with optimized silicidation condition to induced DS.
A CKNOWLEDGMENT
The authors would like to thank the IME SPT staff for the device fabrication and characterization support. The author
Y. K. Chin would like to thank NTU and Chartered Semiconductor Manufacturing for the joint graduate scholarship.
Fig. 4.
Total series resistance R
Total with L
G
= of the DSS MOSFET and SB MOSFET
50 nm and channel diameter of 10 nm measured at V
DS for various applied V
GS
. The indicated series resistance R
SD is normalized to the SiNW diameter and is extracted at higher V
GS
V
GS
= 10 V by extrapolating the R
Total
. The DSS MOSFET has a much smaller R
SD curve to than that of the SB
MOSFET.
The series resistance of SiNW MOSFETs is also characterized for both DS and SB devices, as shown in Fig. 4. The series resistance of a SiNW MOSFET is of particular interest due to the small dimensions of the NiSi–Si point contact and the extension of the SiNW from the channel to the S/D. The total series resistance R
Total series resistance R
SD
(indicated in data points) is plotted against the applied gate voltage V
GS at V
DS
= 50 mV. The is normalized to the SiNW diameter and is extracted by extrapolating an exponentially decaying curve to V
GS
= 10 V [14]. The R significant, with R
SD
SD difference for both devices is
= 6467 Ω
·
μ m for the SB MOSFET as compared to approximately 40 times lower R
SD
= 153 Ω
·
μ m for the DSS MOSFET. For a Schottky device, series resistance consists of two major components: S/D silicide sheet resistance and SB contact resistance. As both devices are silicided with the same condition, the main contributor to the R
SD reduction is attributed to the much lower SB contact resistance of the DSS
MOSFET as a result of the high doping level at the NiSi–Si interface.
IV. C ONCLUSION
Using top-down technology, true GAA SiNW DSS
MOSFET without parasitic polysilicon stringer has been successfully demonstrated and characterized. The results show that
DSS MOSFET is superior to its SB MOSFET counterpart.
The DSS MOSFET exhibits higher electrical performance in terms of I
ON and I
ON
/I
OFF ratio, good short-channel performance with constant SS of approximately 90 mV/dec down to
L
G
= 100 nm, as well as a significant
∼
40
× reduced series resistance. The improvement is attributed to the thin layer of segregated dopants piling up at the NiSi–Si point contact of the SiNW DSS MOSFET. It is expected that the device performance can be further improved by using thinner ther-
R EFERENCES
[1] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D
Schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices , vol. 53, no. 5, pp. 1048–1058, May 2006.
[2] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices ., 3rd ed.
Hoboken, NJ: Wiley, 2007, p. 304.
[3] C. Wang, J. P. Snyder, and J. R. Tucker, “Sub-40 nm PtSi Schottky source/drain metal–oxide–semiconductor field-effect transistors,” Appl.
Phys. Lett.
, vol. 74, no. 8, pp. 1174–1176, Feb. 1999.
[4] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, K. M. Hoe,
G. Cui, and P. S. Lee, “Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel,”
IEEE Electron Device Lett.
, vol. 29, no. 10, pp. 1167–1170, Oct. 2008.
[5] S. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee,
M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, “Schottky barrier S/D MOSFETs with highK gate dielectrics and metal-gate electrode,” IEEE Electron Device Lett.
, vol. 25, no. 5, pp. 268–270, May 2004.
[6] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du,
C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier source/drain MOSFET using ytterbium silicide,” IEEE Electron Device
Lett.
, vol. 25, no. 8, pp. 565–567, Aug. 2004.
[7] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution for high-performance Schottky barrier height engineering with dopant segregation technique,” in VLSI Symp. Tech. Dig.
, Jun. 2004, pp. 168–169.
[8] A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, “High-performance
50-nm-gate-length Schottky-source/drain MOSFETs with dopant segregation junctions,” in VLSI Symp. Tech. Dig.
, 2005, pp. 158–159.
[9] J. W. Peng, S. J. Lee, G. C. A. Liang, N. Singh, S. Y. Zhu, G. Q. Lo, and
D. L. Kwong, “Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors,” Appl. Phys. Lett.
, vol. 93, no. 7, p. 073 503, Aug. 2008.
[10] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi,
C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D. L. Kwong,
“High-performance fully depleted silicon nanowire (diameter
≤
5 nm) gate all-around CMOS devices,” IEEE Electron Device Lett.
, vol. 27, no. 5, pp. 383–386, May 2006.
[11] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal,
C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye,
G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channelorientation and low temperature on device performance,” in IEDM Tech.
Dig.
, 2006, pp. 548–551.
[12] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, L. J. Tang,
P. S. Lee, and C. K. F. Ho, “Nickel-silicided Schottky junction CMOS transistors with gate-all-around nanowire channels,” IEEE Electron Device Lett.
, vol. 29, no. 8, pp. 902–905, Aug. 2008.
[13] K. H. Yeo, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Cho, K. H. Hong, S. Yun,
M. S. Lee, N. Cho, K. Lee, D. Hwang, B. Park, D. W. Kim, D. Park, and B. I. Ryu, “Gate-all-around (GAA) twin silicon nanowire MOSFET
(TSNWFET) with 15 nm length gate and 4 nm radius nanowires,” in
IEDM Tech. Dig.
, Dec. 2006, pp. 1–4.
[14] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and
K. De Meyer, “Analysis of the parasitic S/D resistance in multiple-gate
FETs,” IEEE Trans. Electron Devices , vol. 52, no. 6, pp. 1132–1140,
Jun. 2005.
Authorized licensed use limited to: Nanyang Technological University. Downloaded on August 31, 2009 at 23:42 from IEEE Xplore. Restrictions apply.