The Effect of Die Attach Layer Delamination on the Thermal Performance
of Plastic Packages
Asif Chowdhury1, Bruce Guenin2, ChanHee Woo1, SeungMo Kim1, Seri Lee2
1
R&D Center, Anam Semiconductor, 280-8, 2GA, Songsu-Dong
SongDong Ku, Seoul, Korea.
Tel: (822) 460-5456, Fax: (822) 460-5462
e-mail: achow@amkor.com
To be presented at the
ECTC Conference,
May 25-28, 1998,
Seattle, Washington
2
Amkor Electronics, Inc.
1900 South Price Road, Chandler, AZ 85248, USA.
Tel: (602) 821-5000, Fax: (602) 821-6730
e-mail: bguen@amkor.com,
Abstract
Plastic semiconductor packages uptake moisture under
ambient conditions. This can cause delamination at various
interfaces within the package during the reflow process for
board mounting. Delamination in the die attach region is
known to increase the thermal resistance of that interface,
leading to increased die temperatures and reduced
reliability. This paper investigates the effect of die attach
layer delamination on the thermal performance of standard
and heatslug MQFP package designs by means of
measurement and thermal simulation. A series of severe
temperature/moisture conditions was used to produce
delamination in these packages. A thermal model for the
delaminated interface was validated experimentally. It is
shown that the maximum acceptable % of delamination is
highly dependent on the power in the application and the
degree to which the power is evenly dissipated over the
surface of the die. The larger power levels made possible
by the use of heatslug packages and external heat sinks lead
to a lower tolerance for delamination than would be
indicated in lower power applications.
Introduction
With the semiconductor industry driving towards
miniaturization, increasing power and device speed there
have been a growing demand for improved thermal
performance of plastic packages. Many new designs have
evolved in plastic packages that use exposed or embedded
heat slugs or exposed pads to better facilitate heat flow out
of the package. Materials with higher thermal conductivity
are also being investigated to improve the thermal
performance of these packages.[1] It has been shown that,
for plastic packages, the best heat flow path is from the die
through the die attach material, leadframe paddle, mold
compound and leads. More than 80% of the heat from the
die flows along this path for standard plastic packages.[2]
In the case of thermally enhanced packages the die is likely
to be attached directly on a metal slug or spreader. In this
case most of the heat flows out of the package through the
slug or through the leads via the slug/spreader.[3] In either
case there is a concern as to how delamination in the die-to-
paddle interface, i.e., in the die attach region, affects the thermal
performance of the package. The concern in the industry is that
even if a package passes the 85oC, 85% RH (JEDEC level 1)
moisture resistant test [4], it can still have die attach layer
delamination caused by the reflow process (during board mount)
which will adversely affect the package thermal performance.
This paper investigates the relationship between the die attach
delamination and the package thermal resistance as functions of
the package type and of the uniformity of heat generation on the
die using both experimental and computer simulation methods.
JEDEC classifies plastic packages by their ability to resist
moisture induced delamination during the soldering process
according to an accelerated schedule of temperature, humidity,
time exposures.[4] In this study the packages were subjected to
various moisture/temperature conditions for whatever time was
required to achieve the necessary percent delamination in the die
attach region. In doing so, typical JEDEC moisture level tests
were exceeded in achieving the largest values of delamination.
From this point onward the word “delamination” will refer to
die attach region delamination only, unless otherwise specified.
Package Description
For this study two package types have been chosen, MQFP
and PowerQuad2.[5] Cross sectional view of the two package
types are shown in Figure 1. The PowerQuad2 is an MQFP with
a heatslug that is exposed at the bottom of the package. The
heatslug is attached to the leadframe with polyimide tape. In case
of PowerQuad2, the die is attached directly to the heatslug with
die attach material. The critical package dimensions are shown
in Table 1.
Package/
Thickness
(mm)
Lead
Count
Body
(mm)
Pad or
Heatslug
(mm)
Die
(mm)
MQFP/
3.37
PowerQuad2/
3.37
208
28x28
11.0x11.0
208
28x28
14.75x14.75
7.7x7.7x
0.66
7.7x7.7x
0.66
Table 1 Critical package dimensions
Die
Au Wire
Lead
Paddle
a)
Tape
Heat Slug
Die Attach Material
Die Attach Material
Lead
b)
Au Wire
Die
Figure 1 Cross section of (a) MQFP and (b)
PowerQuad2 package
Procedures
Test Sample Preparation
All packages were assembled using silicon thermal test
dies, having no backside metal, i.e., the backside is bare
silicon.
It has been observed that delamination at any interface
is dependent on the moisture present in the package.[6]
This theory was applied in our effort to introduce %
delamination in the die attach region. Table 2 shows the
material set and thermal conductivity of each material
chosen for the packages.[7]
Package
Component
Leadframe
Heat Slug*
Tape*
Die
Die Attach
Material
Thickness
(mm)
Cu Alloy C7025
0.1524
OFHC
1.67
Tomoegawa
0.065
Silicon, PST-5
0.66
Ablestik
--84-1LMISR4
Wire
Gold, 1.3 mil
--dia
Mold
Nitto
--Compound
MP8000CH4
*Only applicable for PowerQuad2 package.
K
(W/mK)
250
390
0.22
89
2.5
413
0.7
Table 2 Material set for the packages with respective
thermal conductivity.
The target die attach region delamination was 0%-10%, 20%35%, 45%-55%, 70%-80% and 90%-100% for each package
type. The reason for this distribution is that it is difficult to
introduce an exact % delamination. After assembly completion,
all units were checked for delamination using a SAT (Scanning
Acoustic Tomography) technique.[8] A SONIX SAT machine
was used. After that, the units were baked in 125 °C for 24 hours
in order to drive any moisture out of the package. The units then,
were subjected to various moisture conditions for different
lengths of times. After moisture soak the units were put through
VPS (vapor phase shock) reflow at 220oC. At this point the
packages were checked for delamination again using SAT. The
target % delamination was achieved by a trial and error method;
i.e.: if the delamination was found to be less than the target value
then the units were put back in the temperature/humidity
chamber and the test cycle was performed again. Typical
temperature and humidity conditions used were (a) 30oC/60%
RH, (b) 85oC/60% RH and (c) 85oC/85% RH. The units were
typically put in 30 °C/60% RH for one day and then put through
VPS reflow. If the target % delamination was not achieved, then
the units were subjected to higher temperature and humidity
conditions for two hours at a time and put through VPS again.
This kind of cycle was repeated as necessary to induce the target
delamination. Once the target delamination was established, the
units were dry baked one more time to drive out any remaining
moisture and board mounted for thermal testing. This process
flow is summarized in Figure 2.
SAT images were analyzed using a photo editor program to
calculate the exact percent delamination in the die attach region.
Metallographic Examination
To understand the delamination mode, eight units with a
known percentage of delamination were cross-sectioned. For this
purpose units were sawn diagonally and then polished using
Silicon Carbide abrasive paper and 1 micron diamond particle
suspended in an oil base. The samples were then photographed
using a high-magnification optical imaging system.
Thermal Tests
The thermal tests consisted of the measurement of the junctionto-ambient (ΘJA) and junction-to-case (ΘJC) thermal resistances,
performed in accordance with applicable SEMI and JEDEC
standards.
Each of the tests consists of the measurement of the center
die temperature ,TJ, a reference temperature, TX, and the applied
power. The resultant thermal resistance, ΘJX, is calculated from
the following formula:
Θ JX =
TJ − TX
P
For ΘJA measurements, the reference temperature is the upstream
temperature of the incoming air, TA. For ΘJC measurements, it is
the case temperature, TC, located at the center of the package on
the side facing the underside of the die.
Both the measurement of TJ and the application of power to
the die was facilitated by the use of thermal test dies, specifically
designed for that purpose (Delco, PST-5). The test dies provided
for the measurement of TJ by means of a diode structure in the
center of the die. Each die contains a thin film resistor heater
End of Assembly
SAT
Dry Bake (125o C, 24 hrs)
Moisture Soak
VPS (220o C)
SAT
No
Target %
Delam
Achieved
Yes
Dry Bake (125o C, 24 hrs)
Board Mount
Figure 2. Typical process flow for
introducing delamination.
that covers more than 85% of the die surface, consistent
with the JEDEC guideline.[9]
The packages were mounted to test boards with one
signal layer and two internal planes compliant with the
JEDEC specification.[10]
ΘJA tests were performed on most of the samples at 3 air
velocities: 0, 1.0, and 2.5 m/s, in a closed-circuit wind
tunnel having a 30.5 cm square test section, with the board
in the horizontal orientation. Measurements in natural
convection conditions in the wind tunnel were shown to
correlate very closely with results obtained in a JEDECstandard 30.5 x 30.5 x 30.5 cm (1 ft3 ) sealed chamber.[11]
In order to reduce the total test time, selected packages
were tested only at 0 m/s. A single power level was used
for each of the package types during these tests: 1.5 W for
the MQFP packages and 2.0 W for the PowerQuad2
packages
ΘJC tests were performed on the PowerQuad2 packages
in accordance with the appropriate SEMI Specification
[12], augmented by certain enhancements. These consist of an
improved method of measuring the case temperature, the
insulation of the board-mounted package from the ambient air
(with a 2.54 cm thick layer of Styrofoam), and the application of
a specified contact force (1.8 kgf) between the package and the
copper block. The package was placed in contact with the
water-cooled copper block, having a contact area of 1.25 cm sq.
A thin layer of thermal grease was applied to the surface of the
block before mounting the package to enhance the heat transfer
across the interface. This arrangement allows access to a portion
of the slug for mounting a thermocouple to the slug beyond the
contact region with the block. A type K thermocouple was
mounted to the slug with a small amount of thermal grease in the
contact area and held in place with a small piece of adhesive
foam tape.
Thermal Simulation
The thermal simulation was performed using a commercial
finite element analysis, FEA, software package.[13] The
simulated environment replicated that of the PowerQuad2
package in the ΘJC test fixture. To adequately represent the heat
transfer within the package in this situation, it was only
necessary to include the die, die attach, and heatslug. Adiabatic
boundary conditions were applied to all surfaces not represented
as in contact with the copper block. The component dimensions
and thermal conductivity values are given in Tables 1 and 2.
The delaminated region was represented as an area with a
constant air gap, bounded by the outer edges of the die and by
the non-delaminated portion of the die attach, which was
assumed to be square in shape and centered on the die. The
thickness of the die attach and the air gap were determined by
correlating the ΘJC test results with the FEA results at 0% and
100% delamination, respectively. The simulation was used to
calculate the center and peak die temperatures.
The thermal model for the delaminated region, validated in
the analysis of the test packages, was used to predict the impact
of delamination on a silicon chip with a much more localized
heat generation, occupying only 10% of the total die area. This
is representative of mixed signal (analog/digital) applications.
Results
SAT
At the end of assembly, in case of MQFP, all units showed
zero delamination. For PowerQuad2 packages all units showed
die attach delamination around 12%-25% after assembly. A
fairly even distribution of % delamination was achieved for both
the packages that were either within the target % delamination
range or very close to it.
Typical SAT images of the progressive % delamination for
MQFP and PowerQuad2 are shown in Figure 3.
Metallographic Examination
From the cross-sectioned units it was seen that the
delaminated region is thin compared to the die attach epoxy
region and it always occurs between die attach and die.
Figure 4 shows a typical micrograph of a cross-sectioned
MQFP package. The average bond line thickness was measured
to be 22 µm. The average air gap was measured to be in the
range of 2 to 3 µm.
Thermal Test
Figure 5 presents the thermal test data in graphical form
versus the % delamination. Figures 5a and 5b show ΘJA and ΘJC
data for the PowerQuad2 package. Figure 5c presents the ΘJA
data for the MQFP package. At an arbitrary % delamination,
ΘJA for the PowerQuad2 package is much lower than that of the
MQFP package. This is due to the effect of the heat slug in
more effectively coupling heat flow to the package leads,
whence it is conducted to the test board. The distribution of the
data between 0 and 100% illustrate reasonable success in
achieving the target values of delamination. The effect of
increasing the % delamination from 0 to 100% produced a
similar increase in ΘJA independent of package type and velocity
and in ΘJC..
a)
(°C/W)
a)
0 m/s
14
1 m/s
12
2.5 m/s
JA
b)
16
10
Figure 3. SAT image (T-SCAN) showing
progressive % delamination under die for
(a) MQFP and (b) PowerQuad2.
Black area represents delamination.
8
0
Pad
JC
Die Attach
Epoxy
(°C/W)
b)
20
40
60
80
100
Die Attach Delamination (%)
2
1.6
1.2
0.8
0.4
0
0
JA
(°C/W)
c)
20
40
60
80
100
Die Attach Delam ination (%)
28
0 m/s
26
1 m/s
24
2.5 m/s
22
20
Die
Air Gap
Figure 4. A typical micrograph of a cross-sectioned
unit showing delamination.
0
20
40
60
80
100
Die Attach Delam ination (%)
Figure 5. Thermal data for PowerQuad2 and MQFP
packages versus % delamination.
Figure 6 displays the deviation of ΘJX (ΘJA or ΘJC )
from its value at 0% delamination. Figure 6a indicates that,
for the PowerQuad2 packages, both ΘJA and ΘJC exhibit the
same trend, with 100% delamination producing the same
change from the 0% value of about 1.5°C/W. The graph in
Figure 6b superimposes the deviation in ΘJC measured for
the PowerQuad2 package over the ΘJA data for the MQFP
package. This shows that the change in the ΘJC data
adequately represents the change in ΘJA for both packages.
The subsequent thermal simulation results will focus on
analyzing the ΘJC results, due to the smaller amount of
scatter in those data.
a) 2.0
JC
JA , 0 m/s
1.0
JA , 1 m/s
0.5
JA , 2.5 m/s
0.0
JX
(0%) (°C/W)
1.5
definition of ΘJmaxC for ΘJC calculated in this way. Due to the
symmetry of the delamination assumed in the model, the
maximum value of TJ occurs at the corners of the die. The
temperature distribution on the die surface is illustrated for 75%
delamination in Figure 7b. The elevated temperature in the
corners of the die is due to the constriction resistance in the
silicon for heat to converge from the surface of the die to the
contact region.[14]
There is a considerable difference between the calculated
values of ΘJC based on the center and maximum values of TJ.
From a reliability point of view, it is the maximum junction
temperature that is of real interest. Hence, in the subsequent
evaluation of the derating of the power capability of these
packages due to delamination, the more conservative ΘJmaxC and
ΘJmaxA will be used, rather than the usual ΘJC and ΘJA. In this
analysis, ΘJmaxA is calculated as a function of % delamination by
equating the deviation in ΘJmaxA from its 0% value to the
deviation in ΘJmaxC from its value at 0%.
JC, Fit
-
-0.5
JX
0
20
40
60
80
a)
100
2
JX
-
JX
(0%) (°C/W)
2.0
1.5
JA , 0 m/s
1.0
JA , 1 m/s
0.5
JC
b)
( °C/W)
D/A De lam ination (%)
Model,
Max
1.6
1.2
Model,
Center
0.8
0.4
Meas .,
Center
0
0
JA , 2.5 m/s
20
40
60
80
100
D/A De lam ination (%)
0.0
JC, PQ2
-0.5
0
20
40
60
80
100
D/A De lam ination (%)
Figure 6 Deviation in ΘJA or ΘJC from value at 0%
Thermal Simulation
Correlation with Test Results
Figure 7a presents a comparison of the calculated
results and measured values for ΘJC for TJ measured at the
center of the die. The assumed values of thickness of the
die attach and the air gap are 22µm and 2.1µm,
respectively. The results are presented explicitly in Table
3. The agreement in the range of 0-50% delamination and
at 100% is good. The agreement in the range of 75-85% is
worse. The model assumed that the thermal conductivity
of the die attach in the region remaining in contact does not
degrade with increasing delamination.
These results
suggest that there is some degradation in the die attach
thermal conductivity as the delamination approaches 100%.
It should be noted that the value of the air gap determined
from the thermal simulation is in good agreement with that
measured microscopically.
Figure 7a also displays the calculated value for ΘJC
based upon the maximum value of TJ. We hereby adopt the
b)
Figure 7. a) Comparison of calculated and measured
values of ΘJC and b) temperature contours on die surface
calculated for 75% delamination case.
% Delam
0
25
50
75
100
Meas.
Θ JC
(Center)
(°C/W)
0.26
0.31
0.47
0.90
1.57
Model
Θ JC
Θ JmaxC
(Center) (Corner)
(°C/W)
(°C/W)
0.27
0.27
0.30
0.40
0.35
0.69
0.44
1.05
1.65
1.63
Table 3. Comparison of measured and modeled
values of ΘJC for TJ at center and corner of die.
Figure 8 illustrates the % increase in ΘJmaxA due to the
occurrence of a given % of delamination under various air
flow conditions, which serve to produce a variation in ΘJA.
In Figures 8a and 8b, the MQFP and PowerQuad2 are
assumed to be in the same range of air velocity conditions
explored in this paper. An upper x-axis is included that
provides a means of determining the dissipated power
associated with the indicated value of ΘJA, assuming a 60°C
temperature difference between the junction and the air. [A
60°C temperature rise is typical of many applications.] The
MQFP shows only a minimal % change in ΘJmaxA. Even at
100% delamination, the maximum change in ΘJmaxA is just
above 6%. The highest power level achieved for this
package consistent with the temperature difference
criterion is 2.8W. It is attained at an air velocity of 2.5 m/s.
Since the PowerQuad2 has a smaller range of values of ΘJA,
a given % of delamination produces a greater % change in
ΘJmaxA than that observed for the MQFP. In order to keep
the increase in ΘJmaxA at 5% or less, the % delamination
must to kept below 50%. The highest power level available
in these conditions is 7.1W, attainable at an air velocity of
2.5 m/s.
Figure 8c illustrates the impact of delamination on a
high-thermal-performance situation, in which an external
heat sink is assumed to be attached to the slug of the
PowerQuad2 package. A suitable heat sink could readily
decrease ΘJA to 4°C/W and enable a power dissipation of
15W. However, in order to keep the increase in ΘJmaxA to
less than 5%, the highest acceptable level of delamination
should be maintained at under 25%.
a) MQFP, b) PowerQuad2, and c) PowerQuad2 with heat sink
Effect of Concentrated Heat Source
A second situation is explored that serves to illustrate
another factor that can exacerbate the effect of
delamination on the junction temperature. This occurs
when the silicon chip has devices on it that dissipate most
of the total power over a small fraction of the total area of
the chip.
A significant difference in the calculated values of ΘJC and
ΘJmaxC is evident between this case and the previous one in
which the power was dissipated evenly over the die
surface. A comparison of these parameters for the two
cases is presented in Figure 9a. Here, ΘJmaxC is more than
twice as large as it was in the other case. Figure 9b
illustrates the substantial thermal gradient that exists
between the heat generating portion of the die and the
surrounding silicon. This thermal gradient is due to the
spreading resistance for heat flow in the silicon. It is
exacerbated, in general for thinner dies. This effect is
much more serious for GaAs dies, which have a thermal
conductivity one-third that of silicon. The impact of the
spreading resistance in the present case is manifest vividly
in Figure 10, which shows the impact of delamination on
ΘJmaxC and the power capability of the package. There are
two negative effects on the thermal performance. The first
is that ΘJmaxC increases more rapidly with increasing
delamination than in the previous case (Fig. 8b) for
delamination greater than 50%. The second is that, at a
4
Max
3
Center
2
1
Max,
Fig. 7
0
Center
Fig.7
JC
( °C/W)
a)
0
20
40
60
80
100
D/A De lam ination (%)
b)
Figure 9. a) Effect of delamination on ΘJC for chip
with concentrated power dissipation; b) calculated
temperature contours at 75% delamination.
given % delamination, ΘJA is higher than in the previous case.
Hence, at the same % of delamination, the maximum power that
can be dissipated in the package is reduced. This comparison is
best illustrated by reference to Figure 11, which indicates the
maximum power achievable at a given % of delamination in the
standard test environment. For example, looking at the highest
value of the baseline ΘJA in each graph (at 0 m/s airflow), with
the uniformly heated die, a power level of 4.5W is possible even
at 75% delamination. With the locally heated die, this can not
even be achieved at 0% delamination.
[Note to the reader: It should be emphasized that the achievable
power dissipation in an actual application at a given air velocity
can differ significantly from that in the standard test
environment. It typically will be smaller in the application.]
Discussion
A primary benefit of this work is that the thermal
properties of the delaminated region are examined by
modeling and testing. The increase in the ΘJA and ΘJC with
delamination correlate very well
with the % of
delamination. A simple thermal model that postulates a
constant air gap of 2µm in the delaminated region accounts
well for the data.
As should be clear from the preceding analyses, the
thermal impact of a given % of delamination on the
increase in the die temperature can only be determined with
a close look at the details of the die construction, package
construction, and the total dissipated power required by the
application.
Using the thermal model for the delaminated interface
validated in this study, it is possible to predict the effect of
delamination for other package styles and other die designs
with some confidence. The only caveat is that the findings
of this study have been demonstrated only for a single
materials set, consisting of the die attach and the molding
compound. The molding compound plays an indirect role
in the heat transfer across the delaminated interface
because it provides the compressive stress across that
interface. One should not assume that the magnitude of the
delamination gap and the subsequent impact on thermal
performance will be the same for other materials.
On another cautionary note, it should be emphasized
that the industry practice of monitoring the center die
temperature leads to a severe underestimate of the peak die
temperature due to delamination. It is strongly suggested
that test dies with temperature sensors in the corners as
well as in the center be used when evaluating the effect of
delamination on thermal performance.
Conclusions
The effect of die attach region delamination on package
thermal performance was measured experimentally and
analyzed using thermal simulation techniques for two
different package types. For the material set examined, it is
shown that the delaminated interface can be represented by
a constant air gap of 2µm thickness for a wide range of %
delamination. It was shown that, for relatively low power
applications involving silicon chips having uniform heat
generation over most of the die surface, even 100%
delamination will not cause a serious overheating of the
die. However, as the power dissipated by the chip
increases to the levels made possible by heatslug designs,
the requirements for delamination must get more stringent,
with the precise percentage dependent on the total power
and the chip design. In the situation in which an external
heat sink is used, the requirements for delamination must
get even more restrictive
Acknowledgement
The authors would like to express sincere thanks to Y.
H. Ka for his help with thermal measurements, Nick
Fletcher for his help with thermal simulation, B. H. Moon
for his help with % delamination measurement techniques,
to You Yun Jung, Moon Ho Jung & Park Yong Jun of the
R&D lab at Anam, Korea, for their significant
contributions to this work, and to Dan Rodkey, Delco, for
supplying the thermal test dies.
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