United States Patent
(151
Patel
[45] Nov.21, 1972
3,703,705
[54] MULTI-CHANNEL SHIFT REGISTER
[72] Inventor: Arvind M. Patel, Wappingers Falls,
Primary Examiner—Charles E. Atkinson
Attorney—Hani?n & Jancin and Harold H. Sweeney,
Jr.
[73] Assignee: International Business Machines
Corporation, Armonk, N.Y.
[22] Filed:
Dec. 31, 1970
[21] Appl. No.: 103,205
[57]
ABSTRACT
A linear feedback shift register for operating on a plu
rality f of parallel inputs according to a generator
polynomial to produce encoding and decoding is pro
vided having a plurality r of shift register stages X0 . . .
[52]
[51]
US. Cl ................ ..340/l46.l AL, 340/1461 BE
Int. Cl ............................................. ..G06f 11/12
[58] Field of Search.340/l46.l, 146.1 AL, 146.l BE;
235/153
[56]
X,_, each corresponding to one of the terms in the
generator polynomial. A ?rst plurality of modulo 2 ad
dition means connect, for modulo 2 addition, each of
said f data
Inputs Z¢+f_1, ZH.]_2, . . . , 2H,‘, Z‘ of the
shift register to the output of an individual one of the
References Cited
last f register stages X,_,, XHH, . . . , XM according to
111C relationship Z¢+{_1 to X,-._{, Z1444 t0 Xr_f+1, . . . , Z!
UNITED STATES PATENTS
to X,_,. A second plurality of modulo 2 addition
3,452,328
6/1969
Hsiao et a1 ...... ..340/146.1 AL
3,465,287
9/1969
Kennedy et al...340/146.1 AL
3,601,800
8/1971
Lee ................ ..340/146.1 AL
OTHER PUBLICATIONS
means are connected to the respective inputs of the
?rst XHH shift register stages. The ?rst feedback con
nection from the output of each of said ?rst plurality
of modulo 2 addition means in said f shift register
stages is connected to each of two preceding second
modulo 2 addition means in accordance with the rela
Linear-Feedback"S'hiftlRegister Circuits, IEEE Trans:
actions of Electronic Computers, Dec. 1964 (EC-l3),
pp. 738-740.
HSiaOi Single-Channel Error, Correction...,in....en_.£-.
Channel System, IEEE Transactions on Computers,
Vol. C-l7, NO. 10, October 1968, pp. 935-943.
tionship XHH to X1 and X2; XFM to X2 and X3; X,.,
to XL,“ and XHH. A third modulo 2 addition means
connects each output of the ?rst plurality of modulo 2
addition means to the register stages detennined in ac
cordance with the non-zero coefficients in the genera
tor polynomial.
7 Claims, 2 Drawing Figures
3,703,705
1
2
MULTI-CHANNEL SHIFT REGISTER
BACKGROUND OF THE INVENTION
a XF-l )
This invention relates to a linear feedback shift re
gister and, more particularly, to an improved feedback 5
denotes the partitioning of the state vector X5
shift register for processing bytes of data wherein the
Zr: (lax-1, 2144-2, - - - ‘2m, Zr)
bits are processed in parallel.
It is known that binary data in the form of a message
denotes the input data sequence;
can be checked after utilization or transmission for er
rors. It is also known that a shift register can be utilized
is a matrix of (Pf) rows and r columns where the ?rst f
to perform the encoding of the transmitted data and the
decoding of the received data. The shift register is
columns are 0's and the next (r-j) columns are an
(r-f) identity matrix; and
mechanized in accordance with a particular selected
generator polynomial. The generator polynomial deter
mines the feedback connections to be made in the shift
register so as to provide a division of the incoming bi
.G
._.._
.T
nary message polynomial by the generator polynomial.
D:
The result of the division is a remainder which is
defined as the checking character. For each different
binary message, there is a unique combination of a quo 20
GTHl
tient plus a remainder. This remainder, by itself, carries
enough error detection information that it alone is
where G is the vector:
transmitted as the check bits. As can be seen by analo~
gy to decimal division, the remainder varies cyclically
25
[G0, G1! G2’ ' ' ' a Gr-l]
over the range of message polynomials. For this reason,
these codes are called “cyclic codes.” Because of this
which is obtained from the generator polynomial G(x)
cyclic property, messages with the same check bit pat
= G°$G1x® Ggxz, . . . , Gpc”
and T is given by:
tern are kept numerically remote from each other.
There are well known rules for selecting the generator 30
polynomial to give particular detecting and correcting
properties.
.
In the decoding of the transmitted message, an
identical shift register is used. The message is divided
by the same generator polynomial to obtain the 35
remainder. If the message has been transmitted cor
rectly, the remainder should be the same as the
remainder generated in the encoding shift register. US.
Pat. No. 3,465,287, issued to Joseph C. Kennedy and
John H. Sorg, Jr. on Sept. 2, 1969 discloses a multi 40
channel feedback shift register mechanized so as to en
parallel shift register generated in accordance with the
above connections is capable of processing f bits in
code and decode cyclic codes wherein the data bits are
processed in parallel.
parallel.
It is an object of the present invention to provide an
improved multi-channel feedback shift register for
processing parallel data.
and matrix TI is the 1”‘ power of the matrix T.
The invention has the further advantage that the
The invention has the further advantage that it is
45 operable upon any detection code available to serial
feedback shift register circuits.
The foregoing and other objects, features and ad
It is another object of the present invention to pro
vide a multi~channel shift register for processing paral
lel input data wherein the input binary message is ap
vantages of the invention will be apparent from the fol
lowing more particular description of a preferred em
plied at the higher order stages of the feedback shift re
bodiment of the invention as illustrated in the accom
gister.
panying drawings.
It is a further object of the present invention to pro
vide a multi-channel feedback shift register wherein the
’
FIG. 1 is a schematic diagram of a prior art serial
feedback shift register adapted for encoding or decod
hardware is simpli?ed by partitioning of the state vec
mg.
tor of the shift register.
55
FIG. 2 is a schematic diagram of a multi-channel
Brie?y, the above objects of this invention are ac
feedback shift register for encoding and decoding
complished by providing a parallel input feedback shift
register for encoding and decoding a binary message
parallel input information.
wherein a plurality of shift register stages r are con
nected in accordance with the expression:
60
The serial shift register circuit shown in FIG. 1 is
designed on the bases of the checking or generator
polynomial l + x2 -l-x‘5 +x“. The generator polynomial
determines the feedback connections 10 that are made
from the output 12 of the serial shift register to the in
puts of various shift register stages. For example, the
65 output 12 of the shift register is connected to the initial
shift register stage x0. It is also connected to an EX
denotes the contents of the shift register at time t + f
where f is equal to the number of parallel channels:
CLUSIVE OR circuit 14 prior to the x2 stage. Likewise,
the feedback is connected to an EXCLUSIVE OR cir
3,703,705
3
4
cuit 16 just prior to the x15 shift register stage. These
ing shift register represents the syndrome. A non-zero
EXCLUSIVE OR circuits have as the other input
syndrome indicates an error in the receive data.
thereto the input from the immediately preceding shift
Assuming a binary message 16 bits in length as fol
lows:
register stage. It should be noted that the input 18 to
the shift register is at the high order end of the shift re
gister rather than the low order end as was the case in
1101011110010011
is processed in the shifting register of FIG. 1, the fol
the previously mentioned US. Pat. No. 3,465,287. The
input 18 is connected to an EXCLUSIVE OR circuit 20
with the output of the last shift register stage of the shift
lowing table de?nes the various transition states of the
register:
TABLE I.—STATE TRANSITION TABLE FOR SERIAL SI-IIF'I‘ REGISTER
Contents of Shift Register
1
I
0
1
0
1
I
1
1
O
0
I
0
O
l
I
16
X0
X1
x1
XII
x‘
xi!
x6
X7
x8
X11
X10
XII
XII
XIZ
Xll
0
1
0
0
I
1
0
I
0
I
I
1
0
0
0
0
I
0
0
I
0
0
I
1
0
1
0
I
I
I
0
0
0
0
(l
I
0
1
1
l
1
0
0
0
I
0
I
1
0
0
l
0
0
1
0
l
I
1
I
0
O
0
l
0
1
l
0
0
0
0
0
I
0
1
1
1
1
0
0
0
I
0
1
1
0
O
0
0
0
1
O
l
I
1
1
0
0
0
I
0
I
1
0
0
0
0
0
l
0
1
l
I
1
0
0
0
I
0
I
0
0
0
0
0
0
1
0
I
1
I
1
0
0
0
1
0
0
0
0
0
0
0
0
I
0
1
1
1
1
0
0
O
l
0
0
0
0
0
0
0
0
1
0
I
1
1
1
O
0
0
0
0
0
0
0
0
0
0
0
I
0
1
1
I
I
0
0
0
0
0
0
0
0
0
0
0
0
1
0
I
1
I
l.
0
0
0
O
0
0
0
0
0
0
0
0
1
0
I
I
l
l
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
I
I
0
0
0
0
0
0
0
0
0
0
0
O
0
I
0
l
1
I
0
1
0
0
1
I
0
1
0
0
0
I
1
I
Check character ________________ . .
register which, in this example, is x“ connected as the
x15
OQHDF
In FIG. 2, there is shown a multi-channel feedback
other input thereto. Even though the input 18 to the
shift register that processes 8 bits in parallel which
shift register is at the high order end, the contents of 30 forms a byte of information. A single shift in this circuit
the shift register is still shifted towards the high order
with any 8 bit input sequence is equivalent to 8 con
end from the low order end. Thus, when the last bit of
secutive shifts in the serial circuit of FIG. 1 with the
the message sequence is entered, the contents of the
same input sequence. The circuit is shown having an
shift register represents the check character or
input binary sequence of 8 parallel bits Z0, 21, . . . .21.
35
remainder. Actually, the connection of the shift re
These inputs are each fed to a respective EXCLUSIVE
gister provides a division of the inputted binary
OR circuit 22 associated with one of the higher order
message by the generator polynomial G(x) ,which, as
stages in the shift register. The zo input is fed to the EX
previously mentioned, is l + X2 + 1:15 +x“ in the FIG. 1
CLUSIVE OR circuit 22 which has as the other input
example. The remainder of this division is the checking
40 thereto the output of the shift register stage x“. The in
character which remains in the register. The serial shift
puts designated by successively increasing integers are
register of FIG. I has 16 stages, designated by the letter
X with a superscript number indicating the place of the
corresponding term in the generator polynomial. It
fed to the shift register stages designated by successive
ly decreasing integers. The output 24 of the shift re
should be noted that the non-zero terms in the genera 45 gister is also taken from the higher order stages of the
register which, in the case being considered, are it8
tor polynomial are represented in the linear feedback
through x“. The circuit is designed to utilize the same
shift register by register stages having a connection
generator polynomial l + x2 + x15 + x“ as was used to
from a feedback line while the 0 co-ef?cient terms in
provide the division in the serial register of FIG. 1. It is
apparent that the various connections and arrangement
do not have a direct feedback connection.
'50 of
the parallel shift register stages cannot be easily
The same shift register can be used for decoding. The
deduced form the serial shift register arrangement.
received message bits are entered into the shift register
Table II which follows is the State Transition Table
at the input 18 at the high order end similar to the shift .
of the Multi~Channel Feedback Shift Register of FIG. 2
when used for encoding. The check character
when processing the same binary message, namely:
generated in the encoding shift register is also shifted 55
1l0lOll1lOOlOOll
into the decoder shift register. When the last bit of the
check character is entered, the contents of the decod
as was processed through the shift register of FIG. 1 ,
the polynomial are represented by register stages that
TABLE II.——STATE TRANSITION TABLE OF THE MULTI-CHANNEL FEEDBACK SHIFT REGISTER
Input
Number of the shift
1,"
1.1
‘1.1
7.1
24
Contents of shift register
z5
z6
7,1
x"
(1
..
1!...
.
..
.
..
..
Chuck character" ..
i'
l
(I
l
l
U
l
l
U
l
(I
(l
l
l
1
(I
l
(I
(l
5
3,703,705
6
shown in Table I. The binary message in the parallel
shift register is handled in the form of 2 bytes:
selected. The generator polynomial or checking
polynomial is denoted by:
(ll0lOlll)and(lOOlOOll)
G(x)=G°+G,x+G,x’+...-l-G,x'
(I)
The ?rst byte consists of the ?rst half (8) of the bits of 5 The stage vector X, = (x0, x, , . . . , .rM)l denotes the
contents of the shift register circuit at time t. The com
the 16-bit message. Each successive bit of the byte cor
panion matrix of the polynomial G(x) is denoted by T.
responding to the z.) . . . z, inputs to the register. The
The particular companion matrix T shown here is the
companion matrix for the connections given in the seri
al shift register previously described. Let Z, denote the
data bit entering the serial shift register at time t. Then,
result is that the parallel circuit of FIG. 2 produces the
same check character as that produced by the circuit of
FIG. 1 but 8 times faster. It will be appreciated from
this Table that the same check character is arrived at in
the shifting operation of the serial shift register is given
by the modulo 2 matrix equation:
2 shifts, each shift being caused by the input of an 8-bit
byte in parallel as described above. As can be seen in
FIG. 2, the shift register stages x° ° . . . x“5 are arranged
in two groups 1:“ . . .x" and x8 . . . x“. The outputs of the
where G is the vector (G0, G1, G2, . . . ,GH) and T is
?rst group x° . . . x" are fed to the shift register stages
given by:
that are successively 8 channels away. For example, the
output 36 of the x° register stage is fed to an EXCLU
SIVE OR circuit 34 preceding the x 8 stages. Likewise,
the output 36 of the x1 stage is fed to the EXCLUSIVE
1
0
1
O
O
0
O
O
. . . 1
T:
OR circuit 34 preceding the x’ stage. This sequence of
connections continues with the output of the x7 stage
being connected as an input to the x“ stage of the shift
register. The outputs of the second group of shift re 25
gister stages at8 . . . x15 are fed directly to EXCLUSIVE
Assuming that 2,2,“,
G0 G1 G2. . . . ,ZHH
. Gr_1 are the f data bits
(a byte) entering successively into the serial shift re
OR circuits 22 as one of the inputs along with the
gister during the f consecutive shifting operations. The
message bit inputs z7 . . . 20, respectively. The output 30
contents of the shift register at the end of f shifts is
from each of these EXCLUSIVE OR circuits 22 is also
connected via a feedback connection 32 to the suc
O
0
30
eeeding two shift register channels. For example, the
output 30 of the x8 shift register stage is fed from the
denoted by the vector XM. Using equation (2) itera
tively, f times, the equation is obtained as follows:
X¢+f=XlTf@Z¢GTf_l@Z!+| GTI_Z® . . . Z(_J'_1G
EXCLUSIVE OR circuit 22 back to an EXCLUSIVE
(4)
In this equation TJ is the j‘“ power of the matrix T.
Letting Z, denote the input data sequence as follows:
OR circuit 34 preceding each of the x‘ and at’ stages.
Likewise, the output 30 of the EXCLUSIVE OR circuit 35
Zr: (ZH-f-h ZtH-z, - - - 921-1’ Z1)
22 following the shift register stage I9 is fed back to the
EXCLUSIVE OR circuits 34 preceding the x2 and Jr3
Let D denote the following partitioned matrix:
adjacent shift register stages. This sequence of connec
tions continues with the EXCLUSIVE OR circuit 22
following the 1:“ shift register stage being connected to
the EXCLUSIVE OR circuits 34 preceding the x8 and
x” stages. The output of the modulo 2 adder or EX
CLUSIVE OR circuits 22 are fed into a common EX
CLUSIVE OR circuit 26 which has the one output 28.
The output connection 28 of the common EXCLU
SIVE OR circuit 26 is connected as an input to the x°
(5)
shift register stage in the ?rst group of shift register
stages and is also connected to the EXCLUSIVE OR
circuit 34 preceding the x‘ stage. This same output 28
from the common EXCLUSIVE OR circuit 26 is fed as
Then, equation (4) can be rewritten as:
Xl+!'= X¢Tf@ 21D
50
an input to the EXCLUSIVE OR circuit 34 which
precedes the 1:15 stage. These conditions are deter
mined by the connection matrix D, where D will be
derived hereafter from the generator polynomial.
55
In order to better understand the operation as well as
the various connections that must be made in con
(6)
The parallel circuit realized from equation (6) has the
property that with an input byte Z, (f bits in parallel), it
changes from state X, to X“, in a single shift. This is the
equivalent operation to f shifts of the corresponding
serial shift register with the same input data entered
serially.
The matrix T can be partitioned as follows:
structing a particular feedback shift register for encod
ing and decoding, the general design thereof will be ex
pressed mathematically. Thus, the multi-channel feed
60
(7)
back shift register has f channels and is capable of
processing f bits in parallel to generate in the encoding
mode the check character and to generate, in the
decoding mode, the syndrome. It will be appreciated,
where I,- is the r x r identity matrix. In general, it can be
shown that T’ is equal to the following partitioned
that one shift in the parallel circuit is equivalent to f 65 matrix:
shifts in the corresponding serial shift register discussed
above. The number f is a positive integer, smaller than
the degree r of the generator polynomial which is
(8)
3,703,705
v.1
8
where D is given by equation (5) above. The D matrix
can be obtained by the following method using the ex
ample given in the serial shift register discussion above
of the shift register to the output of an individual one of
the last f register stages:
where the generator polynomial l + x’ + x“ + x“ is
5
used. Noting that the vectors G, GT, GT2 , . . . ,GTH
according to the relationship:
represents the contents of the serial shift register as the
vector G is shifted f—l times. Table III lists these vec
ZH-I-1 to Xrq, zip-z to arms. - - . .2‘ to XH;
tors for the generator polynomial example. The
matrices D and T’ can be obtained using Table III and
a second plurality of modulo 2 addition means con
equations (5) and (8). It should be noted that the im 10
nected to respective inputs of the ?rst x,_,+z shift
plementation of the equation (6) produces a parallel
register stages;
circuit. The matrix T’ contains D as a sub-matrix. it has
been found that proper partitioning of the state vector
a ?rst feedback connection from the output of each
of said ?rst plurality of modulo 2 addition means in
results in considerable savings in hardware in the paral 15
said f shift register stages to each of two preceding
lel version of the feedback shift register. The state vec
tor can be partitioned into two parts:
second modulo 2 addition means in accordance
with the relationship:
TABLE III.—ROWS OF THE MATRIX D
Contents of the Serial CRC Register
Number of the shift
X1
x:
x;
X4
X5
xi
x1
Xs
xv
r-nwaue l-irtho OQH cov-wl OGMI-C QOob-IH OQMH QHOD HOQ b-‘OQ
i
I X?)
l
l
l
|
(9)
where:
- ,xr-r to xr-I-H and
30
X11 = (x0, X1, - - ' Jr-I-i)!
(10)
X3= (xv-1. xr-H-b - - - .xmh
(11)
a third modulo 2 addition means connecting each
output of said first plurality of modulo 2 addition
Using equations (8) and (9), the equation (6) can be
rewritten as follows:
XI-i-FXtI (0|Ir—f)$(X¢2G3Z¢) (D)
35
(12)
means to the register stages determined in ac
cordance with the non-zero coefficients in the
generator polynomial.
2. A linear feedback shift register according to claim
1 wherein said second plurality of modulo 2 addition
means connected to the respective inputs of the ?rst
x,_ 1+2 shift register stages performs modulo 2 addition
on the pair of said ?rst feedback connections from ad
jacent pairs of said ?rst modulo 2 addition means.
3. A linear feedback shift register according to claim
The implementation of equation (12) produces the
parallel circuit of FIG. 2. Thus, it should be appreciated
that with any polynomial G(x) degree r, parallel feed
back shift register can be generated which processes f
bits in parallel (f 5 r). It should also be appreciated
that the hardware can be minimized by the proper par
titioning of the matrices in the state transition equation
1, wherein said third modulo 2 addition means con
for the parallel circuit. In the situation where f > r, the 45 nects each output of said ?rst plurality of modulo 2 ad
theory can be applied without any change, except that
dition means to a fourth modulo 2 addition means in
the partitioning will be applied to the D matrix rather
the input of the register stages determined in ac
than to the T’ matrix. This is observable since D, in this
cordance with the non-zero coef?cients in the genera
case, contains T’ as one of its partitions.
tor polynomial.
While the invention has been particularly shown and
4. A linear feedback shift register according to claim
described with reference to a preferred embodiment
3, wherein said second plurality of modulo 2 addition
thereof, it will be understood by those skilled in the art
means connected to the input of the ?rst X,_;+z shift re
that various changes in form and detail may be made
gister stages has a feedback input from the third modu
without departing from the spirit and scope of the in
lo 2 addition means determined in accordance with the
vention.
What is claimed is:
55 non-zero coefficients in the generator polynomial
l. A linear feedback shift register for operating on a '
plurality f of parallel inputs according to a generator
polynomial to produce a check character comprising:
a plurality r of shift register stages X0. . . XM each
thereby serving as the modulo 2 adder for the second
and fourth modulo 2 addition means.
5. A linear feedback shift register according to claim
1, wherein the shift register output is taken from the
output of the last f register stages:
corresponding to one of the terms in the generator
polynomial;
a ?rst plurality of modulo 2 addition means connect
ing, for modulo 2 addition, each of said f data bit 65
inputs:
6. A linear feedback shift register according to claim
1 , wherein the remainder in said shift register following
a shift register operation on a message input is fed into
an identical shift register used for decoding following
9
3,703,705
7.19,. .
said message utilization to thereby produce an error
responding to the ?rst partition X,‘ of the register;
syndrom which should equal 0 if there is no error in the
Z, denotes the input data sequence;
utilized message.
Z1: (ZH'Fh 11+”, - - - ‘2H4’ 2:)
7. A linear feedback shift register according to claim
and D denotes the partioned matrix:
1, wherein said plurality r of shift register stages X0. . . 5
)(,_l are connected in accordance with the expression:
where:
10
denotes the contents of the shift register at time t+f 15
where G is the vector:
where f is equal to the number of parallel channels and
f E r;
(G0, G1’ G21 ' ' - iGr-l)
which is obtained from the generator polynomial:
G(x) = GOGBGI x696“: , . . . ,Gr x’
and T and T’ are matrices defined as follows:
represents the partioning f the shift register;
(0 | I”)
25
is a matrix of (rJ) rows and r columns where the ?rst f
columns are 0's and the next (r.f) columns are a (r_,f)
identity matrix which de?nes the connections cor
_ li__________
T" [606192 . . . 0H]
and TI is the 1'" power of the matrix T.
it
35
40
45
50
55
65
*
=0:
1:
*