724
APPENDIX A
•
LOGIC CIRCUITS (Corrisponde al cap. 2 - Elementi di logica)
PROBLEMS
A.1
Implement the COINCIDENCE function in sum-of-products form, where
COINCIDENCE = XOR.
A.2
Prove the following identities by using algebraic manipulation and also by using truth
tables.
(a) a ⊕ b ⊕ c = abc + abc + abc + abc
(b) x + wx = x + w
(c) x1 x 2 + x 2 x3 + x3 x 1 = x1 x 2 + x3 x 1
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
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PROBLEMS
A.3
725
Derive minimal sum-of-products forms for the four 3-variable functions f 1 , f 2 , f 3 , and
f 4 given in Figure PA.1. Is there more than one minimal form for any of these functions?
If so, derive all of them.
x1
x2
x3
f1
f2
f3
f4
0
0
0
1
1
d
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
d
1
0
0
1
0
d
d
1
0
1
0
0
0
d
1
1
0
1
0
1
1
1
1
1
1
1
1
0
Figure PA.1 Logic functions for
Problem A.3.
A.4
Find the simplest sum-of-products form for the function f using the don’t-care condition
d, where
f = x1 (x2 x 3 + x2 x3 + x 2 x 3 x4 ) + x2 x 4 (x 3 + x1 )
and
d = x1 x 2 (x3 x4 + x 3 x 4 ) + x 1 x 3 x4
A.5
Consider the function
f (x1 , . . . , x4 ) = (x1 ⊕ x3 ) + (x1 x3 + x 1 x 3 )x4 + x1 x 2
(a) Use a Karnaugh map to find a minimum cost sum-of-products (SOP) expression
for f .
(b) Find a minimum cost SOP expression for f , which is the complement of f . Then,
complement (using de Morgan’s rule) this SOP expression to find an expression for
f . The resulting expression will be in the product-of-sums (POS) form. Compare
its cost with the SOP expression derived in Part a. Can you draw any general
conclusions from this result?
A.6
Find a minimum cost implementation of the function f (x1 , x2 , x3 , x4 ), where f = 1 if
either one or two of the input variables have the logic value 1. Otherwise, f = 0.
A.7
Figure A.6 defines the 4-bit encoding of BCD digits. Design a circuit that has four
inputs labeled b3 , . . . , b0 , and an output f , such that f = 1 if the 4-bit input pattern
is a valid BCD digit; otherwise f = 0. Give a minimum cost implementation of this
circuit.
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APPENDIX A
A.8
•
LOGIC CIRCUITS
Two 2-bit numbers A = a1 a0 and B = b1 b0 are to be compared by a four-variable
function f (a1 , a0 , b1 , b0 ). The function f is to have the value 1 whenever
v(A) ≤ v(B)
where v(X ) = x1 × 21 + x0 × 20 for any 2-bit number. Assume that the variables A
and B are such that |v(A) − v(B)| ≤ 2. Synthesize f using as few gates as possible.
A.9
Repeat Problem A.8 for the requirement that f = 1 whenever
v(A) > v(B)
subject to the input constraint
v(A) + v(B) ≤ 4
A.10
Prove that the associative rule does not apply to the NAND operator.
A.11
Implement the following function with no more than six NAND gates, each having
three inputs.
f = x1 x2 + x1 x2 x3 + x 1 x 2 x 3 x4 + x 1 x 2 x3 x 4
Assume that both true and complemented inputs are available.
A.12
Show how to implement the following function using six or fewer two-input NAND
gates. Complemented input variables are not available.
f = x1 x2 + x 3 + x 1 x4
A.13
Implement the following function as economically as possible using only NAND gates.
Assume that complemented input variables are not available.
f = (x1 + x3 )(x 2 + x 4 )
A.14
A number code in which consecutive numbers are represented by binary patterns that
differ only in one bit position is called a Gray code. A truth table for a 3-bit Gray code
to binary code converter is shown in Figure PA.2a.
(a) Implement the three functions f 1 , f 2 , and f 3 using only NAND gates.
(b) A lower-cost network for performing this code conversion can be derived by noting
the following relationships between the input and output variables.
f1 = a
f2 = f1 ⊕ b
f3 = f2 ⊕ c
Using these relationships, specify the contents of a combinational network N that can
be repeated, as shown in Figure PA.2b, to implement the conversion. Compare the
total number of NAND gates required to implement the conversion in this form to the
number required in Part a.
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PROBLEMS
3-bit Gray code
inputs
a
b
c
f1
f2
f3
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
1
1
0
1
0
0
1
1
1
a
?
Binary code
outputs
N?
f1
b
?
N?
(a) Three-bit Gray code to
binary code conversion
c
?
N?
f2
(b) Code conversion network
f3
Figure PA.2 Gray code conversion example for Problem A.14.
A.15
Implement the XOR function using only 4 two-input NAND gates.
A.16
Figure A.37 defines a BCD to seven-segment display decoder. Give an implementation
for this truth table using AND, OR, and NOT gates. Verify that the same functions are
correctly implemented by the NAND gate circuits shown in the figure.
A.17
In the logic network shown in Figure PA.3, gate 3 fails and produces the logic value 1
at its output F1 regardless of the inputs. Redraw the network, making simplifications
x1
x3
2
1
6
F2
4
8
5
x2
3
F1
x4
7
Figure PA.3 A faulty network.
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f
728
APPENDIX A
•
LOGIC CIRCUITS
wherever possible, to obtain a new network that is equivalent to the given faulty network
and that contains as few gates as possible. Repeat this problem, assuming that the fault
is at position F2, which is stuck at a logic value 0.
A.18
Figure A.16 shows the structure of a general CMOS circuit. Derive a CMOS circuit
that implements the function
f (x1 , . . . , x4 ) = x 1 x 2 + x 3 x 4
Use as few transistors as possible. (Hint: Consider series/parallel networks of transistors.
Note the complementary series and parallel structure of the pull-up and pull-down
networks in Figures A.17 and A.18.)
A.19
Draw the waveform for the output Q in the JK circuit of Figure A.31, using the input
waveforms shown in Figure PA.4 and assuming that the flip-flop is initially in the 0 state.
1
Clock
0
1
J
0
1
K
0
Figure PA.4 Input waveforms for a JK flip-flop.
A.20
Derive the truth table for the NAND gate circuit in Figure PA.5. Compare it to the truth
table in Figure A.24b and then verify that the circuit in Figure A.26 is equivalent to the
circuit in Figure A.25a.
A
B
Q
Q
Figure PA.5 NAND latch.
A.21
Compute both the setup time and the hold time in terms of NOR gate delays for the
negative edge-triggered D flip-flop shown in Figure A.29.
A.22
In the circuit of Figure A.27a, replace all NAND gates with NOR gates. Derive a
truth table for the resulting circuit. How does this circuit compare with the circuit in
Figure A.27a?
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PROBLEMS
729
A.23
Figure A.33 shows a shift register network that shifts the data to the right one place at
a time under the control of a clock signal. Modify this shift register to make it capable
of shifting data either one or two places at a time under the control of the clock and an
additional control input ONE/TWO.
A.24
A 4-bit shift register that has two control inputs — INITIALIZE and RIGHT/LEFT —
is required. When INITIALIZE is set to 1, the binary number 1000 should be loaded
into the register independently of the clock input. When INITIALIZE = 0, pulses at
the clock input should rotate this pattern. The pattern rotates right or left when the
RIGHT/LEFT input is equal to 1 or 0, respectively. Give a suitable design for this
register using D flip-flops that have preset and clear inputs as shown in Figure A.32.
A.25
Derive a three-input to eight-output decoder network, with the restriction that the gates
to be used cannot have more than two inputs.
A.26
Figure A.35 shows a 3-bit up counter. A counter that counts in the opposite direction
(that is, 7, 6, . . . , 1, 0, 7, . . . ) is called a down counter. A counter capable of counting in
both directions under the control of an UP/DOWN signal is called an up/down counter.
Show a logic diagram for a 3-bit up/down counter that can also be preset to any state
through parallel loading of its flip-flops from an external source. A LOAD/COUNT
control is used to determine whether the counter is being loaded or is operating as a
counter.
A.27
Figure A.35 shows an asynchronous 3-bit up-counter. Design a 4-bit synchronous upcounter, which counts in the sequence 0, 1, 2, . . . , 15, 0 . . . . Use T flip-flops in your
circuit. In the synchronous counter all flip-flops have to be able to change their states
at the same time. Hence, the primary clock input has to be connected directly to the
clock inputs of all flip-flops.
A.28
A switching function to be implemented is described by the expression
f (x1 , x2 , x3 , x4 ) = x1 x3 x 4 + x 1 x 3 x4 + x 2 x 3 x 4
(a) Show an implementation of f in terms of an eight-input multiplexer circuit.
(b) Can f be realized with a four-input multiplexer circuit? If so, show how.
A.29
Repeat Problem A.28 for
f (x1 , x2 , x3 , x4 ) = x1 x 2 x3 + x2 x3 x4 + x 1 x 4
A.30
(a) What is the total number of distinct functions, f (x1 , x2 , x3 ), of three binary
variables?
(b) How many of these functions are implementable with one PAL circuit of the type
shown in Figure A.43?
(c) What is the smallest change in the circuit in Figure A.43 that should be made to
allow any three-variable function to be implemented with a single PAL circuit?
A.31
Consider the PAL circuit in Figure A.43. Suppose that the circuit is modified by adding
a fourth input variable, x4 , whose uncomplemented and complemented forms can be
connected to all four AND gates in the same way as the variables x1 , x2 , and x3 .
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APPENDIX A
•
LOGIC CIRCUITS
(a) Can this modified PAL be used to implement the function
f = x1 x 2 x 3 + x 1 x2 x 3 + x 1 x 2 x3
If so, show how.
(b) How many functions of three variables cannot be implemented with this PAL?
A.32
Complete the design of the up/down counter in Figure A.47 by using the state assignment
S0 = 10, S1 = 11, S2 = 01, and S3 = 00. How does this design compare with the one
given in Section A.13.1?
A.33
Design a 2-bit synchronous counter of the general form shown in Figure A.50 that
counts in the sequence . . . , 0, 3, 1, 2, 0, . . . , using D flip-flops. This circuit has no
external inputs, and the outputs are the flip-flop values themselves.
A.34
Repeat Problem A.33 for a 3-bit counter that counts in the sequence . . . , 0, 1, 2, 3, 4,
5, 0, . . . , taking advantage of the unused count values 6 and 7 as don’t-care conditions
in designing the combinational logic.
A.35
In Section A.13, D flip-flops were used in the design of synchronous sequential circuits.
This is the simplest choice in the sense that the logic function values for a D input are
directly determined by the desired next-state values in the state table. Suppose that JK
flip-flops are to be used instead of D flip-flops. Describe, by the construction of a table,
how to determine the binary value for each of the J and K inputs for a flip-flop as a
function of each possible required transition from present state to next state for that
flip-flop. (Hint: The table should have four rows, one for each of the transitions 0 → 0,
0 → 1, 1 → 0, and 1 → 1; and each J and K entry is to be 0, 1, or “don’t care,” as
required.) Apply the information in your table to the design of individual combinational
logic functions for each J and K input for each of the two flip-flops of the 2-bit binary
counter of Problem A.33. How does the simplicity of the logic required compare to
that needed for the design of the counter using D flip-flops?
A.36
Repeat Problem A.34 using JK flip-flops instead of D flip-flops. The general procedure
for doing this is provided by the answer to Problem A.35.
A.37
In the vending machine example used in Section A.13.4 to illustrate the finite state
machine model, a single binary output, z, was used to indicate the dispensing of merchandise. Change was not provided as an output. The purpose of this problem is to
expand the output to include providing proper change. Assume that the only input
sequences of dimes and quarters are: 10-10-10, 10-25, 25-10, and 25-25. Coincident
with the last coin input, the outputs to be provided for these sequences are 0, 5, 5, and
20, respectively. Use two new binary outputs, z 2 and z 3 , to represent the three distinct
outputs. (This does not correspond directly to coins in use, but it keeps the problem
simple.)
(a) Specify the new state table that incorporates the new outputs.
(b) Develop the logic expressions for the new outputs z 2 and z 3 .
(c) Are there any equivalent states in the new state table?
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REFERENCES
A.38
731
Finite state machines can be used to detect the occurrence of certain subsequences in
the sequence of binary inputs applied to the machine. Such machines are called finite
state recognizers. Suppose that a machine is to produce a 1 as its output coincident with
the second 1 in the pattern 011 whenever that subsequence occurs in the input sequence
applied to the machine.
(a) Draw the state diagram for this machine.
(b) Make a state assignment for the required number of flip-flops and construct the
assigned state table, assuming that D flip-flops are to be used.
(c) Derive the logic expressions for the output and the next-state variables.
A.39
Repeat Part a only of Problem A.38 for a machine that is to recognize the occurrence
of either of the subsequences 011 and 010 in the input sequence, including the cases
where overlap occurs. For example, the input sequence 110101011. . . is to produce the
output sequence 000010101. . . .
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SOLUTIONS - Appendix A – Logic Circuits
A.1. The truth table for the COINCIDENCE function is
x1
x2
COINCIDENCE
0
0
1
1
0
1
0
1
1
0
0
1
COINCIDENCE = x1 x2 + x1 x2 = (x1 ⊕ x2 )
A.2. Proof for identity (a):
(a ⊕ b) ⊕ c = (a ⊕ b)c + (a ⊕ b)c
= abc + abc + abc + abc
Proof for identity (b):
x + wx
= (x + w)(x + x)
= x+w
Proof for identity (c):
x1 x2 + x 2 x3 + x 3 x1
= x1 x2 + x2 x3 (x1 + x1 ) + x3 x1
= x 1 x2 + x 1 x 2 x3 + x 3 x1 x2 + x 3 x 1
= x 1 x2 + x 3 x 1
A.3. Using Karnaugh maps get:
x1 x2
x3
00
01
11
10
0
1
0
1
1
1
1
1
1
0
A minimum cost expression for f1 is
f 1 = x 1 x 2 + x 1 x2 + x 1 x3
1
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Another expression that has the same cost is
f 1 = x 1 x 2 + x 1 x2 + x 2 x3
x1 x2
x3
00
01
11
10
0
1
1
0
0
1
1
1
1
0
The minimum cost expression for f2 is
f 2 = x 1 + x 2 x3
x1 x2
x3
00
01
11
10
0
d
0
1
d
1
1
1
1
0
The minimum cost expression for f3 is
f 3 = x 1 x2 + x 1 x3
x1 x2
x3
00
01
11
10
0
0
1
1
d
1
1
d
0
d
A minimum cost expression for f4 is
f 4 = x 2 x3 + x 2 x 3
Another expression that has the same cost is
f 4 = x 2 x3 + x 1 x3
2
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A.4. The corresponding Karnaugh map is
x1 x2
x3 x4
00
01
11
10
00
0
1
1
d
01
0
d
1
1
11
0
0
1
d
10
0
0
1
0
A minimum-cost SOP expression is
f = x 2 x3 + x 1 x2 + x 1 x3
Another expression that has the same cost is
f = x 2 x3 + x 1 x2 + x 1 x4
A.5. The Karnaugh map is
x1 x2
x3 x4
00
01
11
10
00
0
0
1
1
01
1
1
1
1
11
1
1
1
1
10
1
1
0
1
(a) The minimum-cost SOP expression is
f = x 4 + x 1 x3 + x 1 x3 + x 1 x2
(b) The minimum-cost SOP expression for the complement of f is
f = x 1 x 3 x4 + x 1 x2 x3 x 4
Complementing this expression using de Morgan’s rule gives
f = (x1 + x3 + x4 )(x1 + x2 + x3 + x4 )
3
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This expression requires 2 OR gates, one AND gate and 9 inputs to gates, for a
total cost of 12. The SOP expression requires 3 AND gates, one OR gate and 10
inputs to gates, for a total cost of 14. The apparent conclusion is that for some
functions the POS implementation is less expensive than the SOP implementation, and vice versa.
A.6. The corresponding Karnaugh map is
x1 x2
x3 x4
00
01
11
10
00
0
1
1
1
01
1
1
0
1
11
1
0
0
0
10
1
1
0
1
A minimum-cost SOP expression is
f = x 1 x2 x 3 + x 2 x 3 x4 + x 1 x3 x4 + x 1 x 2 x3 + x 1 x3 x 4 + x 1 x 2 x4
The minimum-cost POS expression is
f = (x1 +x2 +x3 +x4 )(x1 +x2 +x3 )(x1 +x2 +x4 )(x1 +x3 +x4 )(x2 +x3 +x4 )
The cost of the SOP expression is 31, comprising 7 gates and 24 inputs to gates.
The cost of the POS expression is 27, comprising 6 gates and 21 inputs. Therefore, the POS expression leads to the minimum-cost implementation.
A.7. The desired function, f , has the value 1 for the rst ten rows of the truth table in
Figure A.6. The value of f for the remaining six rows is 0. The corresponding
Karnaugh map is
b3 b2
00
01
11
10
00
1
1
0
1
01
1
1
0
1
11
1
1
0
0
10
1
1
0
0
b1 b0
4
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Hence, the expression
f = b3 + b1 b2
describes the required circuit.
A.8. The comparison function, f , is de ned by the map
a1 a0
b1 b0
00
01
11
10
00
1
0
d
0
01
1
1
0
0
11
d
1
1
1
10
1
1
0
1
The minimum-cost SOP expression is
f = a 1 a 0 + b 1 b0 + a 0 b1 + a 1 b0 + a 1 b1
The minimum-cost POS expression is
f = (a1 + b1 )(a0 + b1 + b0 )(a1 + a0 + b0 )
The cost of the SOP expression is 21, comprising 6 gates and 15 inputs to gates.
The cost of the POS expression is 15, comprising 4 gates and 11 inputs. This
describes the lowest-cost circuit.
A.9. The comparison function, f , is de ned by the map
a1 a0
b1 b0
00
01
11
10
00
0
1
1
1
01
0
0
1
1
11
0
0
d
d
10
0
0
d
0
The minimum-cost circuit is speci ed by the expression
f = a1 b1 + a0 b1 b0
5
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A.10. The associative rule would require that
(w ↑ y) ↑ z = w ↑ (y ↑ z)
The left-hand side of this expression gives
(w ↑ y) ↑ z
= wyz
= wy + z
The right-hand side gives
w ↑ (y ↑ z) = wyz
= w + yz
These expressions do not represent the same function. For example, when w =
y = 1 and z = 0, the left hand side is equal to 1 while the right hand side is
equal to 0.
A.11 Simplifying the expression for f into
f = x1 x2 + x1 x2 (x3 x4 + x3 x4 )
and manipulating it using de Morgan’s rule, we can get the following circuit:
x1
x3
x2
x4
f
x3
x4
x1
x2
A.12. A possible circuit is
x1
x2
x1
f
x4
x3
6
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A.13. A possible circuit is
x1
x3
f
x2
x4
A.14. (a) The sum-of-products expressions are
f1
= a
f2
= a⊕b
= ab + ab
f3
= a⊕b⊕c
= abc + abc + abc + abc
These AND-OR circuits can be implemented using only NAND gates by a direct
transformation as explained in Figure A.8. The expressions for f 1 , f2 and f3
require 0, 3 and 5 gates, respectively, plus 3 gates to invert the input variables a,
b and c.
(b) The general block in Figure PA.2b can be implemented as
Since the leftmost block need not have an input from the left side, the XOR gate
is not needed in that block, and input a is wired directly to the output of the
block. Thus, only two XOR gates are needed. They can be implemented with a
total of 8 NAND gates (see Problem A.15).
7
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A.15. The required circuit is
x1
x1 ⊕ x2
x2
A.16. Consider the a function only. The implementation given in Figure A.37 can be
seen to be correct by the following argument. The input to the inverter must be
a. The 2-level NAND network implements a sum-of-products expression for the
0s of the truth table column for a. (See Figure A.8). The 4-input NAND gate
accounts for the input valuation (x1 , x2 , x3 , x4 ) = (0, 0, 0, 1), and the 3-input
NAND gate accounts for the input valuation (x1 , x2 , x3 , x4 ) = (0, 1, 0, 0) coupled with the “don’t care” entry at (x1 , x2 , x3 , x4 ) = (1, 1, 0, 0). The remaining
functions in the given implementation can be veri ed in the same way.
The AND, OR, NOT implementation follows directly via replacement of the
individual NAND gate networks by AND and OR gates as shown in Figure A.8.
A.17. The stuck-at-1 fault at F1 reduces the network to
x1
x2
x3
6
1
8
f
5
x4
7
The stuck-at-0 fault at F2 reduces the network to just a wire that implements
f = x4
8
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A.18. As explained in Section A.5.1, in a CMOS circuit the pull-up network implements the function f and the pull-down network implements its complement f.
In our case
f = x 1 x 2 + x3 x 4
and
f = (x1 + x2 )(x3 + x4 )
The term (x1 + x2 ) is realized as a parallel connection of NMOS transistors
driven by inputs x1 and x2 . Similarly, the term (x3 + x4 ) is realized as a parallel
connection of NMOS transistors driven by inputs x3 and x4 . These two parallel
subcircuits have to be connected in series to realize the product of the two terms.
In the pull-up network, the term x1 x2 is realized as a series connection of PMOS
transistors driven by inputs x1 and x2 . Similarly, the term x3 x4 is realized as
a series connection of PMOS transistors driven by inputs x3 and x4 . A parallel
connection of these subcircuits realizes x 1 x2 + x3 x4 .
Therefore, the desired circuit is
Vsupply
x2
x3
x1
x4
f
x1
x2
x3
x4
9
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.19. The waveforms are
1
Clock
0
J
1
0
K
1
0
Q
1
0
A.20. The truth table for the NAND latch is
A
B
Q
Q
0
0
1
1
0
1
0
1
1
1
0
0/1
1
0
1
1/0
This truth table describes the same behavior as the truth table in Figure A.24b
if we let A = S and B = R. The only difference is when A = B = 0 causing Q = Q
= 1, but this input valuation should not be used in an SR latch. The two NAND
gates at the input of the circuit in Figure A.26 provide the required inversion of
signals S and R when Clk = 1.
A.21. Point P3 follows changes at D with 1 gate delay, and point P4 follows changes at
D with 2 gate delays. If we assume that both P3 and P4 are to be stable at their
correct values no later than when the clock goes to 0, then the minimum setup
time is 2 gate delays.
For calculating hold time, the critical case is when P1 is set to 1 as a result of the
clock going to 0. This is the case when D = 1 at the clock edge and the ip- op
is to be set into the 1 state. The D line must hold for at least 1 gate delay after the
trailing edge of the clock so that the output of gate 2 can get to 1 and maintain
the output of gate 1 at 0 for proper operation. Therefore, the hold time is 1 gate
delay.
10
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.22. Using all NOR gates gives the truth table
Clk
D
Q(t + 1)
0
0
1
0
1
x
0
1
Q(t)
Therefore, the circuit is a gated D latch which is set to the value of D input
when Clk = 0.
A.23. The modi ed circuit is
One ⁄ Two
In
D
Clock
Q
D
Q
D
Q
D
Q
Q
Q
Q
Q
A.24. A possible circuit is
Right ⁄ Left
P
D
Q
Q
D
Q
D
Q
D
Q
Q
Q
Q
C
C
C
Clock
Initialize
11
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.25. The 3-input decoder circuit is
x1
7
6
5
x2
4
3
2
1
0
x3
A.26. The up/down counter can be implemented as follows:
U /D
1
T
Clock
P
P
P
Q
Q
T
T
Q
Q
C
Q
C
Q1
Q
C
Q2
Count ⁄ Load
External source
12
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
Q3
A.27. A 4-bit synchronous counter can be implemented as
1
T
Clock
Q
T
Q0
Q
T
Q1
Q
Q
Q
Q2
T
Q
A.28. (a) The truth table for f implemented using an 8-input multiplexer is
x1
x2
x3
f
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
x4
0
x4
x4
0
x4
(b) The truth table using a 4-input multiplexer is
x3
x4
f
0
0
1
1
0
1
0
1
x2
x1
x1
0
13
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
Q
Q
Q3
A.29. (a) The truth table for f implemented using an 8-input multiplexer is
x1
x2
x3
f
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x4
x4
x4
1
0
1
0
x4
(b) It cannot be done with a single 4-input multiplexer.
A.30. (a) The total number of distinct functions of three binary variables is
3
22 = 256
(b) Functions that cannot be implemented are those requiring 3 or more product
terms in the minimal sum-of-products expression, e.g. x1 x2 + x2 x3 + x1 x3 .
(c) Connect all four AND gates to a single OR gate.
A.31. (a) Using the modi ed PAL, f can be implemented as
x1
x2 x3
x1 x2
x4
x3
x1 x2
x3
f
(b) Two. They are x1 ⊕ x2 ⊕ x3 and its complement.
14
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.32. In this case the state-assigned table is
Present
state
Next state
x=0
x=1
y2 y1
Y 2 Y1
Y2 Y 1
1 0
1 1
1 1
Output z
x=0
x=1
0 0
0
0
0 1
1 0
0
0
0 1
0 0
1 1
1
1
0 0
1 0
0 1
0
0
The next-state and output equations are
Y2
Y1
z
= xy1 + y 1 x
= x ⊕ y2
= y 2 y1
15
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.33. The state table is
Present
state
Next
state
S0
S3
S1
S2
S2
S0
S3
S1
Present
state
Next
state
y y
2 1
Y2 Y1
0 0
1 1
0 1
1 0
1 0
0 0
1 1
0 1
The state-assigned table is
The next-state and output equations are
Y2
= y2
Y1
z2
= y 1 y 2 + y 1 y2
= y2
z1
= y1
16
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.34. The state table is
Present
state
Next
state
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S0
The state-assigned table is
Present
state
Next
state
y3 y2 y1
Y3 Y2 Y1
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
0 0 0
1 1 0
d d d
1 1 1
d d d
The next-state and output equations are
Y3
= y 1 y2 + y 1 y3
Y2
Y1
= y 1 y2 + y 1 y 2 y 3
= y1
z3
= y3
z2 = y 2
z1 = y 1
17
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.35. J and K inputs needed to cause the desired transitions are
Present
state
Next
state
J
K
0
0
0
d
0
1
1
d
1
0
d
1
1
1
d
0
The state-assigned table for the solution in Problem A.33 becomes
Present
state
Next
state
Inputs for
JK ip- ops
y2 y1
Y2 Y1
J2 K2 J1 K1
0 0
1 1
1 d 1 d
0 1
1 0
1 d d 1
1 0
0 0
d 1 0 d
1 1
0 1
d 1 d 0
The next-state equations are
J2
= 1
K2
J1
= 1
= y2
K1
= y2
These equations are simpler than those using D ip- ops, because the toggle feature of JK ip- ops is naturally suitable for implementation of counter circuits.
18
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.36. The state-assigned table is
Present
state
Next
state
y3 y2 y1
Y3 Y2 Y1
J3 K3 J2 K2 J1 K1
0 0 0
0 0 1
0 d 0 d 1 d
0 0 1
0 1 0
0 d 1 d d 1
0 1 0
0 1 1
0 d d 0 1 d
0 1 1
1 0 0
1 d d 1 d 1
1 0 0
1 0 1
d 0 0 d 1 d
1 0 1
0 0 0
d 1 0 d d 1
1 1 0
d d d
d d d d d d
1 1 1
d d d
d d d d d d
Inputs for
JK ip- ops
The next-state equations are
J3
K3
= y 1 y2
= y1
J2
K2
= y1 y 3
= y1
J1
K1
= 1
= 1
19
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.37. Let the three outputs be de ned as:
z1 = 1 denotes that mechandise has to be dispensed
z2 = 1 denotes that the change is 20 cents
z3 = 1 denotes that the change is 5 cents
The outputs are speci ed as shown in the following state-assigned table
Present
state
Next state
Outputs
x1 x 2 = 00 x1 x 2 = 01 x1 x 2 = 10 x1 x 2 = 11 x1 x 2 = 00 x1 x 2 = 01 x1 x 2 = 10 x1 x 2 = 11
y2 y1
Y2 Y1
Y2 Y1
Y2 Y1
Y2 Y1
z1 z2 z3
z1 z2 z3
z1 z2 z3
z1 z2 z3
S0
0 0
0 0
0 1
1 1
-
0 0 0
0 0 0
0 0 0
-
S1
0 1
0 1
1 0
0 0
-
0 0 0
0 0 0
1 0 1
-
S2
1 0
1 0
0 0
0 0
-
0 0 0
1 0 0
-
-
S3
1 1
1 1
0 0
0 0
-
0 0 0
1 0 1
1 1 0
-
The next-state and output equations are
Y2
= x 1 x 2 y2 + x2 y 2 y1 + x1 y 2 y 1
Y1
z3
= x1 x2 y1 + (x1 + x2 )y 2 y1
= x2 y2 y1 + x1 y 2 y1
z2
z1
= x1 y2
= (x1 + x2 )y2 + x1 y1
There are no equivalent states in the table.
20
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.38. The state table is
Present
state
Next state
Output z
x=0
x=1
x=0
x=1
S0
S1
S0
0
0
S1
S1
S2
0
0
S2
S1
S0
0
1
The state-assigned table is
Present
state
Next state
Output z
x=0
x=1
x=0
x=1
y2 y1
Y 2 Y1
Y2 Y1
0 0
0 1
0 0
0
0
0 1
0 1
1 0
0
0
1 0
0 1
0 0
0
1
1 1
d d
d d
d
d
The next-state and output equations are
Y2
= xy1
Y1
z
= x
= xy2
21
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
A.39. The state table is
Present
state
Next state
Output z
x=0
x=1
x=0
x=1
S0
S1
S0
0
0
S1
S1
S2
0
0
S2
S1
S0
1
1
The state-assigned table is
Present
state
Next state
Output z
x=0
x=1
x=0
x=1
y2 y1
Y 2 Y1
Y2 Y1
0 0
0 1
0 0
0
0
0 1
0 1
1 0
0
0
1 0
0 1
0 0
1
1
1 1
d d
d d
d
d
The next-state and output equations are
Y2
= xy1
Y1
z
= x
= y2
22
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl