ES 330 Electronics II
Fall 2016
Sect
Lectures
Location
Instructor
Office
Office Hours
Email
Tel
001
Monday
9:00 am to
9:50 am
Salazar
2001
Dr.
Donald
Estreich
Salazar
Room
2010C
Monday 12:00 Noon - 1:15 pm;
Wednesday 9:00 – 9:55 am
or by special arrangement
dbe@sonic.net
(707)
6642030
001
Wednesday
10:00 am to
10 :50 am
Salazar
2001
Dr.
Donald
Estreich
Salazar
Room
2010C
Monday 12:00 Noon - 1:15 pm;
Wednesday 9:00 – 9:55 am
or by special arrangement
dbe@sonic.net
(707)
6642030
Sect
Laboratory
Location
Instructor
Office
Office Hours
Email Tel
002
Monday
10:00 am to
11 :50 am
Salazar
2005
Dr.
Donald
Estreich
Salazar
Room
2010C
Monday 12:00 Noon - 1:15 pm;
Wednesday 9:00 – 9:55 am
or by special arrangement
dbe@sonic.net
(707)
6642030
Course Description : (2 Units; 2 hours of lecture and 1 laboratory session weekly)
Presents fundamental concepts used in semiconductor electronic circuits (discrete and integrated). Covers basic
functionality of diodes, BJT and (MOS)FET transistors in electronic circuits – finding DC terminal voltages and
currents (biasing), calculating low and high frequency response of electronic circuits (includes single-stage,
differential & multi-stage amplifiers), calculating input and output impedances, and applying feedback in
electronic circuit design. Laboratory covers analog circuits from lectures with emphasis on design of such
circuits.
Prerequisite: ES 230 Electronics I, or consent of the instructor.
Required Textbook: Adel S. Sedra & Kenneth C. Smith, Microelectronic Circuits, 7th edition, Oxford
University Press, New York, 2015. ISBN 978-0-19-933913-6 (Note: Must be the seventh edition.)
ES330 Class Website: The ES 330 Website is found at:
http://www.sonoma.edu/esee/courses/es330/
Homework, solutions to homework problems, formal assignments and handout notes are available on the ES
330 Electronics Website.
Course Learning Objectives:
Upon completion of ES 330, a student will be able to:
A. Apply fundamental device and circuit design concepts to a variety of analog semiconductor electronic circuits
B. Apply the core operational principles of semiconductor devices (e.g., bipolar junction transistor and MOS field-effect
transistor) to electronic circuit design
C. Calculate terminal voltages and currents (i.e., DC bias points) in electronic circuits
D. Apply AC small-signal transistor models for analyzing and designing electronic circuit performance
E. Calculate important performance parameters of electronic circuits
F. Analyze differential circuit configurations with application to Differential pairs, operational amplifiers, DC amplifiers
and Gilbert multipliers
G. Understand and appreciate the differences involved in the design of discrete electronic circuits versus design of silicon
transistor integrated circuits
H. Demonstrate an ability to make electrical measurements on such electronic circuits and write formal laboratory reports
I. Develop critical thinking skills through electronic circuit analysis and design
Course Grading:
Homework assignments (approximately weekly)
Two midterms
Final examination
Laboratory exercises
Total =
25%
25%
25%
25%
100%
Grading:
95 to 100 is an A
87 to 89 is a B+
80 to 82 is a B73 to 76 is a C
67 to 69 is a D+
60 to 62 is a D-
and
90 to 94 is an A83 to 86 is a B
77 to 79 is a C+
70 to 72 is a C63 to 66 is a D
0 to 59 is an F
The class grade will be based upon the following activities:
1. Homework: Homework will be assigned approximately weekly. Homework is an important part of the process of
learning for engineers and homework will both reinforce topics covered in class and introduce auxiliary topics which
extend the material covered in lectures. Homework must be turned in by the end of the class period of the day it is
due. Late homework will be penalized by subtracting 20% per day from its score. No homework will be accepted
after 5 days.
2. Examinations: There will be three exams during the semester – two midterms and one final examination.
Together they contribute to one-half of the course grade. Examinations are based upon class lectures, assigned
reading in the textbook and worked homework problems. The final examination will test the content of the entire course
and the student’s ability to apply the principles learned during the course. A student will receive a grade of 0 (zero) if
he or she does not appear for an exam without a prior acceptable excuse. You must let the instructor know in
advance if you must miss an examination, at which time you will be given an opportunity to take the examination
early by special arrangement. There may also be unannounced short “shock quizzes” at any time at the discretion
of the instructor. No makeup is possible for missing a “shock quiz” and their scores are included in the midterm
scores.
3. Laboratory assignments: Construct selected electronic circuits and perform appropriate electrical measurements on
these circuits. Specific questions will be asked for each exercise. A circuit design project may be assigned. Formal
laboratory reports are required which summarize and present the results of each assigned laboratory experiment.
4. Class attendance and participation: Regular attendance is strongly encouraged because course content beyond that
of the textbook may be presented and clarifying examples may be worked out in class. In addition, questions during
lectures are strongly encouraged to clarify course material. The instructor believes that if a student must miss a class
session that out of courtesy they must notify the instructor before the class. For SSU policies on class attendance see
http://www.sonoma.edu/uaffairs/policies/studentinfo.shtml 4. Academic Honesty: You are responsible to behave ethically & honestly. Copying, cheating, forgery, and other
unethical or dishonest actions are not tolerated, will result in a zero grade, and may be reported to SSU authorities. For
more information on the SSU academic honesty policy please refer to
http://www.sonoma.edu/uaffairs/policies/cheating_plagiarism.htm
5. Learning Disabilities: Students requiring special accommodations should meet with the instructor the first
or second week of the course to discuss how to meet their needs during the semester. Prior to meeting with the
instructor, be sure your have met with the SSU Disability Services office on the first floor of Salazar Hall to be
familiar with their policies. You may consult their website at
http://www.sonoma.edu/uaffairs/policies/disabilitypolicy.htm 6. Other SSU policies: Be sure you understand the policies that specifically affect you as a student of this
course. For example:
Add/Drop Policy: http://www.sonoma.edu/uaffairs/policies/disabilitypolicy Grade Appeal Policy: http://www.sonoma.edu/uaffairs/policies/gradepolicy.htm 7. Civility: Keep cell phones and pagers TURNED OFF during the entire lecture and lab period – no
exceptions! Show respect for your fellow students and keep in mind that SSU is a learning environment. If for
some reason issues arise during the semester, please inform the instructor of the situation so that they can be
resolved.
Fall 2016 ES330 Student Outcomes:
ABET Student Outcomes (a) an ability to apply knowledge of mathematics, science, and engineering (b) an ability to design and conduct experiments, as well as to analyze and interpret data (c) an ability to design a system, component, or process to meet desired needs (d) an ability to function on multi-­‐disciplinary teams (e) an ability to identify, formulate, and solve engineering problems (f) an understanding of professional and ethical responsibility (g) an ability to communicate effectively (h) the broad education necessary to understand the impact of engineering solutions in a global and societal context (i) a recognition of the need for, and an ability to engage in life-­‐long learning (j) a knowledge of contemporary issues (k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice Assessment Methods:
Assessment of student learning:
(1) Examinations (midterms and final examination)
(2) Homework
(3) Laboratory Reports and Laboratory Project
Assessment of course quality:
(1) Student survey
(2) Student verbal and peer instructor feedback
Fall 2016 ES330 Class Lecture and Exam Schedule:
Course Learning Objectives B,C,D,E,F,G,I H Level of Support 4 3 A,B,D,E,F,G,I 4 Not supported 4 Not supported 2 Not supported 2 2 2 C,D,E,F,G,I H I A,H,I H Date Topic Date Topic Aug 22 Aug 29 No class Review Transistors (MOSFET and BJT) from Chapters 5 and 6. Introduction to physical features of transistors Aug 24 Aug 31 Sept 5 Labor Day – SSU closed Sept 7 Sept 12 Section 7.3 Basic transistor configurations – Three configurations; amplifier characterization; CE versus CS amplifier; degeneration with E and S resistors; CG and CB amplifiers Discrete transistor amplifier circuits – CS and CS amplifiers (w/ coupling caps); frequency response of gain stages Finish Chapter 7 and begin Chapter 8 (Section 8.1). Integrated circuit design versus discrete circuit design – IC design philosophy MIDTERM 1 Sept 14 Class Introduction Start Chapter 7 – Section 7.1 Transistor amplifiers – basic principles; voltage gain; VTC; linearity; large-­‐signal vs. small-­‐
signal; bias point Q Section 7.2 Small-­‐signal operation & models -­‐-­‐ MOSFET case versus the BJT case; summarize when to use MOSFET and when to use BJT Discrete transistor amplifiers (continued) – Source and emitter flowers; when to include output r0; general rules for biasing MOSFET and BJT gain stages Oct 10 Section 8.2 Current sources and current mirrors in MOS and BJT integrated circuits; current steering and scaling Oct 12 Oct 17 Section 8.4 CG and CB amplifiers; advantages and disadvantages of CG and CB stages Oct 19 Oct 24 Section 8.6 Improved current mirrors; cascode MOSFET mirrors; Wilson BJT current mirror; Wilson MOSFET mirror Oct 26 Monday Sept 19 Sept 26 Oct 3 Wednesday Sept 21 Frequency response – Bode plots and pole-­‐zero diagrams in greater detail. Sept 28 Review for Midterm 1 & Questions answered Oct 5 Review of Midterm 1 results and continue with Chapter 8 (Section 8.1) on Building Blocks of IC Design Section 8.3 Basic gain stages: CS and CE amplifiers; Parameters of interest (such as intrinsic gain, bandwidth, etc.) and transistor loads Section 8.5 Cascode stages and cascading in general; MOSFET cascode; voltage partitioning in cascode; multi-­‐cascode and folded cascode; BJT cascode Section 8.7 Transistor stage pairing; CC-­‐CE, CD-­‐CS and CD-­‐CE pairs; Darlington configuration; CC-­‐CB and CD-­‐CG configurations Oct 31 Nov 7 Nov 14 Nov 21 Nov 28 Dec 5 Dec 12 Begin Chapter 9 (Section 9.1) – MOSFET differential pair; operation of diff pair; common-­‐
mode signals; large-­‐signal versus small-­‐signal operation; using current source loads; cascoded diff pair Review for Midterm 2 & Questions answered Review of Midterm 2 results and begin Section 9.3 on common-­‐
mode rejection in diff pairs Section 9.5 Diff amps with current mirrors; differential to single ended conversion; differential gain versus common-­‐
mode gain; CMRR; operational amplifier design using diff pair Begin Chapter 10 on Frequency Response (Sections 10.1 and 10.2) -­‐-­‐ -­‐3 dB response; related to Bode plot; Short Circuit Time Constant (SCTC) method for fL; internal capacitances and high frequency responses; short-­‐
circuit unity current gain frequency fT Section 10.4 HF gain function; Open Circuit Time Constant (OCTC) method for fH; application of the OCTC method; Example for CE amplifier Final Exam Note: Thanksgiving holiday is Nov 24th and 25th. Nov 2 Section 9.2 BJT differential pair; basic operation and input CM operation; large-­‐signal and small-­‐
signal operation Nov 9 MIDTERM 2 Nov 16 Section 9.4 DC offsets and biasing of differential stages; imperfect symmetry in diff pairs Section 9.6 Multistage amplifier design; 2-­‐stage op amp example; cascading versus cascoding Nov 23 Nov 30 Section 10.3 High frequency amplifier response; CE response and CS response; Miller’s theorem; using Miller’s theorem Dec 7 Review for final exam – Questions and more questions Dec 14 No class during finals week Fall 2016 ES330 Laboratory Schedule: Date Monday Aug 22 Aug 29 Topic No class or laboratory on Monday General orientation for laboratory; Discussion of rules and guidelines; laboratory report format; safe laboratory practices. Limitations of semiconductor devices. Sept 5 Sept 12 Labor Day – SSU closed Characterizing BJT and MOSFET devices (or what did you remember from ES 230?) – DC characteristics of both NPN BJT and NMOS FET devices. Sept 19 NMOS common-­‐source amplifier Sept 26 NPN BJT common-­‐emitter amplifier Oct 3 NMOS common-­‐source amplifier with source resistor degeneration & NPN BJT common-­‐
emitter amplifier with emitter resistor degeneration Oct 10 NMOS common-­‐gate amplifier & NPN BJT common-­‐base amplifier Oct 17 NMOS source follower (common-­‐drain) & NPN BJT emitter follower (common-­‐collector) Oct 24 NMOS differential amplifier (comparing methods to establish tail current) Oct 31 NPN BJT differential amplifier (comparing methods to establish tail current) – comparing NMOS and BJT differential amplifiers) Nov 7 Selection of Laboratory Project (Guidelines and project selection – consulting with those needing help on selection). Nov 14 Work on laboratory Project Nov 21 Work on laboratory Project Nov 28 Demonstration of Project to class Dec 5 Make-­‐up Session Some possible “Laboratory Projects” might be variable gain amplifier (there are several different ways to perform the gain variation), phase-­‐shift oscillator, multiplier/modulator, variable attenuator using MOSFET devices, multi-­‐vibrator, class-­‐B push-­‐pull power amplifier, DC amplifier (challenge is controlling the drift), BICMOS gate, and many others. Note: Thanksgiving holiday is Nov 24th and 25th.