Warp 
HDL Development System
User’s Guide
Cypress Semiconductor
3901 North First Street
San Jose, CA 95134
(408) 943-2600
October 1998
Part Number CY3120DOC
The following are trademarks or registered trademarks of Cypress Semiconductor Corporation: Warp,
Warp2, Warp3, Nova, Galaxy, Flash370, UltraLogic, Impulse3, UltraGen, pASIC380, ISR, MAX340.
The following are trademarks or registered trademarks of Viewlogic Systems:
Powerview, Workview, Workview PLUS, ViewDraw, ViewSim, ViewTrace, ViewText, Cockpit, VCS.
The following are trademarks or registered trademarks of Microsoft Corporation: Microsoft, Windows,
Windows 3.1, Windows 3.11, Windows NT, Windows 95.
The following is a registered trademark of Intel Corporation: Pentium.
The following is a trademark of Hewlett Packard Corporation: HP-UX.
The following are trademarks of Mentor Graphics Corporation: QuickHDL, V-System.
The following is a trademark of Veribest, Inc.: Veribest.
The following is a registered trademark of AT&T: UNIX.
The following are trademarks or registered trademarks of Synopsys, Inc.: Synopsys, Design Compiler, VSS.
The following are trademarks or registered trademarks of Cadence Design Systems Inc.: Verilog, Leapfrog,
Verilog-XL.
The following are trademarks or registered trademarks of Sun Microsystems, Inc.: Sun SparcStation,
Solaris.
The following is a registered trademark of Open Software Foundation: Motif.
The following are trademarks or registered trademarks of Bristol Technology, Inc.: Wind/U, HyperHelp,
Xprinter.
The following is a trademark or registered trademark of Adobe, Inc.: Acrobat Reader.
The following are registered trademarks of Aldec, Inc.: Active-HDL Sim, Active-HDL FSM, Active-VHDL,
Active-State Editor.
Cypress Semiconductor Corporation may revise this publication from time to time without notice. Some
states or jurisdictions do not allow disclaimer of express or implied warranties in certain transactions;
therefore, this statement may not apply to you.
All other brand or product names are trademarks or registered trademarks of their respective companies or
organizations.
Copyright © 1998, 1997, 1996 Cypress Semiconductor Corporation. All rights reserved.
Cypress Software License Agreement
Cypress Software License Agreement
LICENSE. Cypress Semiconductor Corporation ("Cypress") hereby grants you, as a Customer and
Licensee, a single-user, non-exclusive license to use the enclosed Cypress software program
("Program") on a single CPU at any given point in time. Cypress and its Licensors retain title to
the software and any patents, copyrights, trade secrets, and other intellectual property rights
therein. Cypress authorizes you to make archival copies of the software for the sole purpose of
backing up your software and protecting your investment from loss.
Product(s) provided under this agreement are copyrighted and licensed (not sold). Cypress does
not transfer title to the Products to Licensee.
Product(s) provided under this agreement may contain or be derived from portions of materials
provided by a third party under license to Cypress. Cypress has assumed responsibility for the
selection of such materials to produce the Product(s) licensed hereunder. THE THIRD PARTY
DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED WITH RESPECT TO THE USE
OF SUCH MATERIALS IN CONNECTION WITH THE PRODUCT(S), INCLUDING
(WITHOUT LIMITATION) ANY WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE.
Product(s) provided under this agreement may contain or be derived from portions of materials
provided by a third party under license to Cypress. The third party may enforce any of the
provisions of this agreement, to the extent such third party materials are affected. Additionally,
any limitation of liabilities described in this agreement also applies to any third-party supplier of
materials supplied to Licensee. Cypress and its third-party supplier limitations of liabilities are
not cumulative. Such third party supplier is an intended beneficiary of this section.
TERM AND TERMINATION. This Agreement is effective from the date the diskettes are
received until this Agreement is terminated. The unauthorized reproduction or use of the Program
and/or documentation will immediately terminate this Agreement without notice. Upon
termination you are to destroy both the Program and the documentation.
COPYRIGHT AND PROPRIETARY RIGHTS. The Program and documentation are protected
by both United States Copyright Law and International Treaty provisions. This means that you
must treat the documentation and Program just like a book, with the exception of making archival
copies for the sole purpose of protecting your investment from loss. The Program may be used by
any number of people, and may be moved from one computer to another, so long as there is No
Possibility of its being used by two people at the same time.
RESTRICTIONS. The Software contains copyrighted material, trade secrets, and other proprietary
information. In order to protect them you may not decompile, reverse engineer, disassemble, or
iii
Cypress Software License Agreement
otherwise reduce the Software to a human-perceivable form. You may not modify or prepare
derivative works of the Software in whole or in part. You may install up to one copy on a single
computer and make one copy of the Software in machine-readable form for backup purposes
only. You must reproduce on each copy of the Software the copyright and any other proprietary
legends that were on the original copy of the Software.
DISCLAIMER. THIS PROGRAM AND DOCUMENTATION ARE LICENSED "AS-IS,"
WITHOUT WARRANTY AS TO PERFORMANCE. CYPRESS EXPRESSLY DISCLAIMS
ALL WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS OF THIS PROGRAM
FOR A PARTICULAR PURPOSE.
LIMITED WARRANTY. The diskette on which this Program is recorded is guaranteed for 90
days from date of purchase. If a defect occurs within 90 days, contact the representative at the
place of purchase to arrange for a replacement.
RESELLING. The reselling or distribution of this product can be done by Cypress authorized
distributors only.
GOVERNMENTAL USE. Use, duplication and disclosure of the Software by or for any
government or government agency is subject to restrictions; including but not limited to
restrictions set forth in subdivisions (c)(1)(ii) of the Rights in Technical Data and Computer
Software clause at U.S. DFARs 252.227-7013. If used or delivered pursuant to a defense
contract, or the restrictions set forth in Commercial Computer Software - Restricted Rights
at FAR 252.227-19, or equivalent agency supplement, as applicable.
Manufacturer is ALDEC, Inc., 3 Sunset Way, Nevada, 89011.
EXPORT RESTRICTION. You agree that you will not export or reexport the Software,
reference images or accompanying documentation in any form without the appropriate
government licenses. Your failure to comply with this provision is a material breach of
this Agreement.
BENCHMARKING. This license Agreement does not convey to you the right to publish
performance benchmarking results involving any Cypress Warp products. Permission to publish
performance benchmarking results involving any Cypress Warp products must be received in
writing from Cypress Semiconductor prior to publishing.
LIMITATION OF REMEDIES AND LIABILITY. IN NO EVENT SHALL CYPRESS BE
LIABLE FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM
PROGRAM USE, EVEN IF CYPRESS HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. CYPRESS'S EXCLUSIVE LIABILITY AND YOUR EXCLUSIVE
iv
Cypress Software License Agreement
REMEDY WILL BE IN THE REPLACEMENT OF ANY DEFECTIVE DISKETTE AS
PROVIDED ABOVE. IN NO EVENT SHALL CYPRESS'S LIABILITY HEREUNDER
EXCEED THE PURCHASE PRICE OF THE SOFTWARE.
ENTIRE AGREEMENT. This Agreement constitutes the sole and complete Agreement between
Cypress and the Customer for use of the Program and documentation. Changes to this Agreement
may be made only by written mutual consent.
GOVERNING LAW. This Agreement shall be governed by the laws of the State of
California, and without reference to conflict of laws principles. If for any reason a court of
competent jurisdiction finds any provision of this License, or portion thereof, to be
unenforceable, that provision of the License shall be enforced to the maximum extent
permissible so as to effect the intent of the parties, and the remainder of this License shall
continue in full force and effect. This License constitutes the entire agreement
between the parties with respect to the use of this Software and related documentation, and
supersedes all prior or contemporaneous understandings or agreements, written or oral,
regarding such subject matter. Should you have any question concerning this Agreement,
please contact:
Cypress Semiconductor Corporation
Attn: Legal Counsel
3901 N. First Street
San Jose, CA 95134-1599
408-943-2600
v
Cypress Software License Agreement
vi
Contents
User’s Guide
Contents
Chapter 1
Introduction ......................................................................... 1
1.1 Overview of Warp............................................................ 2
1.2 VHDL Warp Capabilities ................................................. 4
1.3 Verilog Warp Capabilities................................................ 5
1.4 About this User’s Guide .................................................. 6
Chapter 2
Command Line Language .................................................. 7
2.1 Warp Command Line Switches ....................................... 8
2.1.1 Warp Command Syntax......................................... 8
2.2 Warp Command Options................................................. 9
2.2.1 The -d Option......................................................... 9
2.2.2 The -b Option....................................................... 10
2.2.3 The -a Option....................................................... 11
2.2.4 The -e Option....................................................... 11
2.2.5 The -f Option........................................................ 11
2.2.6 The -h Option....................................................... 13
2.2.7 The -l Option ........................................................ 14
2.2.8 The -m Option...................................................... 14
2.2.9 The -o Option....................................................... 15
2.2.10 The -p Option..................................................... 15
2.2.11 The -q Option..................................................... 16
2.2.12 The -r Option...................................................... 16
2.2.13 The -s Option ..................................................... 16
2.2.14 The -t Option...................................................... 16
2.2.15 The -verilog Option ............................................ 17
2.2.16 The -v Option ..................................................... 17
2.2.17 The -w Option .................................................... 17
2.2.18 The -xor2 Option................................................ 17
2.2.19 The -yl Option .................................................... 18
2.2.20 The -ygs Option ................................................. 18
2.2.21 The -yga Option ................................................. 18
2.2.22 The -ygc Option ................................................. 18
2.2.23 The -yh Option ................................................... 19
2.2.24 The -yv Option ................................................... 19
viii
Warp User’s Guide
Contents
2.2.25 The -yu Option ................................................... 19
2.2.26 The -ys0 Option ................................................ 20
2.2.27 The -yp Option ................................................... 20
2.2.28 The -yw Option .................................................. 20
2.2.29 The -yi33 Option ................................................ 20
2.3 Recommendations ........................................................ 21
2.4 Warp Output .................................................................. 21
Chapter 3
Schematic Entry with Workview Office........................... 23
3.1 Overview ....................................................................... 24
3.2 LPM Library................................................................... 25
3.2.1 What Is LPM? ...................................................... 25
3.2.2 How to Use LPM.................................................. 26
3.2.3 Getting Started..................................................... 27
3.2.4 Adding an LPM Element ...................................... 30
3.2.5 Changing an LPM Element.................................. 31
3.2.6 Creating/Modifying a Non-LPM Element ............. 33
3.3 Exporting the Schematic ............................................... 34
3.4 Schematic to Symbol .................................................... 35
3.5 VHDL To Symbol .......................................................... 36
3.6 Symbol to VHDL............................................................ 36
3.7 Update Library............................................................... 37
3.8 Display Hierarchy .......................................................... 37
Chapter 4
Schematic Entry with Powerview .................................... 39
4.1 Overview ....................................................................... 40
4.2 LPM Library................................................................... 42
4.2.1 What Is LPM? ...................................................... 42
4.2.2 How to Use LPM.................................................. 42
4.2.3 Creating the lpmlocal Library ............................... 44
4.2.4 Creating an LPM Element.................................... 44
4.2.5 Modifying an LPM Element.................................. 46
4.2.6 Creating/Modifying a Non-LPM Element ............. 46
Warp User’s Guide
Contents
4.3 Exporting the Schematic ............................................... 47
4.4 Back-Annotation............................................................ 49
4.5 Schematic to Symbol .................................................... 50
4.6 VHDL To Symbol .......................................................... 51
4.7 Symbol to VHDL............................................................ 51
4.8 Update Library............................................................... 52
4.9 Display Hierarchy .......................................................... 53
Chapter 5
Synthesis ........................................................................... 55
5.1 Synthesis Directives ...................................................... 56
5.1.1 Understanding Synthesis Directives .................... 56
5.1.2 Design Flow and Strategy for Using Directives ... 56
5.1.3 Available Directives ............................................. 59
5.1.4 VHDL Synthesis Directives.................................. 60
5.1.4.1 Scope and Inheritance
60
5.1.4.2 Applying Directives .................................... 60
5.1.5 Verilog Synthesis Directives ................................ 62
5.1.5.1 Scope and Inheritance
62
5.1.5.2 Applying Directives .................................... 62
5.2 VHDL Synthesis ............................................................ 64
5.2.1 Example 1—DRAM Controller ............................. 64
5.2.1.1 First Pass
68
5.2.1.2 Second Pass -- State Machine Gray Encoding 70
5.2.1.3 Third Pass -- Synthesis_off ....................... 71
5.2.2 Example 2—Multiply and Accumulate Function .. 73
5.2.2.1 First Pass -- Default Options
73
5.2.2.2 Second Pass -- Area Optimization ............ 74
5.2.3 Area Optimization ................................................ 74
5.2.3.1 The GOAL Directive
74
5.2.3.2 The SYNTHESIS_OFF Directive .............. 75
5.2.3.3 The FF_TYPE Directive ............................ 76
5.2.4 Specific Control.................................................... 77
5.2.4.1 The FF_TYPE Directive (CPLD Only)
77
5.2.4.2 The NODE_NUM Directive ....................... 77
x
Warp User’s Guide
Contents
5.2.4.3 The LAB_FORCE Directive (CPLD Only) . 78
5.2.4.4 The SUM_SPLIT Directive (CPLD Only) ... 79
5.2.4.5 The POLARITY Directive (CPLD Only) ..... 80
5.2.5 Speed Optimization ............................................. 80
5.2.5.1 The GOAL Directive
81
5.2.6 Documentation Directives.................................... 81
5.2.6.1 The PART_NAME Directive
81
5.2.6.2 The ORDER_CODE Directive ................... 82
5.2.6.3 The PIN_NUMBERS Directive .................. 82
5.3 Verilog Synthesis .......................................................... 83
5.3.1 Example —Multiply and Accumulate Function .... 83
5.3.1.1 First Pass -- Default Options
83
5.3.1.2 Second Pass -- Area Optimization ............ 84
5.3.2 Area Optimization ................................................ 84
5.3.2.1 The GOAL Directive
84
5.3.2.2 The SYNTHESIS_OFF Directive .............. 85
5.3.2.3 The FF_TYPE Directive ............................ 86
5.3.3 Specific Control.................................................... 86
5.3.3.1 The FF_TYPE Directive (CPLD Only)
86
5.3.3.2 The NODE_NUM Directive ....................... 87
5.3.3.3 The LAB_FORCE Directive (CPLD Only) . 87
5.3.3.4 The SUM_SPLIT Directive (CPLD Only) ... 88
5.3.3.5 The POLARITY Directive (CPLD Only) ..... 89
5.3.4 Speed Optimization ............................................. 89
5.3.4.1 The GOAL Directive
90
Chapter 6
Synthesis Directives ......................................................... 91
6.1 Introduction ................................................................... 92
6.2 Synthesis Directives ...................................................... 96
6.2.1 enum_encoding ................................................... 96
6.2.2 ff_type .................................................................. 97
6.2.3 goal ...................................................................... 98
6.2.4 lab_force ............................................................ 100
6.2.5 no_factor............................................................ 101
6.2.6 no_latch ............................................................. 102
Warp User’s Guide
Contents
6.2.7 node_num.......................................................... 104
6.2.8 opt_level ............................................................ 105
6.2.9 order_code......................................................... 106
6.2.10 part_name........................................................ 107
6.2.11 pin_avoid ......................................................... 108
6.2.12 pin_numbers .................................................... 110
6.2.13 polarity ............................................................. 112
6.2.14 state_encoding ................................................ 113
6.2.15 sum_split.......................................................... 115
6.2.16 synthesis_off.................................................... 116
6.2.17 slew_rate ......................................................... 117
6.2.18 low_power........................................................ 118
6.3 Control File (VHDL Users) .......................................... 120
6.4 Control File (Verilog Users) ......................................... 122
6.5 Warp Synthesis Directives with ViewDraw (Warp3 VHDL)124
6.5.1 Warp Synthesis Directives................................. 124
6.5.2 Supported ViewDraw Attributes......................... 125
6.6 Synthesis Directive Format Summary ......................... 126
Chapter 7
LPM................................................................................... 129
7.1 Introduction ................................................................. 130
7.2 LPM Modules .............................................................. 132
7.2.1 MCNSTNT ......................................................... 132
7.2.2 MINV.................................................................. 133
7.2.3 MAND ................................................................ 134
7.2.4 MOR .................................................................. 136
7.2.5 MXOR ................................................................ 138
7.2.6 MBUSTRI........................................................... 140
7.2.7 MMUX................................................................ 142
7.2.8 MDECODE ........................................................ 144
7.2.9 MCLSHIFT......................................................... 146
7.2.10 MADD_SUB..................................................... 148
7.2.11 MCOMPARE.................................................... 150
7.2.12 MMULT ............................................................ 152
xii
Warp User’s Guide
Contents
7.2.13 MABS............................................................... 154
7.2.14 MCOUNTER .................................................... 155
7.2.15 MLATCH .......................................................... 158
7.2.16 MFF ................................................................. 160
7.2.17 MSHFTREG..................................................... 163
7.3 Other Cypress Modules .............................................. 166
7.3.1 MPARITY........................................................... 166
7.3.2 MBUF................................................................. 167
7.3.3 MGND................................................................ 168
7.3.4 MVCC ................................................................ 169
7.3.5 IN ....................................................................... 170
7.3.6 OUT ................................................................... 171
7.3.7 TRI ..................................................................... 172
7.4 Cypress Exceptions to LPM Standard ........................ 173
7.4.1 Which Options of LPM Do We Support? ........... 173
7.5 Hints and Techniques ................................................. 174
7.5.1 How to Best Use the LPM_HINT ....................... 174
7.5.2 MADD_SUB....................................................... 175
7.5.3 MCOUNTER ...................................................... 176
Chapter 8
Simulation........................................................................ 177
8.1 VHDL Simulation ......................................................... 178
8.1.1 VHDL Pre-synthesis Simulation......................... 179
8.1.2 Simulators.......................................................... 180
8.1.2.1 ModelT V-System
180
8.1.2.2 SpeedWave ............................................. 180
8.1.2.3 Other Simulators ..................................... 182
8.1.3 VHDL Post-synthesis Simulation ....................... 183
8.1.3.1 TestBenches and Post-Synthesis Simulation 183
8.1.3.2 Post-synthesis Simulation of PLDs and CPLDs
185
8.1.4 Post-synthesis Simulators ................................. 187
8.1.4.1 ViewSim
187
8.1.4.2 ModelT V-System .................................... 187
8.1.4.3 SpeedWave ............................................. 188
Warp User’s Guide
Contents
8.1.4.4 Other Simulators ..................................... 189
8.2 Verilog Simulation ....................................................... 190
8.2.1 Verilog Pre-synthesis Simulation ....................... 190
8.2.2 Verilog Post-synthesis Simulation ..................... 191
8.2.2.1 Test Benches and Post-Synthesis Simulation 191
8.2.2.2 Post-synthesis Simulation of PLDs and CPLDs
194
8.2.2.3 Select a Design and a Simulator ............. 195
8.2.2.4 Compile a Design .................................... 195
8.2.3 Post-synthesis Simulators ................................. 196
8.2.3.1 Verilog-XL
197
8.2.3.2 VeriBest ................................................... 197
8.2.3.3 VCS ......................................................... 197
8.2.3.4 Model T ................................................... 198
Chapter 9
Report File ....................................................................... 199
9.1 Introduction ................................................................. 200
9.2 Front End Compiler ..................................................... 200
9.2.1 VHDL Front End ................................................ 200
9.2.2 Verilog Front End............................................... 201
9.3 Front End Synthesis and Optimization ........................ 203
9.4 CPLD/PLD Fitting........................................................ 205
9.4.1 Technology Mapping and Optimization ............. 205
9.4.2 Equations........................................................... 206
9.4.3 Fitting ................................................................. 209
9.4.4 Static Timing Analysis........................................ 213
Chapter 10
Device Programming ...................................................... 215
10.1 Device Programming................................................. 216
10.2 Generating a JEDEC File.......................................... 216
10.3 Generating POF Files for MAX340 CPLDs ............... 219
10.4 Device Programmers ................................................ 219
xiv
Warp User’s Guide
Contents
Appendix A
Error Messages .............................................................. 221
Appendix B
FLASH370/U LTRA 37000 Node Numbers...................... 249
Appendix C
Glossary........................................................................... 261
Warp User’s Guide
Contents
xvi
Warp User’s Guide
Chapter
Introduction
1
1
Introduction
1
1.1
Overview of Warp
The Warp™ synthesis compiler is a state-of-the-art VHDL compiler for designing with
PLDs and CPLDs. Warp accepts either VHDL or Verilog text input (mixing VHDL and
Verilog in the same design is currently not supported in Warp), and then synthesizes and
optimizes the design for the target hardware. Warp then outputs a JEDEC map for
programming PLDs and CPLDs, as shown in Figure 1-1.
The JEDEC map that Warp produces when targeting PLDs and CPLDs can be used to
program parts with a device programmer.
ViewDraw
schematic
capture
Text Editor
VHDL
Export VHDL
Warp
synthesis
compiler
JEDEC
Map
Program
Device
Simulate
Figure 1-1 Tool flow for VHDL Warp (Warp2, Warp2Sim, Warp3).
2
Warp Reference Manual
Introduction
1
Text Editor
Verilog
Warp
synthesis
compiler
JEDEC
Map
Program
Device
Simulate
Figure 1-2 Tool flow for Verilog Warp (Warp2, Warp2Sim).
Warp Reference Manual
3
Introduction
1
1.2
VHDL Warp Capabilities
Warp utilizes a VHDL subset geared for synthesis of designs for programmable logic.
Some highlights of Warp:
4
•
VHDL is an open, non-proprietary language, and a de facto standard for
describing electronic systems. It is mandated for use by the DOD and supported
by every major CAE vendor.
•
VHDL allows designers to describe designs at different levels of abstraction.
Designs can be entered as descriptions of behavior (high level of abstraction), as
state tables and Boolean entry descriptions (intermediate level), or at gate level
(low level of abstraction).
•
Warp supports the IEEE1164 standard which allows the user to specify threestated logic and don’t care logic directly in his behavioral VHDL.
•
Warp supports numerous data types, including enumerated types, integer types,
user-defined type, and others.
•
Warp supports the for... generate loop construct for structural
descriptions, providing a powerful, efficient facility for describing replication in
low-level designs.
•
Warp incorporates state-of-the-art optimization and reduction algorithms,
including automatic selection of optimal flip-flop type (D- type/T- type).
•
Warp includes Cypress’ UltraGen™ module generation technology which
automatically identifies complex datapath operators in VHDL code and replaces
them with a speed or area optimized module specific for the target device.
•
While users can specify the signal-to-pin mapping for their designs, Warp can
also map signals from the designs to pins on the target device automatically,
making it easy to retarget designs from one device to another.
•
Warp can automatically assign state encoding (e.g. gray code, one-hot, binary)
for efficient use of device resources.
•
Warp supports all Cypress PLD and CPLD families, including the Ultra37000™,
FLASH370 ™ and MAX340 ™ (compatible with the MAX5000™) series
families.
•
Warp supports simulation output for many third party simulators including
VHDL and Verilog®.
•
Warp3 supports schematic and VHDL libraries based on the Library of
Parameterized Modules (LPM), to provide easy integration with third party EDA
tools.
•
Warp has a sophisticated GUI with an interactive editor for easy compiling and
VHDL library maintenance.
Warp Reference Manual
Introduction
1.3
Verilog Warp Capabilities
1
Warp utilizes a Verilog subset geared for synthesis of designs for programmable logic.
Some highlights of Warp:
•
Verilog is an open standard for describing electronic systems. It is supported by
every major CAE vendor.
•
Verilog allows designers to describe designs at different levels of abstraction.
Designs can be entered as descriptions of behavior (high level of abstraction), as
state tables and Boolean entry descriptions (intermediate level), or at gate level
(low level of abstraction).
•
Warp supports the IEEE 1364-1995 Verilog standard.
•
Warp incorporates state-of-the-art optimization and reduction algorithms,
including automatic selection of optimal flip-flop type (D- type/T- type).
•
Warp includes Cypress’ UltraGen™ module generation technology which
automatically identifies complex datapath operators in Verilog code and replaces
them with a speed or area optimized module specific for the target device.
•
While users can specify the signal-to-pin mapping for their designs, Warp can
also map signals from the designs to pins on the target device automatically,
making it easy to retarget designs from one device to another.
•
Warp can automatically assign state encoding (e.g. gray code, one-hot, binary)
for efficient use of device resources.
•
Warp supports all Cypress PLD and CPLD families, including the Ultra37000™,
FLASH370 ™ and MAX340 ™ (compatible with the MAX5000™) series
families.
•
Warp supports simulation output for many third party simulators including
VHDL and Verilog®.
•
Warp3 supports Verilog libraries based on the Library of Parameterized Modules
(LPM), to provide easy integration with third party EDA tools.
•
Warp has a sophisticated GUI with an interactive editor for easy compiling and
Verilog library maintenance.
Warp Reference Manual
5
Introduction
1
1.4
About this User’s Guide
This section describes the contents of the remainder of this manual.
Chapter 2 of the manual describes the command line interface, including:
•
Warp command line switches
•
recommendations for synthesizing into CPLD devices
Chapter 3 describes Schematic Entry with Workview Office:
Chapter 4 describes Schematic Entry with Powerview:
Chapter 5 describes Synthesis:
Chapter 6 describes the use of synthesis directives including:
•
format of the Control file (.ctl)
•
description and syntax of supported .ctl file directives and attributes
•
supported ViewDraw® attributes
Chapter 7 provides a reference to the Library of Parameterized Modules (LPM) as
implemented in Warp including:
•
the LPM specification as supported by Warp in ViewDraw and VHDL
•
non-LPM symbols included in Warp
•
LPM specifications not supported by Warp
•
Area vs. speed guidelines for LPM implementations
Chapter 8 describes Simulation with Warp.
Chapter 9 gives a description of messages found in the report file (.rpt) to aid in
understanding the results of Warp synthesis.
Chapter 10 describes device programming with Warp.
Appendix A provides a numerical listing of Warp error messages.
Appendix B provides node number information for the FLASH370 ™ devices.
Appendix C is a glossary of Warp/VHDL terminology.
6
Warp Reference Manual
Chapter
Command Line
Language
2
2
Command Line Language
2.1
2.1.1
Warp Command Line Switches
Warp Command Syntax
On Unix workstations, run Warp by typing the warp command from a shell window. On
IBM PCs and compatibles running Windows, run Warp by typing the warp command in
the Command Line box in response to the File->Run menu item in the File Manager.
This chapter documents the warp command and its options.
warp
[filename]
[-d device]
[-b filename]
[-a[library] filename [filename...]]
[-e#]
[-f {d | t | o}]
[-f {p | k}]
[-ff]
[-fh]
[-fl]
[-fn]
[-fub]
[-fu {h | l | z}]
[-h]
[-m]
[-l[library]]
[-o {0 | 1 | 2}]
[-p package-name]
[-q]
[-r[library] filename]
[-s[library] path]
[-t[top]]
[-v#]
[-verilog]
[-w#]
[-xor2]
[-yl]
[-yg {a | s | c}]
[-yh]
[-yp]
[-yv#]
[-yu]
[-ys0]
2
[-yw]
8
Warp User’s Guide
Command Line Language
[ ] indicates optional arguments.
{ } indicates a selection (one of the choices must be selected).
| indicates a choice.
# implies a numeric (integer) argument of an option.
The warp command runs the Warp synthesis compiler.
Typing warp with no arguments brings up a help screen showing the available options for
the warp command. This is the same as typing warp -h.
Typing warp followed by the name of a file compiles the named file and, if compilation is
successful, synthesizes the design. This is equivalent to using the -b command line switch.
All options listed are case-insensitive; however, filenames may be case-sensitive
depending on the host platform.
2.2
Warp Command Options
Numerous options control the execution of the warp command from the command line.
This section documents Warp’s command line options.
The warp command options used most frequently are -d, -b, and -a. These three options
are described first, followed by the remaining options in alphabetical order.
Note that when using the Warp command line interface on a Sun workstation, the
command and its options are case-sensitive. On an IBM PC or compatible computer, they
are not.
2.2.1
The -d Option
The -d option specifies a target device for synthesis. If this option is not included on the
command line, Warp chooses a target device in the following order:
•
It searches for a part_name attribute in the file being synthesized and targets the
device specified by that attribute.
•
If no part_name attribute is found, then it searches for an architecture that
identifies a device as a top-level entity and targets that device.
•
If no such architecture is found, then it uses the last device targeted by a previous
Warp run from the same directory.
•
Otherwise, an error is returned.
Warp User’s Guide
9
2
Command Line Language
Example:
warp -d c371 myfile.vhd
This example targets a CY7C371, compiling and synthesizing the source file myfile.vhd.
Allowable arguments for the -d option consist of the letter c followed by a part identifier,
usually consisting of the three rightmost digits of the part’s name (for example, c335,
c371, etc.). Notable exceptions to this rule are the arguments c22v10 and c22vp10,
which target a PAL22V10 and PAL22VP10, respectively.
Each time the -d option is used in a warp command, it creates a subdirectory within the
current directory in which compilation results are stored, if such a subdirectory does not
already exist. The name of this subdirectory consists of the letters lc followed by the part
identifier used in the argument to the -d option (for example, an argument of c371 creates
an lc371 subdirectory). This subdirectory becomes the work library for that Warp run.
2
In addition, the -d option causes Warp to look for a library in a subdirectory of the warp
directory (default: c:\warp). This subdirectory is named \lib\lcdevice-name. This library
has the same root name as the -d option’s argument, followed by the extension .vhd (for
example, the path to the c22v10 library is c:\warp\lib\c22v10 \c22v10.vhd).
When Warp interprets the -d option on the command line, Warp creates a subdirectory for
the specified device if one does not already exist within the current directory, compiles the
appropriate library file(s) for the device within the new sub-directory, assigns the path of
the new subdirectory to the “work” logical name, and writes or revises the warp.rc file (if
necessary) to reflect the new path to the work library.
2.2.2
The -b Option
The -b option specifies the VHDL source file to compile. All packages referenced within
the file, via the USE clause, are also compiled. If compilation is successful, this option
also causes Warp to synthesize the design, producing a .jed file.
The -b option assumes that the file to be compiled has an extension of .vhd, unless a
different extension is specified on the command line.
The -b option is implied if a filename is included on the command line and no other option
is present.
Example:
warp myfile.vhd
This command compiles a file named myfile.vhd. If compilation is successful, the file is
synthesized, producing the appropriate output file.
10
Warp User’s Guide
Command Line Language
2.2.3
The -a Option
The -a option analyzes one or more files and adds them to the work library or to a
different, user-specified library. To specify a library other than work, follow the -a option
immediately (without an intervening space) with the name of the library.
The -a option assumes that the file to be compiled has an extension of .vhd, unless a
different extension is specified on the command line.
Examples:
warp -a file1 file2 -b myfile.vhd
This command compiles two files named file1.vhd and file2.vhd and adds them to the
work library. If those two files compile successfully, Warp compiles myfile.vhd. If
compilation is successful, myfile.vhd is synthesized, producing the appropriate output file.
warp -amylib file1 file2 -b myfile.vhd
This command is identical to the previous, except that results from the compilation of
file1.vhd and file2.vhd are written into a subdirectory called mylib.
For more information about libraries and their use, refer to Chapter 1, VHDL.
2.2.4
The -e Option
The -e option specifies the maximum number of non-fatal errors that can occur on a single
Warp run before Warp exits.
Example:
warp -e5 -b myfile.vhd
2.2.5
The -f Option
The -f option enables certain global fitter options. -f must be followed (without an
intervening space) by one of the arguments d, t ,o, f, h, n, k, u or p. (Multiple uses of the f option are allowed on a single line.) Arguments d, t, and o are mutually exclusive.
Arguments k and p are also mutually exclusive. The meanings of these arguments are as
follows:
•
-fd forces registered equations to a D-type registered form (forces use of D-type
flip-flops). For some devices, this may result in a non-minimal solution for an
output register. This is the default if the -f option is not specified.
Related VHDL attribute: ff_type
Warp User’s Guide
11
2
Command Line Language
•
-ft forces the use of T-type flip-flops for registered equations. For some devices,
this may result in a non-minimal solution for an output register. If the target PLD
does not support a physical T-type flip-flop, the equation is converted to a D-type
registered form using the formula D = T XOR Q. Use of this option may lead to
fitter errors if the target device cannot support either a physical T-type flip-flop
or product-term programmable XOR function.
Related VHDL attribute: ff_type
•
2
-fo tells the fitter to optimize the Warp-generated design for either D-type or Ttype flip-flops, whichever produces the smaller equation set. If the target PLD
does not support a physical T-type flip-flop, the equation is converted to a D-type
registered form using the formula
D = T XOR Q.
Related VHDL attribute: ff_type
•
-ff tells the fitter to ignore any user-specified pin assignments and assign pins
itself.
Note – In the -ff option, Warp always assigns pins itself, overriding any
pin assignments made in the source file (for example, by the use of the
pin_numbers attribute or the control file).
•
-fh writes out the JEDEC output file for PLD or CPLD devices in hexadecimal
format. This can effect a considerable (quadruple) savings in storage space for
JEDEC files but may have some programmer ramifications.
•
-fk forces the fitter to preserve the user specified polarity for all outputs. This is
the opposite of the -fp option which optimizes for the optimal polarity. The -fk
option is not recommended for most designs but is useful in certain cases when
the user is able to determine the proper polarity for all the signals, such as when
board design considerations require a certain polarity.
Related VHDL attribute: polarity
12
•
-fl allows the fitter to perform three-level logic factoring instead of the normal
two-level (sum of products) factoring.
•
-fn affects all devices and causes any fixed-node-numbers/fixed-flip-flops found
in the design to be ignored. This is similar to the -ff option which affects only
pins.
•
-fp logically reduces output signals via Espresso during the optimization process.
This option selects the output polarity that produces the minimum number of
Warp User’s Guide
Command Line Language
product terms. This is the opposite of the -fk option.
Related VHDL attribute: polarity
Note – The -ff and -f p arguments can be used in conjunction with the
-fd, -fo, or -ft arguments (for example, -fo -ff -fp).
Example:
warp -b myfile.vhd -fo -ff -fp
2
This command compiles and synthesizes a file named myfile.vhd.
During synthesis, Warp is directed to optimize the design to use either
D- or T-type flip-flops (-fo), ignore any pin assignments in the file (-ff),
and optimize output polarity (-fp).
2.2.6
•
The -fuh, -ful and -fuz options cause unused I/Os of the devices to be
programmed to either drive a high (-fuh) or low (-ful) value or simply three-state
(-fuz) it. In Release 3.5, the PLD and CPLD I/Os were automatically threestated. With these options, the user can now control the exact behavior of such
unused I/Os. For certain devices where the macrocell portion of the cell is used
but the I/O is left unused (a buried node), the -fuh and the -ful options simply
connect the output-enable signal to logic level one causing the I/O pin to see the
state of the buried macrocell. This means that the I/Os associated with the buried
nodes switch as the buried nodes switch. For I/O cells that are connected to
unused macrocells, the macrocell is programmed to drive the value specified by
this option.
•
The -fub option is intended to be used in conjunction with the -fuh and the -ful
options. When this option is used along with the -fuh and the -ful options, the I/
Os related to the buried nodes are three-stated, and the -fuh and -ful options
affect only the I/Os associated with unused macrocells.
The -h Option
The -h (“help”) option lists the available options, their syntax, and meanings. Executing
warp with this option is the same as executing warp with no command line options.
Example:
warp -h
This command prints the warp command’s available options, syntax, and meanings.
Warp User’s Guide
13
Command Line Language
2.2.7
The -l Option
The -l option lists the contents of the work library (default) or any user-specified library.
To specify a library other than work, follow the -l option immediately (without an
intervening space) by the name of the library. The listing of library contents includes the
type and name of each design unit and the name of the file in which the unit is found.
Examples:
warp -l
This command lists the contents of the work library.
warp -lmylib
2
This command lists the contents of library mylib.
2.2.8
The -m Option
This option, which can be used in conjunction with the -a and -b options, enables a smart
compile of the specified VHDL files. Generally, without this option, Warp compiles all the
specified files. When this option is specified, Warp compiles only those files that have
been modified since the last compile. Library files (the ones specified with the -a option)
are recompiled if they have been modified since the last compile, if this is the first time
one or more of these files have been modified, or if any of the lower level files have been
modified. The top level file is dependent on the target device. In a PLD or CPLD device,
the top level file depends on the JEDEC (.jed) file. The top level file also depends on the
control (.ctl) file. Warp stores this dependency information in the warp.mk file in the
current directory.
14
Warp User’s Guide
Command Line Language
2.2.9
The -o Option
The -o option specifies the level of optimization to perform on the design. The -o option
should be followed by a number which indicates the effort.
•
An argument of 0 provides no minimization. In fact, an effort is made to preserve
the equation as-is if the design contained equations in a sum-of-products form.
This option is recommended only when the whole design has been handoptimized.
•
An argument of 1 provides a fast but inefficient optimization of the design. This
option may produce equations of lower quality; it also disables several high level
syntheses of structures such as latches, multiplexers, XORs and design
optimization algorithms such as logic factoring and state machine minimization.
•
An argument of 2 provides maximum optimization. This option invokes the
industry standard Espresso logic minimizer resulting in the most thorough
optimization possible. In addition to performing a better equation optimization,
this option enables many other technologies which cause the design to use fewer
device resources. This option is highly recommended for all designs.
Related VHDL attribute: opt_level
Example:
warp -d c381a -fl -o2 myfile.vhd
The command compiles and synthesizes a file named myfile.vhd, enabling the highest
level of optimization available.
2.2.10
The -p Option
The -p option specifies the device package and speed bin to use when synthesizing a
design for a target device. This option affects the specific pin numbers that are being
specified in the VHDL source code or the control file. This option also determines the
device timing characteristics for PLD and CPLD devices to be used when generating
timing models and timing reports. Valid package and speed bin combinations can be found
in the “Ordering Code” column of the ordering information table for each device in the
Cypress Semiconductor Programmable Logic Data Book.
Example:
warp -d c371 -p CY7C371-143JC -b myfile.vhd
This command compiles and synthesizes the design called myfile.vhd into a CY7C371143 in a JC package. This means that any user specified pin numbers must correspond to
the pin numbers on a JC package of a CY7C371.
Warp User’s Guide
15
2
Command Line Language
2.2.11
The -q Option
The -q (“quiet”) option suppresses the printing of status messages during compilation.
This leads to a less cluttered screen when compilation and synthesis are finished. This is
the default when running Warp via the Galaxy graphical user interface.
Example:
warp -q myfile.vhd
This command compiles and synthesizes a file named myfile.vhd, quietly.
2
2.2.12
The -r Option
The -r option removes design units contained in one or more files from the work library or
from a user-specified library. To specify a library other than work, follow the -r option
immediately (without an intervening space) by the name of the library.
Examples:
warp -r file1.vhd
This command removes the design units contained in file file1.vhd from the work library.
warp -rmylib file1.vhd
This command removes the design units contained in file file1.vhd from library mylib.
2.2.13
The -s Option
The -s option pairs a library name with a path. The name of the library and its path are
written into the warp.rc file in the current directory. To use a library other than work with
a VHDL description, follow the -s option immediately (without an intervening space)
with the name of the library.
Example:
warp -smylib c:\usr\myname\mydir
This command pairs the library name mylib with the path c:\usr\myname\mydir.
2.2.14
The -t Option
When a design file has more than one entity (VHDL) or module (Verilog), the -t option is
used to specify the top-level entity/module.
Example:
warp -ttop-unit
16
Warp User’s Guide
Command Line Language
This command makes the entity/module top-unit as the top-level entity/module.
2.2.15
The -verilog Option
The -verilog option invokes the Verilog version of Warp.
Example:
warp -verilog -d c371 myfile.v
2.2.16
The -v Option
The -v option controls a very important aspect of Warp synthesis. After synthesis, Warp
performs a task called virtual substitution. For a more detailed explanation of virtual
substitution, refer to Chapter 6, Synthesis Directives. The -v option has a numeric
argument that controls the aggressiveness of the virtual substitution algorithm. The range
of numbers allowed is 0 to 11, where a value of 0 does not perform any virtual
substitution (for compatibility with previous releases) and a value of 11 performs virtual
substitution even against the better judgement of the algorithm to isolate large
combinatorial nodes and force it to a node in the device. The higher the number, the fewer
nodes are created. Typically, for CPLD devices, a high number is a good choice because
these devices tend to have macrocells capable of handling large equations. This option can
be viewed as a cost threshold which, when crossed, forces a device node.
The default value for this option is 10. The example below sets the node creation
threshold at 5.
Example:
warp -v5 -o2 -fl1 -d c384a -b myfile.vhd
2.2.17
The -w Option
The -w option specifies the maximum number of warnings that can appear as a result of a
single Warp run before Warp quits.
Example:
warp -w5 -b myfile.vhd
2.2.18
The -xor2 Option
Warp User’s Guide
17
2
Command Line Language
The -xor2 option passes along any XOR operators found in the design to the fitter for
PLD or CPLD devices. If this option is disabled, any XOR operators contained within the
design are flattened, and it would be up to the fitter to detect the XOR contained within the
equation. For most devices, an XOR is not available in the target architecture, in which
case the XOR must eventually be expanded. For CPLD devices which provide an XOR
(MAX340 family), the XOR usage is very specific. This option is not recommended
because with the -o2 option, the software can decide the best implementation for the set of
equations. This option is global to the design and affects XOR operators found in all
portions of the design (such as library architectures and lower level user design files).
2
Example:
warp -d c382a -xor2 myfile.vhd
2.2.19
The -yl Option
By default (if -o2 is used), Warp synthesizes latches for the FLASH370 family; however,
sometimes this is not desirable if global resources are limited or if synthesizing latches
could potentially affect the partitioning of designs into the device. The -yl option disables
latch synthesis.
2.2.20
The -ygs Option
This option causes Warp to synthesize all datapath operators found in the design so that
they are optimized for speed.
Related synthesis directive attribute: goal
2.2.21
The -yga Option
This option causes Warp to synthesize all datapath operators found in the design so that
they are optimized for area.
Related synthesis directive attribute: goal
2.2.22
The -ygc Option
This option causes Warp to synthesize all datapath operators found in the design so that
they are optimized for neither area nor speed but rather implemented as simple
combinatorial equations. If a simple combinatorial equation is not available, an area
efficient one is selected. If an area one is not available, then a speed implementation is
selected. Every datapath operator has at least one implementation available.
Related synthesis directive attribute: goal
18
Warp User’s Guide
Command Line Language
2.2.23
The -yh Option
This option is applicable to the Ultra37000 family. This option causes Warp to disable the
bushold feature.
2.2.24
The -yv Option
This option controls the amount of information that is reported in the report file. The -yv
option should be followed by a digit. The default is 0. Numbers higher than zero produce
more verbose report files useful for debugging. By default (with a value of 0), the report
file only indicates major events during synthesis.
2.2.25
The -yu Option
This option causes the Warp compiler to synthesize the top level sorts of the design
differently. Normally, Warp converts all types to wires. This implies that arrays are
exploded into individual bits. Enabling this option will cause Warp to preserve the vectors
in their original form. This behavior makes simulating with test-benches easier. Refer to
the Simulation Chapter in the User’s Guide
Warp User’s Guide
19
2
Command Line Language
2.2.26
The -ys0 Option
This option disables the sensitivity list checking performed by Warp during synthesis.
This option has been provided for compatibility with pre 4.2 software. By using this
option, one can disable sensitivity list checking.
2
Note – Having a proper sensitivity list is very important if the pre-synthesis simulation results are expected to match post-synthesis simulation
results. All sensitivity list violations are treated as Warnings. In future
releases, such violations will be treated as Errors.
2.2.27
The -yp Option
This option forces all the logic blocks in the Ultra37000 devices to low power mode. In
the low power mode, logic blocks consume 50% less power and slow down by 5 ns.
Related synthesis directive attribute: low_power
2.2.28
The -yw Option
This option sets as the default slew rate for Ultra37000 devices to slow. If this option is not
used, the default slew rate for the Ultra37000 devices is fast. In the fast slew rate mode,
the outputs switch at 3V/ns max. In the slow slew rate mode, the outputs switch at 1V/ns
max. There is a 2-ns delay for I/Os using the slow slew rate mode.
Related synthesis directive attribute: slew_rate
2.2.29
The -yi33 Option
This option is applicable to Ultra37000 and Flash370i devices. When this option is used, it
is equivalent to tying the VCCO pins of the corresponding device to 3.3 volts. The default
value of VCCO is 5.0V. When a lower (3.3V) VCCO is used, the device outputs slow
down by a certain amount, as specified in the datasheets. The fitter and the post-JEDEC
simulation models generate accurate timing information according to the option selected.
20
Warp User’s Guide
Command Line Language
2.3
Recommendations
Most options described in this section are useful in certain circumstances. For designs
targeting CPLD and PLDs, Cypress recommends the following command line:
Example:
warp device -o2 -fo -fp filename
2.4
Warp Output
A Warp run produces numerous output files, of which the following are important to the
user: .jed files for targeting PLDs or CPLDs, and .rpt files for analyzing compilation
results.
A successful Warp run produces two output files in the current directory:
•
filename.jed
•
filename.rpt
The .jed file is a fuse map that a PLD programmer can use.
The .rpt file is an ASCII text file that contains fitter statistics; informational, warning, and
error messages from the Warp run; and pinout information for the synthesized design.
Warp User’s Guide
21
2
Command Line Language
2
22
Warp User’s Guide
Chapter
3
Schematic Entry with
Workview Office
3
Schematic Entry with Workview Office
3.1
Overview
This chapter is for Warp3 VHDL users on the Windows 95 and Windows NT platforms
only.
The Warp tools use VHDL as the primary design entry mechanism. Warp3, however,
also supports schematic entry as a design entry mechanism via the Workview Office,
using ViewDraw. Warp3 also supports mixed-mode design entry where portions of the
design are entered in VHDL and portions are entered in ViewDraw, graphically.
When using ViewDraw, Warp3 provides a very powerful and sophisticated user interface
that allows users to capture designs efficiently. With Warp3, the user can:
3
•
use VHDL descriptions, schematics, or both to describe any design
•
compile and synthesize the resulting design description
•
fit the resulting logic circuits into a particular PLD or CPLD (the resulting files may be
used for programming the device)
•
verify the design with a timing simulator
There are several other tasks that can be performed, but this overview describes how to
use ViewDraw for design entry. Figure 8-1 shows this process flow.
24
Warp User’s Guide
Schematic Entry with Workview Office
VHDL
Schematics
Warp
3
VHDL Compiler
Viewsim
Simulation
Im
lse
pu
3
Device Programmer
Figure 3-1 Warp3 design flow
3.2
3.2.1
LPM Library
What Is LPM?
LPM is an acronym for Library of Parameterized Modules. This is a specification
maintained by the Electronics Industries Association (EIA). The LPM specification
contains a small set of highly parameterizable library elements. This specification is based
on the EDIF (Electronic Design Interchange Format) version 2.0.1 standard and also
specifies how data containing these parameterized modules can be interchanged between
third party CAE systems.
Cypress has chosen the LPM standard for its schematic library because of its flexibility
and interoperability. Warp3 provides a graphical user interface to allow design entry with
these LPM elements. With this graphical interface, the user can create, modify and
manage LPM elements. To obtain a detailed description of the library and its
functionality, refer to the LPM chapter in the Warp Reference manual.
The rest of this chapter assumes that the user is familiar with Workview Office and
Warp User’s Guide
25
Schematic Entry with Workview Office
ViewDraw.
3.2.2
How to Use LPM
LPM is a set of parameterized elements where the number and width of the pins can be
varied. The ViewDraw schematic capture system does not allow the pins for a given
symbol block to vary, so Warp automatically and dynamically creates and maintains
custom symbols that are pre-programmed for a specific use.
For example, there is a common interface for an LPM_COUNTER. With this interface,
the user can select or deselect many options such as enable, carry-in, or load. Instead of
creating a symbol that has all possible pins for a given symbol, Warp automatically
creates a custom symbol that has only those features required by the user. This is done
because some of the LPM elements have a rather large number of optional features, and
without a mechanism to create dynamic symbols, design entry with such symbols would
be cumbersome.
3
When the user requests an LPM symbol configured in a certain way, Warp creates this
element and stores it in a special library called lpmlocal. The lpmlocal library consists of
a set of symbols and data files that manage all the symbols in a user’s private library. The
names assigned to these dynamically created symbols are meaningful only to the software
and do not imply anything about the symbol itself. The lpmlocal library should never be
edited by users manually. Warp automatically creates and manages this information.
26
Warp User’s Guide
Schematic Entry with Workview Office
3.2.3
Getting Started
Before elements can be added or modified, a project needs to be open, LPM initialized,
and ViewDraw started.
=> Click on the Start button. From the Warp R4 menu, select Warp Toolbar. This
starts the Project Manager.
=> Click on the Initialize LPM Library
button from the Warp toolbar. This
starts the initialize LPM Wizard to guide you through the process.
There are two basic processes: creating an initial project or creating a project when at
least one other project already exists.
1.
Creating an initial project. If there are no existing projects, the wizard displays a note
to that effect.
=> Click on the Create button. The resulting dialog box is illustrated in Figure 3-2.
Figure 3-2 Create project wizard dialog box
=> Enter the Project name (w2tutor in this example).
Warp User’s Guide
27
3
Schematic Entry with Workview Office
=> Enter the location of the project files (c:\w2tutor in this example).
=> Enter the Primary project directory (c:\w2tutor in this example).
=> Click Next to continue.
=> The wizard displays the configured LPM Libraries. You can change them if
needed. Click Next to continue.
=> The wizard configures Viewdraw. Click Finish to continue.
=> If the directories do not exist, the wizard prompts you whether to create them.
Click Yes to finish.
3
2.
If a project exists, the last open project information is displayed. To create a new
project:
=> Click on the Change button.
=> Enter the Project name (w2tutor in this example).
=> Enter the location of the project files (c:\w2tutor in this example).
=> Enter the Primary project directory (c:\w2tutor in this example).
=> Click Next to continue.
=> The wizard displays the configured LPM Libraries. You can change them if
needed. Click Next to continue.
=> The wizard configures Viewdraw. Click Finish to continue.
=> If the directories do not exist, the wizard prompts you whether to create them.
Click Yes to finish.
ViewDraw is started. The ViewDraw interface is illustrated in Figure 3-4.
28
Warp User’s Guide
Schematic Entry with Workview Office
3
Figure 3-3 Select a Viewlogic project
Warp User’s Guide
29
Schematic Entry with Workview Office
3
Figure 3-4 ViewDraw interface
3.2.4
Adding an LPM Element
To create an LPM element, click on the Add LPM icon
or button on the Warp
toolbar. When this menu item is selected, The Add LPM Symbol dialog box is displayed.
Click on the type of module to be instantiated.
30
Warp User’s Guide
Schematic Entry with Workview Office
3
Figure 3-5 Add LPM Symbol
A setup dialog box is displayed for the selected symbol. All of the options available for the
selected module can be modified and applied to the symbol. Figure 3-6 illustrates the set
up dialog box for Mcounter.
Figure 3-6 Mcounter dialog box
3.2.5
1.
Select the appropriate options in the dialog box.
2.
Click on the Accept or OK button when complete.
3.
Position the symbol within the schematic. Use the mouse to move the symbol to
the desired location in the schematic.
Changing an LPM Element
Warp User’s Guide
31
Schematic Entry with Workview Office
To change an existing LPM symbol in the schematic:
3
32
1.
Click on the symbol to select it. Only one symbol can be selected for
modification.
2.
Click on the Change LPM Symbol icon
or button on the Warp toolbar. This
brings up the appropriate set up dialog box for the selected symbol. It is the same
dialog box that was used to create the symbol.
3.
Change the desired options. Click OK or Accept to apply the changes to the
symbol and close the dialog box. Cancel can be used to exit the dialog box
without applying any changes.
Warp User’s Guide
Schematic Entry with Workview Office
3.2.6
Creating/Modifying a Non-LPM Element
A non-LPM element is essentially a user or library symbol which does not constitute a
parameterized symbol. Instances of these elements are created using the regular
ViewDraw methods.
Note – This method should not be used to edit or create instances of
LPM symbols. Other than this restriction, an LPM symbol is similar to
any other symbol within ViewDraw.
To create an non-LPM symbol, select Add->Component from the ViewDraw menu. To
modify a non-LPM symbol:
1.
Click on the symbol to select it.
2.
Click the right mouse button to access an options menu. This menu changes
depending upon the item selected.
3.
Select Properties from the menu.
4.
Modify the properties as needed.
Warp User’s Guide
33
3
Schematic Entry with Workview Office
3.3
Exporting the Schematic
Prior to exporting the schematic, it must be saved and verified. Use the File -> Save &
Check menu item from ViewDraw. Resolve any errors and re-save until the schematic is
correct.
Once the schematic is verified and saved, the design can be converted into VHDL and
compiled into a PLD or CPLD device. Click on the Export VHDL icon
or button to
access the Export VHDL dialog box illustrated in Figure 3-7.
3
Figure 3-7 Export VHDL dialog box
In this dialog box, Design Name is simply the name of the schematic being netlisted and
Output Directory is the directory in which the netlist should be created. Leaving the
Output Directory blank creates the netlist in the current project directory.
At this time, the user can also choose the type of netlist to be produced by the netlister.
Currently, two types are supported: bit and std_logic. In VHDL, each signal has a type
associated with it. This option simply allows a choice between these two different types.
The bit type is supported only for compatibility with the previous release. The std_logic
type is recommended for all new designs.
Click OK to perform the following actions:
•
Check and Save the current schematic if it is not already saved.
•
Invoke the batch program hi1076 to perform the actual netlisting.
•
Netlist any synthesis directives found in the design.
The output file name has the same name as the top level design with a .vhd extension. This
file also contains a hierarchical netlist for all the lower level blocks. Once this file is
created, the design is ready to be synthesized using the Warp compiler.
34
Warp User’s Guide
Schematic Entry with Workview Office
3.4
Schematic to Symbol
In Warp3, a symbol can be generated for a schematic circuit. The resulting symbol can
then be instantiated in other, higher-level schematics. To generate a symbol from the
schematic:
1.
Save the schematic.
2.
Click on the Schematic to Symbol icon
3.
Reorder the inputs and outputs for the same on the Schematic to Symbol dialog
box.
4.
Once the pin ordering is complete, click on OK to create the symbol.
or button on the Warp toolbar.
Figure 3-8 Schematic To Symbol dialog box
Note – A new symbol cannot be generated if the symbol is already
loaded into ViewDraw. To work around this problem, simply close all
other ViewDraw windows or re-renter ViewDraw and only load the
schematic for which the symbol is needed.
Warp User’s Guide
35
3
Schematic Entry with Workview Office
3.5
VHDL To Symbol
This utility is useful for designing in a bottom-up fashion, in which the user starts at the
lowest level (being VHDL) and works up to a top-level graphical schematic.
The VHDL To Symbol
utility can be invoked by clicking on the VHDL to Symbol
icon or button on the Warp toolbar. Enter the name of the VHDL file (without the .vhd
extension). The VHDL To Symbol translator requires that the VHDL file be first compiled
using Galaxy as a non top-level file. Refer to the Galaxy chapter in this manual for details.
3
Figure 3-9 VHDL to Symbol dialog box.
When this utility is invoked, a list of the available VHDL components is displayed. If the
list does not include all of the components you were expecting, check the .vhdl file for
syntax errors. Select the components to be generated. The order of the pins for each of the
symbols is determined by the order they were listed in the VHDL file. VHDL components
must be defined within a package.
Note – A new symbol cannot be generated if the symbol is already
loaded into ViewDraw. To work around this problem, close all other
ViewDraw windows or re-renter ViewDraw and only load the
schematic for which the symbol is needed.
3.6
Symbol to VHDL
The Symbol to VHDL
utility translates a ViewDraw symbol to a VHDL file. The
VHDL file has the same name as the symbol, except with a .vhd extension. The symbol
name should be a VHDL legal name. The VHDL entity name is the same as the symbol
name.
36
Warp User’s Guide
Schematic Entry with Workview Office
3.7
Update Library
CAUTION – This utility should be used to rebuild a library that has
been destroyed, lost or must be synchronizied when transporting
schematics.
The lpmlocal library contains symbols that are sequentially named as the user requests
new LPM symbols. It is highly likely that two different users using different lpmlocal
libraries can have like-named LPM symbols with totally different feature sets. Or,
symbols may exist in one library but not another.
Sharing or transporting of user schematics would therefore be impossible. To solve this
problem, Warp provides a synchronization utility.
To perform the synchronization:
3.8
1.
Back up your schematic and the lpmlocal libraries.
2.
Click on the Update LPM Symbols icon
or button on the Warp toolbar to
access the utility. The current library is replaced with the symbols from the
current schematic. All hierarchy conflicts are resolved when the symbols are
regenerated.
3.
Verify the updated library to ensure it is correct.
Display Hierarchy
The Display Hierarchy icon
or button prints the hierarchy for a schematic. The
hierarchy information is also saved in a .hir file in the project directory. This information
is helpful to view a schematic’s organization when the schematic contains many lower
level schematics or modules.
Note – This utility cannot analyze the hierarchy of VHDL modules.
Warp User’s Guide
37
3
Schematic Entry with Workview Office
3
38
Warp User’s Guide
Chapter
4
Schematic Entry with
Powerview
4
Schematic Entry with Powerview
4.1
Overview
This chapter is for Warp3 users on the UNIX and Windows 3.1 environments only.
Window 95 and Windows NT users should refer to Chapter 3, Schematic Entry with
Workview Office
The Warp tools use VHDL as the primary design entry mechanism. Warp3, however,
also supports schematic entry as a design entry mechanism via ViewDraw. Warp3 also
supports mixed-mode design entry where portions of the design are entered in VHDL and
portions are entered in ViewDraw, graphically.
When using ViewDraw, Warp3 provides a very powerful and sophisticated user interface
that allows users to capture designs efficiently. With Warp3, the user can:
•
Use VHDL descriptions, schematics, or both to describe any design
•
Compile and synthesize the resulting design description
•
Fit the resulting logic circuits into a particular PLD or CPLD (the resulting files may
be used for programming the device)
• Verify the design with a timing simulator
There are several other tasks that can be performed, but this overview describes how to
use ViewDraw for design entry. Figure 4-1 shows this process flow.
4
40
Warp User’s Guide
Schematic Entry with Powerview
VHDL
Schematics
Warp
VHDL Compiler
Viewsim
Simulation
Im
lse
pu
3
4
Device Programmer
Figure 4-1 Warp3 design flow
Warp User’s Guide
41
Schematic Entry with Powerview
4.2
4.2.1
LPM Library
What Is LPM?
LPM is an acronym for Library of Parameterized Modules. This is a specification
maintained by the Electronics Industries Association (EIA). The LPM specification
contains a small set of highly parametrizable library elements. This specification is based
on the EDIF (Electronic Design Interchange Format) version 2.0.0 standard and also
specifies how data containing these parameterized modules can be interchanged between
third party CAE systems.
Cypress has chosen the LPM standard for its schematic library because of its flexibility
and interoperability. Warp3 provides a graphical user interface to allow design entry with
these LPM elements. With this graphical interface, the user can create, modify and
manage LPM elements. To obtain a detailed description of the library and its
functionality, the user should refer to LPM Chapter of the Warp Reference Manual.
The rest of this chapter assumes that the user is familiar with ViewDraw and the
Powerview or Workview PLUS environment.
4
4.2.2
How to Use LPM
Since LPM is a set of parameterized elements where the number and width of the pins can
be varied, and the ViewDraw schematic capture system does not allow the pins for a given
symbol block to vary, Warp automatically and dynamically creates and maintains custom
symbols that are pre-programmed for a specific use.
For example, there is a common interface for an LPM_COUNTER. With this interface,
the user can select or deselect many options such as enable, carry-in, or load. Instead of
creating a symbol that has all possible pins for a given symbol, Warp automatically
creates a custom symbol that has only those features required by the user. This is done
because some of the LPM elements have a rather large number of optional features, and
without a mechanism to create dynamic symbols, design entry with such symbols would
be cumbersome.
When the user requests an LPM symbol configured in a certain way, Warp creates this
element and stores it in a special library called lpmlocal. The lpmlocal library consists of
a set of symbols and data files that manage all the symbols in a user’s private library. The
names assigned to these dynamically created symbols are meaningful only to the software
and do not imply anything about the symbol itself. The lpmlocal library should never be
edited by users manually. Warp automatically creates and manages this information.
42
Warp User’s Guide
Schematic Entry with Powerview
ViewDraw uses the viewdraw.ini file to locate libraries. ViewDraw searches the current
project directory as well as the directories listed in the WDIR environment variable for
this initialization file. This file contains, among other things, a set of library names and the
directories where these libraries can be found. A sample viewdraw.ini file is shipped with
Warp and can be found in the warpstd subdirectory where Warp is installed. A portion of
this file is shown here:
| Format: DIR [DirType(s)] DirPath (LibName)
|
|
DirType:
p or pw - primary / writable
|
w
- writable (read/write)
|
r
- read-only
|
m or rm - read-only megafile
|
|
DirPath:
directory specification
|
|
LibName:
library name aka library alias or VHDL library
|
name (optional) 32 characters or less.
Must begin with a letters
DIR [p] .
DIR [r] c:\warp\lib\sheet (sheet)
DIR [r] c:\warp\lib\io (io)
DIR [r] c:\warp\lib\mcparts (mcparts)
DIR [r] c:\warp\lib\prim (primitive)
Lines starting with the “|” character are comments. The first directory below the
comments is the current project directory, and the rest of the directories are libraries. To
this list of libraries, another library must be added that represents the lpmlocal library.
This library must be writable by the user because Warp creates symbols dynamically on
behalf of the user. An example of such a library would be:
DIR [w] c:\mydir\myproj\lpmlocal (lpmlocal)
where c:\mydir\myproj\lpmlocal is a directory where Warp stores the symbols it creates.
Without a valid location for the lpmlocal library, the Warp LPM functionality will be
disabled. If this directory is being shared by other users in a network environment, this
directory must be writable by everyone using this library. The viewdraw.ini file should
be copied to the current project directory, and then this change should be made to the file.
Warp User’s Guide
43
4
Schematic Entry with Powerview
4.2.3
Creating the lpmlocal Library
When ViewDraw is invoked for the first time in a new Viewlogic project, the LPM
functionality is disabled and step-by-step instructions are printed on how to enable the
LPM functionality and the creation of the lpmlocal library.
4.2.4
Creating an LPM Element
To create an LPM element once ViewDraw has been opened for editing a schematic, use
the menu item Add->LPM Symbol.
4
Figure 4-2 Add LPM Symbol
44
Warp User’s Guide
Schematic Entry with Powerview
When this menu item is selected, ViewDraw prompts the user for the type of module to be
instantiated. This dialog box, titled Add Cell, is shown in Figure 4-3:
Figure 4-3 Add Cell dialog box
The user selects the desired module by single clicking the left mouse button. This action
results in another dialog box that prompts the user to enter all the options that are
applicable for the module selected. For example, if the Mcounter module was selected, the
following dialog box would pop up:
Figure 4-4 Mcounter dialog box
After selecting the appropriate items in this dialog box, a single mouse click on the Accept
button removes this dialog box. At this point, the custom symbol that Warp has
dynamically created is attached to the cursor and is ready to be placed in the schematic.
Warp User’s Guide
45
4
Schematic Entry with Powerview
4.2.5
Modifying an LPM Element
If the user wishes to modify an LPM symbol already placed in the schematic, he should
first select the LPM symbol to be modified and then choose the
Change->LPM Symbol menu item. Only one LPM symbol may be selected at a time.
When this menu item is selected, Warp displays the appropriate dialog box for the given
LPM symbol, identical to the dialog box that was used during the initial creation of the
LPM symbol.
4.2.6
Creating/Modifying a Non-LPM Element
A non-LPM element is essentially a user or library symbol which does not constitute a
parameterized symbol. Instances of these elements are created using the regular
ViewDraw methods. The Add->Comp menu item is used to create an instance of a nonLPM symbol, and the Change->Comp menu item should be used to change an existing
instance. These menu items should not be used to edit or create instances of LPM
symbols. Other than this restriction, an LPM symbol is similar to any other symbol within
ViewDraw.
4
46
Warp User’s Guide
Schematic Entry with Powerview
4.3
Exporting the Schematic
Once the schematic has been completed, the design can be converted into VHDL and
compiled into a PLD device. This can be accomplished by using the menu item Cypress>Export VHDL:
4
Figure 4-5 Export VHDL menu selection
Warp User’s Guide
47
Schematic Entry with Powerview
When this option is selected, the following dialog box pops up:
Figure 4-6 Export VHDL dialog box
In this dialog box, Design Name is simply the name of the schematic being netlisted and
Output Directory is the directory in which the netlist should be created. Leaving the
Output Directory blank will create the netlist in the current project directory.
4
At this time, the user can also choose the type of netlist to be produced by the netlister.
Currently, two types are supported: bit and std_logic. In VHDL, each signal has a type
associated with it. This option simply allows a choice between these two different types.
The bit type is supported only for compatibility with the previous release. The std_logic
type is recommended for all new designs.
Clicking the left mouse button on the button marked Accept will cause the following
actions:
•
Check and Save the current schematic if it is not already saved.
•
Invoke the batch program hi1076 to perform the actual netlisting.
• Netlist any synthesis directives found in the design.
The output file name has the same name as the top level design with a .vhd extension. This
file also contains a hierarchical netlist for all the lower level blocks. Once this file is
created, the design is ready to be synthesized using the Warp compiler.
48
Warp User’s Guide
Schematic Entry with Powerview
4.4
Back-Annotation
Once a design has been successfully placed into a device, Warp allows the user to fix the
pinout for that design.
To back-annotate pin-numbers into the design schematic, the user must select the menu
item Cypress->Back-Annotation....
4
Figure 4-7 Back-Annotation menu selection
A simple dialog box appears showing the design name to be back-annotated. Clicking on
OK does the following:
•
Invokes a batch program that queries the pinout results and creates a list of pin names
and their associated pin-numbers.
•
Edits the current schematic (and all its associated sheets) to place the # attribute, so
that future VHDL netlisting will force the pins to be placed in the same location.
The buses are back-annotated in a special way. Buses require that multiple pin-numbers
must be back-annotated. This is accomplished by creating an attribute with a “,” (comma)
separated list of pin-numbers.
Note – Back-annotation will have no effect if the design has not been
successfully fit or placed and routed into a device.
Warp User’s Guide
49
Schematic Entry with Powerview
4.5
Schematic to Symbol
In Warp3, the user can use the Schematic to Symbol found in the Cypress menu to
generate a symbol for a schematic circuit. The resulting symbol can then be instantiated in
other, higher-level schematics.
When Schematic to Symbol is run, a dialog box allows the inputs and the outputs of the
symbol to be reordered. Once the ordering of the pins is satisfied, clicking on Accept will
create the symbol.
4
Figure 4-8 Schematic To Symbol dialog box
Note – A new symbol cannot be generated if the symbol is already
loaded into ViewDraw. To work around this problem, simply close all
other ViewDraw windows or re-renter ViewDraw and only load the
schematic for which the symbol is needed.
50
Warp User’s Guide
Schematic Entry with Powerview
4.6
VHDL To Symbol
The VHDL To Symbol utility can be invoked in ViewDraw under the Cypress menu bar.
This utility differs from the Viewlogic VHDL2sym tool, which can be found in the Circuit
Design drawer. The Cypress version of the VHDL To Symbol translator requires that the
VHDL file be first compiled using Galaxy as a non top- level file.
When this utility is invoked, a list of VHDL components for which symbols can be
generated is displayed so that the user can select exactly which symbols need to be
generated. If errors have been detected for symbols, the dialog box for VHDL To Symbol
allows viewing these errors. The order of the pins for each of the symbols is determined by
the order in which they were listed in the VHDL file. Please note that these VHDL
components must be defined within a package.
This utility is useful for designing in a bottom-up fashion, in which the user starts at the
lowest level (being VHDL) and works up to a top-level graphical schematic.
Note – A new symbol cannot be generated if the symbol is already
loaded into ViewDraw. To work around this problem, simply close all
other ViewDraw windows or re-renter ViewDraw and only load the
schematic for which the symbol is needed.
4
To run VHDL To Symbol, invoke the VHDL To Symbol and enter the name of the VHDL
file (without the .vhd) extension.
4.7
Symbol to VHDL
Symbol to VHDL takes as input the name of a symbol, and translates a ViewDraw symbol
into a VHDL file. The VHDL file has the same name as the symbol, except with a .vhd
extension. This implies that the symbol name should be a VHDL legal name. The VHDL
entity name is the same as the symbol name.
Figure 4-9 Symbol to VHDL dialog box
Warp User’s Guide
51
Schematic Entry with Powerview
4.8
Update Library
CAUTION – This utility should be used to rebuild a library that has
been destroyed, lost or must be synchronizied when transporting
schematics.
The lpmlocal library contains symbols that are sequentially named as the user requests
new LPM symbols. It is highly likely that two different users using different lpmlocal
libraries can have like-named LPM symbols with totally different feature sets. Or,
symbols may exist in one library but not another.
Sharing or transporting of user schematics would therefore be impossible. To solve this
problem, Warp provides a synchronization utility.
To perform the synchronization:
4
1.
Back up your schematic and the lpmlocal libraries.
2.
Select the Cypress->Update LPM Symbols to access the utility. The current library is
replaced with the symbols from the current schematic. All hierarchy conflicts are
resolved when the symbols are regenerated.
Figure 4-10 Cypress Update LPM Symbols
52
Warp User’s Guide
Schematic Entry with Powerview
4.9
Display Hierarchy
The Display Hierarchy menu item prints the hierarchy for a schematic. The hierarchy
information is also saved in a .hir file in the project directory. This information is helpful
to view a schematic’s organization when the schematic contains many lower level
schematics or modules.
Note – This utility cannot analyze the hierarchy of VHDL modules.
4
Warp User’s Guide
53
Schematic Entry with Powerview
4
54
Warp User’s Guide
Chapter
Synthesis
5
5
Synthesis
5
5.1
Synthesis Directives
This chapter introduces synthesis directives, what they are, what they are used for, how to
and when to use them. This chapter is organized into five sections. The first section is an
introduction. It explains directives and discusses a strategy for using them effectively. It
also includes two design examples. The second section describes those directives that can
be used to optimize a design for the fewest device resources. The third section describes
those directives that can be used to optimize a design for timing goals, including operating
frequency, clock to output delay, setup time, and combinatorial propagation delays. The
fourth section describes directives used for controlling the type and location of specific
resources used in a device. The final section describes directives used for documentation,
including part selection and pin number assignment. For a summary of the synthesis
directive formats, see Section 6.6 Synthesis Directive Format Summary
5.1.1
Understanding Synthesis Directives
Synthesis directives may be used to influence the implementation of a design. They are
used in an iterative fashion to refine, improve, or constrain the results of synthesis. For
example, the goal directive is used by the synthesizer to select either area-efficient or
speed-efficient design implementations. Synthesis directives may be applied to
components that have been either instantiated in a schematic or inferred by the synthesizer
from VHDL/Verilog HDL code. Synthesis_off creates a factoring point for logic
equations and is used for area or speed optimization (or both). The pin_numbers directive
specifies the pin numbers to be used for signals. These and other directives are discussed
in this chapter. The next section discusses a strategy for designing with synthesis
directives.
5.1.2
Design Flow and Strategy for Using Directives
Directives are a powerful mechanism to influence the synthesis process, but they should
be used judiciously. Careless or excessive use of directives can, in fact, subvert the very
design goals that are sought. This section describes a strategy for using directives and
choosing the appropriate one(s) to achieve the user’s goals.
Until the user becomes familiar with the effects of using the different directives, Cypress
does not recommend applying any of them in the first iteration of a design. After synthesis
and fitting the design may fit in the desired device and meet timing goals. In this case, the
design is complete—no directives are necessary. If, however, after the initial iteration of
synthesis and fitting, the design does not fit or meet timing goals, the design may need
tuning. Tuning, illustrated in Figure 9-1, is the process of (1) identifying and applying an
appropriate directive that may help to reduce resource utilization or realize timing targets,
(2) resynthesizing and fitting the design, and (3) verifying that the design meets area and
56
Warp User’s Guide
Synthesis
speed goals. In some cases, this tuning process may have to be repeated in order to
compare multiple implementations of the design.
Warp User’s Guide
5
57
Synthesis
5
Figure 5-1 Tuning
58
Warp User’s Guide
Synthesis
5.1.3
Available Directives
Table 5-1 can be used to select an appropriate directive for tuning a design. Those
directives listed first are most likely to have the greatest impact on a design
implementation and should be selected first when tuning. The other directives are used in
special cases or for documentation purposes. Device selection and pin number assignment
are included in the documentation category, although they are also functional directives
that can have a significant impact on area and speed. Later in this chapter, each of the
directives listed in the table is explained in greater detail, with the focus on understanding
scenarios when using a particular directive is appropriate. The syntax and effect of all
directives is explained in the Synthesis Directives Chapter 6.
For each directive listed in Table 5-1, the “Used for...” column indicates whether the
directive can be used for area optimization, speed optimization, specific control, or
documentation. The next section describes how to apply directives.
Table 5-1 Available Synthesis Directives
Used for...
Directive
area
speed
goal
x
x
state_encoding
x
x
synthesis_off
x
x
x
dont_touch
x
x
x
no_latch
x
x
x
lab_force
control
doc.
x
low_power
X
pin_avoid
x
polarity
x
sum_split
x
node_num
x
ff_type
x
opt_level
x
x
part_name
x
x
x
order_code
x
x
x
Warp User’s Guide
x
59
5
Synthesis
Table 5-1 Available Synthesis Directives
5
Used for...
Directive
pin_numbers
area
speed
x
x
slew_rate
5.1.4
control
doc.
x
x
VHDL Synthesis Directives
5.1.4.1
Scope and Inheritance
Each of the synthesis directives has a scope: some are intended for signals, others for
components. Some of the directives also have an inheritance. A directive intended for a
signal can be placed on an architecture or entity so that all signals defined in that
architecture or entity inherit that directive. This is called hierarchical inheritance. Not all
directives have an inheritance. Non-hierarchical directives are meant for the exact object
that they are attached to and will be ignored if not applied to the appropriate object.
Hierarchical directives have the following order of precedence (from least to greatest):
•
entity
•
architecture
•
component declarations
•
component instantiations
•
signals
Thus, a hierarchical directive placed on an architecture is overridden by a directive placed
on a signal within that architecture. In other words, a hierarchical directive intended for a
signal, if placed on an architecture, serves as a default for all signals within that
architecture. Likewise, a hierarchical directive placed on a component instantiation
overrides a directive placed on an architecture. This allows for an occurrence of a
component to have a different value than the default directive for all components.
5.1.4.2
Applying Directives
Some directives are available via the command line or Galaxy switches. Warp also
provides three other methods for applying synthesis directives: with VHDL attributes,
with schematic attributes, or with a top-level control file. Values of directives passed
through the GUI or the command line act as default values. Directives applied using
VHDL attributes, schematic attributes, or the control file override default values. The only
60
Warp User’s Guide
Synthesis
exceptions are the part_name and order_code directives. The GUI or command line,
discussed below, will override all part_name and order_code attributes.
Using the GUI or command line. Certain directives may be controlled from the GUI or
command line. An example of this is the goal attribute which can be selected to provide
area or speed optimization. If speed is selected, then it becomes the default value.
However, if a component has a VHDL or schematic goal attribute applied to it, and the
value of the attribute is area, then the speed value is overridden with the area value for that
component.
Using VHDL attributes. VHDL permits the use of user-defined attributes to adorn
objects with information. Warp has thus created a user-defined (as opposed to pre-defined)
attribute for each directive. This permits a directive to be applied to an object with the use
of an attribute. The general syntax of an attribute used to place a directive on a signal is of
the form:
attribute directive_name of object:class is value;
Such attributes are placed in the appropriate declarative region of the VHDL code,
typically in either the entity declarative region or the architecture body declarative region.
The object is the actual name or identifier of the entity, architecture, component
instantiation label, or signal. Class is used to identify the class of the object (i.e., entity,
architecture, or component instantiation label, or signal).
Examples of applying directives using attributes are given below. Next is a discussion of
the application of directives with schematic attributes and a top-level control file.
Using schematic attributes. Directives may be applied to objects in schematics (with
Warp3) using attributes by selecting the appropriate object and choosing Attribute from
the Add menu. After selecting Add->Attribute, a dialog box appears in which the user may
enter the directive in the form:
directive_name=value
The goal directive for area or speed optimization is not applied as an attribute. It is selecte
during the addition or modification of an LPM symbol. The directive selected here
overrides the command line or GUI switch.
Using a control file. A top level control file may also be used to specify synthesis
directives. In the case of conflict, directives placed in a control file override directives
specified with VHDL or schematic attributes. The format of the control file is defined in
Chapter 6, Synthesis Directiveschapter of the Warp Reference Manual. Each directive
may be applied in the control file using a syntax similar to that of attributes:
attribute directive_name [of] object[:class] is value[;]
The words in square brackets [ ] are optional and are simply ignored. Specifying the class
is also optional.
Warp User’s Guide
61
5
Synthesis
The section 5.2 illustrates how to apply directives in a design by using the tuning strategy
shown previously. The sections 5.2.1 and 5.2.2 demonstrate the tuning using two
examples. These design examples were compiled using a pre-release version of the Warp
software. Your results may vary slightly from those presented here, but the general
concepts remain true.
5
5.1.5
Verilog Synthesis Directives
5.1.5.1
Scope and Inheritance
Each of the synthesis directives has a scope: some are intended for signals, others for
components. Some of the directives also have an inheritance. A directive intended for a
signal can be placed on a module so that all signals defined in that module inherit that
directive. This is called hierarchical inheritance. Not all directives have an inheritance,
however. Non-hierarchical directives are meant for the exact object that they are attached
to and will be ignored if not applied to the appropriate object.
Hierarchical directives have the following order of precedence (from least to greatest):
•
entity
•
component instantiations
•
signals
Thus, a hierarchical directive placed on a module is overridden by a directive placed on a
signal within that module. In other words, a hierarchical directive intended for a signal, if
placed on a module, serves as a default for all signals within that module. Likewise, a
hierarchical directive placed on a component instantiation overrides a directive placed on
a module. This allows for an occurrence of a component to have a different value than the
default directive for all components.
5.1.5.2
Applying Directives
Some directives are available via the command line or Galaxy switches. Warp also
provides three other method for applying synthesis directives: with a top-level control file.
Values of directives passed through the GUI or the command line act as default values.
Directives applied using the control file override default values. The only exceptions are
the part_name and order_code directives. The GUI or command line, discussed below,
will override all part_name and order_code attributes.
Using the GUI or command line. Certain directives may be controlled from the GUI or
command line. An example of this is the goal attribute which can be selected to provide
area or speed optimization. If speed is selected, then it becomes the default value.
62
Warp User’s Guide
Synthesis
However, if a component has a VHDL or schematic goal attribute applied to it, and the
value of the attribute is area, then the speed value is overridden with the area value for that
component.
Using a control file. A top level control file may also be used to specify synthesis
directives. The format of the control file is defined in Chapter 6, Synthesis Directives.
Each directive may be applied in the control file using a syntax similar to that of attributes:
attribute directive_name [of] object[:class] is value[;]
The words in square brackets [ ] are optional and are simply ignored. Specifying the class
is also optional.
Section 5.3 illustrates how to apply directives in a design by using the tuning strategy
shown previously. The design example in section 5.3.1 demonstrates tuning. The design
example is compiled using a pre-release version of the Warp software. Your results may
vary slightly from those presented here, but the general concepts remain the same.
Warp User’s Guide
63
5
Synthesis
5
5.2
5.2.1
VHDL Synthesis
Example 1—DRAM Controller
The code of the following listing is used to describe a fictitious DRAM controller.
Understanding the details of the code is not necessary for comprehending the subsequent
design optimization strategy.
library ieee;
use ieee.std_logic_1164.all;
entity example is port(
clk, rst, ads, burst:in std_logic;
address:
in std_logic_vector(31 downto 0);
cas, ras, ack, ref: buffer std_logic;
row_col_address:out std_logic_vector(11 downto 0));
end example;
use work.std_arith.all;
architecture controller of example is
type states is (idle, asdet, rasa, casa, w1, w2, w3,
nocas, refad, wr1, wr2);
signal state, next_state: states;
signal match, ref_req:std_logic;
signal count: std_logic_vector(23 downto 0);
signal captured_address: std_logic_vector(31 downto 0);
signal captured_burst:std_logic;
signal col_ad:std_logic_vector(11 downto 0);
signal burst_cnt:std_logic_vector(1 downto 0);
constant re_ad:std_logic_vector(11 downto 0) := (others
=> ‘0’);
alias row_ad: std_logic_vector(11 downto 0) is captured_address(23 downto 12);
begin
-- latch in address, and value of burst
adreg: process (clk, rst)
begin
if rst = ‘1’ then
captured_address <= (others => ‘0’);
captured_burst <= ‘0’;
elsif clk’event and clk= ‘1’ then
if ads = ‘1’ then
64
Warp User’s Guide
Synthesis
captured_address <= address;
captured_burst <= burst;
end if;
end if;
end process;
5
-- check address contents to see if memory access
match <= ‘1’ when captured_address(31 downto 24) =
“00000000” else ‘0’;
-- DRAM address multiplexer
mux: process (state, col_ad, row_ad)
begin
case state is
when refad | wr1 | wr2 =>
row_col_address <= re_ad;
when rasa | casa | w1 | w2 | w3 =>
row_col_address <= col_ad;
when asdet =>
row_col_address <= row_ad ;
when others =>
row_col_address <= (others => ‘-’);
end case;
end process;
-- column address, Intel order
col_ad(11 downto 2) <= captured_address(11 downto 2);
col_ad(1) <= captured_address(1) xor burst_cnt(1);
col_ad(0) <= captured_address(0) xor burst_cnt(0);
-- Burst counter:
bcount: process (clk, rst)
begin
if rst = ‘1’ then
burst_cnt <= “00”;
elsif clk’event and clk = ‘1’ then
if state = idle then
burst_cnt <= “00”;
elsif state = w3 then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end process;
-- DRAM refress request counter
counter: process (clk, rst)
Warp User’s Guide
65
Synthesis
begin
if rst = ‘1’ then
count <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if ref = ‘1’ then
count <= (others => ‘0’);
else
count <= count + 1;
end if;
end if;
end process;
ref_req <= ‘1’ when count = “101010101010101010101000” else ‘0’;
5
-- DRAM state machine
control: process (state, ref_req, match)
begin
case state is
when idle =>
cas <= ‘1’; ras <= ‘1’;
ack <= ‘1’; ref <= ‘0’;
if ref_req = ‘1’ then
next_state <= refad;
elsif ads = ‘1’ then
next_state <= asdet;
end if;
when asdet =>
cas <= ‘1’; ras <= ‘1’;
ack <= ‘1’; ref <= ‘0’;
if match = ‘1’ then
next_state <= rasa;
else
next_state <= idle;
end if;
when rasa =>
cas <= ‘1’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘0’;
next_state <= casa;
when casa =>
cas <= ‘0’; ras <= ‘0’;
66
Warp User’s Guide
Synthesis
ack <= ‘1’; ref <= ‘0’;
5
next_state <= w1;
when w1 =>
cas <= ‘0’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘0’;
next_state <= w2;
when w2 =>
cas <= ‘0’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘0’;
next_state <= w3;
when w3 =>
cas <= ‘0’; ras <= ‘0’;
ack <= ‘0’; ref <= ‘0’;
if (captured_burst = ‘1’ and burst_cnt /= “11”)
then
next_state <= nocas;
else
next_state <= idle;
end if;
when nocas =>
cas <= ‘1’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘0’;
next_state <= casa;
when refad =>
cas <= ‘1’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘1’;
next_state <= wr1;
when wr1 =>
cas <= ‘1’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘0’;
next_state <= wr2;
when wr2 =>
Warp User’s Guide
67
Synthesis
cas <= ‘1’; ras <= ‘0’;
ack <= ‘1’; ref <= ‘0’;
5
next_state <= idle;
end case;
end process;
-- clock state machine
clocked: process (clk, rst)
begin
if rst = ‘1’ then
state <= idle;
elsif clk’event and clk = ‘1’ then
state <= next_state;
end if;
end process;
end controller;
5.2.1.1
First Pass
On this first pass, use the default synthesis and fitting options which yield the results
summarized in Table 5-2.
Table 5-2 First pass CPLD results
First Pass (default)
Macrocells
79
Product terms
225
tS (ns)
6.0
tSCS (ns)
10.0
tCO (ns)
16.0
limiting factor
tCO
This design requires a 128 macrocell member of the FLASH370 family of CPLDs. Not
surprisingly, it has excellent speed. This is because the design is essentially a state
machine, counters, and a little bit of combinational logic.
68
Warp User’s Guide
Synthesis
A tuning cycle will not likely improve upon the speed and area of this CPLD
implementation for two reasons: (1) The area versions of the counters will require just as
many macrocells and product terms as the speed versions. This is because this counter is
implemented very efficiently using T-type flip-flops. (2) Using the state_encoding
attribute with the one_hot_one value will neither increase performance (it is already at its
maximum—one pass through the logic array) nor reduce the number of required
macrocells. In fact, a one-hot implementation will require more macrocells. It may reduce
the number of product terms, but the current implementation uses only 35% of the
available product terms. Gray encoding will require the same number of macrocells, but
could possibly require fewer product terms. So, even though the current implementation is
satisfactory, resynthesize and fit the design using the “gray” value for the state_encoding
directive.
Warp User’s Guide
69
5
Synthesis
5
5.2.1.2
Second Pass -- State Machine Gray Encoding
This pass implements the state_encoding directive with a VHDL attribute placed in the
architecture body declarative region where the state type is declared:
attribute state_encoding of states:type is gray;
Warp reports the following fitter error:
Error: Signal stateSBV_3 uses too many input
signals,(logic+OE+AR+AP).
This error indicates that one of the state bits requires more than the 36 inputs. The
FLASH370 allows only 36 inputs into a given logic block (no other CPLD has more).
Examine the report file to find the equation that verifies the veracity of this error message
and to see what can be done to correct it. The equation is as follows:
/stateSBV_3.D =
/stateSBV_0.Q * /stateSBV_3.Q * /stateSBV_2.Q *
/count_2.Q * /count_1.Q * /count_0.Q * count_5.Q *
/count_4.Q * count_3.Q * /count_8.Q * count_7.Q *
/count_6.Q * count_11.Q * /count_10.Q * count_9.Q *
/count_14.Q * count_13.Q * /count_12.Q *
count_17.Q * /count_16.Q * count_15.Q *
/count_20.Q * count_19.Q * /count_18.Q *
count_23.Q * /count_22.Q * count_21.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_31.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_30.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_29.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_28.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_27.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_26.Q
+ /stateSBV_0.Q * /stateSBV_3.Q * /stateSBV_2.Q *
/ads
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_25.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
captured_address_24.Q
+ /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q
+ /stateSBV_1.Q * stateSBV_2.Q
+ stateSBV_0.Q * stateSBV_2.Q
70
Warp User’s Guide
Synthesis
Here, notice that the equation for this state-bit requires all inputs of the counter. This is
due to the state transition out of the idle state when ref_req is asserted. In addition, notice
that captured_address is required. This is due to the state transitions out of the asdet state
when match is asserted. In the sequential encoding, the third bit of the state vector does
not require all of these inputs: the capture_address inputs are used with a different state
bit. To avoid this problem, this equation must be factored. A natural point to break this
equation is with the captured_address signals or counter signals. The user can create a
factoring point by applying the synthesis_off directive to either the match signal or the
ref_req signal (or both). The next pass will show how to create one with the match signal.
Creating this break-point will require a second pass through the logic array. This will
result in additional delay and require additional resources. Obviously, the implementation
will be inferior to the one achieved in the first pass. Nonetheless, this example will show
how to work around this problem for instructional purposes. After all, it would be nice to
know how to get around a problem like this one, if the user encountered it in the first pass.
It is interesting to note that the state encoding affected the number of terms in an equation.
5.2.1.3
Third Pass -- Synthesis_off
The synthesis_off directive is applied with a VHDL attribute, placed in the architecture
declarative region where the match signal is declared:
attribute synthesis_off of match:signal is true;
The design fits. The report file indicates that gray encoding is used:
State variable 'state' is represented by a Bit_vector
(0 to 3).
State encoding (gray) for 'state' is:
casa :=
"0010";
idle :=
"0000";
asdet := "0001";
rasa :=
"0011";
casa :=
"0010";
w1 :=
"0110";
w2 :=
"0111";
w3 :=
"0101";
nocas := "0100";
refad :=
"1100";
wr1 :=
"1101";
wr2 :=
"1111";
Warp User’s Guide
71
5
Synthesis
The equations also show that match was used as a factoring point:
5
/stateSBV_3.D =
/stateSBV_0.Q * /stateSBV_3.Q * /stateSBV_2.Q *
/count_2.Q * /count_1.Q * /count_0.Q * count_5.Q *
/count_4.Q * count_3.Q * /count_8.Q * count_7.Q *
/count_6.Q * count_11.Q * /count_10.Q * count_9.Q *
/count_14.Q * count_13.Q * /count_12.Q *
count_17.Q * /count_16.Q * count_15.Q *
/count_20.Q * count_19.Q * /count_18.Q *
count_23.Q * /count_22.Q * count_21.Q
+ /stateSBV_0.Q * stateSBV_3.Q * /stateSBV_2.Q *
/match.CMB
+ /stateSBV_0.Q * /stateSBV_3.Q * /stateSBV_2.Q *
/ads
+ /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q
+ /stateSBV_1.Q * stateSBV_2.Q
+ stateSBV_0.Q * stateSBV_2.Q
match =
/captured_address_31.Q * /captured_address_30.Q *
/captured_address_29.Q * /captured_address_27.Q *
/captured_address_26.Q * /captured_address_25.Q *
/captured_address_24.Q * /captured_address_28.Q
The area and speed results are summarized in Table 5-3. This implementation requires
fewer product terms, but has slower performance than the first implementation.
Table 5-3 Third pass CPLD results
72
First Pass
(Defaults)
Second Pass
(Gray Encode)
Third Pass
(Synthesis_off)
Macrocells
79
Fit Error
80
Product terms
225
Fit Error
202
tS (ns)
6.0
Fit Error
6.0
tSCS (ns)
10.0
Fit Error
19.0
tCO (ns)
16.0
Fit Error
16.0
limiting factor
tCO
Fit Error
tSCS
Warp User’s Guide
Synthesis
5.2.2
Example 2—Multiply and Accumulate Function
5
The code of the following listing is a multiply and accumulate design.
library ieee;
use ieee.std_logic_1164.all;
entity math is port (
clk, rst, mac:std_logic;
a, b:in std_logic_vector(7 downto 0);
q: buffer std_logic_vector(15 downto 0));
end math;
use work.std_arith.all;
architecture math of math is
begin
p1: process (rst, clk)
begin
if rst = ‘1’ then
q <= (others => ‘0’);
elsif clk’event and clk=’1’ then
q <= (a * b) + q;
end if;
end process;
end math;
5.2.2.1
First Pass -- Default Options
Once again, the first pass uses the default Galaxy options. This means speed optimization.
With these options, the design will not fit (Table 5-4) because it requires too many
macrocells. It also requires nearly all of the available product terms. So, pursue area
optimization.
Table 5-4 First pass CPLD results
First Pass (Defaults)
Macrocells
132
Product terms
620
tS (ns)
N/A
tSCS (ns)
N/A
tCO (ns)
N/A
limiting factor
Warp User’s Guide
did not fit
73
Synthesis
5
5.2.2.2
Second Pass -- Area Optimization
The results of area optimization are summarized in Table 5-5:
Table 5-5 Second pass CPLD results
First Pass (Defaults)
Second Pass (Area)
Macrocells
132
120
Product terms
620
605
tS (ns)
N/A
87.0
tSCS (ns)
N/A
66.0
tCO (ns)
N/A
7.0
did not fit
tS
limiting factor
The setup time for this combination of operations—multiply and accumulate—is the
limiting factor for the maximum frequency of this design.
5.2.3
Area Optimization
This section describes the directives and techniques required to successfully implement a
logic design with the minimum device resources (minimum area) being utilized. The focus
of this section is to provide recommended techniques for area optimization.
5.2.3.1
The GOAL Directive
attribute goal of architecture_name : architecture is area;
or command line option: -yga
The goal value of area indicates that all modules inferred from VHDL operators will be
optimized for area. The Warp synthesizer will select an implementation that is optimized
to use the minimum device resources. A 16-bit adder example with the goal directive
placed on an architecture is shown below. This code will generate a ripple carry adder with
a 2-bit group as the basic unit. This adder would be implemented as carry-look-ahead if
the goal was set to speed. A comparison of the results after compilation for each goal and
74
Warp User’s Guide
Synthesis
target device type is shown in Table 5-6.
5
Table 5-6 Results of GOAL directives
CPLD
Area Opt.
Speed Opt.
23 macrocells
35 macrocells
8 passes
3 passes
library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity add16_a is port(
a, b:in std_logic_vector (15 downto 0);
sum:out std_logic_vector (15 downto 0));
end add16_a;
architecture archadd16_a of add16_a is
ATTRIBUTE goal OF archadd16_a : ARCHITECTURE IS area;
begin
sum <= a + b;
end;
5.2.3.2
The SYNTHESIS_OFF Directive
ATTRIBUTE synthesis_off OF signal_name : signal IS true;
When the synthesis_off directive is set to true, a signal is made into a factoring point for
logic equations. This directive keeps the signal from being substituted out during the
optimization process. The node number is used to reference a macrocell within a CPLD.
Synthesis_off is useful for the following reasons:
•
It gives the user control over which equations or sub-expressions need to be factored
into a node.
•
It provides better results for designs where a signal with a large functionality is being
used by many other signals. If left alone, the fitter would collapse all the internal
signals (which is desirable in many cases) and may drive the design's resource
requirements beyond the available limits.
•
It helps in cutting down on compile time for designs which have a lot of “signal
redirection” (signals getting inverted or reassigned to other signals). This directive
Warp User’s Guide
75
Synthesis
provides the logic optimizer a better control over the optimization process, by reducing
the number of signals it needs to deal with.
5
By using the synthesis_off directive, the user can assign the commonly used signal to a
node and bring down the resource utilization.
A side effect of using the synthesis_off directive is that the design will now take an extra
pass through the array to achieve the same functionality. The extra pass may be required
anyway, if more than 16 Product Terms are required.
This directive is recommended only on combinatorial signals. Registered signals are
assigned to a node by natural factoring, and the synthesis_off directive on these signals is
redundant.
This directive can be associated with signals declared both in VHDL and schematics. The
BUF component can also be used in schematics and VHDL to achieve the same results as
the synthesis_off directive. Please refer to the Warp Synthesis manual for more details.
This directive allows the designer to force multiple passes through logic cells for optimal
density. The following example uses the synthesis_off directive and uses 30 Macrocells
in a CY7C371. This same design requires 43 Macrocells in a CY7C371 without using the
synthesis_off directive:
library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity cpldadd is port(
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0);
c: in std_logic_vector(7 downto 0);
sum: out std_logic_vector(7 downto 0));
end cpldadd;
architecture areacpldadd of cpldadd is
signal intsum: std_logic_vector(7 downto 0);
attribute synthesis_off of intsum:signal is true;
begin
intsum <= a + b;
sum <= intsum + c;
end areacpldadd;
5.2.3.3
76
The FF_TYPE Directive
Warp User’s Guide
Synthesis
ATTRIBUTE ff_type OF signal_name : signal IS ff_opt;
or command line option: -fo
The ff_type value of ff_opt tells Warp to synthesize the signal_name to the optimum
flip-flop type for the logic implemented. A flip-flop is chosen based on the fewest
resources required to implement the logic function. For instance, a D-type flip-flop may
be chosen for register data storage functions, while a T-type (toggle) flip-flop may be
chosen for counters. This option is recommended for all designs unless the designer has
specific requirements to force the use of a different flip-flop.
5.2.4
Specific Control
This section describes specific control features of the Warp synthesis tool.
5.2.4.1
The FF_TYPE Directive (CPLD Only)
ATTRIBUTE ff_type OF signal_name : signal IS ff_d;
or command line option: -fd
The ff_type value of ff_d tells Warp to synthesize the signal_name using a D-type flipflop. This will force the synthesizer to use a D-type flip-flop to generate signal_name.
This directive will typically only be used if the Warp synthesis tool is not using the D-type
flip-flop where the designer intends.
ATTRIBUTE ff_type OF signal_name : signal IS ff_t;
or command line option: -ft
The ff_type value of ff_t tells Warp to synthesize the signal_name using a T-type flipflop. This will force the synthesizer to use a toggle flip-flop to generate signal_name.
This directive will typically only be used if the Warp synthesis tool is not using a toggle
flip-flop, which the designer intends for functional reasons.
5.2.4.2
The NODE_NUM Directive
ATTRIBUTE node_num OF signal_name : signal IS integer ;
or command line option: -fn [n=node location]
The node_num directive locks a signal to a specific location in the target device. This
directive overrides the default placement that the Warp tool would assign automatically.
This directive applies to any combinatorial or sequential node within the design.
Example:
Warp User’s Guide
77
5
Synthesis
library ieee;
use ieee.std_logic_1164.all;
5
ENTITY node_num_test IS
PORT (clk, ff_D: IN STD_LOGIC; -- Flip-flop clock, D-input
ff_Q : OUT STD_LOGIC); -- Flip-flop Q output
ATTRIBUTE node_num OF ff_Q:SIGNAL IS 398;
END node_num_test;
ARCHITECTURE arch_node_num_test OF node_num_test IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1';
ff_Q <= ff_D; -- Generate output
END PROCESS;
END arch_node_num_test;
The previous code segment ensures the signal ff_Q is generated from the macrocell
driving node 398 in a CY7C374 device. Node 398 refers to buried macrocell A in logic
block #1 in a CY7C374. Refer to the Flash370 appendix in the Warp Reference manual
for specific node numbers. This directive allows the designer to manually place logic to
override the Warp floor planner.
5.2.4.3
The LAB_FORCE Directive (CPLD Only)
ATTRIBUTE lab_force OF signal_name : signal IS “string”;
The lab_force directive aids in grouping signals together as a requirement to the fitter.
The string contains the name of the logic block. This directive will force signal_name to
the string internal logic block without regard for I/O pin assignments. In most designs, the
automatic assignment by the fitter is acceptable. In some cases, the user may want to
constrain the fitter to obtain better partitioning than can be performed automatically. This
directive should only be used if the user is intimately familiar with the target CPLD
architecture. This directive can cause routing difficulties if logic is placed in an area that
can block routing paths.
Examples:
ATTRIBUTE lab_force OF ff_Q:SIGNAL IS “B2”;
This will force the signal ff_Q to the lower half of logic block B in a FLASH370 device. In
the following example:
ATTRIBUTE lab_force OF ff_Q:signal IS “B1”;
78
Warp User’s Guide
Synthesis
The signal ff_Q is forced to the upper half of logic block B.
5.2.4.4
5
The SUM_SPLIT Directive (CPLD Only)
ATTRIBUTE sum_split OF signal_name : signal IS value;
The sum_split value can be balanced or cascaded. The default value is balanced. Use
the balanced value if reliable balanced timing is desired at the expense of area. The
following figure describes the balanced sum split concept:
ATTRIBUTE sum_split OF sum_signal:signal IS balanced;
Split
to 16
18
OR
Result
Split
to 2
Figure E-2 The balanced sum split concept
The cascaded method uses only two macrocells to implement an equation. There is no
control over which product term is assigned to which macrocell. The signals that are not
split into macrocell #1 will arrive at macrocell #2 sooner, thereby making the timing for
the outputs different based on different arrival times. If these output signals are registered,
then of course the timing generated at the outputs are the same.
ATTRIBUTE sum_split OF sum_signal:signal IS cascaded;
Warp User’s Guide
79
Synthesis
5
16
Split
to 16
18
OR
Result
2
Figure E-3 The cascaded sum split
Which sum_split method to use depends on the area constraints and how the design is
implemented. Use the balanced method first and then the cascaded, if the design did not fit
using balanced.
5.2.4.5
The POLARITY Directive (CPLD Only)
ATTRIBUTE polarity OF signal_name : signal IS value;
The polarity directive is used to select polarity for signals in a design. There are two
options for polarity, pl_keep and pl_opt. The pl_keep option will instruct the Warp
compiler to keep the polarity of a signal as currently specified in the design. The pl_keep
option is useful to instruct the compiler about the desirable output sense of a signal at
power up. When a circuit is initialized, it may be desirable to provide an output as a “1” or
“0” and maintain this condition without the compiler changing the sense for optimization
reasons. In another case, it may be desirable to keep signal senses in order to debug
designs in the simulator without being concerned about compiler-induced internal
inversions. In most cases, however, the pl_opt is the best choice. This option allows the
compiler to change the sense of internal signals to provide the best optimization for a
design.
5.2.5
Speed Optimization
This section describes the synthesis directives and techniques that may be used in
optimizing a design for performance. In most cases, the techniques for speed optimization
are device dependent.
80
Warp User’s Guide
Synthesis
5.2.5.1
The GOAL Directive
ATTRIBUTE goal OF architecture_name: architecture IS speed;
The goal value of speed indicates that all arithmetic modules inferred from VHDL
operators will be optimized for speed. The Warp synthesizer will select an implementation
that is optimized to achieve the best performance. This is a good first step to take when
optimizing a design for performance. To demonstrate the goal directive, observe the
performance delta in the following 8-bit adder example implemented in a FLASH370
CPLD:
library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity add8_a is port(
a, b: in std_logic_vector (7 downto 0);
sum: out std_logic_vector (7 downto 0));
end add8_a;
architecture archadd8_a of add8_a is
attribute goal of archadd8_a: architecture is speed;
begin
sum <= a + b;
end;
Results with goal set to area was 57.0 ns (17.5 Mhz) worst case delay.
Results with goal set to speed was 27.0 ns (37 Mhz) worst case delay.
5.2.6
Documentation Directives
5.2.6.1
The PART_NAME Directive
ATTRIBUTE part_name OF entity_name: entity IS “part_name”;
A user may want to specify a particular device so that the original design documents
specify which device it was designed for. This directive will override any target device
command line switch or a Galaxy dialog box setting.
entity counter is port (
a,b: in std_logic;
...
);
attribute part_name of counter: entity is “c371”;
end entity counter;
Warp User’s Guide
81
5
Synthesis
5
5.2.6.2
The ORDER_CODE Directive
ATTRIBUTE order_code OF entity_name: entity IS “order_code”;
A particular package and speed bin of a device can be specified to the Warp synthesis tool
by using the directive order_code within the design to ensure timing information reflects
the speed grade of the desired part. The order codes can be found in the Ordering Code
column of the ordering information table for each device in the Cypress Semiconductor
Programmable Logic Data Book. Timing delays for CPLDs are calculated according to
the speed bin specified by this directive, or if no directive is specified in the VHDL code,
the compiler will use the directive specified in the device window of Galaxy.
entity counter is port (
a,b: in std_logic;
...
);
attribute order_code of counter: entity is “CY7C37166JC”;
end entity counter;
5.2.6.3
The PIN_NUMBERS Directive
ATTRIBUTE pin_numbers OF entity_name: entity IS “string”;
Once a design has been completed and the board is defined, it may be desirable to
maintain the pin out configuration when modifications to the programmable logic design
are made. Locking signals to a particular pin can be accomplished by using the
pin_numbers directive in the design.
entity counter is port (
a,b: in std_logic;
...
);
attribute pin_numbers of counter: entity is “a:6 b:7 ”;
end entity counter;
It is recommended that whenever possible, particularly the first time a design is fitted to a
device, the pins of a device should not be locked. When the pins are not locked, the fitting
tools can choose the optimal fitting arrangement within the device for performance as well
as minimal resource utilization. In some rare occasions, certain pin arrangements can
render a fitting impossible.
Once a design has been fitted to a device (and the tool has already chosen a working pin
configuration), the pin assignments can be back-annotated to the design schematic. The
pin_numbers directive can also be used to set the pins of the design.
82
Warp User’s Guide
Synthesis
5.3
Verilog Synthesis
5.3.1
5
Example —Multiply and Accumulate Function
The code of the following listing is a multiply and accumulate design.
module mac (rst, clk, dataa, datab, prod);
input rst;
input clk;
input [7:0] dataa;
input [7:0] datab;
inout [15:0] prod;
reg [15:0] q;
always @(posedge rst or posedge clk)
begin
if (rst == 1’b 1)
q <= {16{1’b0}};
else
q <= dataa * datab + q;
end
assign prod = q;
endmodule // module mac
5.3.1.1
First Pass -- Default Options
The first pass uses the default Galaxy options. This means speed optimization. With these
options, the design will not fit (Table 5-7) because it requires too many macrocells. It also
requires nearly all of the available product terms. So, pursue area optimization.
Table 5-7 First pass CPLD results
First Pass (Defaults)
Macrocells
132
Product terms
620
Warp User’s Guide
83
Synthesis
Table 5-7 First pass CPLD results
5
tS (ns)
N/A
tSCS (ns)
N/A
tCO (ns)
N/A
limiting factor
5.3.1.2
did not fit
Second Pass -- Area Optimization
The results of area optimization are summarized in Table 5-8:
Table 5-8 Second pass CPLD results
First Pass (Defaults)
Second Pass (Area)
Macrocells
132
120
Product terms
620
605
tS (ns)
N/A
87.0
tSCS (ns)
N/A
66.0
tCO (ns)
N/A
7.0
did not fit
tS
limiting factor
The setup time for this combination of operations—multiply and accumulate—is the
limiting factor for the maximum frequency of this design.
5.3.2
Area Optimization
This section describes the directives and techniques required to successfully implement a
logic design with the minimum device resources (minimum area) being utilized. The focus
of this section is to provide recommended techniques for area optimization.
5.3.2.1
The GOAL Directive
attribute goal of module_name : module is area;
or command line option: -yga
The goal value of area indicates that all modules inferred from VHDL operators will be
84
Warp User’s Guide
Synthesis
optimized for area. The Warp synthesizer will select an implementation that is optimized
to use the minimum device resources. A 16-bit adder example with the goal directive
placed on an architecture is shown below. This code will generate a ripple carry adder with
a 2-bit group as the basic unit. This adder would be implemented as carry-look-ahead if
the goal was set to speed. A comparison of the results after compilation for each goal and
target device type is shown in Table 5-9.
Table 5-9 Results of GOAL directives
CPLD
Area Opt.
Speed Opt.
23 macrocells
35 macrocells
8 passes
3 passes
47.0 ns worst case
delay
19.5 ns worst case
delay
module add2s (dataa, datab, sum);
input [15:0] dataa;
input [15:0] datab;
output [15:0] sum;
assign sum = dataa + datab;
endmodule // module add2s
5.3.2.2
The SYNTHESIS_OFF Directive
ATTRIBUTE synthesis_off OF signal_name : signal IS true;
When the synthesis_off directive is set to true, a signal is made into a factoring point for
logic equations. This directive keeps the signal from being substituted out during the
optimization process. The node number is used to reference a macrocell within a CPLD.
Synthesis_off is useful for the following reasons:
•
It gives the user control over which equations or sub-expressions need to be factored
into a node.
Warp User’s Guide
85
5
Synthesis
5
•
It provides better results for designs where a signal with a large functionality is being
used by many other signals. If left alone, the fitter would collapse all the internal
signals (which is desirable in many cases) and may drive the design's resource
requirements beyond the available limits.
•
It helps in cutting down on compile time for designs which have a lot of “signal
redirection” (signals getting inverted or reassigned to other signals). This directive
provides the logic optimizer a better control over the optimization process, by reducing
the number of signals it needs to deal with.
By using the synthesis_off directive, the user can assign the commonly used signal to a
node and bring down the resource utilization.
A side effect of using the synthesis_off directive is that the design will now take an extra
pass through the array to achieve the same functionality. The extra pass may be required
anyway, if more than 16 PTs are required.
This directive is recommended only on combinatorial signals. Registered signals are
assigned to a node by natural factoring, and the synthesis_off directive on these signals is
redundant.
This directive allows the designer to force multiple passes through logic cells for optimal
density.
5.3.2.3
The FF_TYPE Directive
ATTRIBUTE ff_type OF signal_name : signal IS ff_opt;
or command line option: -fo
The ff_type value of ff_opt tells Warp to synthesize the signal_name to the optimum
flip-flop type for the logic implemented. A flip-flop is chosen based on the fewest
resources required to implement the logic function. For instance, a D-type flip-flop may
be chosen for register data storage functions, while a T-type (toggle) flip-flop may be
chosen for counters. This option is recommended for all designs unless the designer has
specific requirements to force the use of a different flip-flop.
5.3.3
Specific Control
This section describes specific control features of the Warp synthesis tool.
5.3.3.1
The FF_TYPE Directive (CPLD Only)
ATTRIBUTE ff_type OF signal_name : signal IS ff_d;
86
Warp User’s Guide
Synthesis
or command line option: -fd
The ff_type value of ff_d tells Warp to synthesize the signal_name using a D-type flipflop. This will force the synthesizer to use a D-type flip-flop to generate signal_name.
This directive will typically only be used if the Warp synthesis tool is not using the D-type
flip-flop where the designer intends.
ATTRIBUTE ff_type OF signal_name : signal IS ff_t;
or command line option: -ft
The ff_type value of ff_t tells Warp to synthesize the signal_name using a T-type flipflop. This will force the synthesizer to use a toggle flip-flop to generate signal_name.
This directive will typically only be used if the Warp synthesis tool is not using a toggle
flip-flop, which the designer intends for functional reasons.
5.3.3.2
The NODE_NUM Directive
ATTRIBUTE node_num OF signal_name : signal IS integer ;
or command line option: -fn [n=node location]
The node_num directive locks a signal to a specific location in the target device. This
directive overrides the default placement that the Warp tool would assign automatically.
This directive applies to any combinatorial or sequential node within the design.
5.3.3.3
The LAB_FORCE Directive (CPLD Only)
ATTRIBUTE lab_force OF signal_name : signal IS “string”;
The lab_force directive aids in grouping signals together as a requirement to the fitter.
The string contains the name of the logic block. This directive will force signal_name to
the string internal logic block without regard for I/O pin assignments. In most designs, the
automatic assignment by the fitter is acceptable. In some cases, the user may want to
constrain the fitter to obtain better partitioning than can be performed automatically. This
directive should only be used if the user is intimately familiar with the target CPLD
architecture. This directive can cause routing difficulties if logic is placed in an area that
can block routing paths.
Examples:
ATTRIBUTE lab_force OF ff_Q:SIGNAL IS “B2”;
This will force the signal ff_Q to the lower half of logic block B in a FLASH370 device. In
the following example:
Warp User’s Guide
87
5
Synthesis
ATTRIBUTE lab_force OF ff_Q:signal IS “B1”;
5
The signal ff_Q is forced to the upper half of logic block B.
5.3.3.4
The SUM_SPLIT Directive (CPLD Only)
ATTRIBUTE sum_split OF signal_name : signal IS value;
The sum_split value can be balanced or cascaded. The default value is balanced. Use
the balanced value if reliable balanced timing is desired at the expense of area. The
following figure describes the balanced sum split concept:
ATTRIBUTE sum_split OF sum_signal:signal IS balanced;
Split
to 16
18
OR
Result
Split
to 2
Figure E-4 The balanced sum split concept
The cascaded method uses only two macrocells to implement an equation. There is no
control over which product term is assigned to which macrocell. The signals that are not
split into macrocell #1 will arrive at macrocell #2 sooner, thereby making the timing for
the outputs different based on different arrival times. If these output signals are registered,
then of course the timing generated at the outputs are the same.
ATTRIBUTE sum_split OF sum_signal:signal IS cascaded;
88
Warp User’s Guide
Synthesis
5
16
Split
to 16
18
OR
Result
2
Figure E-5 The cascaded sum split
Which sum_split method to use depends on the area constraints and how the design is
implemented. Use the balanced method first and then the cascaded, if the design did not fit
using balanced.
5.3.3.5
The POLARITY Directive (CPLD Only)
ATTRIBUTE polarity OF signal_name : signal IS value;
The polarity directive is used to select polarity for signals in a design. There are two
options for polarity, pl_keep and pl_opt. The pl_keep option will instruct the Warp
compiler to keep the polarity of a signal as currently specified in the design. The pl_keep
option is useful to instruct the compiler about the desirable output sense of a signal at
power up. When a circuit is initialized, it may be desirable to provide an output as a “1” or
“0” and maintain this condition without the compiler changing the sense for optimization
reasons. In another case, it may be desirable to keep signal senses in order to debug
designs in the simulator without being concerned about compiler-induced internal
inversions. In most cases, however, the pl_opt is the best choice. This option allows the
compiler to change the sense of internal signals to provide the best optimization for a
design.
5.3.4
Speed Optimization
This section describes the synthesis directives and techniques that may be used in
optimizing a design for performance. In most cases, the techniques for speed optimization
are device dependent.
Warp User’s Guide
89
Synthesis
5
5.3.4.1
The GOAL Directive
ATTRIBUTE goal OF module_name: module IS speed;
The goal value of speed indicates that all arithmetic modules inferred from Verilog
operators will be optimized for speed. The Warp synthesizer will select an implementation
that is optimized to achieve the best performance. This is a good first step to take when
optimizing a design for performance. To demonstrate the goal directive, observe the
performance data in the 16-bit added example in section 5.3.2.1.
Results with goal set to area was 47.0 ns worst case delay.
Results with goal set to speed was 19.5 ns worst case delay.
90
Warp User’s Guide
Chapter
6
Synthesis Directives
6
Synthesis Directives
6.1
Introduction
VHDL Designs:
In three different ways, synthesis directives supplied to the Warp compiler can control
many aspects of Warp synthesis and post synthesis results. Certain directives have global
defaults which command line options or Galaxy can override. All synthesis directives can
be controlled by inserting these directives directly into the source VHDL design. Most of
the directives can also be set in the control file described in Section 6.3, Control File
(VHDL Users).
Synthesis directives in Warp are specified using the VHDL attribute mechanism. VHDL
allows attributes to be placed on almost any object, but the target application determines
how these attributes are interpreted. Each synthesis directive that Warp supports has a
scope and an inheritance mechanism. Certain synthesis directives are intended for signals,
and others are intended for components. This defines the scope of the attribute. Warp also
supports an inheritance mechanism for many of the synthesis directives. An attribute
intended for a signal, for example, can be placed on an architecture or entity so that all
signals defined in that architecture or entity and any signals defined in any of the lower
level components obtain that attribute. This method of inheritance is called hierarchical.
Other attributes, however, are not hierarchical and are meant for the exact object to which
they are attached.
6
Hierarchical attributes also have a certain precedence. Hierarchical attributes can be
placed on the following types of VHDL objects:
•
entity
•
architecture
•
component declaration
•
component instantiation (component label)
•
signal
Of these objects, the entity has the lowest precedence, and the signal has the highest
precedence. Thus, a synthesis directive placed on an architecture can be overridden by a
particular signal within that architecture. In other words, directives placed on an
architecture serve as a default for all signals derived by that architecture.
92
Warp User’s Guide
Synthesis Directives
For example, consider the directive ff_type. This directive controls the flip-flop type for
architectures that support multiple flip-flop types (the FLASH370 family supports both Dtype and T-type flip-flops). The following example shows how to assign D-type flip-flops
for all signals in the architecture except for a signal called x which uses a T-type flip-flop.
architecture myarch of myentity is
signal x,y,z : std_logic ;
attribute ff_type of myarch:architecture is ff_d ;
attribute ff_type of x:signal is ff_t ;
begin
myproc: process (clk)
begin
if (clk’event AND clk = ‘1’) then
x <= NOT x ;
y <= a ;
z <= d ;
end if ;
end process ;
end myarch ;
In this example, signals y and z are assigned a D-type flip-flop due to the inheritance from
the architecture, and the signal x is assigned a T-type flip-flop because it has a higher
precedence.
This chapter shows the syntax, scope, inheritance, and purpose of each synthesis directive.
Read the Synthesis chapter in the Warp User’s Guide for details on how to best utilize
these directives.
Verilog Designs:
In two different ways, synthesis directives supplied to the Warp compiler can control
many aspects of Warp synthesis and post synthesis results. Certain directives have global
defaults which command line options or Galaxy can override. Most of the directives can
also be set in the control file described in Section 6.4, Control File (Verilog Users).
Synthesis directives in Warp are specified using the VHDL attribute mechanism. Each
synthesis directive that Warp supports has a scope and an inheritance mechanism. Certain
synthesis directives are intended for signals, and others are intended for components. This
defines the scope of the attribute. Warp also supports an inheritance mechanism for many
of the synthesis directives. An attribute intended for a signal, for example, can be placed
on a module so that all signals defined in that module and any signals defined in any of the
lower level components obtain that attribute. This method of inheritance is called
hierarchical. Other attributes, however, are not hierarchical and are meant for the exact
object to which they are attached.
Warp User’s Guide
93
6
Synthesis Directives
Hierarchical attributes also have a certain precedence. Hierarchical attributes can be
placed on the following types of Verilog objects:
•
module
•
component instantiation (component label)
•
signal
Of these objects, the module has the lowest precedence, and the signal has the highest
precedence. Thus, a synthesis directive placed on a module can be overridden by a
particular signal within that module.
6
94
Warp User’s Guide
Synthesis Directives
For example, consider the directive ff_type. This directive controls the flip-flop type for
architectures that support multiple flip-flop types (the FLASH370 family supports both Dtype and T-type flip-flops). The following example shows how to assign D-type flip-flops
for all signals in the architecture except for a signal called x which uses a T-type flip-flop.
Control file:
attribute ff_type of mymodule: module is ff_d ;
attribute ff_type of x:signal is ff_t ;
Verilog Design:
module mymodule (...) ;
....
always @(posedge clk)
begin
x <= NOT x;
y <= a;
z <= d;
end
6
endmodule
In this example, signals y and z are assigned a D-type flip-flop due to the inheritance from
the architecture, and the signal x is assigned a T-type flip-flop because it has a higher
precedence.
This chapter shows the syntax, scope, inheritance, and purpose of each synthesis directive.
For a list of the synthesis directive formats, see Section 6.6 Synthesis Directive Format
Summary. Read the Synthesis chapter 5 for details on how to best utilize these directives.
Warp User’s Guide
95
Synthesis Directives
6.2
6.2.1
Synthesis Directives
enum_encoding
This directive is applicable only for VHDL designs.
The enum_encoding directive specifies the internal encoding to be used for each value of
a user-defined enumerated type. The internal encoding is reflected in the gate-level design
when targeting a device.
attribute enum_encoding of type-name:type is "string";
The enum_encoding directive takes a single argument, consisting of a string of 0s and 1s
separated by white space (spaces or tabs). Each contiguous string of 0s and 1s represents
the encoding for a single value of the enumerated type. The number of contiguous strings
in the enum_encoding argument must equal the number of values in the enumerated
type.
When included in a Warp description, the enum_encoding directive overrides the value
of a state_encoding directive appearing in the same description.
6
Scope:
Target: Type
Inheritance: None
Related Command-Line-Option: None
Applicable to: All Devices
Example:
type state is (s0,s1,s2,s3);
attribute enum_encoding of state:type is "00 01 10 11";
The first statement in this example declares an enumerated type, called state, with four
possible values. The possible values of type state can therefore be represented in two bits.
The second statement specifies the internal representation of each value of type state.
Value s0’s internal representation is "00". Value s1's internal representation is "01". Value
s2’s internal representation is "10". Value s3’s internal representation is "11".
96
Warp User’s Guide
Synthesis Directives
6.2.2
ff_type
This directive is applicable to both VHDL and Verilog designs.
The ff_type directive specifies the flip-flop type used to synthesize individual signals.
attribute ff_type of signal-name:signal is value;
Legal values for the ff_type directive are ff_d, ff_t, ff_opt, and ff_default.
•
A value of ff_d tells Warp to synthesize the signal as a D-type flip-flop.
•
A value of ff_t tells Warp to synthesize the signal as a T-type flip-flop.
•
A value of ff_opt tells Warp to synthesize the signal to the optimum flip-flop type
(i.e., the one that uses the fewest resources on the target device).
•
A value of ff_default tells Warp to synthesize the signal based on the default flip-flop
type selection strategy, which the command line switches or dialog box settings used
in invoking Warp determine.
Scope:
6
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: -fd or -ft or -fo
Applicable to: PLD and CPLD Devices
Example:
attribute ff_type of abc:signal is ff_opt;
The command above tells Warp to optimize the flip-flop type used to synthesize a signal
named abc.
Warp User’s Guide
97
Synthesis Directives
6.2.3
goal
VHDL:
The goal directive, which affects the synthesis of datapath operators, can be used to
override the global goal objective on an architecture-by-architecture basis.
attribute goal of architecture_name:architecture is value;
Legal values for the goal directive are speed, area and combinatorial.
•
A value of speed indicates that all datapath operators (+,-,*,=,/=,<,>,<=,>=) should be
optimized for speed. The Warp synthesizer automatically selects an implementation of
the operator that is optimized for speed.
•
A value of area indicates that all datapath operators (+,-,*,=,/=,<,>,<=,>=) should be
optimized for area. The Warp synthesizer automatically selects an implementation of
the operator that is optimized for area.
•
A value of combinatorial indicates that all datapath operators (+,-,*,=,/
=,<,>,<=,>=,etc.) are optimized for neither area nor speed but rather implemented as
simple combinatorial equations. If a simple combinatorial equation is not available, an
area efficient one is selected. If an area one is not available, then a speed
implementation is selected. Every datapath operator has at least one implementation
available.
6
Scope:
Target: Architecture or Entity
Inheritance: None
Related Command-Line-Option: -yga or -ygs or -ygc
Applicable to: All Devices
Example:
attribute goal of my_adder:entity is speed;
This directive optimizes the entity called my_adder for speed.
Verilog:
The goal directive, which affects the synthesis of datapath operators, can be used to
override the global goal objective on a module-by-module basis.
attribute goal of module_name:module is value;
Legal values for the goal directive are speed, area and combinatorial.
•
98
A value of speed indicates that all datapath operators (+,-,*,=,/=,<,>,<=,>=) should be
Warp User’s Guide
Synthesis Directives
optimized for speed. The Warp synthesizer automatically selects an implementation of
the operator that is optimized for speed.
•
A value of area indicates that all datapath operators (+,-,*,=,/=,<,>,<=,>=) should be
optimized for area. The Warp synthesizer automatically selects an implementation of
the operator that is optimized for area.
•
A value of combinatorial indicates that all datapath operators (+,-,*,=,/
=,<,>,<=,>=,etc.) are optimized for neither area nor speed but rather implemented as
simple combinatorial equations. If a simple combinatorial equation is not available, an
area efficient one is selected. If an area one is not available, then a speed
implementation is selected. Every datapath operator has at least one implementation
available.
Scope:
Target: Architecture or Entity
Inheritance: None
Related Command-Line-Option: -yga or -ygs or -ygc
Applicable to: All Devices
Example:
6
attribute goal of my_adder:module is speed;
This directive optimizes the entity called my_adder for speed.
Warp User’s Guide
99
Synthesis Directives
6.2.4
lab_force
This directive is applicable to both VHDL and Verilog designs.
The lab_force directive aids in grouping signals together as a suggestion to the fitter. This
attribute is valid only for CPLDs.
attribute lab_force of signal_name:signal is "string";
The string contains the name of the logic block. For the FLASH370 family, this string can
also represent a half logic block (made up of either the top eight macrocells or the bottom
eight macrocells). This directive forces the signal my_signal to the logic block without
actually assigning it to a specific I/O pin.
Normally, the fitter performs partitioning of the design prior to place and route and
produces results that are acceptable for most designs. In some cases, however, the user
might want to constrain the fitter due to board layout considerations.
This is an advanced directive and should be used only when the user is very familiar with
the features of the CPLD.
Scope:
6
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: None
Applicable to: CPLD Devices Only
Examples:
attribute lab_force of my_signal:signal is "A";
This example forces the signal my_signal to the logic block A.
attribute lab_force of my_signal:signal is "B2";
This example forces the signal my_signal to the lower half of logic block B. The half
logic block control is only allowed for the FLASH370 family of devices. The half logic
block designation is achieved by simply appending a 1 or a 2 to specify the top half or the
bottom half, respectively.
100
Warp User’s Guide
Synthesis Directives
6.2.5
no_factor
This directive is applicable to both VHDL and Verilog.
The no_factor directive prevents logic factoring within the Warp synthesis engine to
prevent splitting said node.
attribute no_factor of signal_name:signal is value;
During the optimization phase, the Warp synthesis engine, among other things, aliases
signals which have identical drivers (equations).
Using this directive causes equations to bypass these two actions. This feature can be
useful if the design constraints cause certain identical logic to be duplicated or if the logic
factoring algorithm is being overaggressive.
Scope:
Target: Signal
Inheritance: Hierarchical
Related-Command-line-option: -fl
Applicable to: All Devices
6
Examples:
attribute no_factor of my_signal:signal is true;
This example prevents the signal my_signal from being aliased or from being factored.
VHDL:
In VHDL designs, attributes can be placed on all signals in an architecture as follows:
attribute no_factor of my_architecture:architecture is
true;
This example prevents all signals in my_architecture and its sub-architectures from
being aliased or factored.
Verilog:
In Verilog designs, attributes can be placed on all signals in a module as follows:
attribute no_factor of my_module:module is
true;
This example prevents all signals in my_module from being aliased or factored.
Warp User’s Guide
101
Synthesis Directives
6.2.6
no_latch
This directive is applicable to both VHDL and Verilog.
The no_latch directive prevents latches from being synthesized automatically for the
signal in question.
attribute no_latch of signal_name:signal is value;
Normally, when exhaustive optimization is enabled (with the -o2 option), Warp tries to
synthesize latches where possible for the FLASH370 family. The following example
creates a latch with enable as the enable and a as the latched data for the equation x:
VHDL:
if (enable = ’1’) then
x <= a;
else
x <= x;
end if;
Verilog:
6
if (enable )
x = a;
else
x = x;
Creating a latch in this case saves a product term for the x equation; however, this has
certain other side-effects that might not be desirable:
•
If the synthesizer also produced asynchronous resets/presets for the enable, this might
have caused more global resources (clocks, resets, presets) to be used.
•
Creating a latch might have caused a slower design and introduced setup/hold
problems.
Using the no_latch directive would cause Warp to create simply a signal with a
combinatorial delay.
Scope:
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: -yl
Applicable to: FLASH370 Devices Only
102
Warp User’s Guide
Synthesis Directives
Example:
attribute no_latch of x:signal is true;
In this example, the directive causes latch detection to be disabled for signal x.
6
Warp User’s Guide
103
Synthesis Directives
6.2.7
node_num
This directive is applicable to both VHDL and Verilog designs.
The node_num directive tells Warp to map an internal signal to a specific location on the
target device.
attribute node_num of signal-name:signal is integer;
The node_num directive can take a value of any integer or the value of nd_auto.
Assigning the nd_auto value to a signal tells Warp to map the signal to the location of
best fit on the target device. The node_num directive implicitly applies the synthesis_off
directive to that signal as well. For more information on the synthesis_off directive, see
Section 6.2.16 synthesis_off
Scope:
Target: Signal
Inheritance: None
Related Command-Line-Option: -fn
Applicable to: PLD and CPLD Devices Only
6
Examples:
attribute node_num of my_signal:signal is nd_auto;
The command above maps a signal named my_signal to a Warp-determined macrocell in
the target device.
attribute node_num of my_signal:signal is 23;
The command above maps a signal named my_signal to a specific node within the device
being targeted. This value is both device and package specific and may not be portable to
other packages or devices.
This directive is applicable to both VHDL and Verilog designs.
104
Warp User’s Guide
Synthesis Directives
6.2.8
opt_level
This directive is applicable to both VHDL and Verilog designs.
The opt_level directive instructs Warp on the amount of effort that should be spent
optimizing certain signals.
attribute opt_level of signal_name:signal is integer;
The integer represents the amount of effort. Currently, there are three levels of effort (0, 1
and 2). An opt_level of 0 instructs Warp to turn off all optimization on said signal. This
directive is also passed along to the PLD/CPLD fitters which do the same thing. An
opt_level of 1 causes Warp to perform a simple and quick optimization of equations. An
opt_level of 2 causes Warp to perform the highest level of optimization available. An
opt_level of 2 is recommended for all designs.
Scope:
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: -o#
Applicable to: All Devices
6
Example:
attribute opt_level of my_signal:signal is 0;
This directive disables all optimization on the signal my_signal.
Warp User’s Guide
105
Synthesis Directives
6.2.9
order_code
This directive is applicable to both VHDL and Verilog.
The order_code directive tells Warp which device package and speed bin to use when
synthesizing a design for a target device.
In VHDL, use the following syntax.
attribute order_code of entity-name:entity is "order-code";
In Verilog, use the following syntax.
attribute order_code of module-name:module is "order-code";
The order_code directive specifies the package as well as the speed bin for a particular
device. The order_code tells Warp the pin names and pin ordering for the device and
package that are being targeted.
Legal order codes can be found in the Ordering Code column of the ordering information
table for each device in the Cypress Semiconductor Programmable Logic Data Book.
6
Scope:
Target: Top-level Entity
Inheritance: None
Related Command-Line-Option: -p
Applicable to: All Devices
VHDL Example:
attribute order_code of mydesign:entity is
"PALC22V10-25HC";
This example specifies a package type of PALC22V10-25HC for the entity named
my_design.
Verilog Example:
attribute order_code of mydesign:module is
"PALC22V10-25HC";
This example specifies a package type of PALC22V10-25HC for the module named
my_design.
106
Warp User’s Guide
Synthesis Directives
6.2.10
part_name
This directive is applicable to both VHDL and Verilog.
The part_name directive specifies the device to target for synthesis.
In VHDL, use the following syntax.
attribute part_name of entity-name:entity is "part-name";
In Verilog, use the following syntax.
attribute part_name of module-name:module is "part-name";
The part_name directive tells Warp what part is being targeted for synthesis.
Scope:
Target:Top-level Entity
Inheritance: None
Related Command-Line-Option: -d
Applicable to: All Devices
6
VHDL Example:
attribute part_name of my_design:entity is "c371";
This examples specifies the CY7C371 as the target device for synthesis.
Verilog Example:
attribute part_name of my_design:module is "c371";
This examples specifies the CY7C371 as the target device for synthesis.
Warp User’s Guide
107
Synthesis Directives
6.2.11
pin_avoid
This directive is applicable to both VHDL and Verilog.
The pin_avoid directive is a string type directive that instructs the fitter to avoid mapping
any signals to the specified pins. This directive is only valid on the top-level entity/module
of the design.
In VHDL, use the following syntax.
attribute pin_avoid of entity-name:entity is "string";
In Verilog, use the following syntax.
attribute pin_avoid of module-name:module is "string";
The string used in the directive statement consists of one or more pin-numbers. Each pinnumber must be separated by white space (spaces or tabs). This string can consist of
several smaller, concatenated strings.
This feature can be used if certain pins are being used for some special purposes (such as
with In System Reprogrammable devices -- ISR™ ) or need to be reserved for some future
functionality.
6
When this feature is used, the report file indicates these pins as Reserved in the pin table.
Such pins are named as Reserved# where # is an index.
In the case of PLD or CPLD devices where I/O pins have macrocells associated with
them, this feature does not prevent the fitter from using the buried macrocell portion
associated with that particular pin.
Scope:
Target: Top-level Entity.
Inheritance: None
Related Command-Line-Option: None
Applicable to: FLASH370 Devices Only
VHDL Examples:
attribute pin_avoid of my_design:entity is "2 3 4";
attribute pin_avoid of my_design:entity is "A1 B1 C1";
The first example instructs the fitter to avoid the pins 2, 3 and 4 when trying to place the
design into a device. The second example is a case where the package being used is a PinGrid-Array, in which the pin-numbers are actually alpha-numeric.
Verilog Examples:
108
Warp User’s Guide
Synthesis Directives
attribute pin_avoid of my_design:module is "2 3 4";
attribute pin_avoid of my_design:module is "A1 B1 C1";
The first example instructs the fitter to avoid the pins 2, 3 and 4 when trying to place the
design into a device. The second example is a case where the package being used is a PinGrid-Array, in which the pin-numbers are actually alpha-numeric.
6
Warp User’s Guide
109
Synthesis Directives
6.2.12
pin_numbers
This directive is applicable to both VHDL and Verilog.
The pin_numbers directive maps the external signals of the entity to pins on the target
device.
In VHDL, use the following syntax.
attribute pin_numbers of entity-name:entity is "string";
In Verilog, use the following syntax.
attribute pin_numbers of module-name:module is "string";
The string used in the directive statement consists of one or more pairs of the form signalname:number. Pairs must be separated from each other by white space (spaces or tabs).
This string can consist of several smaller, concatenated strings.
6
Note – If the string contains an embedded line break (carriage return or
line feed), a syntax error may result. Thus, for target devices with lots of
pins, it may be more convenient to express the signal-to-pin mapping as
a series of concatenated strings, making sure to leave a space between
successive concatenated sub-strings.
Scope:
Target: Top-level Entity
Inheritance: None
Related Command-Line-Option: -ff
Applicable to : All Devices
VHDL Examples:
attribute pin_numbers of my_design:entity is
"sig1:1 " &
"sig2:2 " &
"sig3:3 " &
"sig4:4 " &
"sig5:5 " &
"sig6:6 " &
"sig7:7 " &
"sig8:8 ";
This example maps eight signals from entity my_design onto the pins of a target device.
The space character before the endquote on the specifications for signals 4 through 7
110
Warp User’s Guide
Synthesis Directives
guarantees that the string for the pin_numbers directive is syntactically correct.
Even though this directive is called pin_numbers, it can also assign PGA package pinnumbers which are in fact alpha-numeric (such as "A1").
attribute pin_numbers of my_design:entity is
"x:1 y:2 clk:3 a(0):4";
This example maps four signals from an entity called my_design onto the pins of a target
device. Signal x is mapped to pin 1, signal y to pin 2, signal clk to pin 3, and signal a(0) to
pin 4.
Verilog Examples:
attribute pin_numbers of my_design: module is
"sig1:1 " &
"sig2:2 " &
"sig3:3 " &
"sig4:4 " &
"sig5:5 " &
"sig6:6 " &
"sig7:7 " &
"sig8:8 ";
This example maps eight signals from module my_design onto the pins of a target device.
The space character before the endquote on the specifications for signals 4 through 7
guarantees that the string for the pin_numbers directive is syntactically correct.
Even though this directive is called pin_numbers, it can also assign PGA package pinnumbers which are in fact alpha-numeric (such as "A1").
attribute pin_numbers of my_design:module is
"x:1 y:2 clk:3 a(0):4";
This example maps four signals from an entity called my_design onto the pins of a target
device. Signal x is mapped to pin 1, signal y to pin 2, signal clk to pin 3, and signal a(0) to
pin 4.
Warp User’s Guide
111
6
Synthesis Directives
6.2.13
polarity
This directive is applicable to both VHDL and Verilog designs.
The polarity directive specifies polarity selection for individual signals.
attribute polarity of signal-name:signal is value;
Legal values for the polarity directive are pl_keep, pl_opt, and pl_default:
•
A value of pl_keep tells Warp to keep the polarity of the signal as currently specified.
•
A value of pl_opt tells Warp to optimize the polarity of the signal to use the fewest
resources on the target device.
•
A value of pl_default tells Warp to synthesize the signal based on the default polarity
selection strategy. This default is determined by the command line switches or Galaxy
dialog settings, if any, used in invoking Warp.
Scope:
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: -fp or -fk
Applicable to: PLD and CPLD Devices
6
Examples:
attribute polarity of abc:signal is pl_opt;
This example tells Warp to optimize the polarity for signal abc.
attribute polarity of abc:signal is pl_keep;
This example tells Warp to keep the polarity of signal abc as currently specified.
112
Warp User’s Guide
Synthesis Directives
6.2.14
state_encoding
This attribute is applicable only for VHDL designs.
The state_encoding directive specifies the internal encoding scheme for values of an
enumerated type.
attribute state_encoding of type-name:type is value;
The legal values of the state_encoding directive are sequential, one_hot_zero,
one_hot_one, and gray.
When the state_encoding directive is set to sequential, the internal encoding of each
value of the enumerated type is set to a sequential binary representation. The first value in
the type declaration receives an encoding of 00; the second, 01; the third, 10; the fourth,
11; and so on. Sufficient bits are allocated to the representation to encode the number of
enumerated type values included in the type declaration.
When the state_encoding directive is set to one_hot_zero, the internal encoding of the
first value in the type definition is set to 0. Each succeeding value in the type definition
has its own bit position in the encoding. That bit position is set to 1 when the state variable
has that value. Thus, a one_hot_zero encoding of an enumerated type with N possible
values requires N-1 bits. For example, if an enumerated type had four possible values,
three bits would be used in its one_hot_zero encoding. The first value in the type
definition would have an encoding of 000. The second would have an encoding of 001.
The third would have an encoding of 010. The fourth would have an encoding of 100.
One_hot_one state encoding works similarly to one_hot_zero, except that no zero
encoding is used; every value in the enumerated type has a bit position, which is set to one
when the state variable has that value. Thus, a one_hot_one encoding of an enumerated
type with N possible values requires N bits. For example, if an enumerated type had four
possible values, four bits would be used in its one_hot_one encoding. The first value in
the type definition would have an encoding of 0001. The second would have an encoding
of 0010. The third would have an encoding of 0100. The fourth would have an encoding
of 1000.
When the state_encoding directive is set to gray, the internal encoding of successive
values of the enumerated type follow a Gray code pattern, where each value differs from
the preceding one by only one bit.
Warp User’s Guide
113
6
Synthesis Directives
Scope:
Target: Type
Inheritance: None
Related Command-Line-Option: None
Applicable to: All Devices
Examples:
type state is (s0,s1,s2,s3);
attribute state_encoding of state:type
is one_hot_zero;
The first statement in this example declares an enumerated type, called state, with four
possible values. The second statement specifies that values of type state are to be encoded
internally using a one_hot_zero encoding scheme.
type s is (s0,s1,s2,s3);
attribute state_encoding of s:type is gray;
The first line of this example declares an enumerated type, called s, with four possible
values. The second line specifies that values of type s are to be encoded internally using a
Gray code encoding scheme.
6
114
Warp User’s Guide
Synthesis Directives
6.2.15
sum_split
This directive is applicable to both VHDL and Verilog designs.
The sum_split directive directs the fitter to chose a sum_splitting strategy.
attribute sum_split of signal_name:signal is value;
The value of this directive can be one of balanced (the default) or cascaded. This
directive is valid only for CPLDs. If a given product term has 18 product terms and the
device being targeted has a limit of 16 product terms per macrocell, then the following
applies:
•
The balanced method, which is the default, uses 3 macrocells. The set of 18 product
terms are split into two macrocells, and the outputs of these two macrocells are ORed
together to form the final output. At the expense of using more resources, this option
provides reliable timing as the design evolves.
•
The cascaded method uses only two macrocells to implement the equation. One
macrocell is used to absorb 16 product terms while another macrocell is used to absorb
the rest of the product terms (2) which are also ORed with the output of the previous
macrocell.There is no control over which product term is assigned to which macrocell,
however, which makes the timing of the equation unreliable as the design changes. On
the other hand, if this is a registered signal, timing may not be a concern.
Scope:
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: None
Applicable to: CPLD Devices Only
Example:
attribute sum_split of my_signal:signal is cascaded;
This example uses the cascaded strategy if the number of product terms for the signal
my_signal exceeds the limit the CPLD imposes.
Warp User’s Guide
115
6
Synthesis Directives
6.2.16
synthesis_off
This directive is applicable to both VHDL and Verilog designs.
The synthesis_off directive controls the flattening and factoring of expressions feeding
signals for which the directive is set to true. This directive causes a signal to be made into
a factoring point for logic equations, which keeps the signal from being substituted out
during optimization.
attribute synthesis_off of signal_name:signal is value;
The synthesis_off directive can only be applied to signals. The default value of the
synthesis_off directive for a given signal is false. This directive gives the user control
over which equations or sub-expressions need to be factored into a node (i.e., assigned to a
physical routing path).
6
•
When set to true for a given signal, synthesis_off causes that signal to be made into a
node (i.e., a factoring point for logic equations) for the target technology. This keeps
the signal from being substituted out during the optimization process. This can be
helpful in cases where performing the substitution causes the optimization phase to
take an unacceptably long time (due to exponentially increasing CPU and memory
requirements) or uses too many resources.
•
Making equations into nodes forces signals to take an extra pass through the array,
thereby decreasing performance, but may allow designs to fit better.
•
The synthesis_off directive should only be used on combinational equations.
Registered equations are natural factoring points; the use of synthesis_off on such
equations may result in redundant factoring.
Scope:
Target: Signal
Inheritance: Hierarchical
Related Command-Line-Option: -v#
Applicable to: All Devices
Example:
attribute synthesis_off of sig1:signal is true;
This example sets the synthesis_off directive to true for a signal named sig1.
116
Warp User’s Guide
Synthesis Directives
6.2.17
slew_rate
This directive is applicable to both VHDL and Verilog designs.
The slew_rate directive can be used to control the output slew rate of individual pins. This
directive is valid only for the Ultra37000 family of CPLDs.
The slew_rate directive can be used to control the output slew rate. This directive is valid
only for the Ultra37000 family of CPLDs.
attribute slew_rate of signal-name:signal is value;
Legal values for the slew_rate directive are fast and slow.
•
A value of ‘fast’ sets the output slew rate to 3V/ns.
•
A value of ‘slow’ sets the output slew rate to 1V/ns.
If the slew rate directive is not present on a signal, by default it is fast. Slow slew rate is
recommended when noise on the circuit board is a matter of concern. There is a 2-ns delay
for the I/Os using the slow slew rate mode.
6
Scope:
Target: Signal
Inheritance: Hierarchical
Related Command Line Option: -yw
Applicable to: Ultra37000 CPLD Devices only
Example:
attribute slew_rate of sig1: signal is slow;
This example forces slow slew rate on the output signal ‘sig1’.
attribute slew_rate of sig2: signal is fast;
This example forces fast slew rate on the output signal ‘sig2’.
Warp User’s Guide
117
Synthesis Directives
6.2.18
low_power
The low power directive can be used to lower the power consumption in a logic block(s)
by 50%. As a result, the logic block(s) slows down by 5 ns. This directive is valid only for
the Ultra37000 family of CPLDs.
In VHDL, use the following syntax.
attribute low_power of entity_name: entity is "string";
In Verilog, use the following syntax.
attribute low_power of module_name: module is "string";
This directive should be used after a careful analysis of the placement and the timing
performance of the design listed in the fitting section of the Warp report file. If you find
that all the signals placed in tha particular logic block(s) are not speed critical, apply this
directive to that logic block(s) and recompile the design to reduce the power consumption
in the device.
Scope:
6
Target: Top-level entity
Inheritance: None
Related Command Line Option: -yp
Applicable to: Ultra37000 CPLD Devices only
VHDL Example:
attribute low_power of my_design: entity is “b g p”;
This example lowers the power consumption in logic blocks b, g and p. As a consequence,
these logic blocks also become slower.
Verilog Example:
attribute low_power of my_design: module is “b g p”;
This example lowers the power consumption in logic blocks b, g and p. As a consequence,
these logic blocks also become slower.
118
Warp User’s Guide
Synthesis Directives
What is Virtual Substitution?
For the following equations:
x <= a OR b OR c;
y <= NOT x OR d;
The optimizer expands signal x within the equation for y and produce the following
equations:
x <= a OR b OR c;
y <= NOT (a OR b OR c) OR d;
Once this is done, if x is no longer required, the equation for x is removed from the design;
however, if x is also an output pin or if x is being used to drive something other than an
equation (like an RTL component), x is preserved. This process is repeated for all
equations in the design.
This process within Warp is called virtual substitution and is desirable in most cases. For
CPLDs which have a huge appetite for equations, virtual substitution improves
performance and also uses less area. In some cases, however, x could have been a very
large equation or an equation whose negation might have resulted in a very large equation,
causing Warp to take unacceptably long to complete due to constantly expanding CPU
and memory requirements.
A situation might also occur where multiple other outputs (large or small) use signal x,
which might cause the design to use too many resources in the CPLD. In rare situations
such as those mentioned above, setting the synthesis_off directive for signal x to true
creates a factoring point during synthesis and fitting. In PLDs and CPLDs, such nodes are
assigned to a macrocell.
Warp uses a sophisticated algorithm to determine automatically good factoring points
during the process of virtual substitution. In most cases, the conclusions made by Warp
are good, but in certain cases, Warp may be overly aggressive in trying to eliminate as
many nodes as possible. By reducing this aggressiveness (using the -v option), it is
possible to reduce the complexity of the network. By using the -v option and controlling
the aggressiveness of this algorithm, a user can typically find which nodes have the
potential for reducing the network. Once such nodes are identified, the user can then select
the synthesis_off directive to fix permanently the nodes and then go back to the default
behavior of aggressive virtual substitution, thus allowing Warp to substitute any nodes
that user deems should be virtually substituted but the software would have made a hard
node with a lower cost setting.
Warp User’s Guide
119
6
Synthesis Directives
6.3
Control File (VHDL Users)
A control file provides a common location for setting global synthesis directives for a
given design. This gives the user detailed control over many aspects of synthesis while
maintaining a device and vendor independent VHDL source file. The control file allows
the user to attach synthesis directives via the attribute mechanism, and the file supports the
VHDL syntax for these attributes to allow the cutting and pasting of these directives
between the VHDL source and the control file. The file can also be used for backannotating pinout and internal placement information from fitting and place and route
results automatically.
During the process of synthesis, optimization, and factoring, Warp derives many new
signal and node names to realize the design. For example, Warp separates buses into
individual signals. Even though objects such as buses make VHDL design entry much
simpler, no VHDL legal way exists to assign attributes to portions of a bus. In other cases,
Warp produces brand new signal names which may not have any direct correlation to any
single VHDL object within a design. This situation occurs during factorization where
factors are produced by examining the design globally.
6
Only one control file is allowed per design, and the file should have the same base name as
the top-level design file name. For example, for a top-level design whose name is
mydesign.vhd, the control file must be called mydesign.ctl.
A control file is not required. The creation and editing of the control file is an iterative
process, typically done to refine, improve, or constrain the results of synthesis.
The format of the control file is similar to VHDL. A comment begins with a "--" pattern
and terminates at the end of the line. All synthesis directives must be preceded by the
keyword attribute. The directives are not case-sensitive.
attribute directive-name [of] object-name[:class] [is]
value[;]
The line must start with the keyword attribute.
The keywords of and is are optional and are simply ignored.
Class refers to the type of VHDL object. If the class is not specified, a signal is assumed.
Other valid classes include entity, architecture, and label. The label class can be used to
specify a directive intended for a component instantiation.
A synthesis directive is terminated either with a new line, a semi-colon, or a comment.
120
Warp User’s Guide
Synthesis Directives
Directive-name is any synthesis directive specified in the previous section except for the
following:
•
goal
•
state_encoding
•
enum_encoding
•
part_name
•
order_code
Object-name is the name of a signal or component-label. This is the object upon which
the synthesis directive is being placed. Any signal that is visible after the synthesis and in
the report file is a valid object-name. Warp also supports the "*" wild-card character that
allows pattern matching.
Value is the value of the directive. The previous section describes valid values depending
upon the directive.
Synthesis directives override any directives specified directly in the VHDL text for the
design.
This syntax allows users to cut and paste attributes directly from the original VHDL text
and vice-versa with minimal editing.
Example:
-- File mydesign.ctl
-- This is a comment
-- Force ff_type to d-type for signal mysig_1
attribute ff_type of mysig_1:signal is ff_d;
-- long syntax
-- Force ff_type to t-type for signal mysig_2
attribute ff_type mysig_2 ff_t
-- short syntax
-- Wild_card example, select best ff-type
-- for all signals
-- starting with "abcd"
attribute ff_type of abcd* is ff_opt;
This control file example starts with three lines of comments which are denoted by the
"--" at the start of each line. Line 4 specifies that mysig_1 be implemented as a D-type
flip-flop. Line 7 specifies that mysig_2 be inplemented as a T-type flip-flop using the
short syntax. Line 11 instructs the Warp compiler to optimize all signals starting with
abcd for either D or T-type flip-flops.
Warp User’s Guide
121
6
Synthesis Directives
6.4
Control File (Verilog Users)
A control file provides a common location for setting global synthesis directives for a
given design. This gives the user detailed control over many aspects of synthesis while
maintaining a device and vendor independent Verilog source file. The control file allows
the user to attach synthesis directives via the attribute mechanism, and the file supports the
VHDL syntax for these attributes. The file can also be used for back-annotating pinout and
internal placement information from fitting and place and route results automatically.
During the process of synthesis, optimization, and factoring, Warp derives many new
signal and node names to realize the design. For example, Warp separates buses into
individual signals. Even though objects such as buses make Verilog design entry much
simpler, attributes can not be assigned to portions of a bus. In other cases, Warp produces
brand new signal names which may not have any direct correlation to any single Verilog
object within a design. This situation occurs during factorization where factors are
produced by examining the design globally.
Only one control file is allowed per design, and the file should have the same base name as
the top-level design file name. For example, for a top-level design whose name is
mydesign.v, the control file must be called mydesign.ctl.
6
A control file is not required. The creation and editing of the control file is an iterative
process, typically done to refine, improve, or constrain the results of synthesis.
The format of the control file is as follows:
A comment begins with a "--" pattern and terminates at the end of the line. All synthesis
directives must be preceded by the keyword attribute. The directives are not casesensitive.
attribute directive-name [of] object-name[:class] [is]
value[;]
The line must start with the keyword attribute.
The keywords of and is are optional and are simply ignored.
Class refers to the type of Verilog object. If the class is not specified, a signal is assumed.
Other valid classes include module and label. The label class can be used to specify a
directive intended for a component instantiation.
A synthesis directive is terminated either with a new line, a semi-colon, or a comment.
122
Warp User’s Guide
Synthesis Directives
Directive-name is any synthesis directive specified in the previous section except for the
following:
•
goal
•
state_encoding
•
enum_encoding
•
part_name
•
order_code
Object-name is the name of a signal or component-label. This is the object upon which
the synthesis directive is being placed. Any signal that is visible after the synthesis and in
the report file is a valid object-name. Warp also supports the "*" wild-card character that
allows pattern matching.
Value is the value of the directive. The previous section describes valid values depending
upon the directive.
The control file is case insensitive, except for the identifiers, attribute values and the
following keywords: is,of, attribute, options, signal, label, module. These keywords also
can not be used as identifiers.
Example:
-- File mydesign.ctl
-- This is a comment
-- Force ff_type to d-type for signal mysig_1
attribute ff_type of mysig_1:signal is ff_d;
-- long syntax
-- Force ff_type to t-type for signal mysig_2
attribute ff_type mysig_2 ff_t
-- short syntax
-- Wild_card example, select best ff-type
-- for all signals
-- starting with "abcd"
attribute ff_type of abcd* is ff_opt;
This control file example starts with three lines of comments which are denoted by the
"--" at the start of each line. Line 4 specifies that mysig_1 be implemented as a D-type
flip-flop. Line 7 specifies that mysig_2 be inplemented as a T-type flip-flop using the
short syntax. Line 11 instructs the Warp compiler to optimize all signals starting with
abcd for either D or T-type flip-flops.
Warp User’s Guide
123
6
Synthesis Directives
6.5
Warp Synthesis Directives with ViewDraw (Warp3
VHDL)
6.5.1
Warp Synthesis Directives
When using Warp in conjunction with ViewDraw, most of the synthesis directives are
available directly within the ViewDraw graphical interface. ViewDraw users have an
option to choose either the control file described in the previous section or to embed
synthesis directives directly into the schematic.
A synthesis directive within ViewDraw is specified using the attribute mechanism.
Attributes can be placed or modified within Viewdraw using the Viewdraw menu items
Add->Attr... or Change->Attr....
With the exception of pin_numbers, all the other synthesis directives have the exact same
name as the Warp synthesis directive. ViewDraw uses # as the name of the pin_numbers
attribute. The attributes must be attached to the wire connecting to the pin and NOT to the
pin itself. This is especially true for #.
6
Warp supports the use of the following attributes within ViewDraw:
Table 6-1 Supported Attributes Within ViewDraw
124
Attribute
Target
#
Wires (top-level pins only)
ff_type
Any Wire
lab_force
Any Wire
no_factor
Any Wire
no_latch
Any Wire
node_num
Any Wire
opt_level
Any Wire
pin_avoid
Top level symbol
polarity
Any Wire
sum_split
Any Wire
synthesis_off
Any Wire
Warp User’s Guide
Synthesis Directives
With the exception of # and pin_avoid, which can only be placed on a top-level
schematic net, these attributes can also be placed as follows:
•
on the instance of a symbol (corresponds to VHDL label)
•
in the symbol (corresponds to VHDL entity)
•
on the schematic (corresponds to VHDL architecture)
The Warp Export VHDL utility netlists these attributes where they are found, and Warp
uses its hierarchical inheritance rules to interpret these attributes. These rules are
explained at the beginning of this chapter.
6.5.2
Supported ViewDraw Attributes
In addition to the ViewDraw attribute # representing pin assignments, the only other
ViewDraw specific attribute that Warp supports is the $ARRAY attribute.
The $ARRAY component attribute specifies a one- or two-dimensional array of the
component without actually drawing all of the components.
Arrayed components are defined at the schematic level. The $ARRAY attribute is added
to the component to determine the number of occurrences of this component in the logical
database. $ARRAY attributes at the symbol level are ignored.
The format for a one-dimensional component array is as follows:
$ARRAY=n
The format for a two-dimensional component array is as follows:
$ARRAY=x,y
Warp User’s Guide
125
6
Synthesis Directives
6.6
Synthesis Directive Format Summary
Table 6-2 summarizes the synthesis directive formats, values, and command line switches.
Table 6-2 Synthesis Directive formats
Directive
6
Format
Values (D=Default)
Cmd line
goal
attribute goal of arch_name :
architecture is value;
speed (D), area, or
combinatorial
state_encoding
attribute state_encoding of
type_name : type is value;
sequential (D),
one_hot_zero,
one_hot_one, or gray
synthesis_off
attribute synthesis_off of
signal_name : signal is value;
false (D) or true
no_latch
attribute no_latch of signal_name
: signal is value;
false (D) or true
lab_force
attribute lab_force of
signal_name : signal is location;
Example: “A1”
pin_avoid
attribute pin_avoid of
entity_name : entity is location;
Example: “1 2 3”
polarity
attribute polarity of signal_name :
signal is value;
pl_default (D), pl_keep,
or pl_opt
fk
fp
sum_split
attribute sum_split of
signal_name : signal is value;
balanced (D) or
cascaded
--
node_num
attribute node_num of
signal_name : signal is value;
nd_auto (D) or positive
integer
fn
ff_type
attribute ff_type of signal_name :
signal is value;
ff_default (D), ff_d,
ff_t, or ff_opt
opt_level
attribute opt_level of signal_name
: signal is integer;
2 (D), 1, or 0
part_name
attribute part_name of
entity_name : entity is string;
Example: “c371”
order_code
attribute order_code of
entity_name : entity is string;
Example: “PALC22V10p
25HC”
126
ygs
yga
ygc
--
-yl
---
fd
ft
fo
o
d
Warp User’s Guide
Synthesis Directives
Table 6-2 Synthesis Directive formats
Directive
Format
Values (D=Default)
pin_numbers
attribute pin_numbers of
entity_name : entity is string;
Example: “sig1:1 “ &
“sig2:2”
slew_rate
attribute slew_rate of
signal_name:signal is value;
fast (D), slow
low_power
attribute low_power of
entity_name:entity is string;
Example: “a d g”
Cmd line
ff
yw
yp
6
Warp User’s Guide
127
Synthesis Directives
6
128
Warp User’s Guide
Chapter
LPM
7
7
LPM
7
7.1
Introduction
This chapter provides necessary information about each component in the Warp LPM
system libraries.
For each component, the following information is given:
•
a diagram of the component’s symbol, as instantiated on a schematic
•
a listing of the VHDL entity declaration for the component. This information is useful
for determining the order, direction, and type of each port when instantiating the
component in a VHDL file.
•
a listing of the Verilog module declaration for the component. This information is
useful for determining the order, direction, and type of each port when instantiating the
component in a Verilog file.
•
a description of the functionality of the component
The chapter contains the following sections:
•
Section 7.2 LPM Modules
•
Section 7.3 Other Cypress Modules
•
Section 7.4 Cypress Exceptions to LPM Standard
•
Section 7.5 Hints and Techniques
VHDL users:
To use any of the components described in this chapter within a VHDL description,
include the following line in the VHDL file, immediately above the entity and architecture
declarations:
use work.lpmpkg.all;
In the description portion of the component definitions, the following conventions apply:
Port names are identified by: result
Generics are identified by: lpm_width
Values of generics are identified by: lpm_logical
Many of the components in this library have ports that can be selected or deselected in the
symbol. If the port is deselected, it will not show up on the symbol but will be netlisted to
its default value. If these components are implemented with VHDL structural code, those
ports must be both included in the port map and connected to a ‘0’ or ‘1’ if the
functionality that each particular port allows is not needed.
130
Warp User’s Guide
LPM
Verilog users:
To use any of the components described in this chapter within a Verilog description,
include the following line in the Verilog file, immediately above the module declaration.
‘include "lpm.v"
Also make sure that $CYPRESS_DIR/lib/common is specified in the source file search
path of galaxy. If running from command line, use the -I command line option as follows:
warp -I$CYPRESS_DIR/lib/common
In the description portion of the component definitions, the following conventions apply:
Port names are identified by: result
Parameters are identified by: lpm_width
Values of parameters are identified by: lpm_logical
Many of the components in this library have ports that can be selected or deselected in the
symbol. If the port is deselected, it will not show up on the symbol but will be netlisted to
its default value. If these components are implemented with Verilog structural code, those
ports must be both included in the port map and connected to a ‘0’ or ‘1’ if the
functionality that each particular port allows is not needed.
Warp User’s Guide
131
7
LPM
7
7.2
7.2.1
LPM Modules
MCNSTNT
Module Constant Symbol
VHDL Entity Description
entity Mcnstnt is
generic(lpm_width
lpm_cvalue
lpm_hint
port(result
: positive;
: string;
: goal_type);
: out std_logic_vector
((lpm_width-1) downto 0));
end Mcnstnt;
Verilog Module Description
module mcnstnt (result);
parameter lpm_width = 1;
parameter lpm_cvalue = "NULL";
parameter lpm_hint = `SPEED;
parameter lpm_strength = `LPM_NO_STRENGTH;
output [lpm_width - 1:0] result;
..............
endmodule
Description
The result output is a vector lpm_width bits long representing the binary value of
lpm_cvalue.
The lpm_hint value is not used in the architecture.
132
Warp User’s Guide
LPM
7.2.2
MINV
7
Module Inverter Symbol
VHDL Entity Description
entity Minv is
generic(lpm_width
lpm_hint
port(data
result
: positive;
: goal_type);
: in std_logic_vector
((lpm_width-1) downto 0);
: out std_logic_vector
((lpm_width-1) downto 0));
end Minv;
Verilog Module Description
module minv (data, result);
parameter lpm_width = 1;
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
output [lpm_width - 1:0] result;
.........
endmodule
Description
result <= NOT data;
This component represents an expandable inverter. Its size is determined by lpm_width.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
133
LPM
7
7.2.3
MAND
Module AND Symbol
VHDL Entity Description
entity Mand is
generic(lpm_width
lpm_size
lpm_hint
lpm_data_pol
lpm_result_pol
port(data
result
: positive;
: positive;
: goal_type);
: string;
: string);
: in std_logic_vector
(((lpm_width*lpm_size)-1)
downto 0);
: out std_logic_vector((lpm_width-1)
downto 0));
end Mand;
Verilog Module Description
module mand (data, result);
parameter lpm_width = 1;
parameter lpm_size = 1;
parameter lpm_hint = `SPEED;
parameter lpm_data_pol = "NULL";
parameter lpm_result_pol = "NULL";
input
[lpm_width * lpm_size - 1:0] data;
output [lpm_width - 1:0] result;
.........
endmodule
134
Warp User’s Guide
LPM
Description
7
for i in 0 to (lpm_width-1) :
resulti <= data0i AND data1i AND ... data[lpm_size-1]i
This component represents an array of lpm_width AND gates each having lpm_size inputs.
The generics lpm_data_pol and lpm_result_pol are used to select the polarity of each bit
of their respective ports. The position of a bit in the string is the same as it is in the port
vector with a ‘1’ indicating a non-inverted port while a ‘0’ represents an inverted one. If
the generic is not present, the entire port is non-inverted. Access to each bit of each port is
available only from VHDL; the schematic GUI allows polarity selection of the entire port
only.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
135
LPM
7
7.2.4
MOR
Module OR Symbol
VHDL Entity Description
entity Mor is
generic(lpm_width
lpm_size
lpm_hint
lpm_data_pol
lpm_result_pol
port(data
result
: positive;
: positive;
: goal_type;
: string;
: string);
: in std_logic_vector
(((lpm_width*lpm_size)-1)
downto 0);
: out std_logic_vector((lpm_width-1)
downto 0));
end Mor;
Verilog Module Description
module mor (data, result);
parameter lpm_width = 1;
parameter lpm_size = 1;
parameter lpm_hint = `SPEED;
parameter lpm_data_pol = "NULL";
parameter lpm_result_pol = "NULL";
input
[lpm_width * lpm_size - 1:0] data;
output
[lpm_width - 1:0] result;
....
endmodule
Description
for i in 0 to (lpm_width-1) :
136
Warp User’s Guide
LPM
resulti <= data0i OR data1i OR ... data[lpm_size-1]i
This component represents an array of lpm_width OR gates each having lpm_size inputs.
The generics lpm_data_pol and lpm_result_pol are used to select the polarity of each bit
of their respective ports. The position of a bit in the string is the same as it is in the port
vector with a ‘1’ indicating a non-inverted port while a ‘0’ represents an inverted one. If
the generic is not present, the entire port is non-inverted. Access to each bit of each port is
available only from VHDL; the schematic GUI allows polarity selection of the entire port
only.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
137
7
LPM
7
7.2.5
MXOR
Module Exclusive-OR Symbol
VHDL Entity Description
entity Mxor is
generic(lpm_width
lpm_size
lpm_hint
lpm_data_pol
lpm_result_pol
port(data
result
: positive;
: positive;
: goal_type;
: string;
: string);
: in std_logic_vector
(((lpm_width*lpm_size)-1)
downto 0);
: out std_logic_vector((lpm_width-1)
downto 0));
end Mxor;
Verilog Module Description
module mxor (data, result);
parameter lpm_width = 1;
parameter lpm_size = 1;
parameter lpm_hint = `SPEED;
parameter lpm_data_pol = "NULL";
parameter lpm_result_pol = "NULL";
input
[lpm_width * lpm_size - 1:0] data;
output
[lpm_width - 1:0] result;
.......
endmodule
Description
for i in 0 to (lpm_width-1) :
138
Warp User’s Guide
LPM
resulti <= data0i XOR data1i XOR ... data[lpm_size-1]i
7
This component represents an array of lpm_width Exclusive-OR gates each having
lpm_size inputs.
The generics lpm_data_pol and lpm_result_pol are used to select the polarity of each bit
of their respective ports. The position of a bit in the string is the same as it is in the port
vector. A ‘1’ indicates a non-inverted port, a ‘0’ represents an inverted one. If the generic
is not present, the entire port is non-inverted. Access to each bit of each port is available
only from VHDL; the schematic GUI only allows polarity selection of the entire port.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
139
LPM
7
7.2.6
MBUSTRI
Module Bus Tri-State Symbol
Entity Description
entity Mbustri is
generic(lpm_width
lpm_hint
port(tridata
data
enabletr
enabledt
result
: positive;
: goal_type);
: inout std_logic_vector((lpm_width-1)
downto 0);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic;
: out std_logic_vector((lpm_width-1)
downto 0));
end Mbustri;
Verilog Module Description
module mbustri (tridata, data, enabletr, enabledt, result);
parameter lpm_width = 1;
parameter lpm_hint = `SPEED;
inout [lpm_width - 1:0] tridata;
input [lpm_width - 1:0] data;
input enabletr;
input enabledt;
output [lpm_width - 1:0] result;
...........
endmodule
140
Warp User’s Guide
LPM
Description
EnableDT
L
L
L
H
H
H
H
EnableTR
L
H
H
L
L
H
H
TriData
Hi-Z
L
H
L (Data)
H (Data)
L (Data)
H (Data)
Data
X
X
X
L
H
L
H
Result
Hi-Z
L (TriData)
H (TriData)
Hi-Z
Hi-Z
L (Data)
H (Data)
Tridata plus either result or data must be present. If data is present, then enabledt must
be present; if result is present, then enabletr must be present. If either enabletr or
enabledt is ‘0’ is not used, the default value is ‘0’.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
141
7
LPM
7
7.2.7
MMUX
Module Multiplexor Symbol
VHDL Entity Description
entity Mmux is
generic(lpm_width
lpm_size
lpm_widths
lpm_hint
port(data
sel
result
: positive;
: positive;
: positive;
: goal_type);
: in std_logic_vector
(((lpm_width*lpm_size)-1)
downto 0);
: in std_logic_vector
((lpm_widths-1) downto 0);
: out std_logic_vector
((lpm_width-1) downto 0));
end Mmux;
Verilog Module Description
module mmux (data, sel, result);
parameter lpm_width = 1;
parameter lpm_size = 1;
parameter lpm_widths = 1;
parameter lpm_hint = `SPEED;
input [lpm_width * lpm_size - 1:0] data;
input [lpm_widths - 1:0] sel;
output [lpm_width - 1:0] result;
........
endmodule
142
Warp User’s Guide
LPM
Description
Selectlpm_widths-1
L
L
L
L
...
H
...
L
L
L
L
...
Select1
L
L
H
H
...
Select0
L
H
L
H
...
7
Resulti
Datai0
Datai1
Datai2
Datai3
...
Datai[lpm_size-1]
Lpm_widths can be any value >= Log2(lpm_size), where lpm_size must be > 1.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
143
LPM
7
7.2.8
MDECODE
Module Decoder Symbol
VHDL Entity Description
entity Mdecode is
generic(lpm_width
lpm_decodes
lpm_hint
port(data
enable
eq
: positive;
: positive;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: out std_logic_vector((lpm_decodes-1)
downto 0));
end Mdecode;
Verilog Module Description
module mdecode (data, enable, eq);
parameter lpm_width = 1;
parameter lpm_decodes = 1;
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
input enable;
output [lpm_decodes - 1:0] eq;
......
endmodule
144
Warp User’s Guide
LPM
Description
Enable
Datalpm_width-1
...
Data1
Data0
L
H
H
H
H
H
X
L
L
L
...
H
X
L
L
L
...
H
X
L
L
H
...
H
X
L
H
L
...
H
7
Eqlpm_width
High
None
Eq0
Eq1
Eq2
...
Eqlpm_decodes-1
Enable is optional, and the default value is ’1’ if not used on the symbol. There must be at
least 1 eq bit and can be no more than 2lpm_width (2lpm_width >= lpm_decodes > 0).
If eqi is not connected or does not appear in the symbol, the selection of ’I’ results in all
outputs being low. The lpm_hint value is not used in the architecture.
Warp User’s Guide
145
LPM
7
7.2.9
MCLSHIFT
Module Combinatorial Logic Shifter Symbol
VHDL Entity Description
entity Mclshift is
generic(lpm_width
lpm_widthdist
lpm_shifttype
lpm_hint
port(data
distance
direction
result
overflow
underflow
end Mclshift;
: positive;
: natural;
: shift_type;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic_vector((lpm_widthdist-1)
downto 0);
: in std_logic;
: out std_logic_vector((lpm_width-1)
downto 0);
: out std_logic;
: out std_logic);
Verilog Module Description
module mclshift (data, distance, direction, result, overflow, underflow);
parameter lpm_width = 2;
parameter lpm_widthdist = 1;
parameter lpm_shifttype = `LPM_LOGICAL;
parameter lpm_hint = `SPEED;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] distance;
input direction;
output [lpm_width-1:0] result;
output overflow;
output underflow;
........
endmodule
146
Warp User’s Guide
LPM
7
Description
The result will be a vector lpm_width wide resulting from the input data vector
lpm_width wide shifted distance bits in the direction (1=right, 0=left) specified. The size
of the distance port is determined by the value of lpm_widthdist.
The type of shift is specified by lpm_shifttype as either lpm_logical (Default),
lpm_arithmetic, or lpm_rotate.
The sign bit is only extended for lpm_arithmetic and ’0’s are shifted in for lpm_logical.
Overflow occurs when the shifted result exceeds the precision of the result port. For
lpm_logical values, overflow occurs when a ’1’ is shifted past resultn-1. For
lpm_arithmetic values, overflow occurs when the most significant bit (a ’1’ for positive
values or ’0’ for negative values) is shifted past resultn-1.
Underflow occurs when the shifted result contains no significant digits.
The direction, overflow, and underflow ports are optional, and the default value for
direction is ’0’ if it is not used on the symbol.
Lpm_widthdist must be <= log2(lpm_width).
The lpm_hint value is not used in the architecture.
Warp User’s Guide
147
LPM
7
7.2.10
MADD_SUB
Module Add/Subtract Symbol
VHDL Entity Description
entity Madd_sub is
generic(lpm_width
: positive;
lpm_representation : repre_type;
lpm_direction
: arith_type;
lpm_hint
: goal_type);
port(dataa
: in std_logic_vector((lpm_width-1)
downto 0);
datab
: in std_logic_vector((lpm_width-1)
downto 0);
cin
: in std_logic;
add_sub
: in std_logic;
result
: out std_logic_vector
((lpm_width-1) downto 0);
cout
: out std_logic;
overflow
: out std_logic);
end Madd_sub;
Verilog Module Description
module madd_sub (dataa, datab, cin, add_sub, result, cout, overflow);
parameter lpm_width = 1;
parameter lpm_representation = `LPM_UNSIGNED;
parameter lpm_direction = `LPM_NO_TYP;
parameter lpm_hint = `SPEED;
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input cin;
input add_sub;
output [lpm_width-1:0] result;
output cout;
148
Warp User’s Guide
LPM
output overflow;
......
endmodule
7
Description
result <= dataa + datab + cin when
(add_sub = ‘1’ or lpm_direction = lpm_add) else
dataa - datab - cin when
(add_sub = ‘0’ or lpm_direction = lpm_sub) else
null;
cout <= (dataalpm_width-1 AND datablpm_width-1)
OR (dataalpm_width-1 AND Clpm_width-2)
OR (datablpm_width-1 AND Clpm_width-2);
overflow <= Clpm_width-2 XOR Clpm_width-1
Note – Signal C is the internal carry signal and it is not available as a
port on the device.
The valid assignments for lpm_representation are lpm_unsigned and lpm_signed. For
lpm_unsigned, the cout pin is significant and for lpm_signed, the overflow is significant.
The cin, add_sub, cout, and overflow ports are optional. The default value for add_sub
is ’1’ if it is not used on the symbol, and the default value for cin is ’0’ if it is not used on
the symbol. This latter default may cause an unobvious and perhaps undesired affect
because of the definition of cin, which states:
•
if OP = ADD then: low = +0, high = +1
•
if OP = SUBTRACT then: low = -1, high = -0
This implies that if the cin port is not used and the component is adding, there is no carryin. When subtracting, however, there is always a borrow-in or the subtractor will always
be subtracting datab - 1 from dataa.
The lpm_direction generic, which is optional, can be either lpm_add (default) or lpm_sub.
If it is used, the add_sub port may not be.
The lpm_hint generic is applicable to all parts. The area version implements a series of 2bit ripple adders (subtractors) while the speed version implements a series of 2-bit carrylook-ahead adders (subtractors).
Warp User’s Guide
149
LPM
7
7.2.11
MCOMPARE
Module Compare Symbol
VHDL Entity Description
entity Mcompare is
generic(lpm_width
lpm_representation
lpm_hint
port(dataa
datab
alb
aeb
agb
ageb
aleb
aneb
end Mcompare;
: positive;
: repre_type;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic_vector((lpm_width-1)
downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic);
Verilog Module Description
module mcompare (dataa, datab, alb, aeb, agb, ageb, aleb, aneb);
parameter lpm_width = 1;
parameter lpm_representation = `LPM_UNSIGNED;
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] dataa;
input [lpm_width - 1:0] datab;
output alb;
output aeb;
output agb;
output ageb;
output aleb;
output aneb;
150
Warp User’s Guide
LPM
........
endmodule
7
Description
alb <= ‘1’ when dataa < datab else ‘0’;
aeb <= ‘1’ when dataa = datab else ‘0’;
agb <= ‘1’ when dataa > datab else ‘0’;
ageb <= ‘1’ when dataa >= datab else ‘0’;
aleb <= ‘1’ when dataa <= datab else ‘0’;
aneb <= ‘0’ when dataa = datab else ‘1’;
All six output ports are individually optional, but at least one must be connected.
The valid assignments for lpm_representation are lpm_unsigned and lpm_signed.
Warp User’s Guide
151
LPM
7
7.2.12
MMULT
Module Multiplier Symbol
VHDL Entity Description
entity Mmult is
generic(lpm_widtha
lpm_widthb
lpm_widths
lpm_widthp
lpm_representation
lpm_hint
port(dataa
datab
sum
result
: positive;
: positive;
: natural;
: positive;
: repre_type;
: goal_type);
: in std_logic_vector
((lpm_widtha-1) downto 0);
: in std_logic_vector
((lpm_widthb-1) downto 0);
: in std_logic_vector
((lpm_widths-1) downto 0);
: out std_logic_vector
((lpm_widthp-1) downto 0));
end Mmult;
Verilog Module Description
module mmult (dataa, datab, sum, result);
parameter lpm_widtha = 1;
parameter lpm_widthb = 1;
parameter lpm_widths = 2;
parameter lpm_widthp = 2;
parameter lpm_representation = `LPM_UNSIGNED;
parameter lpm_hint = `SPEED;
parameter lpm_avalue = "NULL";
input [lpm_widtha-1:0] dataa;
input [lpm_widthb-1:0] datab;
input [lpm_widths-1:0] sum;
output [lpm_widthp-1:0] result;
.......
152
Warp User’s Guide
LPM
endmodule
7
Description
result <= dataa * datab + sum;
If lpm_widthp < max((lpm_widtha + lpm_widthb),lpm_widths), then only the lpm_widthp
most significant bits are present.
The valid assignments for lpm_representation are lpm_unsigned and lpm_signed.
The sum port is optional, as is its width generic lpm_widths, which has a default value of
‘0’.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
153
LPM
7
7.2.13
MABS
Module Absolute Value Symbol
RESULT
DATA
X
OVERFLOW
LPM_WIDTH = 8
LPM_HINT = SPEED
VHDL Entity Description
entity Mabs is
generic(lpm_width: positive;
lpm_hint: goal_type);
port(data: instd_logic_vector((lpm_width-1) downto 0);
result: outstd_logic_vector((lpm_width-1) downto 0);
overflow: outstd_logic);
end Mabs;
Verilog Module Description
module mabs (data, result, overflow);
parameter lpm_width = 1;
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
output [lpm_width - 1:0] result;
output overflow;
......
endmodule
Description
result <= abs(data)
overflow <= ‘1’ when (data = -2**(n-1)) else ‘0’;
154
Warp User’s Guide
LPM
7.2.14
MCOUNTER
7
Module Counter Symbol
VHDL Entity Description
entity Mcounter is
generic(lpm_width
lpm_direction
lpm_avalue
lpm_svalue
lpm_pvalue
lpm_hint
lpm_modulus
port(data
clock
clk_en
cnt_en
updown
q
aset
aclr
aload
sset
sclr
sload
testenab
testin
Warp User’s Guide
: positive;
: ctdir_type;
: string;
: string;
: string;
: goal_type;
: positive);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
155
LPM
7
Verilog Module Description
module mcounter (data, clock, clk_en, cnt_en, updown, q, aset, aclr, aload,
sset, sclr, sload, testenab, testin, testout);
parameter lpm_width = 1;
parameter lpm_direction = `LPM_NO_DIR;
parameter lpm_avalue = "NULL";
parameter lpm_svalue = "NULL";
parameter lpm_pvalue = "NULL";
parameter lpm_hint = `SPEED;
parameter lpm_modulus = 1;
input [lpm_width - 1:0] data;
input clock;
input clk_en;
input cnt_en;
input updown;
output [lpm_width - 1:0] q;
input aset;
input aclr;
input aload;
input sset;
input sclr;
input sload;
input testenab;
input testin;
output testout;
......
endmodule
156
Warp User’s Guide
LPM
Description
Asynch
Control
H
L
L
H
L
L
L
L
L
Synch
Control
L
H
H
H
L
L
L
L
X
clock
cnt_en
X
L->H
L->H
X
L->H
L->H
L->H
L->H
L->H
X
X
X
X
H
H
H
H
X
clk_
en
X
H
L
X
L
H
H
H
X
testenab
X
X
X
X
X
X
X
X
H
updown
X
X
X
X
X
U
H
L
X
7
q
Async. value.
Sync. value.
No change
Undefined
No change
see 1pm_direction
qprev +1
qprev -1
qi-1, q0 <= testin
testout <= qlpm_width-1;
Aset sets q to the value of lpm_avalue if that generic is present, otherwise it sets q to all
‘1’s. If the lpm_avalue is present, then aclr cannot be used. Aclr sets the value of q to all
‘0’s. The same is true for sset and sclr with lpm_svalue. The load ports (aload and sload)
sets q to the value present on data. The clr is dominant over the set if both are asserted
simultaneously for both synchronous and asynchronous operations.
Clock and q are the only required ports, all others are optional.
If cnt_en is not used on the symbol, its default value is ‘1’. The same is true for updown.
The default value for aset, aclr, aload, sset, sclr, and sload is ‘0’ if they are not used on
the symbol. If aload or sload are used, then there must be a data port.
Testenab, testin and testout are optional; testenab and testin have a default value of ‘0’
if they are not used on the symbol. Either all or none of the test ports must be connected.
Lpm_direction can have values of lpm_up or lpm_down, and if it is used, the updown pin
cannot be used. The lpm_pvalue is unused in the architecture.
The lpm_direction generic can have values of lpm_up which implements an up count only
(q <= qprev + 1) or lpm_down which implements a down count only (q <= qprev - 1).
Warp User’s Guide
157
LPM
7
7.2.15
MLATCH
Module Latch Symbol
VHDL Entity Description
entity Mlatch is
generic(lpm_width
lpm_avalue
lpm_pvalue
lpm_hint
port(data
gate
q
aset
aclr
end Mlatch;
: positive;
: string;
: string;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: out std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic);
Verilog Module Description
module mlatch (data, gate, q, aset, aclr);
parameter lpm_width = 1;
parameter lpm_avalue = "NULL";
parameter lpm_pvalue = "NULL";
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
input gate;
output [lpm_width - 1:0] q;
input aset;
input aclr;
......
endmodule
158
Warp User’s Guide
LPM
Description
datai
X
L
H
gate
L
H
H
aset
L
L
L
aclr
X
L
L
X
X
H
L
X
X
X
X
L
H
H
H
qi
qi
L
H
lpm_avaluei if
present else H
L
L
Aset sets q to the value of lpm_avalue if that generic is present; otherwise, Aset sets q to
all ‘1’s. If the lpm_avalue is present, then aclr cannot be used. Aclr sets the value of q to
all ‘0’s.
Gate and q are the only required ports; all others are optional. If data is not used, then
aset or aclr must be used.
Testenab, testin and testout are not incorporated for this component. The lpm_pvalue and
lpm_hint are not used in the architecture.
Warp User’s Guide
159
7
LPM
7
7.2.16
MFF
Module Flip-Flop Symbol
VHDL Entity Description
entity Mff is
generic(lpm_width
lpm_fftype
lpm_avalue
lpm_svalue
lpm_pvalue
lpm_hint
port(data
clock
enable
q
aset
aclr
aload
sset
sclr
sload
testenab
testin
testout
end Mff;
160
: positive;
: fflop_type;
: string;
: string;
: string;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic;
: out std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic);
Warp User’s Guide
LPM
7
Verilog Module Description
module mff (data, clock, enable, q, aset, aclr, aload, sset, sclr, sload,
testenab, testin, testout);
parameter lpm_width = 1;
parameter lpm_fftype = `LPM_DFF;
parameter lpm_avalue = "NULL";
parameter lpm_svalue = "NULL";
parameter lpm_pvalue = "NULL";
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
input clock;
input enable;
output [lpm_width - 1:0] q;
input aset;
input aclr;
input aload;
input sset;
input sclr;
input sload;
input testenab;
input testin;
output testout;
......
endmodule
Warp User’s Guide
161
LPM
Description
7
Asynch
Control
H
L
L
L
Synch
Control
X
H
H
L
datai
clock
enable
testenab
qi
X
X
X
X
X
L->H
L->H
L->H
X
L
H
X
L
L
L
L
L
L
L
L->H
H
L
L
L
H
L->H
H
L
L
L
X
L->H
H
H
Async value
No change
Sync value
No change
qi for
lpm_fflop_type =
lpm_tff
datai for
lpm_fflop_type=
lpm_dff
datai XOR qi for
lpm_fflop_type =
lpm_tff
datai for
lpm_fflop_type=
lpm_dff
qi-1, q0 <= testin
testout <= qlpm_width-1;
Aset sets q to the value of lpm_avalue if that generic is present; otherwise Aset sets q to
all ’1’s. If the lpm_avalue is present, then aclr cannot be used. Aclr sets the value of q to
all ’0’s. The same is true for sset and sclr with lpm_svalue. The load ports (aload and
sload) sets q to the value present on data. The clr is dominant over the set if both are
asserted simultaneously for both synchronous and asynchronous operations.
The required ports on this component are data, clock, and q, all others are optional.
Testenab, testin and testout are optional; testenab and testin have a default value of ’0’
if they are not used on the symbol. Either all or none of the test ports must be connected.
The lpm_pvalue and lpm_hint are not used in the architecture.
162
Warp User’s Guide
LPM
7.2.17
MSHFTREG
7
Module Shift Register Symbol
VHDL Entity Description
entity Mshftreg is
generic(lpm_width
lpm_direction
lpm_avalue
lpm_svalue
lpm_pvalue
lpm_hint
port(data
clock
enable
shiftin
load
q
shiftout
aset
aclr
sset
sclr
testenab
testin
testout
end Mshftreg;
Warp User’s Guide
: positive;
: shdir_type;
: string;
: string;
: string;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic_vector((lpm_width-1)
downto 0);
: out std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic);
163
LPM
Verilog Module Description
7
module mshiftreg (data, clock, enable, shiftin, load, q, shiftout, aset, aclr,
sset, sclr, testenab, testin, testout);
parameter lpm_width = 2;
parameter lpm_direction = `LPM_LEFT;
parameter lpm_avalue = "NULL";
parameter lpm_svalue = "NULL";
parameter lpm_pvalue = "NULL";
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
input clock;
input enable;
input shiftin;
input load;
output [lpm_width - 1:0] q;
output shiftout;
input aset;
input aclr;
input sset;
input sclr;
input testenab;
input testin;
output testout;
......
endmodule
164
Warp User’s Guide
LPM
Description
Asynch
Control
H
L
L
L
L
L
L
Synch
Control
X
H
H
L
L
L
L
7
clock
enable
load
testenab
qi
X
L->H
L->H
L,H
L->H
L->H
L->H
X
L
H
X
H
H
H
X
X
X
X
H
L
X
L
L
L
L
L
L
H
Async value
No change.
Sync value.
No change.
datai
qi-1, q0 <= shiftin
qi-1, q0 <= testin
shiftout <= qlpm_width-1;
testout <= qlpm_width-1;
Aset sets q to the value of lpm_avalue if that generic is present; otherwise Aset sets q to
all ’1’s. If the lpm_avalue is present, then aclr cannot be used. Aclr sets the value of q to
all ’0’s. The same is true for sset and sclr with lpm_svalue. The clr is dominant over the
set if both are asserted simultaneously for both synchronous and asynchronous operations.
The only required port on this component is clock, all others are optional. If enable is not
used on the symbol, its default value is ’1’. The default value for aset, aclr, aload, sset,
sclr, and sload is ’0’ if they are not used on the symbol. If aload or sload are used, then
there must be a data port. If data is not used, then aset or aclr must be used.
Testenab and testin have a default value of ’0’ if they are not used on the symbol. Either
all or none of the test ports must be connected.
The lpm_pvalue and lpm_hint are not used in the architecture.
Warp User’s Guide
165
LPM
7
7.3
7.3.1
Other Cypress Modules
MPARITY
Module Parity Symbol
ODD
LPM_WIDTH = 8
8
EVEN
LPM_HINT = SPEED
VHDL Entity Description
entity Mparity is
generic(lpm_width: positive;
lpm_hint: goal_type);
port(data: instd_logic_vector((lpm_width-1) downto 0);
even: outstd_logic;
odd : outstd_logic);
end Mparity;
Verilog Module Description
module mparity (data, even, odd);
parameter lpm_width = 1;
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
output even;
output odd;
.......
endmodule
Description
even <= ‘1’ when #of 1’s is an even number.
odd <= ‘1’ when #of 1’s is an odd number.
166
Warp User’s Guide
LPM
7.3.2
MBUF
7
Module Buffer Symbol
VHDL Entity Description
entity Mbuf is
generic(lpm_width
lpm_hint
port(data
result
: positive;
: goal_type);
: in std_logic_vector((lpm_width-1)
downto 0);
: out std_logic_vector((lpm_width-1)
downto 0));
end Mbuf;
Verilog Module Description
module mbuf (data, result);
parameter lpm_width = 1;
parameter lpm_hint = `SPEED;
input [lpm_width - 1:0] data;
output [lpm_width - 1:0] result;
......
endmodule
Description
result <= data;
This component represents an expandable buffer. Its size is determined by lpm_width.
The lpm_hint value is not used in the architecture.
Warp User’s Guide
167
LPM
7
7.3.3
MGND
Module Ground Symbol
VHDL Entity Description
entity Mgnd is
generic(lpm_width
port(x
: positive);
: out std_logic_vector((lpm_width-1)
downto 0));
end Mgnd;
Verilog Module Description
module mgnd (x);
parameter lpm_width = 1;
output [lpm_width - 1:0] x;
......
endmodule
Description
x <= (OTHERS => ‘0’);
This component represents an expandable ground. Its size is determined by lpm_width.
168
Warp User’s Guide
LPM
7.3.4
MVCC
7
Module VCC Symbol
VHDL Entity Description
entity Mvcc is
generic(lpm_width
port(x
: positive);
: out std_logic_vector((lpm_width-1)
downto 0));
end Mvcc;
Verilog Module Description
module mvcc (x);
parameter lpm_width = 1;
output [lpm_width - 1:0] x;
......
endmodule
Description
x <= (OTHERS => ‘1’);
This component represents an expandable VCC. Its size is determined by lpm_width.
Warp User’s Guide
169
LPM
7
7.3.5
IN
Module In Marker
Description
This is an expandable INPUT marker to be used on signals that have mode of IN. Its size
is determined by lpm_width.
170
Warp User’s Guide
LPM
7.3.6
OUT
7
Module Out Marker
Description
This is an expandable OUTPUT marker to be used on signals that have mode of OUT. Its
size is determined by lpm_width.
Warp User’s Guide
171
LPM
7
7.3.7
TRI
Module Three-state Marker
Description
This is an expandable THREE-STATE marker to be used on signals that have mode of
INOUT. Its size is determined by lpm_width.
172
Warp User’s Guide
LPM
7.4
Cypress Exceptions to LPM Standard
7.4.1
7
Which Options of LPM Do We Support?
The LPM specification is written so that many features can be implemented without
forcing all implementations to be identical. This feature is made possible by using a large
number of optional parameters and behaviors in the architectures of the components.
The following is a summary of Cypress’ implementation of those options in the LPM
library:
•
LPM_POLARITY -in Release 5.0, only the MAND, MOR, and MXOR will have
selectable polarity.
•
LPM_HINT - this property is vendor unique and is used to specify a synthesis guide. It
can take the value of SPEED (default), AREA, or COMBINATORIAL.
•
LPM Values - the value properties used in the Cypress LPM library are implemented
as strings.
•
Async operations - the exceptions for asynchronous operations are noted by the fitter
during compilation.
•
Scan Test - all appropriate Cypress LPM library components will have the scan test
feature available. The only exception is the MLATCH component.
•
The following LPM components have no equivalent in the Cypress LPM library:
• LPM_RAM_DQ
• LPM_RAM_IO
• LPM_ROM
• LPM_TTABLE
• LPM_FSM
• LPM_INPAD
• LPM_OUTPAD
• LPM_BIPAD
Warp User’s Guide
173
LPM
7
7.5
Hints and Techniques
7.5.1
How to Best Use the LPM_HINT
The Cypress LPM library includes a few components that may be implemented with the
optional LPM_HINT attribute. This attribute can be set to the values of SPEED, AREA
and COMBINATORIAL. Although this “hint” is used in many ways for module
generation, there are only two components affected by it in the LPM library. Those
components are:
•
MADD_SUB for CPLDs
•
MCOUNTER for CPLDs
The following sections describe the differences obtained for area and speed for example
design components.
The device used for these examples is the CY7C375.
Note – These values are only a guideline and are extremely dependent
upon the particular implementation. Any circuitry added before or after
these components will affect the synthesis of the component.
174
Warp User’s Guide
LPM
7.5.2
MADD_SUB
7
Table 7-1 Results for CY7C375
Design
Name
AREA
SPEED
Comments
PTs
MCs
Passes
PTs
MCs
Passes
ADD1/
SUB1
7
2
1
7
2
1
ADD4/
SUB4
46
6
2
46
8
2
ADD8/
SUB8
92
12
4
95
18
3
ADD16/
SUB16
184
24
8
205
38
3
ADD24/
SUB24
276
36
12
331
58
3
ADD32/
SUB32
368
48
16
473
78
3
Warp User’s Guide
Designs
include
carry-in &
carry-out
175
LPM
7
7.5.3
MCOUNTER
Table 7-2 Results for CY7C375
AREA
SPEED
Design Name
Comments
PTs
PTs
MCs
Passes
UPCNTR1/
DNCNTR1
4
2
1
UPCNTR4/
DNCNTR4
13*
5
1
25*
9
1
UPCNTR16/
DNCNTR16
49*
17
1
UPCNTR24/
DNCNTR24
73*
25
1
97*
33
1
UPCNTR8/
DNCNTR8
UPCNTR32/
DNCNTR32
176
MCs
Passes
Same as SPEED
98*
34
2
Designs
include
load, enable,
and carryout.
* Down
counters use
one fewer
product
term.
Warp User’s Guide
Chapter
8
Simulation
8
Simulation
8.1
VHDL Simulation
Warp supports pre-synthesis VHDL simulation and post-synthesis VHDL simulation. The
supported VHDL simulators are listed in Table 8-1. In order to simulate the design, the
user should be familiar with the desired simulation environment.
Table 8-1 Supported VHDL simulators
Simulator
Vendor
Pre-/Post-synthesis
ViewSim ™
Viewlogic
Post-synthesis
SpeedWave ™
Viewlogic
Pre-/Post-synthesis
V-System™ /QuickHDL™
Model Technology/
Mentor Graphics
Pre-/Post-synthesis
IEEE1164 VHDL
Any
Pre-/Post-synthesis
8
178
Warp User’s Guide
Simulation
8.1.1
VHDL Pre-synthesis Simulation
The Cypress specific pre-synthesis packages are available in $CYPRESS_DIR/lib/prim/
presynth (%CYPRESS_DIR%\lib\prim\presynth on PCs). The BIT type packages are in
the sub-directory bit and STD_LOGIC type packages are in the sub-directory std. The
IEEE packages (stdlogic, numeric_bit and numeric_std) are available in the sub-directory
ieee. Scripts to compile these packages into the current directory are available in scripts
sub-directory. Before running pre-synthesis simulation, the appropriate Cypress library
(BIT type or STD_LOGIC type) needs to be built using the above mentioned scripts.
The BIT or STD_LOGIC type scripts compile the packages into a library whose name is
cypress and location is cypress (cypress.lib for SpeedWave) sub-directory in the current
directory.
We recommend to use simulator vendor supplied IEEE libraries because usually they are
accelerated versions of original IEEE libraries. Cypress supplied IEEE libraries need not
be compiled unless IEEE libraries are not already provided by the simulator vendor. The
IEEE type scripts compile the IEEE packages into a library whose name is ieee and
location is cyieee (cyieee.lib for SpeedWave) sub-directory in the current directory.
8
Warp User’s Guide
179
Simulation
8.1.2
Simulators
8.1.2.1
ModelT V-System
Build Cypress Specific Libraries:
In order to simulate a VHDL design, Cypress specific libraries need to be built into the
current directory. On UNIX platforms, to build the complete library for STD_LOGIC
types, run the following command:
$CYPRESS_DIR/lib/prim/presynth/scripts/vsys_std
Similarly, to build the complete library for BIT types, run the command:
$CYPRESS_DIR/lib/prim/presynth/scripts/vsys_bit
On PCs, invoke the V-System, pull down the File->Directory and select the directory in
which the library is to be compiled. Then in the Transcript window, the following is
entered (note the “do” command) to build STD_LOGIC library:
do %CYPRESS_DIR%\lib\prim\presynth\scripts\vsys_std
To build BIT type library, enter the following command in the Transcript window.
do %CYPRESS_DIR%\lib\prim\presynth\scripts\vsys_bit
Simulate the Target Design:
Before simulating the design make sure that the cypress library path cypress is included in
the library search file.The target design can be analyzed (vcom) and simulated (vsim) with
commands such as the following:
vcom -93 <design>.vhd
vsim -do <design_command_file> <design>
Refer to V-System user's guide for details of V-System commands.
8
If the user already has command files written for ViewSim or SpeedWave (.cmd), they can
be easily converted to V-System (.do) files. In order to make this conversion seamless, the
user must not use the shorthand commands for ViewSim (for example, a for assign, c for
cycle, l for low, h for high). If the longhand conventions are used, they map directly to the
.do file syntax.
8.1.2.2
SpeedWave
Warp directly integrates into Viewlogic’s Powerview and Workview Office
environments. Before running pre-synthesis simulation, make sure that Powerview/
Workview Office setup is completed as described in the installation chapter. You may
have to create a Viewlogic project before running SpeedWave.
180
Warp User’s Guide
Simulation
Build Cypress Specific Libraries:
In order to simulate a VHDL design, Cypress specific libraries need to be built into the
current directory. Use the following commands to build the libraries for your platform.
UNIX Platform:
$CYPRESS_DIR/lib/prim/presynth/scripts/spwv_std
$CYPRESS_DIR/lib/prim/presynth/scripts/spwv_bit
PC Platforms:
%CYPRESS_DIR%\lib\prim\presynth\scripts\spwv_std
%CYPRESS_DIR%\lib\prim\presynth\scripts\spwv_bit
Simulate the target design:
Before simulating the design make sure that the cypress library path cypress.lib is
included in the library search file (default vsslib.ini).
The target design can be analyzed and simulated using the Powerview cockpit icons
VhdlMngr, VhdlAnlz, SpeedWave or the Workview Office tool bar menu button
SpeedWave. In Powerview VhdlMngr is used to create the library search file, VhdlAnlz is
used to analyze the design and SpeedWave is used to simulate the design.
In Workview Office, double clicking on the SpeedWave button brings up the SpeedWave
window. Then the VHDL design can be loaded using File->Load VHDL Design dialog
box and the command file can be loaded using File->Run Command File dialog box.
Refer to Fusion/SpeedWave on-line help for more details.
On UNIX platforms, the target design can also be analyzed (analyze) and simulated
(fusion) with commands such as the following:
analyze -src <design>.vhd -dbg 2 -libfile
<library_search_file>
fusion -cmd <command_file> -vhdl -cfg <configuration_name> libfile <library_search_file>
Warp User’s Guide
181
8
Simulation
If the user already has command files for ViewSim, they can be used with SpeedWave
with minor changes. All port signals must be prefixed with a / in the SpeedWave
command file. This change is not backward compatible with ViewSim. SpeedWave does
not support the vector and check commands.
Note – SpeedWave loads a VHDL module only by means of a
configuration block. So in order to simulate a design using SpeedWave,
the input vhdl file should have a configuration block, which could be an
empty configuration block like the example shown below.
configuration <config_name> of <entity> is
for <architecture>
end for;
end <config_name>;
Note – SpeedWave is not VHDL-93 compliant.
8.1.2.3
Other Simulators
For any other IEEE1164 VHDL compliant simulators, compile the packages in
$CYPRESS_DIR/lib/prim/presynth/std or $CYPRESS_DIR/lib/prim/presynth/bit (on PCs,
%CYPRESS_DIR%\lib\prim\presynth\std or %CYPRESS_DIR%\lib\prim\presynth\bit)
into a Cypress library and the VHDL design file into your work library and simulate using
the target simulator commands.
8
182
Warp User’s Guide
Simulation
8.1.3
VHDL Post-synthesis Simulation
8.1.3.1
TestBenches and Post-Synthesis Simulation
Creating a testbench for verifying a design is an important aspect of the design flow. Warp
can optionally preserve the top level ports of the design so that simulation can be
performed before and after synthesis with the same HDL code driving the two different
models. This driver HDL code is called the test bench. However, there are certain
conventions that the design must comply with to achieve the testbench methodology.
These conventions are derived from either the way synthesis is performed, or the
capabilities of the HDL languages (VHDL or Verilog), or due to the way the device is
modeled.
To enable the preservation of the top level entity ports, use the Enable Testbench Output
in the Generic dialog box of Galaxy or use the command-line option -yu.
When the testbench feature is enabled, the way synthesized names are generated can
differ. This can cause compatibility problems with Warp releases prior to Release 4.2. Let
us assume that we have the following port map in the top level entity:
my_port : in std_logic_vector(1 downto 0) ;
Without the testbench feature enabled and in the pre R4.2 version of Warp, the vector
my_port would have been split into the following two signals:
my_port_1 my_port_0
However, with the testbench feature enabled, these signal names are as created as follows:
my_port(1) my_port(0)
Normally, this would not cause a problem except where the control file is concerned. If
your design has a control file and it is setting synthesis directives for the signals
my_port_1 and/or my_port_0 and the testbench feature is enabled, these directives do not
have any effect because these names are never generated by the synthesis. When using the
testbench feature, synthesis directives should use the names my_port(1) and/or
my_port(0). Such names can be used on all signals (whether they are the top level ports or
not).
Warp User’s Guide
183
8
Simulation
The top level design must adhere to the following conventions for easy use of testbenches.
•
All the top level ports must be of type std_logic or std_logic_vector. Other types
including multi-dimensional arrays may not work because certain languages/
simulators (like Verilog) may not have support for such constructs.
•
Only port modes of IN and INOUT are supported. Other port modes are automatically
converted to INOUT. Normally, you do not have to change your test bench even if you
use other port modes in your top level entity. In most cases, this does not require the
testbench code to be modified even if your original source entity has other port modes.
•
If your top level entity has integer types, they are converted to a std_logic_vector type
that is big enough to contain the range of the integer. This port has the suffix _IBV.
This implies that a change will have to be made to your testbench to accommodate
this. If your original entity contained the following port:
my_int : in integer range 0 to 15 ;
for VHDL it is converted to:
my_int_IBV : in std_logic_vector(3 downto 0) ;
for Verilog it is converted to:
input [3:0] my_int_IBV ;
•
If your top level entity has enumerated types (for state machines), they are converted
to std_logic_vector type that is big enough to contain the state encoding for the same.
This port will have a suffix _SBV. This implies that a change will have to be made to
your testbench to accommodate this.
If your original entity contained the following port:
type state_type is (s0, s1, s2, s3) ;
my_state : inout state_type ;
8
for VHDL it is converted to:
my_state_SBV : inout std_logic_vector(0 to 1) ;
for Verilog it is converted to:
inout [0:1] my_state_SBV ;
184
•
Types such as bit, bit_vector, boolean are all converted to their respective std_logic
types. In most cases, it is not possible to model the post-synthesis models with such
types.
•
The top level entity name should match the top level design file basename. This allows
testbenches to work across all devices and simulators.
Warp User’s Guide
Simulation
•
All ports are output in lower-case, except for the suffixes added by synthesis to
accommodate integers and enumerated types. This is important for designs utilizing
Verilog as the post-synthesis simulation vehicle.
•
The order of ports is preserved. However, the lines that create multiple ports on a
single statement are broken up into individual ports. For example, if the original port
description looked like:
port (a, b : inout std_logic_vector (3 downto 0)) ;
The post-synthesis model’s entity would have:
port (a : inout std_logic_vector (3 downto 0) ;
b : inout std_logic_vector (3 downto 0)) ;
•
8.1.3.2
Warp supports generics at the top level. During synthesis, the current value of the
generic is used but it is not output for post-layout simulation. However, if the
generic is used in expressions, their values are substituted and the resultant
expression is valuated, which produces a value that is actually used during synthesis
and output.
Post-synthesis Simulation of PLDs and CPLDs
For post-synthesis simulation, Warp adheres to the following methodology: it generates
all the VHDL and Verilog files required to simulate the design, and provides an easy way
to compile these HDL (Hardware Description Languages) files within the target
simulation environment. The design flow for the post-synthesis simulation of Cypress
PLD and CPLD devices is shown in Figure 8-1.
8
Warp User’s Guide
185
Simulation
.
Select design and
simulator in Galaxy
Compile and synthesize
verilog files in vlg directory
vhdl files in vhd directory
Compile and simulate
in target simulation
environment
Figure 8-1 Post-Synthesis Simulation design flow for PLDs and
CPLDs
8.1.3.2.1
Select a Design and a Simulator
Select a design and a device from the galaxy window. The supported simulators are listed
in the Devices dialog box of the Galaxy window, under the Post-JEDEC Sim section.
Select the target device and package from the Device and Package menus, respectively,
and the simulator from the Post-JEDEC Sim menu. If you are using the Model T Verilog
simulator, select Verilog-XL as the target simulator.
8
8.1.3.2.2
Compile a Design
After selecting the design, target device, and simulator, compile the design from the
Galaxy window. Warp creates post-synthesis simulation model of the design in vhd (for
VHDL) or vlg (for Verilog) sub-directory. The vhd or vlg sub-directory is created
automatically if it does not already exist. The file name for the post-synthesis simulation
model will have the same base name as the top-level design file.
186
Warp User’s Guide
Simulation
8.1.4
Post-synthesis Simulators
8.1.4.1
ViewSim
Warp directly integrates into Viewlogic’s Powerview and Workview Office environments.
Viewsim can be run by double clicking on the ViewSim icon in the Powerview cockpit or
the Workview Office toolbar. In Workview Office, clicking on the ViewSim button brings
up the ViewSim window. Then pull-down the File->Load Vsm Netlist dialog box to load
viewsim netlist and pull-down File->Run Command File dialog box to load the command
file.
In Powerview the command file can be executed from Misc->Execute->Cmd dialog box
within the ViewSim window.
Refer to ViewSim on-line help for more details. You may have to create a Viewlogic
project before using ViewSim.
8.1.4.2
ModelT V-System
Build Cypress Primitive Library:
A script for compiling the Cypress post-synthesis primitive models is available in
$CYPRESS_DIR/lib/prim/presynth/scripts/vsysprim (on PCs,
%CYPRESS_DIR%\lib\prim\presynth\scripts\vsysprim). When this script is run, the
primitive models are compiled into a library with name primitive and physical location
cyprim sub-directory in the current directory.
On UNIX platforms, to build the complete primitives library, run the command:
$CYPRESS_DIR/lib/prim/presynth/scripts/vsysprim
On PCs, pull down the File->Directory and select the directory in which the library is to
be compiled. Then in the Transcript window the following is entered (note the “do”
command), type the command:
do %CYPRESS_DIR%\lib\prim\presynth\scripts\vsysprim
Simulate the Target Design:
Before simulating the design make sure that the primitive library path cyprim is included
in the library search file. Once the primitive library has been built, the target design can be
compiled (vcom) and simulated (vsim) with commands such as the following:
vcom -93 vhd\<file name>.vhd
vsim <entity name>
Warp User’s Guide
187
8
Simulation
Refer to V-System user’s guide for details of V-System commands.
8.1.4.3
SpeedWave
Before running post-synthesis simulation, make sure Powerview (on UNIX platforms) /
Workview Office (on PCs) setup is completed as described in the Installation chapter.
Build Cypress Primitive Libraries:
A script for compiling the Cypress post-synthesis primitive libraries into current directory
is available in $CYPRESS_DIR/lib/prim/presynth/scripts/spwvprim. When this script is
run, the primitive models are compiled into a library with logical name primitive and
physical location cyprim.lib sub-directory in the current directory. Build the complete
primitives library using the appropriate command for your platform:
UNIX Platforms:
$CYPRESS_DIR/lib/prim/presynth/scripts/spwvprim
PC Platforms:
%CYPRESS_DIR%\lib\prim\presynth\scripts\spwvprim
Simulate the Target Design:
Before simulating the design make sure that the primitive library path cyprim.lib is
included in the library search file (default vsslib.ini). Once the primitive library has been
built, the target design can be analyzed and simulated using the Powerview cockpit icons
VhdlMngr, VhdlAnlz, SpeedWave or Workview Office tool bar menu button SpeedWave.
In Powerview VhdlMngr is used to create the library search file, VhdlAnlz is used to
analyze the design and SpeedWave is used to simulate the design.
8
In Workview Office, double clicking on the SpeedWave button brings up the SpeedWave
window. Then the VHDL design can be loaded using File->Load VHDL Design dialog
box and the command file can be loaded using File->Run Command File dialog box.
Refer to Fusion/SpeedWave on-line help for more details.
On UNIX platforms, the target design can also be analyzed (analyze) and simulated
(fusion) with commands such as the following:
analyze -src vhd/<design>.vhd -dbg 2 -libfile
<library_search_file>
fusion -cmd <command_file> -vhdl -eac <entity> -libfile
<library_search_file>
188
Warp User’s Guide
Simulation
If the user already has command files for ViewSim, they can be used with SpeedWave
with minor changes. All port signals must be prefixed with a / in the SpeedWave
command file. This change is not backward compatible with ViewSim.
8.1.4.4
Other Simulators
For any other IEEE 1164 VHDL compliant simulators, compile the packages in
$CYPRESS_DIR/lib/prim/vhdl (on PCs, %CYPRESS_DIR%\lib\prim\vhdl) into your
primitive library, compile the post-synthesis simulation model in vhd sub-directory into
your work directory and simulate using the target simulator commands. The proper order
of compiling these files can be obtained by looking at one of the scripts in
$CYPRESS_DIR/lib/prim/presynth/scripts/*prim (on PCs,
%CYPRESS_DIR%\lib\prim\presynth\scripts\*prim).
8
Warp User’s Guide
189
Simulation
8.2
Verilog Simulation
Warp supports pre-synthesis VHDL simulation and post-synthesis VHDL and Verilog
simulation. The supported Verilog simulators are listed in Table 8-2. In order to simulate
the design, the user should be familiar with the desired simulation environment.
Table 8-2 Supported Verilog simulators
8.2.1
Simulator
Vendor
Pre-/Post-synthesis
VeriBest ™
Intergraph
Post-synthesis
VCS ™
Viewlogic
Post-synthesis
Verilog-XL ™
Cadence
Post-synthesis
V-System™
Model Technology/
Mentor Graphics
Post-synthesis
IEEE1364 Verilog
Any
Post-synthesis
Verilog Pre-synthesis Simulation
When a Verilog simulator is selected, Warp creates Cypress specific post-synthesis
primitive models, a post-synthesis simulation model of the design and a template file in
the vlg sub-directory. The template file assists the user in submitting the correct set of
Verilog files, in the proper order, to the target Verilog compiler. The steps needed to
simulate the design in different simulator environments are described below.
With the release of Warp 5.0, synthesis of Verilog source designs has been made possible.
Although Cypress does not at this time provide a Verilog simulator, they have provided
some system files necessary for third party simulators to provide pre-synthesis
simulations.
8
Warp uses two source files to accomplish the synthesis of Verilog designs. These files are
located at $CYPRESS_DIR/lib/common. The first file lpm.v is used to define certain
values for the parameters used by the LPM models in the library. The second file rtl.v is
used to define various primitives used by the synthesis engine to map to the internal
architecture of the targeted devices.
When using these models for synthesis, the following lines must be present in the user’s
source design:
‘include “lpm.v”
‘include “rtl.v”
190
Warp User’s Guide
Simulation
The former is necessary to use the LPM modules and the latter to make use of the RTL
modules for inclusion in the user’s design. For pre-synthesis simulations, these lines must
also be included.
In the synthesis process the path to these files was specified with the -i switch on the Warp
command line (i.e.: -i$CYPRESS_DIR/lib/common). For Verilog simulators, this is
accomplished with the +incdir+ switch (i.e.: +incdir+$CYPRESS_DIR/lib/common or
+incdir+$CYPRESS_DIR/lib/prim/presynth/vlg). The latter example is valid since the
Verilog source files are also mirrored at $CYPRESS_DIR/lib/prim/presynth/vlg for
convenience and compatibility with the VHDL pre-synthesis file structure.
In addition to the lpm.v and rtl.v files, the file lpmsim.v is also used for pre-synthesis
simulations. It is not used by Warp in the synthesis process where the synthesis engine
uses models already defined and implemented. However, it is necessary for pre-synthesis
to describe the architecture of the modules.
Typically, the invocation of a simulator that utilizes these collections of modules would
be:
ModelSim/Verilog:
vlog +incdir+$CYPRESS_DIR/lib/common <testbench>.v
<testfile>.v
VeriWell:
veriwell -f <password_file> +incdir+$CYPRESS_DIR/lib/common
<testbench>.v <testfile>.v
The appropriate ‘include clause of course must be present in the user’s source code to
access the desired modules. The file lpm.v contains an ‘include clause that causes the
inclusion of the file lpmsim.v for designs that are not being synthesized by Warp.
8.2.2
Verilog Post-synthesis Simulation
8.2.2.1
Test Benches and Post-Synthesis Simulation
Creating a testbench for verifying a design is an important aspect of the design flow. Warp
can optionally preserve the top level ports of the design so that simulation can be
performed before and after synthesis with the same HDL code driving the two different
models. This driver HDL code is called the test bench. However, there are certain
Warp User’s Guide
191
8
Simulation
conventions that the design must comply with to accomplish the testbench methodology.
These conventions are derived from either the way synthesis is performed, or the
capabilities of the HDL languages (VHDL or Verilog), or due to the way the device is
modeled.
To enable the preservation of the top level entity ports, use the Enable Testbench Output
in the Generic dialog box of Galaxy or use the command-line -yu.
When the testbench feature is enabled, the way synthesized names are generated can
differ. This can cause compatibility problems with Warp releases prior to Release 4.2. Let
us assume that we have the following port map in the top level entity:
my_port : in std_logic_vector(1 downto 0) ;
Without the testbench feature enabled and in the pre R4.2 version of Warp, the vector
my_port would have been split into the following two signals:
my_port_1 my_port_0
However, with the testbench feature enabled, these signal names are as created as follows:
my_port(1) my_port(0)
Normally, this would not cause a problem except where the control file is concerned. If
your design has a control file and it is setting synthesis directives for the signals
my_port_1 and/or my_port_0 and the testbench feature is enabled, these directives do not
have any effect because these names are never generated by the synthesis. When using the
testbench feature, synthesis directives should use the names my_port(1) and/or
my_port(0). Such names can be used on all signals (whether they are the top level ports or
not).
8
192
Warp User’s Guide
Simulation
The top level design must adhere to the following conventions for easy use of testbenches.
•
All the top level ports must be of type std_logic or std_logic_vector. Other types
including multi-dimensional arrays may not work because certain languages/
simulators (like Verilog) may not have support for such constructs.
•
Only port modes of IN and INOUT are supported. Other port modes are automatically
converted to INOUT. Normally, you do not have to change your test bench even you
use other port modes in your top level entity. In most cases, this does not require the
testbench code to be modified even if your original source entity has other port modes.
•
If your top level entity has integer types, they are converted to a std_logic_vector type
that is big enough to contain the range of the integer. This port has the suffix _IBV.
This implies that a change will have to be made to your testbench to accommodate
this. If your original entity contained the following port:
my_int : in integer range 0 to 15 ;
for VHDL it is converted to:
my_int_IBV : in std_logic_vector(3 downto 0) ;
for Verilog it is converted to:
input [3:0] my_int_IBV ;
•
If your top level entity has enumerated types (for state machines), they are converted
to std_logic_vector type that is big enough to contain the state encoding for the same.
This port will have a suffix _SBV. This implies that a change will have to be made to
your testbench to accommodate this.
If your original entity contained the following port:
type state_type is (s0, s1, s2, s3) ;
my_state : inout state_type ;
8
for VHDL it is converted to:
my_state_SBV : inout std_logic_vector(0 to 1) ;
for Verilog it is converted to:
inout [0:1] my_state_SBV ;
•
Types such as bit, bit_vector, boolean are all converted to their respective std_logic
types. In most cases, it is not possible to model the post-synthesis models with such
types.
•
The top level entity name should match the top level design file basename. This allows
testbenches to work across all devices and simulators.
Warp User’s Guide
193
Simulation
•
All ports are output in lower-case, except for the suffixes added by synthesis to
accommodate integers and enumerated types. This is important for designs utilizing
Verilog as the post-synthesis simulation vehicle.
•
The order of ports is preserved. However, the lines that create multiple ports on a
single statement are broken up into individual ports. For example, if the original port
description looked like:
port (a, b : inout std_logic_vector (3 downto 0)) ;
The post-synthesis model’s entity would have:
port (a : inout std_logic_vector (3 downto 0) ;
b : inout std_logic_vector (3 downto 0)) ;
•
8.2.2.2
Warp supports parameters at the top level. During synthesis, the current value of
the parameter is used but it is not output for post-layout simulation. However, if the
parameter is used in expressions, their values are substituted and the resultant
expression is valuated, which produces a value that is actually used during synthesis
and output.
Post-synthesis Simulation of PLDs and CPLDs
For post-synthesis simulation, Warp adheres to the following methodology: it generates
all the VHDL and Verilog files required to simulate the design, and provides an easy way
to compile these HDL (Hardware Description Languages) files within the target
simulation environment. The design flow for the post-synthesis simulation of Cypress
PLD and CPLD devices is shown in Figure 8-3.
8
194
Warp User’s Guide
Simulation
.
Select design and
simulator in Galaxy
Compile and synthesize
verilog files in vlg directory
vhdl files in vhd directory
Compile and simulate
in target simulation
environment
Figure 8-3 Post-Synthesis Simulation design flow for PLDs and
CPLDs
8.2.2.3
Select a Design and a Simulator
Select a design and a device from the galaxy window. The supported simulators are listed
in the Devices dialog box of the Galaxy window, under the Post-JEDEC Sim section.
Select the target device and package from the Device and Package menus, respectively,
and the simulator from the Post-JEDEC Sim menu. If you are using the Model T Verilog
simulator, select Verilog-XL as the target simulator.
8.2.2.4
Compile a Design
After selecting the design, target device, and simulator, compile the design from the
Galaxy window. Warp creates post-synthesis simulation model of the design in vhd (for
VHDL) or vlg (for Verilog) sub-directory. The vhd or vlg sub-directory is created
automatically if it does not already exist. The file name for the post-synthesis simulation
model will have the same base name as the top-level design file.
Warp User’s Guide
195
8
Simulation
8.2.3
Post-synthesis Simulators
8
196
Warp User’s Guide
Simulation
8.2.3.1
Verilog-XL
The template file that Warp creates is design.fls. This file contains a list of verilog files
that need to be compiled in VerilogXL environment. To compile the Verilog files, run the
following command from vlg sub-directory:
verilog -s -f <design_name>.fls
The design is now ready for simulation in VerilogXL environment. Refer to VerilogXL
user’s guide, for details of VerilogXL commands.
8.2.3.2
VeriBest
The template file that Warp creates is design.sup. The format conforms to the support file
format within VeriBest (refer to the VeriBest simulator manual for details). Load the
support file into the VeriBest environment (File->Open_Setup_File) and select the
analyze command to compile. The design is now ready for simulation in the VeriBest
environment. Here is sample command sequence to compile and simulate.
% veribld
File->Open_Setup_File <design>.sup
Analyze
Simulate
// in the above, File, Analyze, Simulate are the
menu buttons in veribld
8.2.3.3
VCS
The template file that Warp creates is design.fls. This file contains the list of files and their
respective order to be compiled with the Verilog compiler. To compile the verilog design
files, run the following command from vlg sub-directory.
vcs -f <design>.fls
The design is now ready for simulation in VCS environment.
Note – Make sure that the vlg directory is in the search path of the
target simulator.
Warp User’s Guide
197
8
Simulation
8.2.3.4
Model T
The template file that Warp creates is design.fls. This file contains the list of files and their
respective order to be compiled with the Verilog compiler. To compile the Verilog design
files, run the following command from vlg sub-directory.
vlog -f <design>.fls
On the PC, run the above command from the transcript window.
8
198
Warp User’s Guide
Chapter
9
Report File
9
Report File
9.1
Introduction
This chapter provides an anatomy of the report file generated by Warp. The report file
generated by Warp has the same base name as the design VHDL/Verilog file but with an
.rpt extension. Interpreting the report file is very important and can help reduce the
amount of time spent debugging designs.
A report file is generated for every file that Warp compiles. If a design is split up among
multiple files, the report file that will probably be most useful is the one for the top level
design.
9
The report file can be broken down into three main sections:
•
Front End Compiler section
•
Front End Synthesis and Optimization section
•
CPLD/PLD Fitting section
The Front End sections are common for all devices.
In conjunction with this section, see Appendix A, Error Messages.
9.2
Front End Compiler
9.2.1
VHDL Front End
Warp is essentially a combination of multiple tools that perform various functions. They
are run in the following order:
•
front end (VHDLFE and TOVIF)
•
synthesis and optimization (TOPLD)
•
fitting (PLA2JED, MAX2JED or C37XFIT)
This section describes the VHDLFE and the TOVIF tools.
After the initial Copyright information is printed, the file being compiled is listed along
with the current set of options in effect. The first tool that runs on a design is the VHDL
parser (called VHDLFE). VHDLFE first associates the symbolic VHDL library work with
a given device. This is a very important step for subsequent phases to produce optimal or
correct implementations of the design for the device being targeted. VHDLFE then parses
the VHDL file and reports any direct external references (libraries, packages, etc.) that are
being made from the current VHDL file.
200
Warp User’s Guide
Report File
VHDLFE’s (parser) main function is to parse or read the VHDL file and check for syntax
errors and a few semantic errors. A syntax check, which is strictly a grammatical check of
the VHDL, deals with the specification of the design. A semantic check, on the other
hand, deals with the meaning of the VHDL being interpreted. Some semantic errors can be
caught by the parser right away and are thus reported by the VHDLFE program.
VHDLFE also reports one other important aspect of a design. VHDLFE detects all
datapath components of a design (essentially VHDL operators that perform math or
comparisons). If these messages do not appear and the design uses these operators, then
more than likely the user has his own implementations for these operators or the user is
NOT using the proper math libraries for device optimized implementations of datapath
operators. Although these messages about datapath operators are informational, the user
should be concerned if they do not appear when non-constant operations are in his design.
Once the VHDL has been found to be syntactically error free, the VHDL file goes through
high level synthesis, and the components of the VHDL file (packages, functions, entities,
architectures, etc.) are then converted to an intermediate format (an expression tree) that
can be translated into simple equations and registers (RTL components and equations) in
the next phase of Synthesis and Optimization. The program that performs this functions
called TOVIF, where VIF is an acronym for VHDL Intermediate Format. When designs
are composed of multiple files and external references, it is important to note what
files/directories are being reported. A common error in compiling libraries is including
multiple files that define VHDL components with identical names. When this happens,
Warp only uses the last file that was compiled.
9.2.2
Verilog Front End
Warp is essentially a combination of multiple tools that perform various functions. They
are run in the following order:
•
front end (VLOGFE and TOVIF)
•
synthesis and optimization (TOPLD)
•
fitting (PLA2JED, MAX2JED or C37XFIT)
This section describes the VLOGFE and the TOVIF tools.
After the initial Copyright information is printed, the file being compiled is listed along
with the current set of options in effect. The first tool that runs on a design is the Verilog
parser (called VLOGFE). VLOGFE first associates the symbolic Verilog library work
with a given device. This is a very important step for subsequent phases to produce
optimal or correct implementations of the design for the device being targeted. VLOGFE
then parses the Verilog file and reports any direct external references (libraries, packages,
etc.) that are being made from the current Verilog file.
Warp User’s Guide
201
9
Report File
VLOGFE’s (parser) main function is to parse or read the Verilog file and check for syntax
errors and a few semantic errors. A syntax check, which is strictly a grammatical check of
the Verilog, deals with the specification of the design. A semantic check, on the other
hand, deals with the meaning of the Verilog being interpreted. Some semantic errors can
be caught by the parser right away and are thus reported by the VLOGFE program.
VLOGFE also reports one other important aspect of a design. VLOGFE detects all
datapath components of a design (essentially Verilog operators that perform math or
comparisons). If these messages do not appear and the design uses these operators, then
more than likely the user has his own implementations for these operators or the user is
NOT using the proper math libraries for device optimized implementations of datapath
operators. Although these messages about datapath operators are informational, the user
should be concerned if they do not appear when non-constant operations are in his design.
9
Once the Verilog has been found to be syntactically error free, the Verilog file goes
through high level synthesis, and the components of the Verilog file (packages, functions,
entities, architectures, etc.) are then converted to an intermediate format (an expression
tree) that can be translated into simple equations and registers (RTL components and
equations) in the next phase of Synthesis and Optimization. The program that performs
this functions called TOVIF, where VIF is an acronym for Verilog Intermediate Format.
When designs are composed of multiple files and external references, it is important to
note what files/directories are being reported. A common error in compiling libraries is
including multiple files that define Verilog components with identical names. When this
happens, Warp only uses the last file that was compiled.
202
Warp User’s Guide
Report File
The following is an example of a Report File for this section:
| | | | | | |
_________________
-|
|-|
|Copyright and version information
-|
|-|
CYPRESS
|-|
|-|
|- Warp VHDL Synthesis Compiler:Version 4 IR x49
-|
|- Copyright (C) 1991, 1992, 1993,
|________________|
1994, 1995, 1996 Cypress Semiconductor
| | | | | | |
============================================================
Compiling: cpu.vhd
Options:
-d c374 -fo -o2 cpu.vhd
============================================================
vhdlfe V4 IR x49: VHDL parser
Sun Jan 21 11:33:35 1996
9
File and options
Date and time of compilation
Library ‘work’ => directory ‘lc374’
Library ‘ieee’ => directory ‘c:\warp\lib\ieee\work’
External references
Using ‘c:\warp\lib\ieee\work\stdlogic.vif’.
Using ‘c:\warp\lib\common\stdlogic\mod_gen.vif’.
cpu.vhd (line 209, col 47): Note: Substituting module ‘warp_cmp_2s_ss’ for ‘=’.
cpu.vhd (line 209, col 70): Note: Substituting module ‘warp_add_2s_ss’ for ‘+’.
cpu.vhd (line 211, col 48): Note: Substituting module ‘warp_add_1s1c_ss’ for ‘+’
vhdlfe:
No errors.
Operator inferencing
tovif V4 IR x49: High-level synthesis
Sun Jan 21 11:34:01 1996
Using ‘c:\warp\lib\common\stdlogic\mod_gen.vif’.
Using ‘c:\warp\lib\common\stdlogic\fdec.vif’.
Using ‘c:\warp\lib\common\stdlogic\finc.vif’.
tovif:
9.3
High level synthesis
No errors.
Front End Synthesis and Optimization
The next phase the VHDL design file goes through is called “Synthesis and
Optimization”. The program that performs this function is called TOPLD. In this phase,
intermediate level constructs (like expression trees, sub-components) are flattened and
converted into their simplest forms (registers, equations, three-state buffers, etc.). The
exact form depends on the features provided by the device being targeted.
One of the most important functions this phase performs is state machine synthesis. State
machines are typically specified in VHDL using enumerated types and encoding schemes.
For every state machine detected, its encoding is printed.
Warp User’s Guide
203
Report File
Since this phase also flattens any hierarchical components being referenced from other
VIF files, the report file includes this information. The following is an example of a report
file targeting a CPLD/PLD.
topld V4 IR x49: Synthesis and optimization
Sun Jan 21 11:35:17 1996
State variable, number of bits
State variable ‘cpu_state’ is represented by a Bit_vector (0 to 1).
State encoding (sequential) for ‘sd_state’ is:
sreset :=
b”00” ;
idle :=
b”01” ;
State
add :=
b”10” ;
compare :=
b”11” ;
Using ‘c:\warp\lib\lc370\stdlogic\c370.vif’.
9
encoding
------------------------------------------------------Alias Detection
------------------------------------------------------------------------------------------------------------Aliased 174 equations, 334 wires.
-------------------------------------------------------
Optimization
------------------------------------------------------Circuit simplification
------------------------------------------------------------------------------------------------------------Circuit simplification results:
Deleted 100 equations/components.
Expanded 130 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
-------------------------------------------------------
Summary of optimization
Optimization involves various steps. The “Alias Detection” stage looks for redundant
equations and simple wires and eliminates them from the system. “Circuit Simplification”
collapses intermediate signals into their fanout (also called Virtual Substitution) and
eliminates unused equations. During virtual substitution, certain nodes could potentially
become very large. When such a condition is detected, it is made into a soft node (a node
that remains in the network), and the process continues. If soft nodes are created, they will
appear in the report file. If the Detailed Report file option is chosen in Galaxy, more
information will appear during Virtual Substitution and Alias Detection.
The process that follows after this stage depends on the architecture of the device being
targeted. See the following two sections for more information.
204
Warp User’s Guide
Report File
9.4
CPLD/PLD Fitting
9.4.1
Technology Mapping and Optimization
The last thing TOPLD does is to output a PLA file that is then processed by the fitter. The
fitter is really more than just a Place and Route tool. Its responsibilities include optimizing
and technology mapping the equations to reduce resource utilization before actual Place
and Route can begin.
The optimization phase is conducted in many phases depending upon the options that are
currently in effect and the nature of the design. Optimization is conducted by two
programs called DSGNOPT and MINOPT. DSGNOPT can be considered as the decision
maker and MINOPT as the optimizer.
The first phase of DSGNOPT reduces the design by removing any equations or wires that
can be expanded into their fanout. DSGNOPT also determines if there are any equations
that need to be converted to nodes. (A node is an equation that will require a macrocell
resource). Among other things, DSGNOPT also performs the following functions:
•
technology mapping (converts all equations to a form supported by the PLD being
targeted)
•
register optimization (selects the best of D-type or T-type implementations)
•
polarity optimization (selects the best of Active High and Active Low
implementations
•
sum-splitting (equations too large for a macrocell are split)
•
global resource reduction (for global resources like resets/presets, tries to adjust the
equations to minimize these resources)
The types of optimizations depends on the device being targeted. For example, certain
PLDs do not support a T-type flip-flop. This means that Register Optimization is not
performed.
Warp User’s Guide
205
9
Report File
9.4.2
Equations
After all the different phases of DSGNOPT, the actual fitter or Place and Route tool is
finally invoked. The exact fitter depends on the type of device being targeted. The
FLASH370 family of devices requires the C37XFIT; the MAX340 family requires
MAX2JED; and all other PLDs require PLA2JED. All of these fitters use the exact same
conventions in their report files, but the exact content depends on the design and the
device.
The first thing any of the aforementioned fitters do is print the final equations. This is
probably the most important part of a report file for debugging a design. To help
understand this portion of the report file, the user will have to understand how equations or
macrocells operate in the particular fitter. Typically, a macrocell has many features. Some
of these include an asynchronous preset, asynchronous reset, output enable, etc. The fitter
also treats the I/O cells (with or without and output enable) simply as a feature of a
macrocell. Each feature of the macrocell is given a one to two letter acronym. Each
equation printed in the report file is expected to be mapped to a particular macrocell and is
actually printed as a group of equations with a common base-name which represents the
name of a macrocell. For example, the following represents an equation for one macrocell
“bterr” which is currently using four features of the macrocell:
9
bterr.D =
b_stateSBV_0.Q * /b_stateSBV_3.Q
bterr.AP =
GND
bterr.AR =
/resetn
bterr.C =
tclock
The conventions used in printing the equations are as follows:
206
•
/ represents an inversion
•
* represents an AND function
•
+ represents an OR function
•
= is an assignment
•
VCC and GND represent constant logic values ’1’ and ’0’ respectively.
Warp User’s Guide
Report File
Table 9-1 describes the common extensions used to represent the various features of a
macrocell
Table 9-1 Common Report File Extensions
Extension
Meaning
Comment
No extension means combinatorial
output or input.
.C
Clock
.D
D-Type flip-flop or Latch input
Requires a .C
.T
T-Type flip-flop input
Requires a .C
.AR,.AP
Asynchronous Reset/Preset
.SR,.SP
Synchronous Reset/Preset
.OE
Output Enable
.Q
Registered feedback from macrocell
.CMB
Combinatorial Feedback from
macrocell
.LH
Latch enable
.X1,.X2
Two inputs of an XOR
.DI
Latch/D-flip-flop input
latch/register
.QI
Feedback from input register/latch
.ARI,.API
Async. reset/preset for .DI
.SRI,.SPI
Sync. reset/preset for .DI
9
Used where there is an XOR in
front of the macrocell.
In the above table, certain combinations are illegal. For example, a macrocell will not be
allowed to be a D-type as well as a T-type. The number of features that are listed per
macrocell/equations depends on the design and the features of the device.
Warp User’s Guide
207
Report File
Sometimes equations may begin with a ‘/’. This indicates that the equation is considered
to be active low. This can happen due to one of two reasons:
•
The device may only support active low input to the feature. For example, AR in the
MAX340 devices must be active low.
•
During the DSGNOPT phase, the fitter determined that active low input requires fewer
resources.
Any inversions that exist for signals in the right hand side of the equation literally refer to
the active-low sense of the signal. This is important to note when a signal is being fed back
into the array and is being generated by a macrocell which is configured to be active low.
Consider the following two examples:
9
Example 1:
a =
c + d
b =
a.CMB * d
Example 2:
/a =
/c * /d
b =
a.CMB * d
The above two examples represent identical functionality. The first example is simple
with everything being active high. In the second example , a is being represented as an
active low signal; however, the signal b’s equation is not modified to compensate for this.
This is done so that when the user is examining b’s equation he does not have to consider
the polarity of each of its inputs. Depending upon the device and the macrocell features,
the fitter automatically adjusts the polarity during the routing phase. This convention also
insulates the equations from the all the various types of macrocells. For example, in some
macrocells, even though the D-input of a D-flip-flop can be generated in active low form
from the product term array, there might be a programmable inverter just before register,
which means that the macrocell might always have an active high output. In some other
devices, such an inverter is available after the macrocell feedback.
208
Warp User’s Guide
Report File
Note – Regardless of what polarity the fitter uses to implement the
individual equations, all outputs at the pins represent the design’s original intentions. This means that if a certain set of inputs should produce a
logic level ’0’ at the pin, that logic level will be preserved regardless of
whether the fitter produced an active low implementation or active high
implementation.
If a signal is being used in an equation and has no extension, it always means that this
signal is being fed into the product term directly from the PIN (Input or I/O). When
equations are too large to be implemented in a macrocell (for example, greater than 16
product terms for the FLASH370 family), such equations are split. Each of the sub
equations is named as prefix “S_n” where “n” is a unique number. When expanders are
produced for the MAX340 family, each of these expander terms is labelled “E_n” where
“n” is a number.
9.4.3
Fitting
After the equations are printed, the place and route phase begins. The exact message that
appears depends on the architecture of the device being targeted. These messages are
mostly informational. One of the actions that happen in this phase is the combination of a
buried node with an INPUT only signal. A buried node represents a signal that is assigned
to a macrocell but never routed to a PIN. When such signals are assigned to a macrocell
which in turn is connected to an I/O pin, the I/O pin can still be used as a pure input to the
design. The buried nodes are printed within parentheses with the INPUT PIN name
concatenated to it. For example, the phrase “(my_internal) my_input” implies that
“my_internal” is a buried node and “my_input” is an input pin sharing the same macrocell.
For small PLDs, the fitting stage is very simple and obvious. The FLASH370 family fitting,
however, deserves some explanation. Once the fitter determines a solution, it prints the
solution for each of the Logic Blocks and for the resources used by each Logic Block
individually. Since the FLASH370 family also uses a unique way of sharing product terms,
the report file also shows how these product terms are mapped.
The following is an example of one of the Logic Blocks placements printed by the
FLASH370 family fitter. “X” represents a product term (PT) in the PT array, and a “+”
represents an empty slot in the PT array. Since the product terms are shared, a “+” means
that the PT is unused for the current macrocell but could be in use by another neighboring
macrocell.
Warp User’s Guide
209
9
Report File
LOGIC BLOCK A PLACEMENT
Messages:
(11:43:47)
Macrocell number
Product term number
________________________________________________________________________________
1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(CUBEtmp3)trseln
Buried node with Input
XXXX++XX++XX++XX................................................................
| 1 |(buffer_1)
......+++X++++++++++++..........................................................
| 2 |eokn
eokn shares PTs with CUBEtmp3
..........XX++XX++XX++XXXX......................................................
| 3 |(syscmd_enb)
Buried node
..............+++++++++++++X++..................................................
| 4>|smdseln
Output with pin fixed
..................++++++++++++XXXX..............................................
| 5 |(bterr)
......................+++++++++++++X++..........................................
| 6 |cycerrn
..........................X+XX++++++++++++......................................
| 7 |(CUBEtmp1)
..............................++++++++X+++++++..................................
| 8 |smseln
Output with pin floating
..................................X+++++++++++++++..............................
| 9 |(CUBEtmp0)
......................................XXXX+XXXXX++++++..........................
|10 |smdman
..........................................X+++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |mioreqn
..................................................XX++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |[i/p]
Macrocell used as Input only
..........................................................++++++++++++++++......
|15 |(c_stateSBV_1)
................................................................XXXXXXXXXXX+++++
________________________________________________________________________________
9
Total count of outputs placed
Total count of unique Product Terms
Total Product Terms to be assigned
Max Product Terms used / available
= 13
= 45
= 55
= 50 /
80
= 62.5 %
In the map for the Logic Block above, the following lines are worth notice. The first
column of the Logic Block indicates the macrocell number within the Logic Block. If the
macrocell number has a “>” sign next to it (for example macrocell #4), the placement was
suggested or fixed by the user. Notice that the first macrocell has a buried node as well as
an input. For macrocell #8, the assignment of the signal was done by the fitter. Macrocell
#14 is being used as an input.
210
Warp User’s Guide
Report File
In the overall statistics for product term utilization, the “Total count of outputs place”
represents how many macrocells are in use for logic. This number comes out to be 13
because macrocells 11, 13 and 14 have no product terms assigned to them. The “Total
count of unique Product Terms” specify exactly that. The next item specifies the total
number of unique and non-unique product terms. The next line describes the number of
product terms actually used to implement the solution. In most cases, this matches the
total number of unique product terms. In this case, these numbers did not match because
the placement caused the sharing to be less than optimal, possibly due to the output enable
banking or other placement constraints.
The following extract from the report file represents the Logic Block from a device pinout standpoint (for example, pin #4 is eokn), and the signals on the left side of the diagram
indicate the inputs to the product term array and their positions within the Programmable
Interconnect Multiplexing unit.
Logic Block A
____________________________________________
|
|= >ad_26
|
|
|
|= >ad_27
|
|
|
|= >c_stateSBV_..
|
|
|
|= >sdrmready.Q
|
|
|
|= >smwrrdyn
| 3|=(CUBEtmp3)trseln
|
|= >ad_22
|
|
|
|= >dmardyn
(buffer_1) =|
|
|
|= >miogntn
|
|
|
|= >ad_23
| 4|= eokn
|
|> not used:94
|
|
|
|= >ad_25
(syscmd_enb) =|
|
|
|= >ad_28.Q
|
|
|
|= >ad_28
| 5|= smdseln
|
|= >CUBEtmp1.CMB
|
|
|
|> not used:99
(bterr) =|
|
|
|= >CUBEtmp0.CMB
|
|
|
|> not used:101
| 6|= cycerrn
|
|= >adhi_30
|
|
|
|= >dmardyn.Q
(CUBEtmp1) =|
|
|
|= >resetn
|
|
|
|> not used:105
| 7|= smseln
|
|= >smerrn
|
|
|
|= >b_stateSBV_..
(CUBEtmp0) =|
|
|
|= >ccrdyn
|
|
|
|= >syscmd_4
| 8|= smdman
|
|= >bt_count_2.Q
|
|
|
|= >bt_count_0.Q
not used:408 *|
|
|
|= >ad_24
|
|
|
|= >syscmd_enb.Q
| 9|= mioreqn
|
|= >c_stateSBV_..
|
|
|
|= >pvalidn
not used:410 *|
|
|
|= >adhi_31
|
|
|
|= >c_stateSBV_..
| 10|= syscmd_2
|
|> not used:118
|
|
|
|> not used:119
(c_stateSBV_1) =|
|
|
|= >smdseln.Q
|
|
|
|= >btrdy.Q
|
|
|
|> not used:122
|
|
|
|= >syscmd_3
|
|
____________________________________________
Warp User’s Guide
211
9
Report File
Information: Macrocell Utilization.
Description
Used
Max
______________________________________
| I/O Macrocells
|
8 |
8 |
| Buried Macrocells |
6 |
8 |
| PIM Input Connects |
32 |
36 |
______________________________________
46 /
52
= 88
%
The previous table shows the macrocell utilization statistics. A macrocell is counted as
used if any part of the macrocell is in use.
9
After such information is printed for each Logic Block in the device, a pin information
table is printed that is essentially a PINOUT for the design targeting a particular device or
package. Following the pin information table, overall statistics for the whole device are
listed. These statistics display the total available resources of the device and the features of
the device.
The following is an example for a FLASH370 device.
Information: Macrocell Utilization.
Description
Used
Max
______________________________________
| Dedicated Inputs
|
2 |
2 |
| Clock/Inputs
|
4 |
4 |
| I/O Macrocells
|
56 |
64 |
| Buried Macrocells |
27 |
64 |
| PIM Input Connects | 166 | 312 |
______________________________________
255 / 446
= 57
CLOCK/LATCH ENABLE signals
Input REG/LATCH signals
Input PIN signals
Input PINs using I/O cells
Output PIN signals
Total PIN signals
Macrocells Used
Unique Product Terms
Required
1
1
4
14
42
62
69
271
%
Max (Available)
4
69
4
14
50
70
128
640
Most items above are self-explanatory. The “I/O Macrocells” and the “Buried Macrocell”
count reflects a count of macrocells where any portion of that macrocell is used. This
report file says that a total of 83 (56 + 27) macrocells (or portions of) are being used;
however, the line that reads “Macrocells Used” indicates that only 69 macrocells are used.
This is because some of the I/O macrocells are being used purely as input. This is
indicated by the line that reads “Input PINs using I/O cells” whose value is 14. This is the
reason the “Macrocells Used” line reads 69 (83 - 14).
212
Warp User’s Guide
Report File
9.4.4
Static Timing Analysis
The last section of the report file for CPLDs contains a static timing analysis report along
with the worst case timing numbers for various parameters. While reading this
information, it is important to note the speed grade of the device that was chosen. There
are many terms that are used in this section of the report file that may not be familiar to the
user. These terms and the waveforms they represent are described in the datasheets for the
devices. Refer to the Cypress Semiconductor Programmamble Logic Databook. An
important thing to note, however, would be that for paths that require multiple passes
through the arrays, the intermediate nodes are also listed.
Warp User’s Guide
213
9
Report File
9
214
Warp User’s Guide
Chapter
10
Device Programming
10
Device Programming
10.1
Device Programming
Once a design has been compiled, synthesized, and simulated, it is ready to be
implemented in silicon. This implementation consists of two steps: the generation of a
programming file and the programming of the device. In this section, both steps will be
discussed for all devices in the Cypress programmable logic family.
The programming file type that the designer generates depends upon the device type to be
programmed. Three programming file types exist for Cypress devices, JEDEC (.jed) and
POF (.pof). The Table 10-1 summarizes the file type needed for each of the Cypress
device types as well as the steps required to generate these files. These steps are described
in detail in this section.
10
Table 10-1 Programming file types
Device Type
Small PLDs, FLASH370
CPLDs
MAX340 CPLDs
10.2
Programming File
Type
How to Generate File
JEDEC
Run Galaxy
Go to Device menu
Output: JEDEC Normal
Compile Design
POF
Run Galaxy
Go to Device menu
Output: JEDEC Normal
Compile Design
Run jed2pof.exe from DOS
Generating a JEDEC File
For programming a small PLD or a FLASH370 CPLD, a JEDEC file is required. In the
Warp design environment, this file is created as the last step of compiling a design. This
programming file will have the same base name as the top-level design file with a .jed
extension.
216
Warp User’s Guide
Device Programming
Two output file formats are possible when a small PLD or CPLD is selected, JEDEC
Normal and JEDEC Hex. Both files contain the same information but slightly differ in
format. Whereas the JEDEC Normal represents fuse addresses and data in binary (0 and
1), the JEDEC Hex represents them in hexadecimal (0 through F). Most device
programmers require the JEDEC Normal format, and the programmer software will
generate errors if the JEDEC Hex file format is used.
Some portions of a JEDEC file are included below to provide an example of the
information that it contains:
Cypress c371 Jedec Fuse File: test.jed
This file was created on 12/11/95 at 10:20:55
by C37XFIT.EXE
06/MAR/95
[v3.17B] 3.5 IR x96
^Bc371*
QP44*
Number of Pins*
QF13274*
Number of Fuses*
F0*
Note: Default fuse setting 0*
G0*
Note: Security bit Unprogrammed*
NOTE DEVICE c371*
NOTE PACKAGE CY7C371-143JC*
NOTE PINS aeqb:2 b_3:10 b_2:11 b_1:13 b_0:32 a_3:33 a_2:35
NOTE PINS a_0:42 a_1:43 *
NOTE NODES *
NOTE NODES *
L000000
000000000010000000000011100000000000000000100000000000000011
100000000000
* Note: LAB 1 BANK OE 0*
L000072
000000010000000011111000000000000000100000000000001000100000
010000000000
* Note: LAB 1 BANK OE 1*
(etc.)
CC3B5*
Note: Fuse Checksum*
QV4151*
Note: Number of Test Vectors*
V0001 NL11HFZZ010NC10Z10ZZZNNZZZL11Z111N0ZLLLHHZLN*
V0002 NL11HLZZ010NC10Z10ZZZNNZZZL11Z111N0ZLLLHHZLN*
V0003 NL11HLZZ000NC10Z10ZZZNNZZZL11Z111N0ZLLLHHZLN*
(etc.)
V4151 NL11FF10Z00NCZZZZZZZZNNZZZLZZZ001N1ZLLHLHZHN*
^CFFA0
Note: File Checksum*
Warp User’s Guide
217
10
Device Programming
At the top of the file is information about the design compilation, including the software
revision number, date of compilation, and filename. Further down in the file is the design
and device information. The QP field (QP44) tells the user that this file is for a 44-pin
device. The QF field denotes the total number of fuses that can be programmed: 13,274
for a CY7C371. A few lines below this are several NOTE fields detailing the device,
package, and signal names for the design signals. The device programmer does not use
these fields, but simulators use them for package-specific pin numbers and signal names
during simulation. Because the programming algorithm does not use this pin information,
but rather only uses the fuse numbers for addressing internal locations within the device,
the user can program any package of a given device type with the same JEDEC for that
device. For example, the designer could use a TQFP package to compile and simulate a
design, and then use the resulting JEDEC file to program a PLCC package of the same
device. In short, the package information in the file is relevant not for programming but
for simulation.
10
After the NOTE fields, the fuse address and data begins. Each L field in the JEDEC file
corresponds to a region of the device. The data following the L field corresponds to the
values to be programmed in those locations (1 = programmed, 0 = unprogrammed).
Near the end of the file are two checksums, a fuse checksum and a file checksum. First,
the fuse checksum represents the sum of all of the fuse values in the JEDEC file. Device
programmers often use this sum to verify that the pattern programmed into the device
(number of fuses programmed) matches the number in the JEDEC file. By reading the
fuse values from a programmed device, the programmer determines the number of fuses
that were programmed. In the sample JEDEC file above, the fuse checksum is C3B5. The
checksum value is always preceded by a C.
The file checksum, which is the last line in the file, represents a total value for all
characters in the JEDEC file, including both fuse values and notes, comments, and signal
names. Using this checksum value, the designer can tell if the programming file has been
corrupted or modified. If the file has been changed, the file checksum computed by the
device programmer will not match the checksum in the file, and an error will be reported.
In the sample JEDEC file, the file checksum is FFA0, preceded by ^C.
Between the fuse checksum and the file checksum are test vectors for the design. Device
programmers use these vectors to test the functionality of the programmed device. Using
these vectors in sequence, the programmer applies inputs to the device and checks the
outputs for the expected values. The QV field, found immediately after the fuse checksum,
represents the number of test vectors. This sample design has 4,151 test vectors. Many
third-party software companies offer products that automatically generate test vectors for
a design using a JEDEC file as the input.
218
Warp User’s Guide
Device Programming
10.3
Generating POF Files for MAX340 CPLDs
The steps required to program the MAX340 CPLDs are identical to those discussed above
for FLASH370 CPLDs with one additional step required to produce the programming file.
After the design is compiled and produces a JEDEC Normal file, that file must be
converted to a POF (.pof) file. POF files are binary programming files which are not based
on the JEDEC standard. Programming algorithms developed for the MAX340 CPLDs use
this format instead of the JEDEC format.
To perform the conversion from JEDEC to POF, the executable jed2pof.exe must be run
from DOS. This program takes the device type and JEDEC filename as input and produces
a file with the same base name and a .pof extension. The part can then be programmed on
a device programmer. If you are using the Warp software on a PC, this utility can be
found in the c:\warp\bin\jed2pof directory. If you are using a workstation, you can
obtain this program from the Cypress Bulletin Board System (BBS) at (408) 943-2954.
10.4
Device Programmers
Cypress sells a programmer called the Impulse3 that supports PROMs, small PLDs and
CPLDs. Different part and package combinations require various programming adapters
that fit onto the base unit of the programmer. By using the correct programming adapter
and generating the programming file as discussed earlier in this section, all of the Cypress
devices can be programmed using Impulse3. Software updates for Impulse3 are free and
are available on the Cypress World Wide Web home page.
Warp User’s Guide
219
10
Device Programming
Other third-party vendors such as Data I/O, BP Microsystems, SMS, System General, and
Logical Devices offer varying degrees of programming support for Cypress devices. The
Data I/O Unisite has the most complete support for Cypress devices of these third-party
programmers. The designer should directly contact the manufacturer of these third-party
programmers for device support questions. The design flow for programming each type of
device is summarized in the following graph.
GALAXY
10
“Device” button
Output: JEDEC Normal
Small PLDs
FLASH370
JEDEC
(.jed)
MAX340
JEDEC
(.jed)
jed2pof.exe
(from DOS)
POF
(.pof)
DEVICE PROGRAMMER
Figure 10-1 Design flow for device programming
220
Warp User’s Guide
Appendix A
Error Messages
A
Error Messages
This appendix lists the error messages that may be returned by the Warp compiler. A brief
explanation is included if the error message is not self-explanatory. When error messages
are grouped, they refer to the same explanation.
Note – %s refers to any string, %d and %ld to a decimal, %c to a character and %x to a hexadecimal number.
E1
:%s: Abort:
E2
:Abort:
This is usually the result of running out of memory. Please contact the system
administrator to see if increasing virtual or real memory is possible on the system.
E3
:Need a '<=' or ':=' here.
An equal sign instead of an assignment operator was used in an expression.
E4
:Missing 'PORT MAP'.
You might be trying to instantiate a component and list a set of ports to be connected but
without the key words PORT MAP.
A
E5
:Use '=', not ':=' here.
The assignment rather than the comparison operator was used in an expression.
E7
:Can't open file.
An input file couldn't be opened for some reason (usually, because the file doesn't exist or
isn't in the current path).
E8
:Syntax error: Can't use '%s' (a %s) here.
An attempt was made to use the wrong character or keyword, or a delimiter is missing.
E9
:Can't take attribute '%s' here.
An attribute was used where not allowed.
E10
:Syntax error at/before reserved symbol ‘%s’.
You used a reserved word in an illegal fashion, e.g., as a signal or variable name.
E14
:%s (line %d, col %d):
This message is more of an informative message than an error message. It tells you where
to look for an error. The message usually appears as part of another message.
E18
:Missing THEN.
A THEN is missing from an IF-THEN-ELSE statement.
E19
:Not a TYPE or SUBTYPE name: %s
A variable or signal was defined that has an unknown type (e.g., "signal x:nerp").
222
Warp Reference Manual
Error Messages
E20
:'%s' already used
An attempt has been made to define a symbol that already exists.
E21
:%s not an enumeration literal of %s
You have attempted to assign or compare a state variable to a value that is not within its
defined enumeration set.
E30
:';' after last item in interface list.
A semicolon was used after the last item in an interface list (the port declaration or
parameter list for a function) instead of a right parenthesis.
E31
:Missing end-quote.
E32
:’%s’ is not an attribute name.
E34
:Undeclared name: %s
You have attempted to use an undeclared (undefined) variable.
E36
:Variable declaration must be in a PROCESS statement.
You have attempted to declare a variable inside an architecture. Signals can be declared in
architectures, but variables have to be declared within a process.
E38
:Bad application version ‘%s’. ‘%s required.
This means that file compiled with one version of Warp are being used in another version
of Warp. If this occurs while Warp is loading a file contained within the Warp installation
directory, you may have to re-install Warp. If this happens while Warp is loading a user
file, please force Warp to re-compile that file.
E39
:Need to recompile ‘%s”
This error occurs when the vif files are out of date. The file listed in the error message
needs to be recompiled with Warp.
E40
:Declaration outside ARCHITECTURE or ENTITY.
An attempt was made to declare a variable outside an architecture or sub-program.
E41
:Not a valid ENTITY declarative item.
You have attempted to declare a variable inside an entity. Variables must be declared
within a process.
E42
:Can't open standard library '%s'.
File cypress.vhd or std.vhd must be available but couldn't be found in the current path.
E43
:'%s' must be a RECORD
You have attempted to use as a record a variable or symbol that was not a record.
E44
:Must be a constant.
Warp Reference Manual
223
A
Error Messages
A constant is required.
W45
:NULL range: %s %s %s.
You defined a bit vector in the wrong range.
E46
:Error limit (%d) exceeded
The default error limit is 10 errors. More than 10 errors causes an abort.
E47
:'%s' not a formal port.
The named item is not a formal port.
E48
:Warning limit (%d) exceeded
The default number of warnings has been exceeded, causing an abort.
E49
:Not a polymorphic object file.
E50
:Bad polymorphic object file version.
The application stopped running before completion or has not been updated correctly.
Delete all files that are not part of the design (temporary files such as *.vif, *.prs files),
then re-load and re-run the Warp.
If Warp is complaining about a library file, however, this is an indication of a corrupted
Warp installation.
A
E51
:Variable '%s' already mapped.
A port is mapped to more than one pin.
E52
:Symbol '%s' declared twice
The same name has been declared twice.
E53
:Name '%s' at end of %s, but no name at start
An un-named construct (e.g., a process) was referred to by a named label at its conclusion.
E54
:Name '%s' at end of %s does not match '%s' at start
The label referenced at the end of a construct does not match the name the construct was
given at its beginning.
E55
:%s used as an identifier
You have attempted to use a reserved word as an identifier.
E56
:Expected %s, but got %s
E57
:Expected %s
E58
:Expected %s or %s
E59
:Expected %s or %s, but got %s
Syntax error: Warp expected a particular character or keyword, but found something else.
E60
224
:Extra COMMA at end of list
Warp Reference Manual
Error Messages
A comma appeared after the last item but before the closing parenthesis in a PORT
statement.
A
Warp Reference Manual
225
Error Messages
E61
:'%s' mode %s not compatible with '%s' mode %s in %s.
An input port was mapped to an output pin, or vice versa.
E62
:Warning:
The beginning portion of a warning message.
E64
:Out of memory.
The application is out of memory. Remove memory resident programs and drivers and rerun the application.
E65
:Fatal error
The beginning portion of a fatal error message.
E66
:Can't index into '%s'
An attempt was made to use the named string as an array when the string is not an array.
E67
:Can't open report file '%s'
The report file couldn’t be opened or created. The most likely causes are that the disk is
write-protected or out of disk space.
E68
:Missing right parenthesis
Syntax error.
A
E69
:Use '<=' for signal assignments.
Used ":=" instead of "<=" as assignment operator.
E70
:Actual '%s' type ‘%s’ not compatible with formal '%s' type ‘%s’
A type mismatch was found.
E71
:Positional choice follows named choice
Positional (unspecified formal port) entries may not follow named entries during a
component instantiation.
E72
:Can't RETURN when in a finite-state-machine
A return statement inside a finite state machine description (a case statement on an
enumerated type) is not supported.
E73
:ALL or OTHERS already used for ‘%s’ for class ‘%s’.
While setting attributes, you can set attribute on ALL objects of a given class or specify a
default attribute any object in this class which does not have this attribute by using the
OTHERS reserved word. However, you will see this error message if you use these
specifiers more than once on a given class.
E74
:'%s' not a field in record '%s' of type '%s'
An attempt was made to use an inappropriate string as a field in a record.
226
Warp Reference Manual
Error Messages
E75
:Sensitivity name not a SIGNAL
A sensitivity list on a process must consist only of signals.
E76
:Unconstrained arrays not allowed here.
E77
:’%s’ not a '%s' enumeration literal
Inappropriate use was made of the named string as an enumeration literal.
E78
:Positional parameter follows named parameter
A positional (unspecified formal port) parameter may not follow a named parameter.
E79
:%s has no parameter to match '%s'
The port map contains a missing parameter.
E80
:Value '%s' out of range ‘%s’.
A limit, such as a vector limit, is out of range. Re-declare the variable or rework the
design.
E81
:Illegal char. '%c' in literal
The named character is not allowed in this literal.
E82
:'%s' conversion to VIF not supported
Synthesis of this VHDL object is not supported.
A
E83
:'%s' conversion to PLD not supported
Synthesis of this VHDL object is not supported.
E86
:Procedure '%s' body not found
The named procedure was declared, but the body of the procedure could not be located.
E87
:Division by 0
E88
:Operation '%s' not supported
The named arithmetic operation is not supported.
E89
:'%s' must be a CONSTANT or VARIABLE
A constant or variable is required in the named instance.
E91
:Not in a loop
E92
:Not in a loop labelled '%s'
An EXIT or a NEXT statement was found that is not inside a loop.
E95
:FOR variable '%s' not a constant
The named FOR variable is not known at compile time.
E96
:Only integer range supported.
An attempt was made to assign an invalid integer range, such as an enumeration range.
Warp Reference Manual
227
Error Messages
E97
:Missing generations scheme.
E98
:Negative exponent %ld
Negative exponents are not supported.
E99
:Cannot assign this to an array or record.
Only an aggregate with a list of values or another array or record may be assigned to an
array or record.
E100 :Too many values (%d) for '%s' of size %d
The list of values in the aggregate was too large for the aggregate to be assigned to an
array or record.
E101 :Can't handle function call '%s' here.
The named function call cannot be handled.
E102 :Variable expected.
Symbol was incorrectly declared. The symbol must be a variable, not a signal.
E103 :'%s' must be an ARRAY
The named string must be an array.
A
E104 :Field name or 'OTHERS' expected
Invalid case statement qualifier.
E105 :Can't delete '%s' from library '%s'
I/O error. The named string cannot be deleted from the named library.
E106 :You need to declare this as a SUBTYPE.
You declared something as a TYPE that should have been declared a SUBTYPE.
E108 :Function '%s' body not found
The named function was declared, but the statements associated with the function could
not be located.
E109 :Expected '%s' to return a constant
A function that was expected to return a constant didn't.
E110 :Array sizes %ld and %ld don’t match.
You tried a dyadic logical operation (AND, OR, XOR) on two vectors of different sizes.
Vector sizes must match for such operations.
E111 :Set_map: ‘%s’ not a ‘%s’
This indicates that an incompatible type of object is being associated with an element of
an aggregate (array or record).
228
Warp Reference Manual
Error Messages
E112 :Positional parameter '%s' follows named parameter
A positional parameter may not follow a named parameter.
E113 :No function '%s' with these parameter types
The named function with the specified expressions was not found.
E114
:Alias type mismatch
E115 :'%s' is not a visible LIBRARY or PACKAGE name
Warp cannot identify the named string as a valid name for a library or package.
E116 :'%s' not in PACKAGE '%s'
The named string is not in the named package.
E117 :Missing/open field '%s' in %s
Missing parameter or port in the named port list.
E118 :Illegal integer/identifier '%s'
Identifiers must begin with a letter.
E119 :Slice (%d TO %d) is outside array '%s' range (%d TO %d)
The named index range of the slice is outside the named index range of the specified array.
The indices of a slice must be within the indices of an array.
E120 :'%s' not an array
The named string is not an array.
E121 :'%s' is not a PACKAGE.
The named string is not a package.
E122 :Invalid connection to formal %s of non-input mode. Must be a SIGNAL.
The named port map parameter may not be an expression, variable, or constant; it must be
a signal or signal function.
E123 :Output parm. '%s' must be a SIGNAL or VARIABLE
The named output parameter must be a single entity, like a signal or variable.
E124 :'%s' is not a COMPONENT
The named string is not a component.
E125 :-s requires a path.
The -s command line option requires a path to the library.
E126 :Wrong number (%d) of indices. %d needed.
The listed number of indices is incorrect for the multi-dimensional array.
Warp Reference Manual
229
A
Error Messages
E127 :Constraint dimension (%d) doesn't match type dimension (%d)
The named constraint dimension doesn't match the named type dimension (constraint
must be in the same number of indices as the array).
E128 :Can’t use multiple-dimension index constraint here.
E129 :Illegal '&' operands: '%s' and '%s'.
Concatenation is not allowed for the named strings. Concatenation is allowed only for
identically typed one-dimensional arrays.
E130 :Bad dimension (%d) for attribute '%s'
The named dimension is incorrect for the named array.
E131 :'%s' mapped twice.
The same actual parameter was mapped to two formals.
E132 :Can’t set elements of unconstrained array
E133 :'%s' wasn't mapped
The actual parameter identified in the message was not mapped to a formal in the port
map.
E134 :Error occurred within '%s' at line %d, column %d in %s.
A descriptive message to inform the user of the exact error location.
A
E135 :Unexpected '%s'.
Syntax error.
E136 :'%s' is not a known ENTITY
An attempt was made to use the named string as an entity name.
E137 :Can't use OTHERS for unconstrained array '%s'
Syntax error.
E138 :%s must be the last case statement alternative.
No case statement alternatives may follow OTHERS.
E139 :Can't use actual function with formal output '%s'
Data is not allowed with the named formal output port.
E140 :Use ':=' for variable assignments.
A string other than ":=" was used for a variable assignment.
E141 :Can't use function(formal) with formal input '%s'
You used an fbx() or fxb() (or some other translation function) in the wrong direction.
230
Warp Reference Manual
Error Messages
E142 :’%s’ not visible here.'
A symbol/variable was used but not declared in the current scope. This typically happens
during a component instantiation or an entity declaration.
E143 :Underbar not allowed at start or end of identifier.
E144 :Cannot assign this to target: %s
Assignments are allowed only on signals, variables or aggregates. Other targets of an
assignment statement are illegal.
E145 :Illegal character ‘%c’.
E146 :You must ASSIGN function to a signal or a variable.
E147 :VAL attribute not allowed for ‘%s’
E148 :Position %ld out of range
Indicates that the index you have asked for is out of range.
E149 :Duplicate label ‘%s’.
More than one component/generate statement might have the same label. All labels must
be unique within their scope.
E150 :’%s’ length %ld doesn’t match ‘%s’ length %ld.
Please examine the port maps for the component. All mappings must have a length that
matches the component declaration.
E151 :’%s’ already has attribute ‘%s’
Please remove one of the duplicate attributes.
E152 :Access variable ‘%s’ is NULL
You probably are trying to access a field of a record which is invalid.
E153 :WAIT not allowed in a process with a sensitivity list.
E154 :Use NOT instead of ‘/’.
VHDL uses ‘NOT’ as the inversion operator.
E155 :Unconstrained output port ‘%s’ cannot be OPEN.
W156 :NULL slice. Direction does not match subtype’s.
When extracting a slice of a vector, the direction (to or downto) of the slice specification
should match the direction of the original vector.
E157 :Cannot evaluate %s(non-constant). Too many values (%ld) in range.
When expanding an array, Warp found too many elements in an array (more than 200).
This might be caused due to indexing an array with a non-constant.
E158 :Too few values (%ld) for ‘%s’ of size %ld
The length of the arrays have to match.
Warp Reference Manual
231
A
Error Messages
E159 :Can’t find ‘%s’ of class ‘%s’ in current declarative region.
The class specification for the item to which an attribute is being set is not valid.
E160 :Block spec. ‘%s’ isn’t an architecture of ‘%s’
E161 :Deferred constant ‘%s’ was never given a value.
E162 :Can’t use ‘%s’ here.
W163 :Array sizes %ld and %ld don’t match for ‘%s’.
E164 :’%s’ is not a discrete type.
E165 :Label ‘%s’ not visible here.
E166 :Guarded assignment to ‘%s’ is not inside a guarded block.
E167 :LENGTH not allowed for ‘%s’. Array required.
E168 :Double underbar not allowed.
E169 :’%s’ is not a group template.
E170 :Group list is not compatible with template ‘%s’.
E171 :WAIT not allowed in function or procedure called from function (%s).
E300 :VHDL parser
Message indicating progress of compilation (not really an error).
A
E301
:High-level synthesis
E302
:Synthesis and optimization
E303
:Verilog Pre-Processor
E304
:Design Unit Extractor
E360 :Library file ‘%s’ is out of date. Recompile with -a.
E361 :Bad library object file ‘%s’
E362 :Error writing to library index
E363 :Error copying '%s' to library
E364 :Can't create library index '%s'
File I/O.
E365 :Bad library index '%s'.
The named index for the library is corrupted. Delete the library and load another copy.
E366 :Can't create library '%s' with path '%s'
File I/O.
W367 :’%s’ library object is missing or is an old version.
Please recompile the library. This is also an indication that some files have been deleted
out of the Warp Library directories or that the installation is improper/incomplete.
E368
E369
E370
232
:Error deleting existing library index entries
:Can't open library '%s' with path '%s'
:Error reading library '%s'
Warp Reference Manual
Error Messages
E371 :Can't find '%s' in library '%s' with path ‘%s’
E372 :Can't open library module '%s'
E374 :'%s' not a PACKAGE
File I/O.
E375 :'%s' is not in '%s'
The named package is not in the named library.
E377 :'%s' from '%s' replaces that from '%s' in library '%s'
Warning message. When a module is compiled into a library, module design units with
names the same as existing names overwrite the existing design units.
E378 :Don't work from within your library directory ('%s')
An attempt was made to run Warp with the named library directory as the current
directory.
E400 :Integer overflow for %d**%d.
This implies that the result of the operation caused an integer overflow.
E401 :Cannot use three-stated signal ‘%s’ in a sequential context because it was
assigned in a blocking statement.
E402
:Cannot use three-stated VARIABLE ‘%s’ in a sequential context.
E411 :GENERATE condition ‘%s’ doesn’t simplify to a constant.
E412 :Port '%' in RTL component '%s' is missing or improper
An attempt was made to use the named RTL component without assigning the named port
or assigning it inappropriately.
E413 :Cannot use SIGNAL ‘%s’ here. No node # is assigned to it.
A signal is used in an expression, but the signal has not been assigned to any node or pin
in a chip.
E414 :Expression too complex: %s
Output assignments must follow a specific format.
E419 :Component’s ‘%s’ mode does not match mode of ‘%s’ in entity.
E426 :Component’s ‘%s’ type ‘%s’ not compatible with type ‘%s’ in entity.
E427 :Target must be a variable.
Target may not be a constant or an aggregate.
E428 :Could not find entity '%s (%s)' for component '%s'
E429 :Could not find entity '%s' for component '%s'
Warp was unable to find the named entity for the named component.
E431
:Bad value for formal ‘%s’. Must be a constant.
Warp Reference Manual
233
A
Error Messages
E432 :Conversion from AONG to '%s' not supported
Finite state machine enumerated type synthesis is not supported.
E433 :Parameter for formal ‘%s’ is ‘%d’. Must be between %d and %d.
E434 :Unsupported PLD '%s'
An attempt was made to compile to an unsupported or nonexistent device.
E435 :Pin ‘%s’ assigned to ‘%s’ is invalid - Please check package pinout.
E436 :Only simple waveform supported. Ignoring assignment.
Warp allows only simple wave forms with no timing information.
E437 :All drivers of '%s' are not internal tristates.
You may have a condition where some of the drivers (equations) for a multiple driven
signal are three-state drivers and some are not. Warp cannot synthesize such constructs.
W437 :Converting multi-driven PORT '%s' to internal tristate.
This is simply a warning indicating that a multiple driven signal was also found to be a
primary I/O signal which currently cannot be mapped to a device. Such signals are
converted to equations which means that the I/O signal will never really be in high
impedance mode.
A
E438 :RTL '%s' not supported for %s
An attempt was made to use the named built-in component for an incorrectly named
device.
E439
:RTL field '%s' too complex: ‘%s’
E440 :Missing RTL field '%s'
An RTL component is missing a port.
E441 :Component formal '%s' has no match in ‘%s’.
Check for an invalid port map or a typo during a component instantiation.
E442 :Invalid module port connection ‘%s’.
E443 :Unresolved signal '%s' has more than one driver
An attempt was made to use more than one driver with the named signal using an
unresolved VHDL type (like bit).
E444 :Device '%s' not supported.
Warp does not support the named device.
E445 :No binding architecture found.
You probably used the wrong device name, or the installation is incomplete, or wrong
CYPRESS_DIR env. variable.
E446
234
:Can’t handle multiple drivers for ‘%s’ in selected device.
Warp Reference Manual
Error Messages
Multiple drivers are not supported by default for certain devices (CPLD/PLDs).
E448
:Reset signal ‘%s’ must be in sensitivity list.
E447 :Can’t handle drivers of different types (components and equations) for
signal ‘%s’.
E449 :Only ‘0’ and ‘1’ allowed in user code.
When using user defined state encoding, only ‘0’s and ‘1’s are allowed.
E450 :Too few (%d) bits. %d required.
E451 :Clock signal ‘%s’ must be in sensitivity list.
E452 :WAIT UNTIL statement must be first in process.
E453 :RESET must be a simple assignment.
E454 :This design produces 0 nodes.
E455 :Async. reset condition is a constant.
The asynchronous reset condition evaluated to a constant. This is probably not the
intention of the design and should be corrected.
E456 :Entity formal ‘%s’ is missing from COMPONENT ‘%s’.
In Warp, all formal ports that are defined in the ENTITY statement must be specified in
the corresponding COMPONENT statement
E457 :Infinite component instantiation recursion at %s:%s.
Even though it is possible for component A to invoke component B which in turn invokes
component A (or a case where component A invokes itself), Warp was unable to resolve
the recursion because it was too deep. The design must be simplified.
E458 :Call depth is %d. Infinite recursion?
You have exceeded an internal limit of 1000 nested function calls. More than likely you
might have an infinite recursion.
E459 :Unconstrained arrays not allowed for binding architecture (%s).
The top level of the design cannot have unconstrained arrays.
W460
E461
E462
E463
:’%s’ unassigned in %s ‘%s’%s%s%s
:Output-enable not supported beneath a WAIT.
:Duplicate CASE choice ‘%s’, already seen on line %d.
:’%s’ -- Can’t handle registered multi driver.
E464
:Generic ‘%s’ needs default value for binding architecture (%s).
E465
W465
W466
E467
:Signal ‘%s’ is floating (not driven by anything).
:Top-level entity ‘%s’ has no output ports.
:WAIT condition is a constant.
:Component ’%s’ not allowed in this device.
Warp Reference Manual
235
A
Error Messages
E468 :CASE statement needs an OTHERS choice.
E469 :CASE statement is missing %d choices.
You must enumerate all possible choices or use the OTHERS clause to define the missing
choices from a CASE statement.
E470 :’IF ... ELSIF (<clock expression>)’ must be 1st in process.
E471 :Can’t find state codes array ‘%s’.
E472 :State codes object ‘%s’ must be a CONSTANT array.
E473 :State codes array ‘%s’ must have indices of type ‘%s’.
E474 :Enum. code %s has different length than prev. codes.
More than likely you have violated a state machine template supported by Warp.
E475 :Component declaration for ‘%s’ is missing a GENERICS list.
In Warp, a COMPONENT declaration for a given ENTITY must contain the same
generics as the entity it is associated with.
E476 :Output-enabled/tristated signal ‘%s’ must be an OUT or INOUT port.
W477 :Device ‘%s’ is not recommend for new designs. Please choose the ‘%si’
instead.
E478 :Cannot assign %s (non-constant). Too many values (%ld) in range.
Ensure that the index into the array is constrained or a constant.
A
W479
E480
E481
:’%s’ should be referenced in the sensitivity list.
:Can’t assign ‘%s’ to aggregate ‘%s’.
:Can’t re-assign ‘%s’ here because it was previously three stated.
E500 :Can't handle '%s' expression.
An unsupported operation was included in an expression.
W507 :No synchronous entry to state '%s' of '%s'.
Warp cannot find an entry to the named state, so the state is not used and can be removed.
W508 :No exit from state '%s' of '%s'.
Warp cannot find an exit from the named state, so the state is a sink.
E510 :Operation '%s' not supported for vectors/integers
Implementation is not supported.
E511 :BIT or array required
Warp does not synthesize integers; a bit or array is required.
E512 :Can’t handle expression '%s' in final equations.
You will see this error message when an unsupported expression construct is used or when
a supported expression construct is used in the wrong place. For example, clk’event can
236
Warp Reference Manual
Error Messages
only appear when describing a sequential element according to the flip-flop template.
E513
:'%s' not a BIT or array
Warp does not synthesize integers; a bit or array is required.
E514 :Only multiplication/division by 2**n is supported.
E515 :Unsupported use of enumeration literal ‘%s’
W520 :Loop appears to be infinite.
E521 :Exit/next not supported under a non-constant condition.
E522 :Illegal operands for addition/subtraction
W522 :Operator ‘%c’: constant truncated to %d bits.
This may occur during operator inferencing if a vectored signal is being added (or
multiplied or subtracted) to an integer constant and the integer constant is larger than the
size of the vector. When this occurs, Warp takes only the least significant bits of the
integer.
E600 :Array lengths %ld, %ld don't match for '%s'.
For the named operation, the named array lengths do not match.
E601 :Bad operand types '%s' and '%s' for operator '%s'.
Type check violation.
A
E602 :Bad operand type '%s' for operator '%s'.
Type check violation.
E603 :Wrong character '%c' in string
Type check violation.
E604 :Expression type '%s' does not match target type '%s'.
Type check violation.
E605 :BOOLEAN required here.
Type check violation.
E606 :Numeric expression required here.
Type check violation.
E607 :Choice type '%s' doesn't match case type '%s'.
Type check violation.
E608 :'%s' not readable. Mode is OUT.
The mode is defined as OUT, so you can't put it on the right side of an expression.
E609 :'%s' not writable. Mode is IN.
The mode is defined as IN, so you can't put it on the left side of an expression.
E610
:SEVERITY_LEVEL required here
Warp Reference Manual
237
Error Messages
An ASSERT statement requires a severity level.
E611 :RETURN not in a function or procedure
A return statement was found that was not inside a function or procedure.
E612 :Can't RETURN a value from a procedure
The application cannot return a value from a procedure; a function is required.
E613 :Function RETURN needs a value.
You attempted to return from a function without specifying a value.
E614 :Return type '%s' does not match function type '%s'.
Syntax error.
E615 :Can't assign to CONSTANT '%s'.
Invalid constant.
E617 :Type mismatch in range.
E618 :’%s’ is of mode LINKAGE.
E619 :Type ‘%s’ does not match element type ‘%s’.
E620 :Only a guarded signal or access variable may be assigned NULL.
E621 :Choice must be locally static.
E622 :CASE expr. must be discrete, or an array of characters.
E623 :Right operand of ‘%s’ must be an integer.
E624 :Left operand of ‘%s’ must be a 1-dim. array of bits or booleans.
E701 :Can’t handle expression ‘%s’ in final equations.
E750 :Can’t open file ‘%s’.
E751 :Error writing to file ‘%s’.
E752 :File name must be a STRING.
E753 :Filename must evaluate to a simple STRING.
E754 :Missing parameter ‘%s’.
E755 :File I/O routine not yet supported
E1100 :Missing/bad pin number: ‘%s’
Check the pin_numbers attribute for the missing or bad pin number specification. The pin
name should be immediately followed by a “:” and then a pin number (or an alpha
numeric for PGA packages).
A
E1101 :’%s’ not a port name in entity ‘%s’
Invalid name in the pin_numbers attribute.
E1102 :Can’t set pin number of composite ‘%s’
One pin number cannot be assigned to a group of signals that might be derived from a
composite or an array.
E1103 :Missing ‘)’ after ‘%s’
238
Warp Reference Manual
Error Messages
Syntax error during a pin_number specification.
E1104 :’%s’ not an array or integer.
You have tried to index into a non-array type signal during a pin_numbers specification.
E1105 :Index ‘%d’ out of range for array ‘%s’
E1106 :’%s’ not a record.
E1107 :Can’t set pin reference name ‘%s’ of composite ‘%s’
E1108 :Pin number %d assigned more than once.
E1110 :Missing space after pin number for ‘%s’
Invalid pin_numbers specification.
E1328
E1331
E1333
E1416
E1500
E1501
E1502
E1503
E1504
E1505
File I/O
:Can’t handle expression ‘%s’ in final equations.
:PORT ‘%s’ has more than one driver.
:Internal Error: Misconnected port
:’%s’ has no signal assigned.
:Error writing ‘%s’.
:Can’t create ‘%s’. You don’t have write permission.
:Can’t write ‘%s’. Out of disk space.
:Can’t create ‘%s’. Too many open files.
:Can’t write ‘%s’. Device is busy.
:Can’t create ‘%s’. Read-only file system.
A
W1715 :Espresso failed for ‘%s’.
Warp uses technology from University of California, Berkeley to perform logic
optimization. The equations in the design may have encountered certain limitations within
Espresso. The message simply indicates, however, that the equation was not minimized
using Espresso and instead a simpler kind of optimization was performed which could
potentially produce non-optimal but logically correct solutions.
Sometimes it helps to look at the design and use factoring techniques (buffering or
synthesis_off) to reduce the fan-in of the equation.
You may also see these kinds of messages from ‘minopt’ during CPLD/PLD fitting. This
is usually a result of the fitter trying to perform polarity/register optimization and an
exponential blowup of the equation occurs. When this happens, it helps if the node in
question has these kinds of optimizations turned off (using the polarity and/or ff_type
directives).
E1800
E1801
E1803
E1804
E1805
:Missing ‘seek’ data in ‘devices.dat’.
:Section ‘%s’ appears twice in ‘devices.dat’.
:Section ‘%s’ not found in ‘devices.dat’.
:Could not find ‘devices.dat’.
:’devices.dat’ line is too long: %s.
Warp Reference Manual
239
Error Messages
E1806 :Already at top of ‘devices.dat’.
E1807 :Can’t find end of ‘%s’ section in ‘devices.dat’.
E1808 :Bad seek data ‘%s’ in ‘devices.dat’.
Check your CYPRESS_DIR environment variable.
E1820 :Unknown order code ‘%s’ for ‘%s’.
E3001 :illegal device
Check legal device/package names in Galaxy.
W3002 :phase ignored
The fitter is ignoring a statement in the .pla file. It is a warning message.
W4000 :Top level entity/module generics/parameters are ignored in post-layout
simulation.
Warp does not support generics in the top level entity/module when the Testbench
generation options is enabled.
W4001 :Unsupported type ‘%s’ for testbenches. Feature disabled.
Warp’s test bench generation module does not support all types of objects being in the top
level entity. Please read the simulation chapter for more information on testbenches.
A
E5002 :Internal error: improper gate type
This error indicates that the primitive gate used is not supported. Primitive gates supported
by Warp are: and, nand, or, nor, xor, xnor, buf, not, bufif0, bufif1, notif0, notif1.
E5004 :’%s’ not visible here.
E5005 :Unconstrained arrays not allowed here.
The specified array must have values for both limits.
E5006 :Illegal char. ‘%c’ in literal
E5007 :Duplicate label ‘%s’.
E5008 :Label ‘%s’ not visible here.
E5009 :’%s’ is not a module.
E5032 :’%s’ is not an attribute name.
E5100 :Verilog parser.
E5101 :Time registers are not supported for synthesis and are ignored.
W5102 :Realtime registers are not supported for synthesis and are ignored.
E5103 :Unsupported net type : %s
240
Warp Reference Manual
Error Messages
The net type %s is not supported in Warp. Supported net types are: wire tri supply0
supply1
E5104 :Port %s not declared in the port list
E5105 :Port ‘%s’ range mis-match. Overriding with the latest declaration.
W5106 :Real registers are not supported for synthesis and are ignored.
W5107 :Event declarations are not supported for synthesis and are ignored.
E5108 :Real numbers not supported
E5109 :Can’t use ‘%s’ here.
E5110 :In/Inout port cannot be register type
E5111 :Port %s not declared as input or output or inout
All the ports must be declared as input or output or inout.
W5112 :Empty port list.
E5113 :Can’t find function ‘%s’
E5114 :Can’t find task ‘%s’
A
E5115 :Identifier of type supply can not be assigned to an expression.
E5116 :Net type expected on the LHS of the assignment. ‘%s’ is not net type
E5117 :Decimal constant size exceeded the limit (%d bits).
E5118 :Net type expected on the LHS of the assignment. ‘%s’ is not net type
E5119 :Register type expected on the LHS of the assignment. ‘%s’ is not register
type.
E5301 :parallel blocks (fork-join) not supported
W5302 :Drive strength ignored.
E5303 :Register type expected on the LHS of the assignment. ‘%s’ is not register
type.
E5304 :Register variable ‘%s’ is also present in a non-blocking assignment
statement
This error indicates that within the same always block, the register variable %s is assigned
in two different ways: non-blocking assignment and blocking assignment.
E5305 :Register variable ‘%s’ is also present in a blocking assignment statement
This error indicates that within the same always block, the register variable %s is assigned
in two different ways: blocking assignment and non-blocking assignment.
Warp Reference Manual
241
Error Messages
E5306 :Loop init assignment target should be a simple variable
E5307 :Loop condition variable ‘%s’ is different from that used in the initial
assignment
E5308 :Loop step variable ‘%s’ is different from that used in the initial assignment
E5310 :forever construct is not supported
E5311 :repeat construct is not supported.
W5312 :Initial statement is not supported for synthesis and is ignored.
E5313 :A delay value can only use an unsigned decimal number, a constant
mintypmax expression, or a parameter identifier.
E5314 :A delay value using a constant mintypmax expression must contain
constant expressions.
E5315 :wait statement is not supported
W5316 :Delays are not supported for synthesis and are ignored.
E5317 :The event control expression needs to be a simple identifier
The event control expressions can be bit-select/part-select/complex expression.
A
E5318 :Synchronous and asynchronous events cannot be mixed in a timing control
An always statement can contain either edge sensitive timing controls posedge/negedge or
asynchronous events. That is, if an always clause contains a posedge or negedge for any
signal, all other signals must have either one of them also.
E5319 :Ambiguous clocking - more than one potential clock could be inferred
E5320 :A single ‘if’ statement testing asynchronous conditions is expected.
E5321 :No clock inferred, Expected a clock for this always statement
E5322 :’if’ statement must have an ‘else’ part for proper clocking.
E5323 :Internal error: bad polarity in edge expression
This is an inter error within Warp. Report the problem to Cypress.
E5324 :Expected a test of ‘%s’ against 1 since a posedge was specified.
E5325 :Expected a test of ‘%s’ against 0 since a negedge was specified.
E5326 :Only a scalar net can be used in a synchronous event expression.
E5327 :Invalid test of ‘%s’, expecting a comparison to 1 or 0.
E5328 :Comparison of ‘%s’ must be against 1 or 0.
242
Warp Reference Manual
Error Messages
E5329 :Bad reset/preset expression ‘%s’
The expression used in the reset/preset expression should be a test for constant one or
zero. Functions and other types of expressions are not allowed.
W5329 :Charge strength is not supported for synthesis and is ignored.
W5330 :Drive strength is not supported for synthesis and is ignored.
E5330 :Loop index should be initialized with a constant
E5331 :Loop condition should be comparison to a constant
E5332 :Loop condition should be a comparison
The operator in the loop condition should be one of the four conditional operators:<, <=,
>, >=
E5333 :Internal error. Invalid call to verilog expression sizing
E5334 :Loop step assignment target must be a simple variable
The loop step assignment should be a simple variable. Bit-selects/part-selects/other
expressions are not allowed.
E5335 :Loop step assignment expression should be an increment or decrement of
the loop variable
Only “+” or “-” are allowed for loop step assignments.
E5336 :Loop step assignment must use the same variable
Same variable must be used in the loop initial statement, step assignment statement.
E5337 :Loop direction is not consistent between the condition and the step
assignment
E5338 :Loop step assignment expression must increment or decrement the loop
variable by 1
E5339 :Case equal operator is not supported
The “===” operator is not supported.
E5340 :Case not equal operator is not supported
The “!==” operator is not supported.
E5341 :disable construct is not supported
E5342 :deassign construct is not supported
E5343 :force construct is not supported
E5344 :release construct is not supported
E5345 :procedural continuous assign construct is not supported
Warp Reference Manual
243
A
Error Messages
E5346 :event trigger statement is not supported
E5347 :memory declaration is not supported.
E5348 :Port concatenation inside module (port list) definition is not supported.
E5349 :Named Port association inside module (port list) definition is not supported.
E5402 :Module %s undefined
E5403 :’%s’ not a port or parameter of module ‘%s’
E5404 :Parameter overrides beyond one level of hierarchy not supported
defparams can only refer to the next level down the hierarchy.
E5405 :’%s’ is not a parameter of module ‘%s’
E5406 :Bad defparam in module ‘%s’. Instance ‘%s’ not found
E5407 :Bad defparam specification. Missing parameter
E5408 :Illegal char ‘%c’ in expression
E5409 :Incompatible CASE comparison. ‘%c’ not allowed in ‘%s’ statement
A
E5410 :UDP declaration is not supported. Refer online help for more details.
Warp does not support the UDPs. If you have UDPs in your design, use the conditional
compilation method to exclude the UDPs for synthesis. That is include the code other than
the UDPs within ‘ifdef WARP, so that Warp does not try to compile the UDPs.
E5411 :Array of instances is not supported
Warp does not support arrays of instances.
E5412 :Specify block is not supported. Refer online help for more details.
Warp does not support the specify blocks. If you have specify blocks in your design, use
the conditional compilation method to exclude the specify blocks for synthesis. That is
include the code other than the specify blocks within ‘ifdef WARP, so that Warp does not
try to compile the specify blocks.
E5413 :Only simple identifiers and bit-selects are allowed as output terminals
For BUF/NOT gates. the output terminals can be either simple identifiers or bit-selects.
E5414 :BUF/NOT gate instantiation should include atleast one input and one
output terminal
In sufficient number of terminals in the primitive gate instantiation statement.
E5415 :Mos switch types are not supported.
Warp does not support the mos switches.
E5416 :Bidirectional pass switch types are not supported.
244
Warp Reference Manual
Error Messages
E5417 :Bidirectional pass switch types with enable are not supported.
E5418 :CMos switch types are not supported.
E5419 :PULLUP switch type is not supported.
E5420 :PULLDOWN switch type is not supported.
E5500 :Could not open ‘%s’ for reading
E5501 :Could not open ‘%s’ for writing
E5510 :Block comment never terminated
E5511 :Invalid `include directive
E5512 :Could not open included file ‘%s’. Path=%s
E5513 :Too many levels of nested `include’s or macro’s.
The number of nesting levels allowed for included files is 50.
E5514 :Expecting identifier after `define, found ‘%s’
E5515 :Expecting identifier after `undef, found ‘%s’
A
E5516 :Macro name must be followed with a white-space or a ‘(‘
E5517 :Premature EOF while defining macro args
E5518 :Expecting identifier for macro arg., found ‘%s’
E5519 :Expecting another argument, got ‘%c’
E5520 :Can’t use ‘%s’ for a macro name
E5521 :Unsupported `default_nettype ‘%s’, expecting ‘wire’ or ‘tri’
E5522 :’%s not supported. Ignored.
E5524 :Undefined macro `%s
E5525 :Required arguments for Macro `%s not found
E5526 :Premature EOF while expanding macro `%s
E5527 :Expecting %d arg.’s for macro `%s, found %d
E5528 :Comments cannot span multiple lines within macro-text
E5529 :Unterminated string in macro definition
E5530 :Macro with ‘()’ must have atleast one argument
E5531 :Expecting identifier after `ifdef, found ‘%s’
Warp Reference Manual
245
Error Messages
E5532 :`endif without a matching `ifdef
E5533 :Missing `endif
E5534 :`else without a matching `ifdef
E5540 :Could not open ‘%s’ for reading
Make sure that you have permission to read the file %s.
E5541 :Could not open ‘%s’ for writing
Make sure that you have write permissions to the project directory.
E5542 :Could not open temporary file ‘%s’ for writing
Make sure that you have write permissions to the project directory.
E5600 :’%s’ already used
E5601 :Functions returning real are not supported.
E5602 :Functions returning realtime are not supported.
E5603 :Functions returning time are not supported.
W5604 :System task enables are not supported for synthesis and are ignored.
A
E5605 :Symbol ‘%s’ is not a function.
%s is not declared as a function.
E5606 :Symbol ‘%s’ is not a task.
%s is not declared as a task.
E5609 :Invalid expression in event control.
Only posedge and negedge timing controls are supported in Warp.
E5610 :Invalid expression for a ‘posedge’ construct.
The posedge event expression in the always sensitivity list must be a simple identifier. Bitselects, simple identifier. Bit-selects, part-selects and other expressions are not supported.
E5611 :Invalid expression for a ‘negedge’ construct.
The negedge event expression in the always sensitivity list must be a simple identifier. Bitselects, part-selects and other expressions are not supported.
E5612 :Symbol ‘%s’ declared twice
W5612 :Gate instance name declared twice. Ignoring the instance name.
E5613 :Multiple concatenations are not allowed on the L.H.S. of an assignment
E5614 :Symbol ‘%s’ declared twice
246
Warp Reference Manual
Error Messages
W5615 :Ignoring Event based timing control. Supported only in an always block
sensitivity list.
E5615 :Integer variable ‘%s’ is not an array vehicle.
E5616 :Can not synthesisze the non-blocking assignment statement in a
function/task
A function/task can not have a non-blocking assignment statement.
E5617 :Always block without sensitivity list.
In Warp, the always block must have a sensitivity list.
E5618 :Function %s, without input arguments.
The function should have at least one input argument.
E5619 :Function without any function item declaration.
E5650 :Right operand of a shift operation should be constant
E5651 :Repeat operand of a concatenation is not a constant
E5652 :Repeat operand of a concatenation must be greater than 0
E5653 :Illegal char ‘%c’ in ternary operator
E5655 :Cannot handle expr ‘%s’ here. Expecting one or both operands to be
contants.
The operator ‘%s’ cannot handle non-constant operands. If you are using this operator in
functions/tasks, please note that the datapath inferencing is not allowed in functions/tasks.
E5656 :Don’t know how to divide by ‘%d’
E5657 :Unsupported operands for ‘%%’. The right side must be a constant and the
left side must be an unsigned quantity.
Warp Reference Manual
247
A
Error Messages
A
248
Warp Reference Manual
Appendix B
FLASH370/U LTRA 37000
Node Numbers
B
Flash370/370i Node Numbers
Tables 2-1 through 2-5 list cross-references for external I/O to internal node-numbers for
the FLASH370/FLASH370i device family
Table 2-1. 7c371/7c371i Node Numbers
Nodes
Pins
Logic Block
117 - 124
2-9
A
125 - 132
14 - 21
A
133 - 140
24 - 31
B
141 - 148
36 - 43
B
Table 2-2. 7c372/7c372i Node Numbers
Nodes
B
Pins
Logic Block
201,203,205,207,209,211,213,215
2-9
A
202,204,206,208,210,212,214,216
Buried
A
217,219,221,223,225,227,229,231
14-21
B
218,220,222,224,226,228,230,232
Buried
B
233,235,237,239,241,243,245,247
24-31
C
234,236,238,240,242,244,246,248
Buried
C
249,251,253,255,257,259,261,263
36-43
D
250,252,254,256,258,260,262,264
Buried
D
Table 2-3. 7c373/7c373i Node Numbers
Nodes
250
Pins
Logic Block
241 - 248
3 - 10
A
249 - 256
12 - 19
A
257 - 264
24 - 31
B
265 - 272
33 - 40
B
273 - 280
45 - 52
C
281 - 288
54 - 61
C
Warp Reference Manual
Table 2-3. 7c373/7c373i Node Numbers
Nodes
Pins
Logic Block
289 - 296
66 - 73
D
297 - 304
75 - 82
D
Table 2-4. 7c374/7c374i Node Numbers
Nodes
Pins
Logic Block
397,399,401,403,405,407,409,411
3-10
A
398,400,402,404,406,408,410,412
Buried
A
413,415,417,419,421,423,425,427
12-19
B
414,416,418,420,422,424,426,428
Buried
B
429,431,433,435,437,439,441,443
24-31
C
430,432,434,436,438,440,442,444
Buried
C
445,447,449,451,453,455,457,459
33-40
D
446,448,450,452,454,456,458,460
Buried
D
461,463,465,467,469,471,473,475
45-53
E
462,464,466,468,470,472,474,476
Buried
E
477,479,481,483,485,487,489,491
54-61
F
478,480,482,484,486,488,490,492
Buried
F
493,495,497,499,501,503,505,507
66-73
G
494,496,498,500,502,504,506,508
Buried
G
509,511,513,515,517,519,521,523
75-82
H
510,512,514,516,518,520,522,524
Buried
H
Warp Reference Manual
B
251
Table 2-5. 7c375/7c375i Node Numbers
Nodes
Pins
Logic Block
473 - 480
143 - 150
A
481 - 488
152 - 159
A
489 - 496
2-
9
B
497 - 504
11 - 18
B
505 - 512
23 - 30
C
513 - 520
32 - 39
C
521 - 528
42 - 49
D
529 - 536
51 - 58
D
537 - 544
63 - 70
E
545 - 552
72 - 79
E
553 - 560
82 - 89
F
561 - 568
91 - 98
F
569 - 576
103 - 110
G
577 - 584
112 - 119
G
585 - 592
122 - 129
H
593 - 600
131 - 138
H
B
252
Warp Reference Manual
Ultra37000 Node Numbers
Tables 2-6 through 2-9 list cross-references for external I/O to internal node-numbers for
the Ultra37000 device family
Table 2-6. CY37256P256 Node Numbers
Nodes
Pins
Logic Blocks
886 - 890, 892, 894, 896, 898-901
A9, B9, C9,
D9, A8, B8,
C8, A7, B7,
A6, C7, B6
A
891, 893, 895, 897
Buried
A
902-906, 908, 910, 912, 914 - 917
A5, D7, C6,
B5, A4, C5, B4,
B
B3, B2, A2, C3,
B1
907, 909, 911, 913
Buried
B
918-922, 924, 926, 928, 930 - 933
D1, E3, E2,
E1, F3, G4, F1,
G3, G2, G1,
H3, H1
C
923, 925, 927, 929
Buried
C
934 - 938, 940, 942, 944, 946 - 949
J4, J3, J2, J1,
K2, K3, K1,
L1, L2, L3, L4,
M1
D
939, 941, 943, 945
Buried
D
950 - 954, 956, 958, 960, 962 - 965
M4, N1, N2,
N3, P1, P2, R1,
P3, R2, T1, P4,
R3
E
955, 957, 959, 961
Buried
E
966 - 970, 972, 974, 976, 978 - 981
T2, U1, T3, U2,
V1, T4, U3,
F
V2, W1, V3,
W2, Y1
Warp Reference Manual
B
253
Table 2-6. CY37256P256 Node Numbers
Nodes
Pins
Logic Blocks
971, 973, 975, 977
Buried
F
982 - 986, 988, 990, 992, 994 - 997
W3, Y2, W4,
V4, U5, Y3,
V5, W5, Y5,
V6, U7, W6
G
987, 989, 991, 983
Buried
G
998 - 1002, 1004, 1006, 1008, 1010 - 1013
Y6, V7, W7,
Y7, V8, W8,
Y8, U9, V9,
W9, Y9, W10
H
1003, 1005, 1007, 1009
Buried
H
W11, V11,
U11, Y12,
W12, V12,
1014 - 1018, 1020, 1022, 1024, 1026 - 1029
U12, Y13,
W13, V13,
Y14, W14
I
1019, 1021, 1023, 1025
I
Buried
Y15, V14,
W15, Y16,
1030 - 1034, 1036, 1038, 1040, 1042 - 1045 U14, V15, V17, J
W18, Y19,
V18, W19, Y20
B
1035, 1037, 1039, 1041
254
Buried
J
W20, V19,
U19, U18,
1046 - 1050, 1052, 1054, 1056, 1058 - 1061 T17, V20,
U20, T18, T19,
T20, R18, P17
K
1051, 1053, 1055, 1057
K
Buried
Warp Reference Manual
Table 2-6. CY37256P256 Node Numbers
Nodes
Pins
Logic Blocks
R20, P18, P19,
P20, N18,
1062 - 1066, 1068, 1070, 1072, 1074 - 1077 N19, N20,
L
M17, M18,
M19, M20, L19
1067, 1069, 1071, 1073
Buried
L
K17, J20, J19,
J18, J17, H20,
1078 - 1082, 1084, 1086, 1088, 1090 - 1093
M
H19, H18, G20,
G19, F20, G18
1083, 1085, 1087, 1089
Buried
M
E20, G17, F18,
E19, D20, E18,
1094 - 1098, 1100, 1102, 1104, 1106 - 1109 C20, E17,
D18, C9, B20,
C18
N
1099, 1101, 1103, 1005
N
Buried
A20, A19, B18,
B17, C17,
1110 - 1114, 1116, 1118, 1120, 1122 - 1125 C16, B16,
O
A16, C15, D14,
A15, C14
1115, 1117, 1119, 1121
Buried
B
O
C13, B13,
A13, D12, C12,
1126 - 1130, 1132, 1134, 1136, 1138 - 1141 B12, A12,
P
B11, C11, A11,
A10, B10
1131, 1133, 1135, 1137
Buried
P
Table 2-7. CY37256P208 Node Numbers
Nodes
886 - 888, 890, 892, 894, 896, 898, 900 - 901
Warp Reference Manual
Pins
185 - 194
Logic Blocks
A
255
Table 2-7. CY37256P208 Node Numbers
Nodes
B
Pins
Logic Blocks
889, 891, 893, 895, 897, 899
Buried
A
902 - 904, 906, 908, 910, 912, 914, 916 - 917
196 - 200, 202 - 206 B
905, 907, 909, 911, 913, 915
Buried
B
918 - 920, 922, 924, 926, 928, 930, 932 - 933
2 - 6, 8 - 12
C
921, 923, 925, 927, 929, 931
Buried
C
934 - 936, 938, 940, 942, 944, 946, 948 - 949
14 - 18, 20 - 24
D
937, 939, 941, 943, 945, 947
Buried
D
950 - 952, 954, 956, 958, 960, 962, 964 - 965
30 - 39
E
953, 955, 957, 959, 961, 963
Buried
E
966 - 968, 970, 972, 974, 976, 978, 980 - 981
41 - 45, 47 - 51
F
969, 971, 973, 975, 977, 979
Buried
F
982 - 984, 986, 988, 990, 992, 994, 996 - 997
54 - 58, 60 - 64
G
985, 987, 989, 991, 993, 995
Buried
G
998 - 1000, 1002, 1004, 1006, 1008, 1010, 1012 - 1013
66 - 70, 72 - 76
H
1001, 1003, 1005, 1007, 1009, 1011
Buried
H
1014 - 1016, 1018, 1020, 1022, 1024, 1026, 1028 - 1029 81 - 90
I
1017, 1019, 1021, 1023, 1025, 1027
I
Buried
1030 - 1032, 1034, 1036, 1038, 1040, 1042, 1044 - 1045 92 - 96, 98 - 102
J
1033, 1035, 1037, 1039, 1041, 1043
J
Buried
1046 - 1048, 1050, 1052, 1054, 1056, 1058, 1060 - 1061 106 - 115
K
1049, 1051, 1053, 1055, 1057, 1059
K
Buried
1062 - 1064, 1066, 1068, 1070, 1072, 1074, 1076 - 1077 117 - 121, 123 - 127 L
1065, 1067, 1069, 1071, 1073, 1075
Buried
L
1078 - 1080, 1082, 1084, 1086, 1088, 1090, 1092 - 1093 134 - 143
M
1081, 1083, 1085, 1087, 1089, 1091
M
Buried
1094 - 1096, 1098, 1100, 1102, 1104, 1106, 1108 - 1109 145 - 149, 151 - 155 N
1097, 1099, 1101, 1103, 1105, 1107
256
Buried
N
Warp Reference Manual
Table 2-7. CY37256P208 Node Numbers
Nodes
Pins
Logic Blocks
1110 - 1112, 1114, 1116, 1118, 1120, 1122, 1124 - 1125 159 - 168
O
1113, 1115, 1117, 1119, 1121, 1123
O
Buried
1126 - 1128, 1130, 1132, 1134, 1136, 1138, 1140 - 1142 170 - 174, 176 - 180 P
1129, 1131, 1133, 1135, 1137, 1139
Buried
P
Table 2-8. CY37256P160 Node Numbers
Nodes
Pins
Logic Blocks
886, 888, 890, 892, 894, 896, 898, 900
143-150
A
887, 889, 891, 893, 895, 897, 899, 901
Buried
A
902, 904, 906, 908, 910, 912, 914, 916
152 - 159
B
903, 905, 907, 909, 911, 913, 915, 917
Buried
B
918, 920, 922, 924, 926, 928, 930, 932
2 - 5, 7 - 9
C
919, 921, 923, 925, 927, 929, 931, 933
Buried
C
934, 936, 938, 940, 942, 944, 946, 948
11 - 18
D
935, 937, 939, 941, 943, 945, 947, 949
Buried
D
950, 952, 954, 956, 958, 960, 962, 964
23 - 30
E
951, 953, 955, 957, 959, 961, 963, 965
Buried
E
966, 968, 970, 972, 974, 976, 978, 980
32 - 39
F
967, 969, 971, 973, 975, 977, 979, 981
Buried
F
982, 984, 986, 988, 990, 992, 994, 996
42 - 49
G
983, 985, 987, 989, 991, 993, 995, 997
Buried
G
998, 1000, 1002, 1004, 1006, 1008, 1010, 1012
51 - 58
H
999, 1001, 1003, 1005, 1007, 1009, 1011, 1013
Buried
H
1014, 1016, 1018, 1020, 1022, 1024, 1026, 1028
63 - 70
I
1015, 1017, 1019, 1021, 1023, 1025, 1027, 1029
Buried
I
1030, 1032, 1034, 1036, 1038, 1040, 1042, 1044
72 - 79
J
Warp Reference Manual
B
257
Table 2-8. CY37256P160 Node Numbers
Nodes
Pins
Logic Blocks
1031, 1033, 1035, 1037, 1039, 1041, 1043, 1045
Buried
J
1046, 1048, 1050, 1052, 1054, 1056, 1058, 1060
82 - 89
K
1047, 1049, 1051, 1053, 1055, 1057, 1059, 1061
Buried
K
1062, 1064, 1066, 1068, 1070, 1072, 1074, 1076
91 - 98
L
1063, 1065, 1067, 1069, 1071, 1073, 1075, 1077
Buried
L
1078, 1080, 1082, 1084, 1086, 1088, 1090, 1092
103 - 110
M
1079, 1081, 1083, 1085, 1087, 1089, 1091, 1093
Buried
M
1094, 1096, 1098, 1100, 1102, 1104, 1106, 1108
112 - 119
N
1095, 1097, 1099, 1101, 1103, 1105, 1107, 1109
Buried
N
1110, 1112, 1114, 1116, 1118, 1120, 1122, 1124
122 - 129
O
1111, 1113, 1115, 1117, 1119, 1121, 1123, 1125
Buried
O
1126, 1128, 1130, 1132, 1134, 1136, 1138, 1140
131 - 138
P
1127, 1129, 1131, 1133, 1135, 1137, 1139, 1141
Buried
P
Table 2-9. CY37192P160 Node Numbers
Nodes
B
258
Pins
Logic Blocks
886 - 888, 890, 892, 894, 896, 898, 900 - 901
143-150
A
889, 891, 893, 895, 897, 899
Buried
A
902 - 904, 906, 908, 910, 912, 914, 916 - 917
152 - 159
B
905, 907, 909, 911, 913, 915
Buried
B
918 - 920, 922, 924, 926, 928, 930, 932 - 933
2 - 5, 7 - 9
C
921, 923, 925, 927, 929, 931
Buried
C
934 - 936, 938, 940, 942, 944, 946, 948 - 949
11 - 18
D
937, 939, 941, 943, 945, 947
Buried
D
950 - 952, 954, 956, 958, 960, 962, 964 - 965
23 - 30
E
953, 955, 957, 959, 961, 963
Buried
E
Warp Reference Manual
Table 2-9. CY37192P160 Node Numbers
Nodes
Pins
Logic Blocks
966 - 968, 970, 972, 974, 976, 978, 980 - 981
32 - 39
F
969, 971, 973, 975, 977, 979
Buried
F
982 - 984, 986, 988, 990, 992, 994, 996 - 997
42 - 49
G
985, 987, 989, 991, 993, 995
Buried
G
998 - 1000, 1002, 1004, 1006, 1008, 1010, 1012 1013
51 - 58
H
1001, 1003, 1005, 1007, 1009, 1011
Buried
H
1014 - 1016, 1018, 1020, 1022, 1024, 1026, 1028
- 1029
63 - 70
I
1017, 1019, 1021, 1023, 1025, 1027
Buried
I
1030 - 1032, 1034, 1036, 1038, 1040, 1042, 1044
- 1045
72 - 79
J
1033, 1035, 1037, 1039, 1041, 1043
Buried
J
1046 - 1048, 1050, 1052, 1054, 1056, 1058, 1060
- 1061
82 - 89
K
1049, 1051, 1053, 1055, 1057, 1059
Buried
K
1062 - 1064, 1066, 1068, 1070, 1072, 1074, 1076
- 1077
91 - 98
L
1065, 1067, 1069, 1071, 1073, 1075
Buried
L
B
Warp Reference Manual
259
B
260
Warp Reference Manual
Appendix C
Glossary
C
Listed here are the definitions of terms encountered frequently in using VHDL/Verilog,
using Warp, and using programmable logic. Note that the context for the VHDL/Verilog
definitions is that of synthesis (as opposed to simulation) modeling.
C
1076 VHDL
The IEEE specification of the VHDL language.
1164 VHDL
The IEEE specification of the std_logic data type.
1364 Verilog
The IEEE specification of the Verilog language.
actual
The name of the pin to which the signal is being mapped, in port maps used in binding
architectures.
always
The statements in an always block are executed continuously in a looping fashion. If
the always block is controlled by a change in the value of the clock, then the logic will
be sequential, otherwise, the logic for the statements is treated as combinatorial.
analysis
The examination of a VHDL description to ensure that it complies with VHDL syntax
rules. During analysis, Warp determines the design elements (packages, components,
entities, and architectures) that make up the description and places these design
elements into a VHDL library and an associated index. The library and index are then
available for use in synthesis by other descriptions.
architecture
The part of a VHDL description that specifies the behavior or structure of an entity.
Entities and architectures are always paired in VHDL descriptions.
attribute
A named characteristic of a VHDL item. An attribute can be a value, function, type,
range, signal, or constant. An attribute can also be associated with one or more names
in a VHDL description, including entity names, architecture names, labels, and
signals. Once an attribute value is associated with a name, the value of the attribute for
that name can be used in expressions.
back annotation
The process whereby timing or pin placement information is sent back to the simulator
or design entry tools.
262
Warp Reference Manual
back end simulation
C
See simulation back end.
banked output enable
(oe) for FLASH370 CPLDs, a bank is defined as half of a lab and the output enable
control for the upper bank of the lab (macrocells 1 to 8) is separate from the output
enable control for the lower bank of the lab (macrocells 9 to 16).
behavioral VHDL
Refers to the coding style of VHDL where the code uses higher, more abstract
constructs, such as “if then else, ” rather than lower, less abstract constructs, such as
boolean equations, to describe a digital design.
behavioral Verilog
Analogous to behavioral VHDL. The code uses higher, more abstract constructs (e.g.
if-else, case - endcase) rather than boolean equations to describe the design.
binding architecture
An architecture used to map the ports of an entity to the pins of a PLD.
bit_vector
A collection of bits addressed by a common name and index number (an array of bits).
combinatorial
Any datapath that is not registered or latched, and therefore does not have a clock or
latch enable associated with its timing parameters.
component
A description of a design that can be used in another design.
component declaration
That part of a VHDL description that defines a component. The component declaration
is usually encapsulated in a package for export via the library mechanism.
component instantiation statement
A statement in a VHDL description that creates an instance of a previously defined
component.
concurrent statement
A statement in an architecture that executes or is modeled concurrently with all other
statements in the architecture.
constant declaration
Warp Reference Manual
263
An element of a VHDL description that declares a named data item to be a constant
value.
C
control file
(CTL) a file used for attaching synthesis directives, attributes, and pin node
information to signals and components to a VHDL design. Separating this from the
VHDL file enables the file to be device independent.
CPLD
(Complex Programmable Logic Device) is a higher density PLD that employs a
central programmable interconnect matrix to internally connect multiple LABs
together.
design architecture
An architecture paired with a previously declared entity that describes the behavior or
structure of that entity.
design unit
An entity declaration, a package declaration, an architecture body, or a package body.
directive driven module generation
Directives that will specify either a speed or area optimized implementing of a
component from a given operator. For instance, the “+” operator could be recognized
as an adder.
directives
Instructions to specify software flow. For instance, a synthesis directive such as
ff_type tells Warp what kind of flip-flop is to be used.
don’t care synthesis/optimization
The use of the don’t care conditions to synthesize the most minimum boolean
equations describing a design.
EDIF
(Electronic Data Interchange Format) an industry standard netlist representation of a
design that is often used to transport a schematic design from one design platform to
another.
entity
That part of a VHDL description that lists or describes the ports (the interfaces to the
outside) of the design. An entity describes the names, directions, and data types of
each port.
264
Warp Reference Manual
export1076/1164
C
The algorithm that takes in a schematic entry and outputs a structural VHDL
representation, which can be read directly into a VHDL compiler such as Warp.
factoring point
In synthesis, the preservation of an intermediate node. For instance, in the following
equations, “x <= a or b” and “ y <= x or c”, the node “x” could be made a factoring
point in the design by the synthesis tool or the node “x” could be eliminated by
implementing “y <= a or b or c”. (See synthesis_off attribute)
fanout
The number of gates that a node must drive.
finite state machine
(FSM) a digital design characterized by multiple states (signals held in registers) and
at least one output such that external or feedback inputs enable transitions from one
state to another.
fitting
A process which converts a description of a design into a programming file, which a
programmer can use to program a logic device such as a PLD or a CPLD.
fixed macrocell assignment
Forces a given function into a specific macrocell in a PLD or a CPLD.
formal
In port maps used in binding architectures, the signal name on the component.
front end simulation
See simulation front end.
function
A subprogram whose invocation is an expression and which therefore returns a value.
See subprogram and procedure.
function body
A portion of a VHDL description that defines the implementation of a function.
function declaration
A portion of a VHDL description that defines the parameters passed to and from a
function invocation, such as the function name, return type, and list of parameters.
function invocation
Warp Reference Manual
265
A reference to a function from inside a VHDL description.
C
functional simulation
See simulation front end.
Galaxy
The name for the Graphical User Interface for the Warp synthesis tool.
gate instantiation
Verilog supports a set of pre-defined gates known collectively as “primitives.” These
are equivalent to modules, but are pre-defined and available to use automatically.
These include and/or gates, but/not gates and butif/notif gates.
generic
A VHDL construct that is used with an entity declaration to allow the communication
of parameters between levels of hierarchy. A generic is typically used to define
parameterized components wherein the size or other configuration are specified during
the instantiation of the component. See entity.
generic map
A VHDL construct that enables an instantiating component to pass environment
values to an instantiated component. Typically, a generic map is used to size an array
or a bit vector or provide true/false environment values.
GUI
(Graphical User Interface) the Galaxy interface for Warp.
half lab
In FLASH370 CPLD devices, the macrocells 1 to 8 or 9 to 16 within a logic block.
HDL
(Hardware description language) is a language such as VHDL or Verilog used to
describe a digital design as an alternate method to schematic entry.
hierarchical VHDL
Uses the instantiation(placement) of pre-defined blocks (components) to build a
structural design.
instantiation
The process of creating an instance (a copy) of a component and connecting it to other
components in the design.
JEDEC file
For PLDs and CPLDs, the programming file created from the Warp compiler.
266
Warp Reference Manual
library
C
A collection of previously analyzed VHDL design units. In Warp, a library is a
directory containing an index and one or more VHDL files.
license file
Is needed only for Warp3 users to run the Viewlogic tools.
logic block
(LAB) one of multiple blocks of logic within a CPLD that are interconnected together
via a global interconnect. A logic block in a CPLD is similar in nature and capability to
a small PLD such as the 22V10. A logic block typically consists of a product term
array, a product term distribution scheme, and a set of macrocells.
logic minimization
In the Warp compiler, the part of the synthesis where the boolean equations of a
design are reduced to the smallest number of product terms.
LPM
(Library of Parameterizable Modules) the new schematic library that enables the user
to select customized components that are optimized for area or performance.
macrocell
A replicated element of logic in PLD and CPLD architectures that typically contains a
configurable memory element, polarity control, and one or more feedback paths to the
global interconnect.
mixed mode VHDL
In schematic capture, a description of a design that mixes symbols described in textual
VHDL with schematic elements.
mode
Associated with signals defined in a VHDL entity’s port declaration or a Verilog
module’s port declaration. A mode defines the direction of communication a signal can
have with other levels of hierarchy.
module
A module is the basic hierachical building block in Verilog. It is equivalent to the
entity-architecture pair in VHDL and includes the port-list, wire and reg declarations,
tasks and functions, etc. The module is a compilable unit.
module generation/operator inferencing
See UltraGen.
Warp Reference Manual
267
package
C
A collection of VHDL declarations, including component, type, subtype, and constant
declarations, that are intended for use by other design units.
package body
The definition of the elements of a package. A package body typically contains the
bodies of functions declared within the package.
package declaration
The declaration of the names and values of components, types, subtypes, constants,
and functions contained in a package.
parameter
Parameter is a keyword used to define constants in a module in Verilog. A parameter
value can be overridden at compile time. Parameters can also be changed at module
instantiation by use of the defparam statement.
partitioning
In an HDL compiler, this is the breakdown of a digital design to a boolean description
of the design. This can also mean the placement of a large design into more than one
target device.
performance
The maximum clock frequency or slowest propagation delay of a design as
implemented in a particular programmable logic device. Performance is typically
measured in nanoseconds for propagation delay or in megahertz for clock frequency.
PIM
(Programmable Interconnect Matrix) in CPLDs, the means with which signals
(dedicated inputs, I/O inputs, and macrocell outputs) are fed back to the same logic
block or distributed to the other logic blocks of the device. The design of the PIM
varies among CPLD vendors and affects the speed, routability, and timing
characteristics of the device.
PLA format
For CPLDs and PLDs, this is the intermediate sum of products boolean description of
a design that is the input file into the fitter for placing the design into a specific device.
PLD
(Programmable Logic Device) is the name of a broad range of products whose
architecture is composed of an AND product term array, a fixed “Oring” of the product
terms, a programmable macrocell (on some PLDs), and an output macrocell (on some
PLDs).
268
Warp Reference Manual
port
A point of connection between a component and anything that uses the component.
port map
An association between the ports of a component and the signals of an entity
instantiating that component. Within the context of a binding architecture, a port map
is a VHDL construct that associates signals from an entity with pins on a PLD.
Powerview
The name of Viewlogic’s design entry and simulation tools, included in Warp3, that
runs on the SUN workstation.
primitives
A schematic element or VHDL component that is not built from other schematic
elements or components.
procedure
A subprogram whose invocation is a statement and which therefore does not return a
value. See subprogram and function.
procedure body
A portion of a VHDL description that defines the implementation of a procedure.
procedure declaration
A portion of a VHDL description that defines the parameters passed to and from a
procedure invocation, such as the procedure’s name and list of parameters.
procedure invocation
A reference to a procedure from inside a VHDL description.
process
A collection of sequential statements appearing in a design architecture.
product term
For CPLDs and PLDs, this is the boolean “anding” of a variable number of signals to
form the “products” part of the “sum of products” implementation that feeds into the
macrocell of the device.
Proseries
The name of Viewlogic’s low-end design entry and simulation tools that run on the
PC.
sensitivity list
Warp Reference Manual
269
C
A list of signals that appears immediately after the process keyword and specifies
when the process statements are activated. The process is executed when any signal in
the sensitivity list changes value.
C
sequential statement
A statement appearing within a process. All statements within a process are executed
sequentially.
signal
A data path from one component to another.
signal declaration
A statement of a signal name, its direction of flow, and the type of data that it carries.
simulation front end
The functional simulation on VHDL code done before the design is synthesized to a
particular device.
simulation back end
The functional or timing simulation done after a design is synthesized to a particular
device.
skew
A measure of the maximum difference between two or more delay paths.
source level simulation
See simulation front end.
std_logic_vector
Same as std_logic except for multiple bits.
structural VHDL/Verilog
Describes a design much like a schematic which instantiates (places) pre-defined
blocks (components) and specifies the exact connection of these components.
subprogram
A sequence of declarations and statements that can be invoked repeatedly from
different locations in a VHDL description. VHDL recognizes two kinds of
subprograms: procedures and functions.
subtype
A restricted subset of the legal values of a type.
subtype declaration
270
Warp Reference Manual
A VHDL construct that declares a name for a new type, known as a subtype. A
subtype declaration specifies the base type and declares the value range of the subtype.
sum-splitting
For PLDs, the result of implementing a large sum or products equation in more than
one pass through the AND array by implementing portions of the product terms in one
or more macrocells on the first pass and ORing the partial results in another macrocell
as a second pass through the AND array.
synthesis
The production of a file to be mapped to a PLD containing the design elements
extracted from VHDL descriptions during the analysis phase. The file is a technologymapped structural netlist description that is fitted to a user-specified device.
synthesis_off
See factoring point.
task
A task in Verilog allows the user to organize their code logically. It is similar to
procedures in programming languages. It has inputs and outputs as arguments, it can
call other tasks and functions and it can contain delay, event and timing control
statements.
type
An attribute of a VHDL data object that determines the values that the object can hold.
Examples of types are bit and std_logic. Objects of type bit can hold values 0
or 1. Objects of type std_logic can hold values of U, X, 0, 1, Z, W, L, H, or -.
UltraGen
The ability of the Warp compiler to infer operations from behavioral VHDL code,
which results in optimal implementations of the basic operations.
Verilog
An alternate HDL to VHDL.
VHDL
(Very High Speed Integrated Circuit (VHSIC) Hardware Description Language) is a
powerful language used to describe digital designs and is the language interpreted by
the Warp compiler.
ViewDraw
The schematic capture tool from Viewlogic that is the schematic capture tool for
Warp3.
Warp Reference Manual
271
C
ViewSim
C
The timing simulation tool from Viewlogic that is used in Warp3.
Workview Office
The name of Viewlogic’s design entry and simulation tools, provided with Warp3 that
runs on the Windows 95 and Windows NT.
272
Warp Reference Manual
Index
- 11
.jed extension
.jed file 21
.rpt file 21
216
Symbols
1076 VHDL 262
1164 VHDL 262
1364 Verilog 262
A
-a option 11
actual 262
alias detection 204
always 262
analysis 262
architecture 262
area 18
area optimization 73, 83
attribute 262
attribute keyword 120, 122
attribute mechanism 92, 93
Attribute placement 125
attributes 59
aynthesis and optimization 203
B
-b option 10
back annotation 262
back end simulation 263
back-annotation 49
banked output enable 263
behavioral Verilog 263
behavioral VHDL 263
binding architecture 263
bit_vector 263
buried nodes 13
C
checksum
file 218
fuse 218
Class of VHDL objects
combinatorial 263
command line 59, 61
Command options
-a 11
-b 10
-d 9
-e 11
-f 11
-h 13
-l 14
-m 14
-o 15
-p 15
-q 16
-r 16
-s 16
-v 17
-w 17
-xor2 17
-yga 18
-ygc 18
-ygs 18
-yl 18
120, 122
I
Index
I
-ys0 20
-yu 19
-yv 19
command syntax 8
Compiler, synthesis 2
component 263
component declaration 263
component instantiation statement 263
concurrent statements 263
constant declaration 263
control file 14, 60, 61, 120, 122, 264
CPLD 264
CPLD/PLD fitting 205
CPLDs 21
CY37192P160 Node Numbers 258
CY37256P160 Node Numbers 257
CY37256P208 Node Numbers 255
CY37256P256 Node Numbers 253
Cypress BBS 219
Cypress modules
IN 170
MBUF 167
MGND 168
MPARITY 166
MVCC 169
OUT 171
TRI 172
D
-d option 9
datapath operators 18
design architecture 264
design unit 264
device package 15
device programmer 218
directive driven module generation 264
Directive-name 121, 123
directives 264
directives, about 92, 93
Don’t care logic 4
don’t care synthesis/optimization 264
274
E
-e option 11
EDIF 264
entity 264
enum_encoding directive 96
equations 206
errors 11
Espresso 15
export1076/1164 265
exporting schematics 34, 47
F
-f option 11
factoring point 265
factoring. See logic factoring
fanout 265
ff_type 75, 85
ff_type directive 97
finite state machine 265
fitter options 11
fitting 200, 201, 265
fixed macrocell assignment 265
formal 265
front end 200, 201
front end compiler 200
front end simulation 265
function 265
function body 265
function declaration 265
function invocation 265
functional simulation 266
G
Galaxy 266
generic 266
generic map 266
global resource reduction 205
glossary (Appendix A) ??–271
goal 73, 80, 83, 89
goal directive 98
GUI 266
GUI in Warp 4, 5
Warp Language Reference Manual
Index
MADD_SUB 148
MAND 134
MBUSTRI 140
MCLSHIFT 146
MCNSTNT 132
MCOMPARE 150
MCOUNTER 155
MDECODE 144
MFF 160
MINV 133
MLATCH 158
MMULT 152
MMUX 142
MOR 136
MSHFTREG 163
MXOR 138
lpmlocal 26, 42, 43
H
-h option 13
half lab 266
HDL 266
help 13
hierarchical attributes 92, 94
hierarchical inheritance 59, 61
hierarchical VHDL 92, 94, 266
I
IEEE1164 VHDL 178
IEEE1364 Verilog 190
Impulse3 219
IN 170
instantiation 266
Intergraph 190
M
J
JEDEC File 216
JEDEC file 12, 14, 266
JEDEC Hex 217
JEDEC map, overview 2
JEDEC Normal 217
JEDEC to POF 219
L
-l option 14
lab_force 77, 86
lab_force directive 100
latches 18
library 267
library management 11, 14, 16
Library of Parameterized Modules (LPM)
license file 267
logic block 267
logic factoring 12, 15
logic minimization 267
LPM 25, 42, 267
LPM (Library of Parameterized Modules)
LPM modules
MABS 154
4, 5
4, 5
Warp Language Reference Manual
-m option 14
MABS 154
macrocell 267
MADD_SUB 148, 175
MAND 134
MBUF 167
MBUSTRI 140
MCLSHIFT 146
MCNSTNT 132
MCOMPARE 150
MCOUNTER 155, 176
MDECODE 144
MFF 160
MGND 168
MINV 133
mixed mode VHDL 267
mixed-mode 24, 40
MLATCH 158
MMULT 152
MMUX 142
mode 267
module 267
module generation 267
MOR 136
MPARITY 166
I
Index
MSHFTREG
MVCC 169
MXOR 138
163
POF files 219
polarity 12, 79, 88
polarity directive 112
polarity optimization 205
port 269
port map 269
Powerview 269
primitives 269
procedure 269
procedure body 269
procedure declaration 269
procedure invocation 269
process 269
product term 269
programming adapters 219
programming file 216
Proseries 269
N
no_factor directive 101
no_latch directive 102
node_num 76, 86
node_num directive 104
node-numbers 12
O
I
-o option 15
Object-name 121, 123
one_hot_one 68
operator inferencing 267
opt_level directive 105
optimization 15, 204
order_code 81
order_code directive 106
Ordering Code 15
OUT 171
output files 21
Q
-q option 16
QP field 218
quiet 16
QV field 218
R
P
-p option 15
package 268
package body 268
package declaration 268
parameter 268
part_name 80
part_name directive 107
partitioning 268
performance 268
PIM 268
pin assignments 12
pin_avoid directive 108
pin_numbers 81
pin_numbers directive 110,
PLA format 268
Placing attributes 125
PLD 268
276
-r option 16
recommendations 21
register optimization 205
report file 200
running Warp. See command syntax
S
124
-s option 16
schematic attributes 60
sensitivity list 269
sequential statements 270
signal 270
signal declaration 270
simulation back end 270
simulation front end 270
skew 270
smart compile 14
Warp Language Reference Manual
Index
soft node 204
source level simulation 270
specifying a target device 9
specifying register types 11
speed 18
speed bin 15
speed optimization 79, 88
SpeedWave 178, 180, 188
state_encoding 68
state_encoding directive 113
std_logic_vectors 270
structural VHDL 270
subprograms 270
subtype 270
subtype declaration 270
sum_split 78, 87
sum_split directive 115
sum-splitting 205, 271
symbol to VHDL 36, 51
synthesis 271
synthesis and optimization 200,
Synthesis compiler 2
Synthesis directives
attribute mechanism 92, 93
enum_encoding 96
ff_type 97
goal 98
lab_force 100
no_factor 101
no_latch 102
node_num 104
opt_level 105
order_code 106
part_name 107
pin_avoid 108
pin_numbers 110
polarity 112
state_encoding 113
sum_split 115
synthesis_off 116
synthesis directives 56
applying 59, 61
listing 57
scope and inheritance 59, 60
strategy 56
summary 89
understanding 56
synthesis_off 70, 74, 84, 271
synthesis_off directive 116
synthesizing latches 18
T
task 271
technology mapping 205
test vectors 218
three-state 13
Three-stated logic 4
Tool flow for Warp 2
TRI 172
tuning 56
type 271
U
201
Warp Language Reference Manual
UltraGen 271
unused I/Os 13
update LPM symbols
37, 52
V
-v option 17
Value of directive 121, 123
VCS 190, 197
VeriBest 190, 197
Verilog 271
Verilog simulation 190
Verilog-XL 190
VerilogXL 197
VHDL 271
class 120, 122
VHDL 1164 4
VHDL simulation 178, 190
VHDL to symbol 36, 51
ViewDraw 24, 40, 271
$ARRAY 125
attributes 125
synthesis directives 124
viewdraw.ini 43
Viewlogic 178
ViewSim 178, 272
I
Index
Virtual substitution
V-System 187
119
W
-w option 17
warnings 17
Warp command options. See Command options
warp command syntax 8
Warp command syntax. See command syntax
warp.rc file 10
Warp3 tool flow 2
work library 10, 11, 14, 16
Workview Office 272
X
XOR 18
-xor2 option
I
17
Y
-yga option 18
-ygc option 18
-ygs option 18
-yl option 18
-ys0 option 20
-yu option 19
-yv option 19
278
Warp Language Reference Manual