Warp 
HDL Development System
Getting Started Manual
Cypress Semiconductor
3901 North First Street
San Jose, CA 95134
(408) 943-2600
June 14, 2002 2:26 pm
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June 14, 2002 2:26 pm
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Contents
Contents
Chapter 1
Installation ............................................................... 1
1.1 PC Installation ...........................................................................2
1.1.1 System Requirements .............................................................. 2
1.1.2 Warp On-line Documents......................................................... 2
1.1.3 Windows Platform Installation .................................................. 3
1.1.3.1 Warp Software ............................................................... 3
1.1.4 PC - Known Installation Problems ............................................ 3
1.1.5 Commonly Asked Questions About PC Installation.................. 3
1.2 Solaris Installation .....................................................................4
1.2.1 Installing the Software .............................................................. 4
1.2.1.1 On Solaris 2.5 ................................................................ 4
1.2.2 Setting up the User’s Environment ........................................... 5
1.2.2.1 For C Shell users: .......................................................... 6
1.2.2.2 For Bourne shell users: .................................................. 6
1.2.3 Run Warp ................................................................................. 7
1.2.4 Setting up the Printer in Galaxy ................................................ 7
1.2.4.1 PPD Files ....................................................................... 7
1.2.4.2 Configuring Wind/U for Printing ...................................... 7
1.2.4.3 Sending Output to a File .............................................. 10
1.2.4.4 Solving Printing Problems ............................................ 10
1.2.5 To Read Warp On-line Documentation................................... 11
Chapter 2
Ultra37000 Tutorials............................................... 13
2.1 Introduction .............................................................................14
2.1.1 Product Descriptions .............................................................. 14
2.1.2 Conventions............................................................................ 14
2.1.3 Differences between Operating Systems ............................... 16
2.2 Designing a Soda Machine for Ultra37000 (VHDL) ................18
2.2.1 Design Description ................................................................. 18
2.2.2 Design Solution ...................................................................... 18
2.2.3 Starting Warp Applications ..................................................... 19
2.2.4 Creating A New Project .......................................................... 19
2.2.5 Creating the VHDL File........................................................... 21
2.2.6 The binctr.vhd VHDL description ............................................ 22
2.2.6.1 Writing the Entity Declaration ....................................... 23
2.2.6.2 Writing the Architecture ................................................ 23
2.2.6.3 Writing the Package Declaration .................................. 25
2.2.6.4 Including the Libraries .................................................. 26
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2.2.7 Creating a Top-Level Description ........................................... 26
2.2.8 Selecting Files for Compilation ............................................... 29
2.2.8.1 To add a VHDL file: ...................................................... 29
2.2.9 Compiling and Synthesizing a Top-Level File......................... 30
2.2.10 Choosing Compiler Options.................................................. 30
2.2.10.1 Setting Unused Outputs ............................................. 31
2.2.10.2 Choosing Tech Mapping Options ............................... 32
2.2.10.3 Choosing a Timing Model for Active-HDL Sim (PC) .. 32
2.2.10.4 Setting the Top-Level File .......................................... 32
2.2.10.5 Compiling and Synthesizing the File .......................... 33
2.2.11 Simulating the Behavior of the Design ................................. 36
2.2.12 Starting Active-HDL Sim ....................................................... 36
2.2.13 Creating a View .................................................................... 37
2.2.14 Setting Stimulus Signal Values............................................. 39
2.2.15 Running the Simulation ........................................................ 42
2.2.16 Starting Active-HDL FSM ..................................................... 44
2.2.16.1 Creating A New Project .............................................. 44
2.2.17 Creating the State Machine .................................................. 48
2.2.18 Selecting the Libraries .......................................................... 55
2.2.19 Generating VHDL ................................................................. 56
2.3 Designing a Parking Garage Monitor (VHDL) .........................59
2.3.1 Design Description ................................................................. 59
2.3.2 Design Solution ...................................................................... 59
2.3.3 Getting Started ....................................................................... 60
2.3.4 Creating a New Project........................................................... 60
2.3.5 Writing the VHDL File ............................................................. 60
2.3.5.1 Writing the Entity Declaration ....................................... 62
2.3.5.2 Writing the Architecture ................................................ 64
2.3.5.3 Writing the Package Declaration .................................. 67
2.3.6 Creating the Top-Level Description ........................................ 69
2.3.7 Selecting Files for Compilation ............................................... 74
2.3.8 Compiling and Synthesizing the Design ................................. 74
2.3.9 Choosing Compiler Options.................................................... 74
2.3.9.1 Setting Unused Outputs ............................................... 74
2.3.9.2 Choosing Tech Mapping Options ................................. 75
2.3.9.3 Choosing a Timing Model for Active-HDL Sim (PC) .... 75
2.3.10 Setting the Top-Level File..................................................... 75
2.3.11 Compiling and Synthesizing the File .................................... 76
2.3.12 Simulating the Behavior of the Design with Active-HDL Sim 78
2.3.13 Starting Active-HDL Sim ....................................................... 78
2.3.14 Creating a View .................................................................... 79
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2.3.15 Setting Stimulus Signal Values............................................. 81
2.3.16 Running the Simulation ........................................................ 83
2.3.17 Back-Annotating Pin Assignment Information ...................... 85
2.4 Designing a Soda Machine for Ultra37000 (Verilog)...............86
2.4.1 Design Description ................................................................. 86
2.4.2 Design Solution ...................................................................... 86
2.4.3 Starting Warp Applications ..................................................... 86
2.4.4 Creating A New Project .......................................................... 87
2.4.5 Creating the Verilog File ......................................................... 88
2.4.6 Creating a Top-Level Description ........................................... 92
2.4.7 Selecting Files for Compilation ............................................... 95
2.4.7.1 To add a Verilog file: .................................................... 96
2.4.8 Compiling and Synthesizing a Top-Level File......................... 96
2.4.8.1 Choosing Compiler Options ......................................... 96
2.4.8.2 Setting Unused Outputs ............................................... 97
2.4.8.3 Choosing Tech Mapping Options ................................. 97
2.4.8.4 Choosing a Timing Model for Active-HDL Sim (PC) .... 97
2.4.8.5 Setting the Top-Level File ............................................ 98
2.4.8.6 Compiling and Synthesizing the File ............................ 98
2.5 Designing a Parking Garage Monitor (Verilog) .....................101
2.5.1 Design Description ............................................................... 101
2.5.2 Design Solution .................................................................... 101
2.5.3 Getting Started ..................................................................... 102
2.5.4 Creating a New Project......................................................... 102
2.5.5 Creating the Verilog File ....................................................... 102
2.5.6 Creating a Top-Level Description ......................................... 103
2.5.7 Selecting Files for Compilation ............................................. 105
2.5.8 Compiling and Synthesizing a Top-Level File....................... 106
2.5.9 Choosing Compiler Options.................................................. 106
2.5.9.1 Setting Unused Outputs ............................................. 106
2.5.9.2 Choosing Tech Mapping Options ............................... 107
2.5.9.3 Choosing a Timing Model for Active-HDL Sim (PC) .. 107
2.5.10 Setting the Top-Level File................................................... 107
2.5.11 Compiling and Synthesizing the File .................................. 108
2.5.12 Simulating the Behavior of the Design ............................... 109
Chapter 3
Delta39K and Quantum38K Tutorials................. 111
3.1 Introduction ...........................................................................112
3.1.1 Product Descriptions ............................................................ 112
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3.1.2 Conventions.......................................................................... 113
3.1.3 Differences between Operating Systems ............................. 115
Delta39K and Quantum38K Design Tutorials (VHDL)....... 116
3.2 Designing a Dual-Port Memory Circuit (VHDL).....................117
3.2.1 Design Description ............................................................... 117
3.2.2 Design Solution .................................................................... 117
3.2.3 Starting Warp Applications ................................................... 117
3.2.4 Creating A New Project ........................................................ 117
3.2.5 Creating the VHDL File......................................................... 120
3.2.6 The dual_port VHDL description .......................................... 121
3.2.6.1 Including the Libraries ................................................ 122
3.2.6.2 Writing the Entity Declaration ..................................... 122
3.2.6.3 Writing the Architecture .............................................. 123
3.2.7 Selecting Files for Compilation ............................................. 125
3.2.7.1 To add a VHDL file: .................................................... 125
3.2.8 Setting the Top-Level File..................................................... 126
3.2.9 Compiling and Synthesizing a Top-Level File....................... 127
3.2.10 Choosing Compiler Options................................................ 127
3.2.10.1 Setting Unused Outputs ........................................... 128
3.2.10.2 Choosing Tech Mapping Options ............................. 128
3.2.10.3 Choosing a Timing Model ........................................ 129
3.2.11 Compiling and Synthesizing the File .................................. 129
3.2.12 Modifying the I/O Standards ............................................... 131
3.2.13 Final code for dual_port.vhd ............................................... 134
3.3 Designing a Single-Port ROM memory circuit (VHDL)..........136
3.3.1 Design Description ............................................................... 136
3.3.2 Starting Warp Applications ................................................... 137
3.3.3 Creating the Design Project.................................................. 137
3.3.4 Creating the VHDL File......................................................... 139
3.3.5 The single_port VHDL description ........................................ 140
3.3.5.1 Including the Libraries ................................................ 141
3.3.5.2 Writing the Entity ........................................................ 141
3.3.5.3 Writing the Architecture .............................................. 141
3.3.6 Adding the File to the Project ............................................... 144
3.3.6.1 To add a VHDL file: .................................................... 144
3.3.6.2 To add a ROM file: ..................................................... 145
3.3.7 Setting the File as Top-Level ................................................ 145
3.3.8 Configuring Compiler Options .............................................. 145
3.3.8.1 Choosing Tech Mapping Options ............................... 146
3.3.8.2 Choosing Messaging Options .................................... 146
3.3.9 Design Compilation and Synthesis ....................................... 147
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3.3.10 The final code for single_port.vhd ...................................... 149
3.4 Designing a Synchronous FIFO memory (VHDL) .................150
3.4.1 Design Description ............................................................... 150
3.4.2 Design Description ............................................................... 150
3.4.3 Starting Warp Applications ................................................... 150
3.4.4 Creating the Design Project.................................................. 150
3.4.5 Creating the VHDL File......................................................... 152
3.4.6 The pll_clocked_fifo VHDL description ................................. 154
3.4.6.1 Including the Libraries ................................................ 154
3.4.6.2 Writing the Entity ........................................................ 154
3.4.6.3 Writing the Architecture .............................................. 155
3.4.7 Adding the File to the Project ............................................... 158
3.4.7.1 Setting the File as Top-Level ..................................... 159
3.4.8 Configuring Compiler Options .............................................. 159
3.4.9 Design Compilation and Synthesis ....................................... 161
3.4.10 The final code for pll_clocked_fifo.vhd ............................... 163
Delta39K and Quantum38K Tutorials (Verilog) ................. 166
3.5 Designing a Dual Port Memory (Verilog)...............................167
3.5.1 Design Description ............................................................... 167
3.5.2 Design Solution .................................................................... 167
3.5.3 Starting Warp Applications ................................................... 167
3.5.4 Creating the Design Project.................................................. 167
3.5.5 Creating the Verilog File ....................................................... 169
3.5.5.1 Including Relevant Libraries ....................................... 170
3.5.5.2 Writing the Module ..................................................... 171
3.5.6 Adding the File to the Project ............................................... 173
3.5.6.1 To add a Verilog file: .................................................. 173
3.5.6.2 Setting the File as Top-Level ..................................... 174
3.5.7 Configuring Compiler Options .............................................. 175
3.5.8 Design Compilation and Synthesis ....................................... 177
3.5.9 Final code for dual_port.v ..................................................... 178
3.6 Designing a single-port ROM memory circuit (Verilog) .........181
3.6.1 Design Description ............................................................... 181
3.6.2 Starting Warp Applications ................................................... 182
3.6.3 Creating the Design Project.................................................. 182
3.6.4 Creating the Verilog File ....................................................... 184
3.6.5 The single_port Verilog description ...................................... 184
3.6.5.1 Including the Libraries ................................................ 184
3.6.5.2 Writing the Module ..................................................... 185
3.6.5.3 Writing the ROM file ................................................... 186
3.6.6 Adding the Files to the Project.............................................. 187
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3.6.6.1 To add a Verilog file: .................................................. 187
3.6.6.2 To add a ROM file: ..................................................... 188
3.6.7 Setting the File as Top-Level ................................................ 188
3.6.8 Configuring Compiler Options .............................................. 188
3.6.9 Design Compilation and Synthesis ....................................... 190
3.6.10 Final code for single_port.v ................................................ 192
3.7 Designing a synchronous FIFO memory (Verilog) ................193
3.7.1 Design Description ............................................................... 193
3.7.2 Design Solution .................................................................... 193
3.7.3 Starting Warp Applications ................................................... 193
3.7.4 Creating the Design Project.................................................. 193
3.7.5 Creating the Verilog File ....................................................... 196
3.7.6 The pll_clocked_fifo Verilog description ............................... 196
3.7.6.1 Including Relevant Libraries ....................................... 197
3.7.6.2 Writing the Module ..................................................... 197
3.7.7 Adding the File to the Project ............................................... 200
3.7.7.1 To add a Verilog file: .................................................. 200
3.7.8 Setting the File as Top-Level ................................................ 200
3.7.9 Configuring Compiler Options .............................................. 201
3.7.10 Design Compilation and Synthesis ..................................... 202
3.7.11 Final code for pll_clocked_fifo.v ......................................... 204
Choosing a Timing Model for Active-HDL Sim (PC) ....... 206
3.7.12 Simulating the Behavior of the Design ............................... 206
3.7.12.1 Starting Active-HDL Sim .......................................... 206
3.7.12.2 Creating a View ........................................................ 208
3.7.12.3 Setting Stimulus Signal Values ................................ 210
3.7.12.4 Running the Simulation ............................................ 213
Chapter 4
Warp Professional & Enterprise Tutorials........ 217
Professional and Enterprise Tutorials ............................... 218
4.1 Designing a Drink Machine in Warp P/E (VHDL) ..................218
4.1.1 Launch the Warp P/E tool..................................................... 218
4.1.2 Creating the Project .............................................................. 218
4.1.3 Starting the Tutorial .............................................................. 220
4.1.3.1 Adding Existing Files .................................................. 221
4.1.3.2 Functional Simulation in Warp Enterprise .................. 222
4.1.3.3 Device Selection in Warp P/E .................................... 223
4.1.3.4 Setting Compiler Options in Warp P/E ....................... 224
4.1.3.5 Compiling the Design ................................................. 225
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4.1.3.6 Viewing the Report File .............................................. 226
4.1.3.7 Timing Simulation in Warp P/E .................................. 226
4.1.3.8 Additional Information ................................................ 226
4.2 Designing a Drink Machine in Warp P/E (Verilog) ................227
4.2.1 Launch the Warp P/E tool..................................................... 227
4.2.2 Creating the Project .............................................................. 227
4.2.3 Starting the Tutorial .............................................................. 229
4.2.3.1 Adding Existing Files .................................................. 230
4.2.3.2 Functional Simulation in Warp Enterprise .................. 231
4.2.3.3 Device Selection in Warp P/E .................................... 232
4.2.3.4 Setting Compiler Options in Warp P/E ....................... 232
4.2.3.5 Compiling the Design ................................................. 234
4.2.3.6 Viewing the Report File .............................................. 235
4.2.3.7 Timing Simulation in Warp P/E .................................. 235
4.2.3.8 Additional Information ................................................ 235
Chapter 5
PSI Device Tutorial .............................................. 237
VHDL PSI Device (CYP25G01K100) Tutorial...................... 238
5.1 Designing with the 25G01 PSI Device (VHDL) .....................238
5.1.1 Design Description ............................................................... 239
5.1.2 Design Solution .................................................................... 240
5.1.3 Starting Warp Applications ................................................... 241
5.1.4 Creating A New Project ........................................................ 241
5.1.5 Creating the VHDL File......................................................... 242
5.1.6 The psi_serdes VHDL description ........................................ 244
5.1.6.1 Including the Libraries ................................................ 244
5.1.6.2 Writing the Entity Declaration ..................................... 244
5.1.6.3 Writing the Architecture .............................................. 245
5.1.7 Selecting Files for Compilation ............................................. 248
5.1.7.1 To add a VHDL file: .................................................... 249
5.1.8 Setting the Top-Level File..................................................... 249
5.1.9 Creating the Control File....................................................... 250
5.1.10 Compiling and Synthesizing a Top-Level File..................... 253
5.1.11 Choosing Compiler Options................................................ 253
5.1.11.1 Setting Unused Outputs ........................................... 253
5.1.11.2 Choosing Tech Mapping Options ............................. 253
5.1.11.3 Choosing a Timing Model ........................................ 254
5.1.12 Compiling and Synthesizing the File .................................. 254
5.1.13 Final code for psi_serdes.vhd............................................. 256
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Verilog PSI Device (CYP25G01K100) Tutorial ................... 260
5.2 Designing with the 25G01 PSI Device (Verilog)....................260
5.2.1 Design Description ............................................................... 261
5.2.2 Design Solution .................................................................... 261
5.2.3 Starting Warp Applications ................................................... 262
5.2.4 Creating a New Project......................................................... 262
5.2.5 Creating the Verilog file ........................................................ 263
5.2.6 The psi_serdes Verilog Description ...................................... 264
5.2.6.1 Module Definition ....................................................... 265
5.2.6.2 Writing the Behavior of the PSI module ..................... 266
5.2.7 Selecting Files for Compilation ............................................. 268
5.2.7.1 To add a Verilog file: .................................................. 268
5.2.8 Setting the Top-Level File..................................................... 269
5.2.9 Creating the Control File....................................................... 270
5.2.10 Compiling and Synthesizing a Top-Level File..................... 272
5.2.11 Choosing Compiler Options................................................ 272
5.2.11.1 Setting Unused Outputs ........................................... 272
5.2.11.2 Choosing Tech Mapping Options ............................. 272
5.2.11.3 Choosing a Timing Model ........................................ 273
5.2.12 Compiling and Synthesizing the File .................................. 273
5.2.13 Final code for psi_serdes.v................................................. 275
VHDL PSI Device (CYP15G04K100) Tutorial...................... 278
5.3 Designing with Frequency Agile PSI .....................................280
5.3.1 Design Description ............................................................... 280
5.3.2 Design Solution .................................................................... 280
5.3.2.1 Programmable Logic .................................................. 280
5.3.2.2 SERDES .................................................................... 281
5.3.3 Starting Warp Applications ................................................... 281
5.3.3.1 For Warp Users .......................................................... 281
5.3.3.2 For Warp Professional Users ..................................... 281
5.3.3.3 For Warp Enterprise Users ........................................ 281
5.3.4 Creating a New Design......................................................... 282
5.3.5 Creating the VHDL File......................................................... 284
5.3.6 The Code Description ........................................................... 285
5.3.6.1 Including the libraries ................................................. 285
5.3.6.2 Writing the Entity Declaration ..................................... 285
5.3.6.3 Writing the Architecture .............................................. 289
5.3.6.4 Selecting Files for Compilation ................................... 293
5.3.6.5 Setting the Top-Level File .......................................... 295
5.3.6.6 Compiling and Synthesizing a Top-Level File ............ 296
5.3.6.7 Choosing Compiler Options ....................................... 296
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5.3.6.8 Compiling and Synthesizing the File. ......................... 297
5.3.7 Starting Warp Professional or Enterprise Applications ......... 299
5.3.8 Creating a New Design......................................................... 299
5.3.8.1 Adding a Design Resource ........................................ 301
5.3.8.2 Compiling and Synthesizing the Design ..................... 301
5.3.8.3 Accessing the Example Waveform ............................ 306
5.3.8.4 Output WaveForms .................................................... 307
5.3.9 Final Code for 15G04.vhd .................................................... 309
Verilog PSI Device (CYP15G04K100) Tutorial ................... 315
5.4 Designing with Frequency Agile PSI .....................................317
5.4.1 Design Description ............................................................... 317
5.4.2 Design Solution .................................................................... 317
5.4.2.1 Programmable Logic .................................................. 317
5.4.2.2 SERDES .................................................................... 318
5.4.3 Starting Warp Applications ................................................... 318
5.4.3.1 For Warp Users .......................................................... 318
5.4.3.2 For Warp Professional Users ..................................... 318
5.4.3.3 For Warp Enterprise Users ........................................ 318
5.4.4 Creating a New Design......................................................... 319
5.4.5 Creating the Verilog File ....................................................... 321
5.4.5.1 Writing the Include Statement .................................... 322
5.4.5.2 Writing the Module Definition ..................................... 322
5.4.5.3 Writing the Behavior of the PSI module ..................... 325
5.4.5.4 Selecting Files for Compilation ................................... 329
5.4.5.5 Setting the Top-Level File .......................................... 330
5.4.5.6 Compiling and Synthesizing a Top-Level File ............ 331
5.4.5.7 Choosing Compiler Options ....................................... 333
5.4.5.8 Compiling and Synthesizing the File. ......................... 334
5.4.6 Starting Warp Professional or Enterprise Applications ......... 336
5.4.7 Creating a New Design......................................................... 336
5.4.7.1 Adding a Design Resource ........................................ 338
5.4.7.2 Compiling and Synthesizing the Design ..................... 338
5.4.7.3 Accessing the Example Waveform ............................ 342
5.4.7.4 Output WaveForms .................................................... 343
5.4.8 Final code for PSI_15G04.v ................................................. 345
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Installation
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1.1
PC Installation
Cypress recommends installing Warp Release 6.3 in a new directory.
When upgrading from Windows 3.x to Windows 95™ or Windows NT™, you must
reinstall the Warp software. This step is not necessary if upgrading from Windows 95™ to
Windows NT™.
1.1.1
System Requirements
Table 1-1 shows the approximate disk space requirements for the various Warp products:
Table 1-1. PC Product Disk Space Requirements
Product
Disk Space Requirements
Warp
65 MB
Warp Professional/Enterprise
420 MB
You will also need extra disk space for your designs.
Cypress recommends that you run Warp on a Pentium® PC, with at least 32MB of RAM
and an additional 32MB of virtual memory. Large designs may require additional memory.
For Warp Professional/Enterprise, the following requirements are the minimum: 128 MB
RAM, Microsoft Windows 95/98 or Windows NT 4.0 with Service Pack 3 or Windows
2000, Microsoft Internet Explorer 4.0 or higher. The amount of physical memory limits
the maximum size of the design that can be simulated in Active-HDL and 256 MB RAM
is highly recommended.
On the PC platform, Warp™ can integrate itself with WorkView Office version 7.5.3.
1.1.2
Warp
On-line Documents
Warp documentation is available on-line and it can be viewed using the Adobe Acrobat
Reader, shipped with the CD-ROM. To install the Acrobat Reader on Windows 95™
and Windows NT™, locate \pc\acroread\ar32e30.exe and double-click your left mouse
button on this file. These files can also be installed into the c:\warp\docs directory during
installation.
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1.1.3
Windows Platform Installation
1.1.3.1
1
Warp Software
1.
Insert the Warp CD into the CD-ROM drive.
2.
Run pc\setup.exe from the CD-ROM.
Note – Cypress recommends that you close all applications before running the Warp installation program.
1.1.4
PC - Known Installation Problems
Problem: Warp fails to install.
Solution: Certain power management tools and screen savers might conflict with the
installation program. Temporarily disable the screen saver during installation. If
power.exe is being run from your autoexec.bat or config.sys, please disable this.
1.1.5
Commonly Asked Questions About PC Installation
Q: Which files are modified by the Warp installation?
A: For Windows 95/NT, only the autoexec.bat file is modified. A detailed description of
the exact changes that are made to this file is listed in the file warppc.txt, which is
available at the end of the installation or on the Warp CD-ROM. The changes vary
depending upon the product that you have installed.
Q: Which OS preferences should be set to run Warp successfully?
A: Since Warp Release 6.3 includes Verilog as well as VHDL, you need to show all file
extensions for file types that are registered. To do this, select View -> Options from the
Windows or NT Explorer and unselect the box that reads: “Hide MS-DOS file extensions
for file types that are registered.”
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1.2
Solaris Installation
The following steps show how to install Warp Release 6.3 on a SUN Sparc station
running Solaris™ 2.5 or later. Table 1-1 shows the disk space requirements:
Table 1-1. UNIX Product Disk Space Requirements
Product - Platform
Disk Space Required
Warp
35 Mbytes
Cypress recommends installing Warp Release 6.3 in a new directory.
The Warp product is also capable of integrating itself with the Viewlogic Powerview®
environment if you already have this. Warp has been tested with Powerview version 6.0.
Warp documentation is available on-line and can be viewed using the Adobe Acrobat
Reader, shipped with the CD-ROM. The Acrobat reader can be installed during Warp
installation or separately (see instructions below).
1.2.1
1.2.1.1
Installing the Software
On Solaris 2.5
1. Mount the CD-ROM.
If the Volume Manager is running, it will automatically mount
the CD-ROM. Otherwise, login as super user on a machine that
has a CD-ROM drive. Run the following commands to create
and mount the /cdrom directory:
mkdir /cdrom
mount -F ufs -r /dev/dsk/c0t6d0s2 /cdrom
2. Local Installation.
cd /cdrom/warp/solaris
./install
To install the Acrobat Reader separately, run the following
commands instead of the previous commands:
cd /cdrom/databook/acrobat/acrosun
./install
After this step is completed, please skip to Step 4.
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3. Remote Installation.
1
If you are installing from a CD-ROM that is on a remote
machine, export the /cdrom directory. Add the following line:
share -F nfs -o ro /cdrom/warp
to the file /etc/dfs/dfstab on the remote machine, if the line
does not already exist. If nfsd is not running, reboot the
machine.
Run the following command to export /cdrom/warp:
shareall
Remote login to the install machine (where you want to install
the software) using the following commands:
rlogin <install machine> -l root
If /cdrom does not exist, run the following command:
mkdir /cdrom
Mount the remote CD-ROM on the install machine, change the
directory to the CD-ROM, and run the installation script by
using the following commands:
mount -r <remote-machine-name>:/cdrom/warp3r50 /cdrom
cd /cdrom/warp/solaris
./install
This program will walk you through the rest of the installation
process.
Unmount the CD-ROM and come back to <CD-ROM_drive
host> machine.
cd /
umount /cdrom
exit
4. Unmount the CD-ROM
Type in these commands:
cd /
umount /cdrom
1.2.2
Setting up the User’s Environment
To run Warp, you need to set some environment variables in the user’s login start up file.
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1.2.2.1
For C Shell users:
Warp Setup:
Add the following lines to your ~/.cshrc file:
setenv CYPRESS_DIR <Warp installation directory>
set path = ($CYPRESS_DIR/bin $path)
Acrobat Reader Setup:
If you have installed the Acrobat Reader, add the following lines to your ~/.cshrc file:
setenv ACROBAT_DIR <Acrobat Reader installation directory>
set path = ($ACROBAT_DIR/bin $path)
Source the ~/.cshrc file.
If you are running Solaris 2.5 or later, make sure that the OpenWindows library (/usr/
openwin/lib) and CDE library (/usr/dt/lib) or Motif 1.2 library are included in the
LD_LIBRARY_PATH before running Warp.
If you have configured Warp to run with Viewlogic tools, also make sure that the WDIR
path includes a writable directory (<pvlocal> above).
1.2.2.2
For Bourne shell users:
Warp Setup:
Add the following lines to $HOME/.profile file in the same order.
CYPRESS_DIR=<Warp installation directory>
PATH=$CYPRESS_DIR/bin:$PATH
export CYPRESS_DIR PATH
Acrobat Reader Setup:
If you have installed the Acrobat Reader, add the following lines to your $HOME/
.profile file:
ACROBAT_DIR=<Acrobat Reader installation directory>
PATH=$ACROBAT_DIR/bin:$PATH
export ACROBAT_DIR PATH
Source the $HOME/.profile file.
If you are running Solaris 2.5 or later, make sure that the OpenWindows library (/usr/
openwin/lib) and CDE library (/usr/dt/lib) or Motif 1.2 library are included in the
LD_LIBRARY_PATH before running Warp.
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If you have configured Warp to run with Viewlogic tools, also make sure that the WDIR
path includes a writable directory (<pvlocal> above).
1.2.3
Run Warp
To run the Warp™ product, run the following command:
galaxy
1.2.4
Setting up the Printer in Galaxy
Galaxy (Warp GUI) on the UNIX platforms uses the cross platform development tool
Wind/U from Bristol Technology. The printer support is provided through Bristol’s
Xprinter product and the online help is provided through Bristol’s HyperHelp product.
When Galaxy is run for the first time, Wind/U’s specific initialization file (.galaxy.windu)
is created in the $HOME directory. This file contains the current printer setup, font
mappings, and other Wind/U tunable parameters. Once you have installed Warp, you must
configure the galaxy.windu file for printing. Cypress recommends that the user utilize the
Xprinter setup dialog, instead of manually editing the galaxy.windu file, as it reduces the
risk of error.
To configure Galaxy for printing, you need to specify the following information for each
printer you want to access:
•
The name of the printer description (PPD) file.
•
The command used to send output to a printer.
1.2.4.1
PPD Files
The Warp installation media includes the PPD files for most commonly used printers. To
verify that the PPD file associated with your printer is included, look at the Printer
Devices dialog (from the Printer Setup dialog, click Install and Add Printer). If your
printer model is not listed, contact your printer vendor to obtain the PPD file for your
printer.
1.2.4.2
Configuring Wind/U for Printing
Once you know the name of the PDD file and the print command for each printer you
want to direct output to, you can configure Wind/U to recognize those printers.
To configure Wind/U to recognize a printer, you must do the following:
1.
Define a port, which is an alias for the print command.
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2.
Associate the port with the printer’s PPD file.
3.
Specify a default printer.
4.
Set printer options.
1.2.4.2.1
Defining a Port
A printer port is an alias for the print command. It appears as part of the printer name in
the Printer Setup dialog.
1.
Display the Ports dialog box. Select Print Setup from the File menu.
2.
Click on the Properties button in the Print Setup dialog box.
3.
Click on the Printer Specific radio button in the Printer Setup dialog box.
4.
Click on the Install button in the Printer Setup dialog box.
5.
Click on the Add Printer button in the Printer Installation dialog box.
6.
Click on the Define New Port button in the Add Printer dialog box.
7.
Enter the new port, in the following format (where “hilbert” is the name of the
print server):
LOCAL=rsh hilbert lp
8.
Click on the Add/Replace button in the Ports dialog box.
9.
Repeat steps 1-8 for each printer you want to print to.
Note – To create a printer port for each available printer queue on
hp700mt systems, click the Spooler button on the Ports dialog box. This
command creates a default printer port for each available printer queue
returned by the lpstat -a command. This command will be supported on
other platforms in future releases.
1.2.4.2.2
To Modify an Existing Port
To modify an existing port using the Print Setup dialog box, perform the following steps:
8
1.
Display the Ports dialog. Select Print Setup from the File menu.
2.
Click on the Properties button in the Print Setup dialog box.
Warp Getting Started Manual
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3.
Click on the Printer Specific radio button in the Printer Setup dialog box.
4.
Click on the Install button in the Printer Setup dialog box.
5.
Click on the Add Printer button in the Printer Installation dialog box.
6.
Click on the Define New Port button in the Add Printer dialog box.
7.
Select the port you want to modify and edit the port information in the Edit Port
edit field in the Ports dialog box.
8.
Click on the Add/Replace button in the Ports dialog box.
9.
The modified port is now included in the list of current port definitions.
1.2.4.2.3
1
To Match a Printer Device to a Port
1.
Navigate to the Add Printer dialog box. Select File -> Print Setup -> Properties > Install -> Add Printer.
2.
In the Printer Devices field, select the description that matches the printer you are
installing. If no description matches your printer, contact your printer vendor for
a printer description (PPD) file and install it in the $CYPRESS_DIR/windu/
xprinter/ppds directory.
3.
Select the desired port in the Current Port Definitions list box and click Add
Selected. The new printer is now included in the list of currently installed
printers.
1.2.4.2.4
To Remove an Installed Printer
1.
Display the Printer Installation dialog box. Select File -> Print Setup ->
Properties -> Install.
2.
In the Currently Installed Printers list box, select the printer you want to remove
and click on Remove Selected.
1.2.4.2.5
Specifying a Default Printer
1.
Display the Options dialog. Select File -> Print Setup -> Properties -> Options
2.
From the Printer Name drop-down list, select the desired printer and click OK.
3.
Click Save in the Printer Setup dialog box.
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1.2.4.2.6
Setting Printer Options
Since printer options vary between printers, use the Printer Setup dialog box to set printer
options. Xprinter reads the PPD file to identify the specific options available for each
printer.
1.2.4.3
1.
Display the Printer Setup dialog box. Select File -> Print Setup -> Properties.
2.
Set all fields to the desired values.
3.
To set additional options, such as selecting a new printer or changing the page
size, click Options.
4.
Set all options to the desired values.
5.
Click Save to make your changes take effect and make them the new default
values, or click Apply to make your changes take effect without changing the
default values.
Sending Output to a File
The default $HOME/.galaxy.windu file contains many printer devices, including the
following:
HP LaserJet 4L PostScript=HP4L Postscript
HP LaserJet 4M PCL Cartridge PCL5=HP4M PCL, FILE:
In all of the default entries, the port is FILE:, which is the only reserved port name. If you
specify FILE: as the port, Wind/U creates a print file instead of sending output to a printer.
When you use a PPD file, you generate PostScript or PCL output that is specific to the
printer. If you use Output Format: Generic (File Only), you generate generic Encapsulated
PostScript or PCL output.
For example, the HP LaserJet 4L PostScript entry creates a PostScript file that includes the
characteristics of the HP 4L PostScript printer. The HP LaserJet 4M PCL entry creates a
PCL file that includes the characteristics of the HP LaserJet 4M PCL printer.
You can also print to a file instead of printer by selecting the Output Format: Generic (file
only) option on the Printer Setup dialog, but doing so creates a generic EPS or PCL print
file that does not take advantage of any special characteristics of your particular printer.
1.2.4.4
Solving Printing Problems
If you have problems printing, the following hints may be helpful:
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1.2.5
•
Start with printing to a PostScript file. You can use PostScript previewers (on
Sun’s Pageview), to see the file. Adding spooling and PCL support later is easy.
•
Make sure that you have a .galaxy.windu file in your home directory.
•
Make sure that there is a PPD file for the printer you are using. See Section
1.2.4.1 for more information on where to find the PPD files included with Warp.
Xprinter requires a PPD file that describes the attributes (paper size, resolution,
color capabilities, paper trays, etc.) for each printer device you want to use. If
your printer is not included in the PPD files supplied with Warp, try the
following:
1.
Contact the printer manufacturer for the PPD file.
2.
Download the PPD file from the Adobe FTP site (ftp.adobe.com:/pub/adobe/
PPDfiles).
3.
Use the PPD file for a similar output device.
To Read Warp On-line Documentation
To read the on-line manuals, run the appropriate command (if you have installed Acrobat
Reader):
Solaris Platform:
acroread <Warp Installation directory>/docs/gs.pdf
acroread <Warp Installation directory>/docs/refmanl.pdf
acroread <Warp Installation directory>/docs/uguide.pdf
On-line documentation files can also be opened from the Acrobat Reader’s file selection
dialog box. The files are in <Warp Installation directory>/doc>.
PC Platforms:
On-line documentation can be found on your CD-ROM in the /docs directory or from the
Galaxy Help menu. For more information on the Acrobat Reader, read the Reader/
ReadMe and Reader/help/reader files in the <Acrobat Reader Installation directory>
directory.
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Chapter
2
Ultra37000 Tutorials
2
Ultra37000 Tutorials
2.1
Introduction
The Warp tutorials demonstrate a common sequence of operations in Warp. The tutorials
show the user how to create, compile, synthesize, and simulate designs.
2
This section presents:
•
product descriptions of Warp
•
some conventions about typography, wording, and illustrations used in this manual
•
the objectives of the tutorials
•
the contents of the tutorials
The tutorials are organized based on the product.
•
2.1.1
Section 2.2 covers Warp tutorials:
•
A coke machine tutorial targeting a Ultra37000 device.
•
A parking garage tutorial targeting a Flash370 device.
Product Descriptions
Warp
Warp users describe electronic designs using VHDL and then compile and synthesize
those descriptions to program Cypress devices, such as small PLDs, MAX340 EPLDs,
FLASH370, Ultra37000, Delta39K and Quantum 38K CPLDs.
Warp consists of :
2.1.2
•
The Warp VHDL IEEE 1076/1164 compliant compiler to translate VHDL text
descriptions into JEDEC files that can be mapped onto programmable devices.
•
On the PC platforms, Warp also contains an FSM editor and Active-HDL Sim, the
post-synthesis timing simulator from Aldec, Inc.
Conventions
The following conventions are used throughout this manual:
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Ultra37000 Tutorials
Table 2-1 Notational Conventions
Font Style
Definition
Menu items
Whenever an item from a menu is referenced, the reference
takes the form menu-name->item-name->item-name... The
first entry in the reference is the name of the menu; the second is the name of the menu item; the third and succeeding
entries indicate choices from sub-menus. Example: Select
File->Open... tells you to pull down the File menu and
select the Open... item from it.
Path names
Italics designate path names and file names.
Bold
Bold designates emphasis or draws attention to new terms.
signal
Courier denotes signal names, VHDL constructs, and
system output.
text
Courier denotes the contents of a text file and also indicates the text of typed commands.
File Naming Conventions
Warp runs on many different platforms: IBM PCs and compatible computers, Sun
workstations, and HP workstations.
IBM PCs and compatible computers specify file locations by designating a disk drive and
using a backslash (\) character to distinguish directory levels, e.g., c:\level1\level2\myfile.
Unix workstations specify file locations using a forward slash (/) and no disk drive
designator, e.g., /level1/level2/myfile.
For consistency and brevity, this manual uses the same notation as IBM PCs and
compatibles when referring to file locations. UNIX platform users are asked to make
appropriate translations.
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Mouse Conventions
The following terms describe common actions you might perform in using this manual:
Table 2-2 Mouse Conventions
2
Action
Definition
Click
Place the mouse cursor over an object, then press and
release the appropriate mouse button.
Double-click
Position the mouse cursor over an object, then press and
release the appropriate mouse button twice in rapid succession.
Drag
Position the mouse cursor over an object or at a specified
location. Press and hold the appropriate mouse button.
While holding down the mouse button, move the cursor to
the new location. Release the mouse button.
Select
Move the cursor over the option to be selected. Click the
appropriate mouse button.
Other Conventions
The following visual indicators denote special situations you may encounter while using
this manual.
Note – This icon indicates a note. This is information you should read
before continuing with a procedure.
Hint – This icon indicates a hint. This is information that could save a
little time, a few keystrokes, or much frustration.
2.1.3
Differences between Operating Systems
Warp operates identically on both UNIX and Windows systems except for start-up
procedure and the appearance of some objects in the display.
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Naming Restrictions
Keep in mind that some UNIX systems have trouble with spaces embedded in file names.
That can be true for IBM PCs and compatible systems, too. Cypress recommends not
using embedded spaces in file names.
If you are working in a system with PCs (Windows platforms) and UNIX workstations
connected to the same network, Cypress advises you to name all VHDL files with lower
case characters.
Differences in Display
Although dialog boxes and prompts may differ in appearance between the two platforms,
their functionality is identical. Screen captures in this manual are taken from the Windows
version of Warp. Differences in the UNIX version are identified when necessary. In most
cases, any adjustments needed to go from Windows to UNIX versions of Warp displays
are obvious.
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Ultra37000 Tutorials
2.2
Designing a Soda Machine for Ultra37000 (VHDL)
This is a step-by-step example of using a low-level VHDL behavioral description and a
high-level VHDL file to instantiate the component contained in the low-level VHDL file.
2
2.2.1
•
Write an entity declaration, architecture, component and package declaration for a
VHDL behavioral description of a simple circuit.
•
Write an entity declaration and architecture that instantiates the simple circuit in a
VHDL description of a higher-level circuit.
•
Run Warp to compile and synthesize the design’s VHDL description.
•
Learn the methodology to simulate the behavior of the design.
Design Description
In this example, you will design a controller for a soft-drink dispensing machine. The
machine has two bins to dispense regular cola and diet cola. Each bin holds three cans of
soft drink. (This could be any value, but three is an easy number to simulate.)
The circuit dispenses a beverage if the user presses a button for that beverage and at least
one can is available. A refill signal appears when both bins are empty. Pressing a reset
signal tells the circuit that the machine has been replenished and the bins are full.
2.2.2
Design Solution
The solution presented in this section proceeds as follows:
First, describe a circuit in IEEE standard VHDL that controls the operation of one bin. It
responds appropriately to a get_drink signal (giving a drink when one is available),
keeps count of the number of cans left in the bin, and sets an empty signal when its bin
becomes empty and is in need of resetting. This circuit is named binctr. You will add
appropriate VHDL to declare this circuit a component and define a package that contains
the component, so you can use the circuit in higher-level designs.
Next, write a top-level description of a circuit that instantiates two binctrs and other logic
as appropriate to describe the larger soda machine design. The larger design is called
refill.
After that, compile and synthesize the binctr and refill VHDL descriptions into a
CY7C37256 JEDEC file.
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2.2.3
Starting Warp Applications
=> On Windows NT and Windows 95 systems, start Warp applications by clicking
on Start, then selecting the appropriate application name from the
Programs -> Cypress -> Warp menu.
=> On UNIX systems, start Warp by typing the application name, such as
galaxy<CR>, from within a shell window.
2.2.4
Creating A New Project
Start Galaxy. Refer to Section 2.2.3 for information on starting applications on your
platform.
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown below in Figure 2-1.
Figure 2-1 New file and project dialog box.
3.
Select VHDL as the Project Type.
4.
Enter the name of the project, "drink".
5.
Enter the project path as follows.
=> On the PC, enter c:\w2tutor\vhdl.
=> On UNIX systems, enter <user_home_directory_path>/w2tutor/vhdl.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
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no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device subfamily (Ultra37000, Flash, MAX, etc.), device name and package type. The user can
traverse the device tree. On the left side of the dialog box are the Devices available and on
the right side are the Packages available for the device selected.
2
Figure 2-2 Select Target Device dialog box with Cypress PLDs in
tree form.
7.
Navigate the tree to CPLD -> Ultra37000 -> c37256.
8.
Highlight the CY37256P160-154AC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
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You have now created a project directory for your designs named
w2tutor. All files pertinent to this tutorial need to be placed in this
project directory. You have also created a project file called drink.pfg
which is now located in the c:\w2tutor directory.
2.2.5
2
Creating the VHDL File
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
Note – You can also create a new text file by clicking on the "New
Text File" button on the project toolbar (
).
This brings up the Galaxy editor (Figure 2-3) where you enter your
VHDL code.
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2
Figure 2-3 Blank Galaxy editor window.
2.2.6
The binctr.vhd VHDL description
The binctr VHDL description is written in three parts:
22
•
the entity declaration declares the name, direction, and data type of each port of the
component
•
the architecture describes the behavior of the component
Warp Getting Started Manual
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•
the package declaration provides the information to Warp to allow binctr to be used
as a component in a higher-level design
The following pages briefly discuss the contents of each of these
sections of the VHDL description. For a detailed explanation on these
VHDL constructs, refer to the text book VHDL for Programmable Logic
included in your software kit.
2.2.6.1
2
Writing the Entity Declaration
=> Type the following lines into your VHDL text editor:
entity binctr is port(
reset, get_drink, clk: in std_logic;
give_drink: inout std_logic;
empty: inout std_logic);
end binctr;
The entity declaration declares the name, direction, and data type of each port of the
component. The entity declaration declares that entity binctr has five external interfaces,
or ports. It has three input ports of type std_logic, named reset, get_drink, and clk,
respectively. It has two input/output (inout) ports, also of type std_logic, named
give_drink and empty, respectively.
The signals give_drink and empty are of mode inout and represent the various states
that the state machine can assume. The architecture definition for the entity binctr
requires that signals give_drink and empty retain their values when all other state
transition conditions are untrue. This forces give_drink and empty to feed back on
themselves apart from being outputs of the state machine. Hence the signals
give_drink and empty are declared with mode inout.
2.2.6.2
Writing the Architecture
=> Type the following lines into your VHDL text editor after your entity
declaration:
architecture archbinctr of binctr is
constant full: std_logic_vector(1 downto 0):= "11";
-- max of 3 drinks/bin
signal remaining: std_logic_vector(1 downto 0);
begin
proc_label: process (clk,reset)
begin
if (reset = ’1’) then
remaining <= full;
empty <= ’0’;
give_drink <= ’0’;
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elsif (clk’event and clk = ’1’) then
if (remaining = "00") then
empty <= ’1’;
give_drink <= ’0’;
elsif (get_drink = ’1’) then
remaining <= remaining - 1;
give_drink <= ’1’;
elsif (get_drink = ‘0’) then
give_drink <= ’0’;
else
give_drink <= give_drink;
remaining <= remaining;
empty <= empty;
end if;
end if;
end process;
end archbinctr;
The architecture portion of a VHDL description describes the behavior of the component
and always appears after the entity description.
2
The first line declares an architecture named archbinctr of entity binctr.
The next two lines declare a constant and a signal, respectively.
•
The constant, named full, determines how many drinks are in a full bin.
•
Signal remaining, of type std_logic_vector keeps track of how many drinks are left
in the bin.
The begin that follows the signal declaration marks the start of the architecture body. All
constant and signal declarations in the architecture of the VHDL code should precede the
begin statement.
A process declaration follows, marked by the keyword process and an ensuing begin.
The process declaration ends with the end process; statement.
The last line end archbinctr; denotes the end of the architecture declaration.
You can add comment lines to your VHDL code by placing "--" before the comment text.
All or part of a line can be commented out as shown on the line that defines the constant
full.
The architecture defines a process which is activated by any changes to the clk or the
reset signal. The process definition shown here is a VHDL template for describing a
synchronous circuit with an asynchronous reset.
Signal handling is processed in the following sequential order:
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•
The process within the architecture is triggered only if there is a change in the logic
levels of the signals clk and reset. These signals are included in the process
sensitivity list. The signal order in the sensitivity list is arbitrary.
•
If signal reset is ‘1’, then signal remaining is set to ‘full’, signal empty is set
to ’0’, and signal give_drink is set to 0. Notice that this means reset has
priority over all other signal declarations in the architecture definition. This forces the
compiler to define the reset as an asynchronous reset for the design.
•
The reset signal needs to be false to initiate the execution of the rest of the
statements in the process declaration.
•
The clock definition statement indicates to the compiler that all registered equations in
the architecture definition are to be synthesized into rising edge triggered flip-flops.
The process can be changed to be falling edge sensitive by altering the clock definition
statement to look like this:
(if clk’event and clk = ’0’).
•
If signal remaining has a value of 00, then signal empty is set to 1 and signal
give_drink is set to 0.
•
If signal remaining is not a 0 and signal get_drink is 1, then signal remaining
is decremented by one and signal give_drink is set to 1.
•
If signal remaining is not 00 and signal get_drink is 0, then signal
give_drink is set to 0.
•
If the if-then-elsif conditions are false, give_drink, remaining and
empty retain their current values.
Several lines ending the if statement, process, and architecture follow. The end statement
of the architecture must contain the same architecture name as shown on the first line of
the architecture.
2.2.6.3
Writing the Package Declaration
=> Type these lines into your VHDL text editor before the entity declaration:
package binctr_pkg is
component binctr
port(reset, get_drink, clk: in std_logic;
give_drink: inout std_logic;
empty: inout std_logic);
end component;
end binctr_pkg;
The package declaration provides the information to the Warp compiler to allow binctr to
be used as a component in a higher-level design.
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Note – The package declaration must appear before the entity
declaration and architecture in the .vhd file.
The first line in the package declaration names the package. The name of the package
must be distinct from the name of any component declared within that package. Using the
convention <entity>_pkg works nicely.
2
The second line declares a component named binctr. The component name that appears
on this line must match the name of an accompanying entity.
The port statement declares the name, direction, and type of each port in the component.
You can copy the port statement from the entity declaration for this purpose.
An end component and end binctr_pkg statement conclude the package
declaration. Note that the package named in the end package statement must match that
shown in the first line of the package declaration.
=> Save the file as c:\w2tutor\vhdl\binctr.vhd.
2.2.6.4
Including the Libraries
=> Insert these lines before the package declaration and before the entity
declaration:
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.std_arith.all;
These lines advise the compiler to link to the IEEE VHDL library, and the Cypress
UltraGen module generation library. These libraries define the various types, modes, and
VHDL constructs used in the VHDL code. The library and use VHDL reserved words
instruct the compiler to include pre-defined libraries and user created VHDL files, in
compiling the selected VHDL code. For details on the std_logic_1164 and std_arith
packages, see Chapter 1, VHDL in the HDL Reference Manual.
2.2.7
Creating a Top-Level Description
Now that you have defined the behavior of the lower level of the circuitry, you can
describe the upper level by instantiating two components and connecting them with
appropriate internal signals:
=> Follow the steps in Section 2.2.5 and create a new text file. Type the following
lines:
library ieee;
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use ieee.std_logic_1164.all;
use work.binctr_pkg.all;
entity REFILL is port (
GIVE_cola: INOUT std_logic;
GIVE_diet: INOUT std_logic;
REFILL_BINS: OUT std_logic;
RESET: IN std_logic;
CLK: IN std_logic;
GET_diet: IN std_logic;
GET_cola: IN std_logic);
2
attribute pin_numbers of refill:entity is
" GIVE_cola:2 GIVE_diet:3 REFILL_BINS:4 RESET:5 CLK:22" &
" GET_diet:17 GET_cola:35" ;
end REFILL;
The first three lines advise the compiler to link to the IEEE VHDL library and the user
created binctr_pkg VHDL package.
The entity declaration declares an entity named refill and defines the names, types,
and mode (direction) of its seven input and output ports.
There is also a pin_numbers assignment attribute which assigns all the signals
declared within the entity port map declaration to user specified pin numbers. Refer to the
Synthesis Directives book in the Warp 6.3 online help for more information on the
pin_numbers attribute.
Note – The pin numbers assigned to the signals in this design are
specific to the CY37256P160-154AC package. If a different package or
device is targeted, the numbers would have to be changed appropriately.
Alternatively, the pin_numbers attribute and the pin_number
assignments can be removed.
Type the following lines into your VHDL editor after the entity declaration.
architecture archREFILL of REFILL is
signal empty_1: std_logic;
signal empty_2: std_logic;
begin
bin_1: BINCTR
port map(RESET => RESET,
GET_DRINK => GET_cola,
CLK => CLK,
GIVE_DRINK => GIVE_cola,
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EMPTY => empty_1);
bin_2: BINCTR
port map(RESET => RESET,
GET_DRINK => GET_diet ,
CLK => CLK,
GIVE_DRINK => GIVE_diet ,
EMPTY => empty_2);
2
refill_bins <= ’1’ when ((empty_1 = ‘1’) and (empty_2 = ‘1’))
else ‘0’;
end archREFILL;
=> Save your top-level VHDL file by choosing File -> Save As. Enter refill.vhd as
the name, then close the file.
The architecture starts by declaring two internal signals, empty_1 and empty_2.
These are used to connect the outputs of the two binctr components to create the
functionality for refill_bins.
The two instantiations of binctr and the creation of the refill_bins equation
complete the VHDL description of this circuit. With this implementation, you have
translated the original vending machine problem into a VHDL design that can be
synthesized into any Cypress programmable logic device. The block diagram for
refill.vhd is shown in Figure 2-4.
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BIN_1
get_diet
get_drink
give_drink
reset
reset
empty
clk
clk
give_diet
logic
2
refill_bins
BIN_2
get_cola
get_drink
give_drink
reset
empty
give_cola
clk
Figure 2-4 Block Diagram for refill.vhd
2.2.8
Selecting Files for Compilation
After the files are created, they need to be added to the project. Galaxy has a Preferences
menu item under the Edit menu that allows you to set the design file extension. These
extensions are used to identify VHDL files. For VHDL projects, the default file name
extensions are: .vhd and .vh.
2.2.8.1
To add a VHDL file:
1.
Use the menu item Project -> Add Files. This accesses a dialog box (Figure 2-5)
where one or more VHDL files can be selected. Files are added in the order they
are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the binctr.vhd file and click Add.
4.
Highlight the refill.vhd file and click Add.
5.
Click OK in the Add Files to Project dialog box.
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Note – To add files from a different directory, click the browse button
to navigate to the project directory.
2
Figure 2-5 Dialog box to select files to compile
2.2.9
Compiling and Synthesizing a Top-Level File
In the following pages, you will run Warp to produce a JEDEC file for a specific target
device, in this case, a CY7C37256 macrocell CPLD.
2.2.10
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
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Figure 2-6 Compile Options dialog box with Synthesis tab chosen.
2.2.10.1
Setting Unused Outputs
Warp gives you the option of turning all of your unused output pins that have unused
macrocells into ‘1’s, ‘0’s, or ‘Z’s. This is a global option and cannot be applied on a signalby-signal basis. This option is useful for driving all unused pins to a certain logic level.
=> Under the Unused Outputs options of the Project -> Compiler Options ->
Synthesis tab, choose Z, the default option of leaving all unused I/O pins to be
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three-stated.
2
Note – When using MAX340 EPLDs and FLASH370 CPLDs, it is a
recommended practice to use external pull-ups for unused I/O pins.
2.2.10.2
Choosing Tech Mapping Options
While compiling registered equations, the fitter uses the directive from Choose FF types
to synthesize equations. Leaving the option Opt selected is the best choice. This enables
the fitter to make the choice between a D-FF and a T-FF implementation and then choose
the implementation that uses the least number of product terms.
=> Under Tech Mapping options in the Synthesis tab, select the Optimal option.
There are a few other useful options in the Tech Mapping options, which are explained in
the Galaxy online help, accessible from the Galaxy Help menu.
2.2.10.3
Choosing a Timing Model for Active-HDL Sim (PC Customers Only)
On the PC platforms, Warp Release 6.3 includes the Active-HDL Sim timing simulator.
This section applies only if you want to simulate your design using Active-HDL Sim
installed on your PC. You can verifty the synthesized design using Active-HDL Sim by
creating the Active-HDLSim/Active-VHDL timing model of the design using Warp.
The refill.vhd file should be compiled with the Active-HDLSim/Active-VHDL timing
model before using Active-HDL Sim.
=> Select Project -> Compiler Options -> Synthesis tab and click on the Timing
Model drop-down menu in the Simulation area.
=> Select Active-HDLSim/Active-VHDL.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
2.2.10.4
Setting the Top-Level File
Once all the necessary VHDL files are added into the project in the correct order, a top
level file can be set. Only the top-level files is actually synthesized, and only one top-level
file is allowed in a project.
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=> Click on refill.vhd.
=> Select Project -> Set Top or click on the Set Top button
project toolbar.
, available on the
=> Once the top-level file has been set, the file symbol marker in the hierarchy will
have a hierarchy symbol (Figure 2-7).
Figure 2-7 Galaxy window showing refill.vhd as the top-level
design.
Note – In order to set the top level file, the file must be selected in the
Project sub-window shown in Figure 2-7.
2.2.10.5
Compiling and Synthesizing the File
=> In your Galaxy window, select Compile -> Project to begin compilation or click
the Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a
CY7C37256 and prints messages to keep you appraised of its progress
in the results sub-window. The Compile - > Project option automatically
recompiles only those files which have been modified since the last
compilation.
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Figure 2-8 Results sub-window showing successful compilation.
This operation generates two files of particular interest:
34
•
refill.jed: is used to program a CY37256 device.
•
refill.rpt: contains pinout and timing information, along with other information about
the final synthesized design. You can see the .rpt file and the output files created by
Warp by clicking on the output view tab in the Project sub-window (Figure 2-9).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
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.
2
Figure 2-9 View of the output files in the Project sub-window.
For more information on what is contained in a report file, refer Chapter 7, Understanding
Ultra37000 in the User’s Guide.
Note – If compilation errors occur, make sure the text of your
binctr.vhd and refill.vhd files are entered exactly as shown earlier in this
chapter -- or, copy the file from the <warp path>\examples\wtutor\vhdl
directory -- and then run Warp again.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
=> Go to the VHDL editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
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2.2.11
Simulating the Behavior of the Design
UNIX Customers
Please refer to the Simulation chapter for details on how to simulate the design after
fitting.
2
PC Customers
In Warp Release 6.3, the synthesized design can be verified using the Active-HDL Sim
simulator. This section applies only if you have Active-HDL Sim installed on your PC.
In this tutorial, you will perform the following steps:
2.2.12
•
Start Active-HDL Sim.
•
Open the refill.vhd file in the w2tutor/vhdl/vhd/ folder.
•
Set the values of the stimulus signals in the simulation.
•
Simulate the design.
•
Examine results to figure out what happened.
Starting Active-HDL Sim
=> Start Active-HDL Sim by selecting Tools -> Active-HDL Sim.
Figure 2-10 The Tools -> Active-HDL Sim selection
=> Open the refill.vhd file by choosing File -> Open VHDL and browse to w2tutor/
vhdl/vhd.
=> Click on refill.vhd.
=> Click on OK. The Active-HDL Sim window should resemble Figure 2-11.
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Figure 2-11 The initial Active-HDL Sim window for refill.vhd.
2.2.13
Creating a View
=> Select Waveform -> Add Signals.
=> Double click on clk in the right pane of the Add Signals dialog box, shown below
in Figure 2-12.
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Figure 2-12 Add Signals dialog box with available signals for creating a view.
=> Double click on the following signals to add them to your new view in the
following order: clk, reset, get_cola, get_diet, give_cola,
give_diet, refill_bins.
=> Click on Add.
=> Your new view should look like Figure 2-13.
Note – The signals in the left pane of the Add Signals dialog box will
be different depending on the package and device selected.
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Figure 2-13 Active-HDL Sim screen of your new view.
2.2.14
Setting Stimulus Signal Values
You need to set the values of the following input signals for your simulation: clk,
reset, get_cola, and get_diet.
Set the clk signal for equally spaced, alternating highs and lows.
=> Select the clk signal in the left pane of the waveform window.
=> Hold the Ctrl key while selecting reset, get_cola, and get_diet.
=> Right click and select the Stimulators option.
=> Click on clk in the Signals frame.
=> Select “Clock” as the Stimulator type from the pull-down menu.
=> In the clock diagram, click on the 1 at the left side of the pane. The box with 1
should turn light grey to indicate it is selected. See Figure 2-14 below.
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Figure 2-14 Clock diagram with 1 selected.
=> Click on the Apply button.
Set reset to high for one rising clock edge. To do so:
=> Select the reset signal in the Signals pane.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following in the “Enter Formula” field:
=> 0 0, 1 75 ns, 0 125 ns
=> Click on the Apply button.
Set get_cola high for four non-consecutive rising clock edges.
=> Select the get_cola signal in the Signals pane.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following in the “Enter Formula” field:
=> 0 0, 1 175 ns, 0 225 ns, 1 375 ns, 0 425 ns, 1 575 ns,
0 625 ns, 1 775 ns, 0 825 ns
=> Click on the Apply button.
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Set get_diet high for four non-consecutive rising clock edges. These four pulses
should come after the four pulses created for the get_cola signal. The first pulse of the
get_diet signal comes no sooner than the tenth rising clock edge. One clock edge for
reset and 8 edges for get_cola (you need four non-consecutive rising clock edges).
=> Select the get_diet signal in the Signals pane.
2
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following in the “Enter Formula” field:
=> 0 0, 1 975 ns, 0 1025 ns, 1 1175 ns, 0 1225 ns, 1 1375
ns, 0 1425 ns, 1 1575 ns, 0 1625 ns
=> Click on the Apply button.
Set reset high for one rising clock edge after the last get_diet request.
=> Select the reset signal in the Signals pane.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Add the following text to the formula after 0 125 ns:
=> , 1 1675 ns, 0 1725 ns
=> Click on the Apply button.
Set get_cola and get_diet high for one rising clock edge, respectively, after the
second reset.
=> Select the get_cola signal in the Signals pane.
=> Add the following text to the formula after 0 825 ns:
=> , 1 1775 ns, 0 1825 ns
=> Click on the Apply button.
=> Highlight get_diet in the Signals pane.
=> Add the following text to the formula after 0 1625 ns:
=> , 1 1875 ns, 0 1925 ns
=> Click on the Apply button and then click on Close.
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The result, when complete, should look like Figure 2-15.
2
Figure 2-15 Active-HDL Sim stimulators dialog box for refill.awf
with all the signals set
2.2.15
Running the Simulation
To simulate the design:
=> Click on the 100ns field and enter in the value of 2000ns.
=> Click on the Run Until button in the toolbar.
Note – To re-initialize the simulation, click on the Restart Simulation
button on the Toolbar or select it from the Simulation -> Restart Simulation menu and select Waveforms -> Clear all Waveforms.
Note – You may wish to change the screen resolution in order to fit all
activity in the waveforms on one screen. Select View -> Zoom -> Out.
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The results should look similar to Figure 2-16:
2
Figure 2-16 Results of the refill.vhd Active-HDL Sim simulation
The simulation starts with the drink machine empty. Notice the state of
the refill_bins signal at the start of the simulation.
When the reset signal goes high at the start of the simulation, the
refill_bins signal is set low. The drink machine is now ready to
dispense drinks.
The drink machine dispenses three colas in response to the first three
requests for a cola. Note the relationship between the pulses in the
get_cola and give_cola signals. After the next request for a cola,
however, the machine does not dispense a drink; the cola bin is empty.
Similarly, the drink machine dispenses three diets in response to the first
three requests for a diet. After the fourth request for a diet, the machine
does not dispense one; the diet bin is empty.
With both bins empty, the refill_bins signal goes high. It stays
high until the reset signal goes high again, telling the machine that
the bins have been replenished. The next two requests, for a cola and a
diet respectively, are honored.
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Note – If the output of your simulation does not register correctly,
make sure that your signals begin and end halfway between rising and
falling clock edges.
2
2.2.16
Starting Active-HDL FSM
The goal of this tutorial is to demonstrate the basic features of Active-HDL FSM. This
section applies only if you have Active-HDL FSM installed on your PC. The particular
state machine it creates will generate a VHDL file, binctr.vhd, which can be used in place
of the binctr.vhd file created in Section 2.2.5 and used in Section 2.2.8, complete with the
same timing.
The reader will be able to compare the differences from handcrafted VHDL to the FSM
generated VHDL. There are many ways to do this state machine and after doing this
tutorial, the reader is encouraged to try alternate solutions. Some solutions to try will be
mentioned at the end of this tutorial.
To start Active-HDL FSM while in Galaxy, select Tools -> Active-HDL FSM.
2.2.16.1
Creating A New Project
When you open Active-HDL FSM, you’ll see a dialog box like Figure 2-17 below.
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Figure 2-17 The State Editor dialog box
1.
Select Use HDL Design Wizard, if it is not already the default selection.
2.
Click OK.
3.
Click on Next.
4.
Select VHDL as your preferred language.
5.
Click Next.
6.
Click the browse button to verify you are in the correct directory, c:\w2tutor\vhdl.
7.
Enter the file name as binctr. This will create a file called binctr.asf.
8.
Click Next. The dialog box you see will look like Figure 2-18.
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Figure 2-18 The Design Wizard - Ports dialog box before entering
ports
Now you’ll create the ports for binctr. You’ll create two inputs and two
outputs.
9.
Click on New. Type reset in the Name: field and make sure that the Input button is
selected
10. Click on New. Type get_drink in the Name: field and make sure that the Input
button is selected.
11. Click on New. Type empty in the Name: field and make sure that the Bidirectional
button is selected.
12. Click on Advanced and make sure that the Registered mode is selected.
13. Click on New. Type give_drink in the Name: field and make sure that the
Bidirectional button is selected. After adding all the inputs and outputs, it should
look like Figure 2-19.
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Note – You’ll notice a green “U?” in the Design Wizard - Ports dialog
box shown in Figure 2-18 and Figure 2-19. This can be safely ignored
and will not be seen in future releases.
2
Figure 2-19 The Design Wizard - Ports dialog box after entering
ports
14. Click on Next.
Note – The Design Wizard will advise you that you have not entered a
port called CLK. Click Yes to have the Design Wizard create a clock
port called CLK.
15. The next dialog box asks how many state machines you are creating. Select One
and click on Finish.
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16. You can zoom in or zoom out by selecting View -> Zoom in or View -> Zoom out
from the Active-HDL FSM menubar.
2.2.17
Creating the State Machine
The default name of the state machine is Sreg0 and is located in the upper left corner of
the state machine. There are two areas: the interface area with ports and symbols and the
state machine area.
2
=> Double click on the text “Sreg0” with the left mouse button. Delete Sreg0 and
type in curstate. Hit Enter/Return.
=> Right click anywhere inside the machine and select Properties from the pop-up
menu. The Machine Properties dialog box, shown in Figure 2-20, is where you
set the properties of the state machine.
Figure 2-20 The Machine Properties dialog box.
=> Under the General tab, the default selections should be Rising and Symbolic.
=> Select the Reset tab. The default selections should be Asynchronous and High.
=> Click on OK to exit this dialog box.
=> Click on the state button
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=> The mouse pointer will be a state symbol. Place it as shown in the Figure 2-21
below.
2
Figure 2-21 The placement of the state machine symbol
=> Double click on the text S1. Type in the following text and hit the enter/return
key:
Start
=> Right click in the diagram and select Properties from the pull-down menu.
The first state in the curstate state machine will be the reset state. This
set of instructions associates the port reset with the start state.
=> Click on the Reset tab.
=> Click on the pull-down menu for the Port Name field. Select reset.
=> Click on the pull-down menu for the State field. Select Start.
=> Click OK to get back to the diagram.
Now we need to create a signal called remaining to be used as a
counter for how many cans of soda are left.
=> Click on the signal button
in the FSM toolbar.
=> Click outside the diagram to the left side of the input ports and place the signal as
shown in Figure 2-22. This makes it a VHDL signal. If we had put the signal
inside the state machine, it would be a VHDL variable.
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Figure 2-22 Figure showing placement of signal.
=> Double click to edit the text, type in the following and press enter/return:
remaining
=> Right click on the signal (not the name) and select Properties.
=> Click on the top left range button once to set the range as 1:0. Make sure that
Registered is selected. The Signal Properties dialog box, shown in Figure 2-23, is
where you’ll set the properties for the signal remaining.
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Figure 2-23 Signal Properties dialog box to set the signal range.
=> Click OK.
=> Click the entry action button
in the FSM toolbar.
=> Place the dot in the Start state symbol and type in the following text:
remaining <=”11”;
empty <= ’0’;
give_drink <=’0’;
=> Create a new state below the Start state symbol.
=> Double click to edit the text, type in the following text and press enter/return:
Idle
=> Click on the transition button
in the FSM toolbar.
=> Click on the Start state symbol, move the mouse pointer down to the Idle state
symbol and click again to set the transition.
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Note – When making a transition arc, you can click on the left mouse
button at multiple points in the white area to make the arc curve the way
you want it.
2
We have now created the idle state. We are going to make a transition
from the start state to the idle state if someone requests a drink.
=> Click on the condition button
in the FSM toolbar, place the pointer on the
transition arrow from Start to Idle, click and type in the following text:
=> get_drink = ’1’
=> Click on the transition action button
in the FSM toolbar, place the pointer
on the transition arrow from Start to Idle, click and type in the following text:
give_drink <=’1’;
remaining <= remaining - 1;
Note – Your text box may sit on top of the condition. When done
entering text, just click on the text box and drag the mouse to move it.
Note – When entering actions, we terminate the VHDL with a “;”.
When entering conditions, we don’t use the semi-colon. This is because
the text you enter as a condition or an action will become the actual
VHDL code that gets created later.
=> Create a new state below the Idle state symbol.
=> Click twice to edit the text, type in the following text and press enter/return:
No_drink
=> Click on the state action button
in the FSM toolbar.
=> Place the dot in the No_drink symbol, type in the following text and press enter/
return:
=> give_drink <= ’0’;
=> empty <= ’1’;
=> Click on the transition button
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=> Click on the Idle state symbol, drag the pointer down to the No_drink state
symbol and click again to set the transition.
We will now add the conditions and actions for leaving the Idle state.
First, if you only have one drink left and someone requests a drink.
=> Click on the condition button
in the FSM toolbar, place the pointer on
the transition arrow from Idle to No_drink, click and type in the following text:
remaining = ”01” and get_drink = ’1’
=> Click on the transition action button
in the FSM toolbar, place the pointer
on the transition arrow from Idle to No_drink, click and type in the following
text:
give_drink <=’1’;
remaining <= remaining -1;
=> Right click on the transition arrow from Idle to No_drink, select Priority from the
menu, select 1 from the numerical choices available and left click the mouse.
Click in the state machine to set the priority.
Note – Priority affects the order conditions are evaluated in the final
code. When done with this tutorial, try changing the priority and
examine the resultant VHDL code.
Second, if someone requests a drink, give the drink and return to the
state.
=> Click on the transition button
in the FSM toolbar.
=> Click on the bottom of the Idle state symbol, drag the pointer out to the left in
the white part of the state machine diagram, left click the mouse, drag the pointer
up, left click the mouse, and drag the pointer to the top of the Idle state and click
again to set the transition. Refer to Figure 2-24 for assistance in placement.
=> Click on the condition button
in the FSM toolbar, place the pointer on
the transition arrow from Idle to Idle, click and type in the following text:
get_drink=’1’
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=> Click on the transition action button
in the FSM toolbar, place the pointer
on the transition arrow from Idle to Idle, click and type in the following text:
give_drink <=’1’;
remaining <= remaining - 1;
2
=> Right click on the transition arrow from Idle to Idle, select Priority from the
menu, select 2 from the numerical choices available and left click the mouse.
Click in the state machine to set the priority.
Third, if no requests, return to the state and set give_drink to zero.
=> Click on the transition button
in the FSM toolbar.
=> Click on the bottom of the Idle state symbol, drag the pointer out to the right in
the white part of the state machine diagram, left click the mouse, drag the pointer
up, left click the mouse, and drag the pointer to the top of the Idle state and click
again to set the transition. Refer to Figure 2-24 for assistance in placement.
=> Click on the condition button
in the FSM toolbar, place the pointer on
the transition arrow from Idle to Idle, click and type in the following text:
get_drink=’0’
=> Click on the transition action button
in the FSM toolbar, place the pointer
on the transition arrow from Idle to Idle, click and type in the following text:
give_drink <=’0’;
=> Right click on the transition arrow from Idle to Idle, select Priority from the
menu, select 3 from the numerical choices available and left click the mouse.
Click in the state machine to set the priority.
The final diagram should look like Figure 2-24.
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Figure 2-24 Final diagram of binctr.asf
2.2.18
Selecting the Libraries
Select Synthesis -> Select Libraries.
=> Type the following text AFTER the default text:
package binctr_pkg is
component binctr
port(reset, get_drink, clk: in std_logic;
give_drink: inout std_logic;
empty: inout std_logic);
end component;
end binctr_pkg;
The package declaration provides the information to the Warp compiler to allow binctr to
be used as a component in a higher-level design.
Note – The package declaration must appear before the entity
declaration and architecture in the .vhd file.
The first line in the package declaration names the package. The name of the package
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must be distinct from the name of any component declared within that package. Using the
convention <entity>_pkg works nicely.
The second line declares a component named binctr. The component name that appears
on this line must match the name of an accompanying entity.
2
The port statement declares the name, direction, and type of each port in the component.
You can copy the port statement from the entity declaration for this purpose.
An end component and end binctr_pkg statement conclude the package
declaration. Note that the package named in the end package statement must match that
shown in the first line of the package declaration.
=> Type in the following text after the package declaration.
library IEEE;
use IEEE.std_logic_1164.all;
library CYPRESS;
use CYPRESS.std_arith.all;
use CYPRESS.lpmpkg.all;
=> Click OK.
2.2.19
Generating VHDL
Select Synthesis -> HDL Code Generation.
Note – You’ll notice that you have one warning about there being no
exit state from the No_drink state. This warning is okay to ignore.
To see your generated VHDL code, click Yes in the dialog box that appears after the code
has been generated. This creates binctr.vhd, which can be used in place of the binctr.vhd
file created in Section 2.2.5 and used in Section 2.2.8. See the final VHDL code listed
below.
After testing the VHDL file in the simulator, try changing the priority on the conditions.
Look at the resultant code and see how it changed. For a different look at VHDL, change
the output ports (select each port, right click on the symbol and select properties from the
pull-down menu) to be combinatorial instead of registered. What happens to the VHDL?
library IEEE;
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use IEEE.std_logic_1164.all;
package binctr_pkg is
component binctr
port (reset, get_drink, clk: in std_logic;
give_drink: inout std_logic;
empty: inout std_logic);
end component;
end binctr_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
library CYPRESS;
use CYPRESS.std_arith.all;
use CYPRESS.lpmpkg.all;
entity binctr1 is
port (CLK: in STD_LOGIC;
get_drink: in STD_LOGIC;
reset: in STD_LOGIC;
empty: inout STD_LOGIC;
give_drink: inout STD_LOGIC);
end;
architecture binctr1_arch of binctr1 is
--diagram signal declarations
signal remaining: STD_LOGIC_VECTOR (1 downto 0);
-- SYMBOLIC ENCODED state machine: curstate
type curstate_type is (Idle, No_drink, Start);
signal curstate: curstate_type;
begin
--concurrent signal assignments
--diagram ACTIONS;
curstate_machine: process (CLK, reset)
begin
if reset='1' then
remaining <= "11";
empty <= '0';
give_drink <= '0';
curstate <= Start;
elsif CLK'event and CLK = '1' then
case curstate is
when Idle =>
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if remaining = "01" and get_drink = '1' then
curstate <= No_drink;
give_drink <= '1';
remaining <= remaining -1;
elsif get_drink = '1' then
curstate <= Idle;
elsif get_drink = '0' then
curstate <= Idle;
give_drink <= '0';
end if;
when No_drink =>
give_drink <= '0';
empty <= '1';
when Start =>
if get_drink = '1' then
curstate <= Idle;
give_drink <= '1';
remaining <= remaining - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end binctr1_arch;
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2.3
Designing a Parking Garage Monitor (VHDL)
This section takes you step-by-step through another example, using hierarchy in creating a
low-level and top-level behavioral description. In this section, you:
•
Write an entity declaration, architecture, and package declaration for a VHDL
behavioral description of a simple counter circuit using the Warp VHDL Browser.
•
Write a top-level entity and architecture design using behavioral VHDL to implement
logic functions and to instantiate the counter circuit, using the Warp VHDL Browser.
•
Run Warp to synthesize the design’s VHDL description.
•
Learn the methodology to simulate the behavior of the design.
When you complete this section, you will know how to:
2.3.1
•
Take advantage of Cypress’ UltraGen module generation technology on various
operators.
•
Choose between Area and Speed optimization to obtain results best suited for your
application.
Design Description
This design keeps track of the total number of cars entering a parking lot garage, the total
number of cars that have left the garage, and the number of cars remaining in the garage.
For this exercise, you set the maximum number of parking lot spaces available to be 32.
You also need to alert the parking lot attendant if the parking lot is empty or full.
Additionally, the attendant should also be able to reset the count of the number of cars in
the garage to a zero, at their discretion.
2.3.2
Design Solution
The solution presented in this chapter proceeds as follows:
You are going to create two VHDL files, counter.vhd and total.vhd. The counter.vhd
file shows the implementation of a counter that increments the count by 1 on the rising
edge of a clock (trigger). It also contains an asynchronous reset signal that resets the
counter to zero. This counter is a variable size counter with default size of a 4-bit output
data.
The top-level VHDL file, total.vhd, instantiates the counter twice. The first counter keeps
track of the incoming cars, and the second counter keeps track of the cars exiting the
parking garage. The top-level file takes the output of the second counter and subtracts it
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from the output of the first counter to give the attendant the number of cars remaining in
the parking lot. There are two signals, lot_empty and lot_full, to let the attendant know if
the garage is empty or full respectively. Set both counters to have data width of 5 bits.
After that, synthesize the counter and total VHDL descriptions into a CY7C371 CPLD.
2
This tutorial reinforces basic VHDL constructs and the concept of hierarchical designs.
This exercise is also intended to make the user more familiar with the Warp tool flow.
2.3.3
Getting Started
=> Start Galaxy on your platform. Refer to Section 2.2.3 for information on starting
applications on your platform.
2.3.4
Creating a New Project
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK.
3.
Select VHDL as the Project Type.
4.
Enter the name of the project, "parking".
5.
Enter the project path as follows:
=> On the PC, enter c:\w2tutor\vhdl.
=> On UNIX systems, enter <user_home_directory_path>/w2tutor/vhdl.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
7.
Navigate the tree to CPLD -> Ultra37000 -> c37256.
8.
Highlight the CY37256P160-154AC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have created a project file called parking.pfg which is now located
in the c:\w2tutor\vhdl directory.
2.3.5
Writing the VHDL File
The VHDL Browser is a good tool for beginners to learn how to design with VHDL. The
Browser also acts as a way to find out the correct syntax for using VHDL constructs.
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There are three parts to the counter.vhd file:
•
the entity declaration declares the name, direction, and data type of each port of the
component
•
the architecture describes the behavior of the component
•
the package declaration provides the information to Warp to allow counter to be used
as a component in a higher-level design
The following pages briefly discuss the contents of each of these sections of the VHDL
description. For a more detailed explanation of these VHDL constructs, refer to the VHDL
for Programmable Logic textbook included in your software kit. Use the VHDL Browser
to create counter.vhd.
Note – During the following tutorial, you will be asked to close out the
Syntax Browser dialog box before entering text into the editor window
after inserting certain syntax in the file. This is because the Syntax
Browser takes the focus from the editor window.
Note – If you would rather not type the counter.vhd file yourself, you
can copy it from the Warp directory. The location for the counter.vhd
file is <warp path>\examples\wtutor\vhdl. From this location, copy
counter.vhd to your project directory. Then, read along for the next few
pages to help you understand the purpose of each section of a VHDL
source file.
=> Select File -> New or click the "New Text File" button on the project toolbar
( ).
=> Select "Text File".
=> Click OK.
=> Choose Templates -> Browser to bring up the VHDL Browser shown in Figure
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(Figure 2-25).
2
Figure 2-25 VHDL Syntax Browser
Note – You can also create a new text file by clicking on the "New
Text File" button on the project toolbar.
2.3.5.1
Writing the Entity Declaration
The entity declaration declares the name, direction, and data type of each port of the
component.
Use the VHDL Browser to create the various parts of counter.vhd.
=> Choose Entity decl. from the Syntax Browser.
=> Double-click on Entity decl. to bring up the VHDL Structure Syntax dialog box
(Figure 2-26).
Figure 2-26 VHDL Structure Syntax dialog for entity declaration.
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=> Type in counter in the field for the Entity name: and type the following
information in the Port list: field without a carriage return.
trigger, reset : in std_logic; count: inout
std_logic_vector(counter_size downto 0)
This adds signals with their modes and types to the entity declaration.
2
Figure 2-27 VHDL structure syntax dialog after entering text.
When you are done entering this information into the VHDL prompter, the VHDL
prompter should look like Figure 2-27.
=> Select OK. The information presented to the prompter gets translated into the
correct VHDL syntax in the VHDL editor.
=> Close the Syntax Browser dialog box.
=> Click in the editor window. In the generic declaration, add counter_size:
integer:= 4; and remove the comment characters at the beginning of the
line. The resulting entity declaration looks like the lines below, except for the
comment line:
entity counter is
-- setting the default size of the counter
GENERIC (counter_size : integer:=4 );
PORT (trigger, reset : in std_logic;
count : inout
std_logic_vector(counter_size downto 0) );
END counter;
=> Place the cursor at the start of counter.vhd.
=> Select Templates -> Browser.
=> Double-click on Library clause in the VHDL Browser to bring up the VHDL
prompter with the Name: field.
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=> Type in IEEE and click OK.
=> Double-click on Use clause from the VHDL Browser to bring up the VHDL
prompter with the Name: field. Type in ieee.std_logic_1164.all and
click OK.
2
=> Double-click on Library clause in the VHDL Browser to bring up the VHDL
prompter with the Name: field.
=> Type in CYPRESS and click OK.
=> Double-click on Use clause from the VHDL Browser and type in
cypress.std_arith.all and click OK.
=> Select File -> Save to save the contents of the VHDL Editor. Save the file as
c:\w2tutor\counter.vhd.
2.3.5.2
Writing the Architecture
The architecture portion of a VHDL description describes the behavior of the component.
The architecture appears after the entity declaration in the .vhd file.
The architecture portion of this design defines a counter that increments by 1, on the rising
edge of the trigger signal. You also need to define an asynchronous reset signal,
reset, to reset the counter bits to 0.
Architecture body definition:
=> Double-click on Architecture in the list of the Browser.
=> Type in archcounter in the field for the Architecture name field and counter
in the Entity name: field. The VHDL prompter for the architecture definition is
shown in Figure 2-28.
Figure 2-28 Architecture dialog box.
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=> Click OK.
The VHDL Browser translates your entries into the correct VHDL
syntax in the VHDL editor. The architecture portion of the counter.vhd
file should look like this:
ARCHITECTURE archcounter OF counter IS
BEGIN
END archcounter;
2
=> Place the cursor after the begin statement in the VHDL Editor.
=> Double click on Process under the Architecture listing from the VHDL Syntax
Browser.
This automatically places the information shown below in the architecture declaration
portion of counter.vhd.
PROCESS
-- Declarations
BEGIN
-- Statements
END PROCESS;
You need to associate a sensitivity list with the process. The process is to be made
sensitive to the signals reset and trigger.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Type (reset, trigger) after the word process in counter.vhd.
=> Place the cursor after the begin statement in the process statement in the
VHDL Editor.
=> Select Templates -> Browser.
=> Highlight if-then-else from the VHDL Browser and double-click on it to bring up
a VHDL prompter.
=> Enter reset=’1’ in the condition field and choose OK.
This adds the following lines to the counter.vhd file:
BEGIN
If reset= ’1’ THEN
--ELSIF <CONDITION> THEN
--ELSE
END IF:
=> Close the Syntax Broswer dialog box and click in the editor window.
=> Place the cursor after the if-then statement.
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=> Select Templates -> Browser.
=> In the VHDL Browser, double-click on Signal assign. from the VHDL Browser.
=> Within the VHDL browser, enter count in the Signal name: field and (others
=>’0’) for the Value: field.
This information tells the compiler that an asynchronous reset signal reset is associated
with the counter and that the counter bits should get reset to a 0 whenever the reset
signal goes high.
2
Instead of count <="0000" you assigned (others => ’0’) in order to preserve the
generic nature of the counter.
For more information about the usage of this operator, refer to the VHDL book located in
the Warp 6.3 online help.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Uncomment the elsif-then statement in the VHDL Browser by deleting the
-- before elsif and replacing <condition> with the following statement:
(trigger’event and trigger = ’1’).
This instructs Warp to make the counter sensitive to the rising edge of
the trigger signal.
=> Place the cursor on the next line after the elsif-then clause in counter.vhd.
=> Select Templates -> Browser.
=> Choose and double-click on Signal assign. from the VHDL Browser.
=> Type count in the Signal name: field and count + 1 in the Value: field and click
OK.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Delete the --else statement, the --declarations statement and the --statements.
When you have completed the architecture and entity declaration for counter.vhd, you
should have the following architecture declaration.
ARCHITECTURE archcounter OF counter IS
BEGIN
PROCESS (reset, trigger)
BEGIN
IF reset='1' THEN
count <= (others => '0');
ELSIF (trigger'event and trigger='1') then
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count <= count+1;
END IF;
END PROCESS;
END archcounter;
=> Select File -> Save to save the file.
2.3.5.3
2
Writing the Package Declaration
The package declaration provides the information to the Warp compiler to allow counter
to be used as a component in a higher-level design.
=> Place the cursor at the start of counter.vhd.
=> Select Templates -> Browser.
=> Double-click on Library clause in the VHDL Browser to bring up the VHDL
prompter with the field name.
=> Type in IEEE and click OK.
=> Double-click on Use clause from the VHDL Browser. Fill the following
information in the VHDL prompter: ieee.std_logic_1164.all
=> Double-click on Package decl. from the VHDL Browser. Type count_lib in
the VHDL prompter.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Place the cursor after the package statement.
=> Select Templates -> Browser.
=> Double-click on Comp. decl. from the VHDL Browser. Type counter in the
Name: field and click OK in the VHDL prompter.
=> Close the Syntax Browser dialog box and click in the editor window.
The port statement declares the name, direction, and type of each port in
the component. You can copy the port statement from the entity
declaration for this purpose or copy the following lines:
GENERIC (counter_size: integer:=4 );
PORT ( trigger, reset : in std_logic;
count : inout std_logic_vector(counter_size
downto 0) );
The package declaration should now look like:
LIBRARY IEEE;
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USE ieee.std_logic_1164.all;
PACKAGE count_lib IS
COMPONENT counter
-- setting the default size of the counter
GENERIC (counter_size: integer:=4 );
PORT ( trigger, reset : in std_logic;
count : inout std_logic_vector(counter_size
downto 0) );
END COMPONENT;
END count_lib;
2
=> Save the file.
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Here is the complete VHDL listing of counter.vhd.
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
LIBRARY CYPRESS;
USE cypress.std_arith.all
2
PACKAGE count_lib IS
COMPONENT counter
-- setting the default size of the counter
GENERIC (counter_size : integer:=4 );
PORT ( trigger, reset : in std_logic;
count : inout std_logic_vector(counter_size
downto 0) );
END COMPONENT;
END count_lib;
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
LIBRARY CYPRESS;
USE cypress.std_arith.all;
entity counter is
-- setting the default size of the counter
GENERIC (counter_size : integer:=4 );
PORT ( trigger, reset : in std_logic;
count : inout std_logic_vector(counter_size
downto 0) );
END counter;
ARCHITECTURE archcounter OF counter IS
BEGIN
PROCESS (reset, trigger)
BEGIN
IF reset='1' THEN
count <= (others => '0');
ELSIF (trigger'event and trigger='1') then
count <= count+1;
END IF;
END PROCESS;
END archcounter;
2.3.6
Creating the Top-Level Description
Create a top-level VHDL file to achieve the desired functionality for a parking garage
counter. Use the component counter discussed earlier. Continue using the VHDL
Browser to create total.vhd.
=> Start a new VHDL file.
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Start by providing the compiler with information on the library and package needed for
the std_logic and std_logic_vector types.
=> Place the cursor at the starting line of the VHDL editor.
=> Select Templates -> Browser.
2
=> Double-click on Library clause to bring up the VHDL prompter with the field
name. Type in IEEE and click OK.
=> Double-click on Use clause from the VHDL Browser. Fill the following
information in the VHDL prompter: ieee.std_logic_1164.all.
=> Double-click on Use clause from the VHDL Browser, typing in
cypress.std_arith.all when prompted.
=> Double-click on Use clause from the VHDL Browser, typing in
work.count_lib.all when prompted.
By using the count_lib package, you are allowing total.vhd access to the counter
model described in counter.vhd.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Place the cursor after the USE clauses.
=> Select Templates -> Browser.
=> Double-click on Entity decl. from the VHDL browser. Type total in the Entity
name: field and car_enter, car_exit, reset, lot_empty, lot_full,
count1, count2, total in the Port list: field and click OK.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Place the cursor on the line before the end statement.
=> Select Templates -> Browser.
=> Double click on Attr. spec.
=> In the Name: field, type synthesis_off.
=> In the Symbols: field, type total.
=> In the Class: field, type signal.
=> In the Value: field, type true.
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=> Click OK.
=> Close out the Syntax Browser dialog box and click in the editor window.
=> Modify the entity port list to include signal type and mode to match the complete
total.vhd entity listing as follows.
This is the complete listing for the entity of total.vhd.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE cypress.std_arith.all;
USE work.count_lib.all;
ENTITY total IS
GENERIC (size:integer:=5);
PORT ( car_enter : in std_logic;
car_exit
: in std_logic;
reset
: in std_logic;
lot_empty
: out std_logic;
lot_full
: out std_logic;
count1: inout std_logic_vector((size-1) downto 0);
count2: inout std_logic_vector((size-1) downto 0);
total : buffer std_logic_vector ((size-1) downto 0));
attribute synthesis_off of total: signal is true;
END total;
=> Save the file as total.vhd.
Now you are ready to create the architecture declaration for total.vhd.
=> Place the cursor after the entity declaration.
=> Select Templates -> Browser.
=> Double-click on Architecture in the VHDL Browser. Type in archtotal in the
Architecture name: field and total in the Entity name: field.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Place the cursor before the begin statement in the architecture declaration.
=> Select Templates -> Browser.
=> Double-click on Signal decl. in the VHDL Browser. Type in full in the Name:
field and std_logic_vector((size-1) in the Type: field.
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=> Close the Syntax Browser dialog box and click in the editor window.
=> Place the cursor after the begin statement.
=> Double-click on Component from the VHDL Browser. Type in counter1 in the
Label: field and counter in the Component: field in the VHDL Browser.
2
=> Double-click on Component from the VHDL Browser. Type in counter2 in the
Label: field and counter in the Component: field in the VHDL Browser.
=> Close the Syntax Browser dialog box and click in the editor window.
=> Uncomment the generic map statement by deleting the -- before generic
map and replacing <association list> with the following statement:
(size-1).
=> Modify the <association list> in the port map declaration for the
label counter1 and counter2 so that it matches the following complete
counter instantiation:
counter1: counter
GENERIC MAP(size-1)
PORT MAP(car_enter, reset, count1);
counter2: counter
GENERIC MAP(size-1)
PORT MAP(car_exit, reset, count2);
counter1 keeps track of the number of cars entering the garage and counter2 keeps track
of cars leaving the garage.
You now want to take the outputs from the two counters, count1 and count2, and
determine the difference between the two. Instead of building a subtractor from gates, use
the UltraGen module generation feature. Warp recognizes the operator “-” and knows that
a subtractor is required. Warp looks at your target device along with your optimization
goal of speed or area, and replaces the “-” operator with a hand-crafted module of a
subtractor from a library pre-optimized for either area or speed and your target device.
=> Type total <= count1 - count2; after the counter instantiations.
=> Type the following lines above the counter instantiations and under the word
begin to generate the lot_empty and lot_full signal:
full <= (others => ’1’);
lot_empty <= ’1’ when (total = "0000") else ’0’;
lot_full <= ’1’ when (total = full) else ’0’;
You could have generated the lot_full signal by comparing total with 11111. However,
defining full as full <= (others => ’1’); allows you to make changes to the size
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of the design without changing the architecture of the VHDL code.
=> Save the file.
You have now finished entering the code for total.vhd. The block diagram for total.vhd
is shown in Figure 2-29, followed by the final version of total.vhd.
reset
car_enter
reset
count1[4:0]
count
car_enter total[4:0]
trigger
car_exit
lot_full
reset
car_exit
trigger
count
logic
lot_empty
count2[4:0]
Figure 2-29 Block Diagram for total.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
USE work.count_lib.all;
ENTITY total IS
GENERIC (size:integer:=5);
PORT (car_enter : in std_logic;
car_exit : in std_logic;
reset : in std_logic;
lot_empty : out std_logic;
lot_full : out std_logic;
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count1 : inout std_logic_vector ((size-1)
downto 0);
count2 : inout std_logic_vector ((size-1)
downto 0);
total : buffer std_logic_vector((size-1)
downto 0));
attribute synthesis_off of total: signal is true;
END total;
2
ARCHITECTURE archtotal OF total IS
SIGNAL full : std_logic_vector((size-1) downto 0);
BEGIN
full <= (others => '1');
lot_empty <= '1' when (total = "0000") else '0';
lot_full <= '1' when (total = full) else '0';
counter1: counter
GENERIC MAP(size-1)
PORT MAP(car_enter, reset, count1);
counter2: counter
GENERIC MAP(size-1)
PORT MAP(car_exit, reset, count2);
total <= count1 - count2;
END archtotal;
2.3.7
Selecting Files for Compilation
=> Add the files counter.vhd and total.vhd to the compile list. Choose Project ->
Add Files. Review Section 2.2.8 if you need help adding files to your project.
2.3.8
Compiling and Synthesizing the Design
2.3.9
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
2.3.9.1
Setting Unused Outputs
Warp gives you the option of turning all of your unused output pins that have unused
macrocells into ‘1’s, ‘0’s, or ‘Z’s. This is a global option and cannot be applied on a signalby-signal basis. This option is useful for driving all unused pins to a certain logic level.
=> Under the Unused Outputs options of the Project -> Compiler Options ->
Synthesis tab, choose Z, the default option of leaving all unused I/O pins to be
three-stated.
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Note – When using MAX340 EPLDs and FLASH370 CPLDs, it is a
recommended practice to use external pull-ups for unused I/O pins.
2.3.9.2
Choosing Tech Mapping Options
While compiling registered equations, the fitter uses the directive from Choose FF types
to synthesize equations. Leaving the option Opt selected is the best choice. This enables
the fitter to make the choice between a D-FF and a T-FF implementation and then choose
the implementation that uses the least number of product terms.
=> Under Tech Mapping options in the Synthesis tab, select the Optimal option.
There are a few other useful options in the Tech Mapping options, which are explained in
the Galaxy online help, accessible from the Galaxy Help menu.
2.3.9.3
ers Only
Choosing a Timing Model for Active-HDL Sim (PC Custom-
On the PC platforms, Warp Release 6.3 includes the Active-HDL Sim timing simulator.
This section applies only if you want to simulate your design using Active-HDL Sim
installed on your PC. You can verifty the synthesized design using Active-HDL Sim by
creating the Active-HDLSim/Active-VHDL timing model of the design using Warp.
The refill.vhd file should be compiled with the Active-HDLSim/Active-VHDL timing
model before using Active-HDL Sim.
=> Select Project -> Compiler Options -> Synthesis tab and click on the Timing
Model drop-down menu in the Simulation area.
=> Select Active-HDLSim/Active-VHDL.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
2.3.10
Setting the Top-Level File
=> Click on total.vhd.
=> Select Project -> Set Top or click on the Set Top button available on the project
toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will
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be green.
2
Figure 2-30 Project sub-window showing total.vhd as the top-level
file.
2.3.11
Compiling and Synthesizing the File
=> In your Galaxy window, select Compile -> Project to begin compilation click
the Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a CY37256
device and prints messages to keep you appraised of its progress in the
results sub-window. The Compile - > Project option automatically
recompiles only those files which have been modified since the last
compilation.
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Figure 2-31 Successful compilation in Results sub-window.
This operation generates two files of particular interest:
•
total.jed is used to program a CY37256 device.
•
total.rpt contains pinout and timing information, along with other information about
the final synthesized design. You can see the .rpt file and the output files created by
Warp by clicking on the output view tab in the Project sub-window (Fig. 2-6).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections. For more information on what is contained in a report
file, refer to the Report File book located in the Warp online help.
=> Close the Galaxy compilation window by clicking on the Close button located at
the top of the Galaxy compilation window.
Note – If compilation errors occur, make sure the text of your
counter.vhd and total.vhd file are entered exactly as shown earlier in
this chapter -- or copy it from the <warp path>\examples\wtutor\vhdl
directory -- and then run Warp again. If compiler errors occur, use the
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Locate Error button to track down the errors. Review the tutorial
information in Section 2.2.10.5 if needed.
2.3.12
2
Simulating the Behavior of the Design with Active-HDL Sim
UNIX Customers
Please refer to Chapter 9, Simulation, in the User’s Guide for details on how to simulate
the design after fitting.
PC Customers
In Warp Release 6.3, the synthesized design can be verified using the Active-HDL Sim
simulator. This section applies only if you have Active-HDL Sim installed on your PC.
In this section of the tutorial, you will perform the following steps:
2.3.13
•
Start Active-HDL Sim.
•
Open the total.vhd file in the w2tutor/vhd/vhd folder.
•
Set the values of the stimulus signals in the simulation.
•
Simulate the design.
•
Examine results to figure out what happened.
Starting Active-HDL Sim
=> Start Active-HDL Sim by selecting Tools -> Active-HDL Sim in Galaxy.
=> Open the total.vhd file by choosing File -> Open VHDL and browse to w2tutor/
vhd/vhd.
=> Click on total.vhd.
=> Click on OK. The Active-HDL Sim window should resemble Figure 2-32.
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Figure 2-32 The initial Active-HDL Sim window for total.vhd.
2.3.14
Creating a View
=> Select Waveform -> Add Signals.
=> The right pane of the dialog box shows the available signals to add to your
waveform. See Figure 2-33.
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Figure 2-33 Add Signals dialog box with available signals for creatinga
view.
=> Double click on the following signals to add them to your new view in the
following order: car_enter, car_exit, reset, lot_empty,
lot_full, count1, count2 and total.
=> Click on Add.
Note – If you disabled “Enable Testbench Output” in the Compiler
Options dialog box in Galaxy, you’ll see the following signals instead of
count1, count2 and total: count1_0, count1_1,
count1_3, count1_4 , count2_0, count2_1,
count2_2, count2_3, count2_4, total_0, total_1,
total_2, total_3 and total_4. You’ll need to create 3 separate buses to merge the signals. To create a bus, highlight the signals you
want to merge, such as count1_0, count1_1, count1_2,
count1_3, count1_4, then right click on the highlighted area and
select “Merge Signals”.
Note – A merged signal has a plus sign to the left side of the signal
name. You can expand and contract the plus sign to show or hide the
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signals that make up the merged signals.
Your new view should look like Figure 2-34.
2
Figure 2-34 Active-HDL Sim screen of your new view.
2.3.15
Setting Stimulus Signal Values
You need to set the values of the following input signals for your simulation:
Oscillate the car_enter signal. This should simulate the cars entering.
=> Select the car_enter signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following text in the “Enter Formula” field:
=> 0 0 ns, 1 20 ns, 0 40 ns, 1 60 ns, 0 80 ns, 1 100 ns, 0
120 ns, 1 140 ns, 0 160 ns, 1 180 ns, 0 200 ns
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Set car_enter to “0”.
=> Set car_enter to low for 120 ns by appending -r 320 ns to the text entered
above in the Formula field.
=> Click on the Apply button and then click on Close.
2
Set reset to high for one rising clock edge. To do so:
=> Select the reset signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following text in the “Enter Formula” field:
=> 0 0, 1 1 ns, 0 41 ns
=> Click on the Apply button and then click on Close.
Set car_exit for 0.
=> Select the car_exit signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following text in the “Enter Formula” field:
=> 0 0 ns
Oscillate the car_exit signal, while the car_enter signal remains low. This should
simulate cars exiting.
=> Add the following text after the above text in the “Enter Formula” field:
=> , 1 200 ns, 0 220 ns, 1 240 ns, 0 260 ns, 1 280 ns, 0
300 ns
=> Click on the Apply button and then click on Close.
The result, when complete, should look like Figure 2-35.
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2
Figure 2-35 Active-HDL Sim stimulators dialog box for total.awf
with all the signals set
2.3.16
Running the Simulation
=> To simulate the design, click on the Run Until button in the toolbar and enter
200ns.
Note – To re-initialize the simulation, click on the Restart Simulation
button on the Toolbar or select it from the Simulation -> Restart Simulation menu and select Waveforms -> Clear all Waveforms.
Note – You may wish to change the screen resolution in order to fit all
activity in the waveforms on one screen. Select View -> Zoom -> Out.
=> The simulation will stop after the specified duration has been simulated.
The results should look similar to Figure 2-36:
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Figure 2-36 Results of the total.vhd Active-HDL Sim simulation
84
•
Notice that when you set the reset signal to high, both counters were set to 0 and
Total was set to 0.
•
The bus Total was created in order to read the value of Total (display is
hexadecimal by default). The other two bus signals, count1 and count2 reflect the
total number of cars have entered and exited the parking garage. The relationship
between the three bus signals is illustrated by the equation: Total = Count1 - Count2.
•
The signal lot_empty was initially high when Total = “00” (hexadecimal).
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•
The signal lot_full becomes high when Total = “1F” (hexadecimal). The
counter is designed to wrap around once it counts to its maximum value (1F).
Therefore, the counter is triggered by car_enter and wraps around to a “00” after
counting to “1F”. This, in turn, makes the signal lot_empty go high.
=> Continue the simulation (click on the Run For button) for another 200 ns and see
how the total changes.
=> From 200 to 300 ns, car_enter is low and car_exit oscillates and hence
the total decrements.
=> From 300 to 400 ns, the car_exit is zero and car_enter oscillates and the
total increments.
2.3.17
Back-Annotating Pin Assignment Information
You can easily lock-in the pin assignment made by the place and route tool.
=> Start Galaxy.
=> Highlight total.vhd by clicking on it. If you do not have total.vhd selected, do a
Project->Add and add total.vhd.
=> Choose Annotate... from the Project pull-down menu.
A window appears giving the name of the file to be back-annotated (in
our case, total.vhd), and giving us the option of back-annotating the
pins, the nodes or both. The Pins option should already be selected.
=> If Pins is not already selected, select it by clicking on the button to the left of
Pins.
=> If Nodes is selected, deselect it by clicking on the button to the left of Nodes.
=> Click on the OK button to back-annotate the pin information.
Note – The back-annotation information is stored in a control file.
Control files have a .ctl extension.
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2.4
Designing a Soda Machine for Ultra37000 (Verilog)
The first example described in the Verilog language will be an implementation of the soda
machine.
2
In this example, you will:
2.4.1
•
Write a Verilog module declaration for a behavioral description of a simple circuit.
•
Run Warp to compile and synthesize the design’s Verilog description.
Design Description
In this example, you will design a controller for a soft-drink dispensing machine. The
machine has two bins to dispense regular cola and diet cola. Each bin holds three cans of
soft drink. (This could be any value, but three is an easy number to simulate.)
The circuit dispenses a beverage if the user presses a button for that beverage and at least
one can is available. A refill signal appears when both bins are empty. Pressing a reset
signal tells the circuit that the machine has been replenished and the bins are full.
2.4.2
Design Solution
The solution presented in this section proceeds as follows:
First, describe a circuit in IEEE standard Verilog that controls the operation of one bin. It
responds appropriately to a get_drink signal (giving a drink when one is available),
keeps count of the number of cans left in the bin, and sets an empty signal when its bin
becomes empty and is in need of resetting. This circuit is named binctr.
Next, write a top-level description of a circuit that instantiates two binctrs and other logic
as appropriate to describe the larger soda machine design. The larger design is called
refill.
After that, compile and synthesize the binctr and refill Verilog descriptions into a
CY37256 JEDEC file.
2.4.3
Starting Warp Applications
=> On Windows NT and Windows 95 systems, start Warp applications by clicking
on Start, then selecting Programs -> Cypress -> Warp R6.3 -> Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as
galaxy<CR>, from within a shell window.
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2.4.4
Creating A New Project
If you have not already started Galaxy, refer to section Chapter 2.2.3, Starting Warp
Applications for information on starting applications on your platform.
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK.
3.
Select Verilog as the Project Type.
4.
Enter the name of the project, "drink".
5.
Enter the project path as follows.
2
=> On the PC, enter c:\w2tutor\vlog.
=> On UNIX systems, enter <user_home_directory_path>/w2tutor/vlog.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of Verilog files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will add files from the Project menu
later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device subfamily (Delta39K, Quantum38K, Ultra37000, Flash, MAX, etc.), device name and
package type. The user can traverse the device tree. On the left side of the dialog box are
the Devices available and on the right side are the Packages available for the device
selected.
7.
Navigate the tree to CPLD -> Ultra37000 -> c37256.
8.
Highlight the 37256P160-154AC package on the right side.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You should see the title of the project and the device information on the
Galaxy title bar (Figure 2-37).
You have now created a project directory for your designs named
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w2tutor/vlog. All files pertinent to this tutorial need to be placed in this
project directory. You have also created a project file called drink.pfg
which is now located in the c:\w2tutor\vlog directory.
2
Figure 2-37 Galaxy window for the project ‘drink.’
2.4.5
Creating the Verilog File
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
This brings up the Galaxy editor (Figure 2-38) where you enter your
Verilog code.
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Figure 2-38 Galaxy editor window
The first file to be coded will be binctr.v.
=> Type the following lines into the editor:
module
input
input
input
inout
inout
binctr (reset, get_drink, clk, give_drink, empty);
reset;
get_drink;
clk;
give_drink;
empty;
parameter full = 2'b 11;
reg tmp_give_drink;
reg tmp_empty;
reg [1:0] remaining;
always @(posedge clk or posedge reset)
begin
if (reset == 1'b 1)
begin
remaining <= full;
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tmp_empty <= 1'b 0;
tmp_give_drink <= 1'b 0;
end
else
begin
if (remaining == 2'b 00)
begin
tmp_empty <= 1'b 1;
tmp_give_drink <= 1'b 0;
end
else if (get_drink == 1'b 1)
begin
remaining <= remaining - 1;
tmp_give_drink <= 1'b 1;
end
else if (get_drink == 1'b 0)
begin
tmp_give_drink <= 1'b 0;
end
else
begin
tmp_give_drink <= give_drink;
remaining <= remaining;
tmp_empty <= empty;
end
end
end
2
assign give_drink = tmp_give_drink;
assign empty = tmp_empty;
endmodule
=> To save your Verilog code on the PC platorms, select File -> Save As... and enter
the filename and the path: c:\w2tutor\vlog\binctr.v. Click OK to save.
=> To save your Verilog code on the UNIX platforms, select File -> Save As... and
enter the filename and the path: <home_directory>/w2tutor/vlog/binctr.v. Click
OK to save.
Verilog Syntax Explanation
A line-by-line explanation of the binctr.v design follows. It is intended to help familiarize
the user with the Verilog HDL used to describe the design.
The module definition names the design and identifies the I/O ports used:
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module binctr (reset, get_drink, clk, give_drink, empty);
The next 5 lines assign the direction of the ports identified by the module definition by
defining them as inputs, outputs or inouts.
input
input
input
inout
inout
reset;
get_drink;
clk;
give_drink;
empty;
2
The parameter full is next defined as a constant of binary value 11:
parameter full = 2'b 11;
The remaining 3 lines of the definition create temporary variables as regs for keeping
track of signals used in the always procedural block:
reg
reg
reg
tmp_give_drink;
tmp_empty;
[1:0] remaining;
The always procedural block describes the action of the design in response to the “clk”
and “reset” signals. In this instance, it is triggered on the positive edge of either.
The body of the block describes the logic followed when either of these triggering signals
is received. The temporary variables are used internally to implement the logic needed.
always @(posedge clk or posedge reset)
begin
if (reset == 1'b 1)
begin
remaining <= full;
tmp_empty <= 1'b 0;
tmp_give_drink <= 1'b 0;
end
else
begin
if (remaining == 2'b 00)
begin
tmp_empty <= 1'b 1;
tmp_give_drink <= 1'b 0;
end
else if (get_drink == 1'b 1)
begin
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remaining <= remaining - 1;
tmp_give_drink <= 1'b 1;
end
else if (get_drink == 1'b 0)
begin
tmp_give_drink <= 1'b 0;
end
else
begin
tmp_give_drink <= give_drink;
remaining <= remaining;
tmp_empty <= empty;
end
2
end
end
To make the internal signals visible to the outside, the temporary variables are assigned to
the ports of the module.
assign give_drink = tmp_give_drink;
assign empty = tmp_empty;
Finally, the definition of the module is terminated with:
endmodule
2.4.6
Creating a Top-Level Description
At this point, the top-level file must be written. The top-level design will instantiate the
binctr.v design that was just finished. In Verilog, this is not accomplished with packages
or libraries, but rather the inclusion of both designs at the time of compilation.
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
This brings up the Galaxy editor where you enter your Verilog code.
This file will become refill.v
=> Type the following lines into your text editor:
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module refill (GIVE_cola,GIVE_diet,REFILL_BINS,RESET,CLK,
GET_diet,GET_cola);
inout
GIVE_cola;
inout
GIVE_diet;
output REFILL_BINS;
input
RESET;
input
CLK;
input
GET_diet;
input
GET_cola;
wire
empty_1, empty_2;
binctr bin_1 (.reset(RESET),
.get_drink(GET_cola),
.clk(CLK),
.give_drink(GIVE_cola),
.empty(empty_1));
2
binctr bin_2 (.reset(RESET),
.get_drink(GET_diet),
.clk(CLK),
.give_drink(GIVE_diet),
.empty(empty_2));
assign REFILL_BINS = (empty_1 == 1'b 1 & empty_2 == 1'b 1)
? 1'b 1 : 1'b 0;
endmodule
=> Save the file as c:\w2tutor\vlog\refill.v on the PC platforms and as
<home_directory>/w2tutor/vlog/refill.v on the UNIX platforms.
Verilog Syntax Explanation
The Verilog code used to implement the top level Verilog design is entirely structural in
nature. The definition of the module with its ports is done with the following lines:
module refill (GIVE_cola,GIVE_diet,REFILL_BINS,RESET,CLK
GET_diet,GET_cola);
inout
inout
output
input
input
input
input
GIVE_cola;
GIVE_diet;
REFILL_BINS;
RESET;
CLK;
GET_diet;
GET_cola;
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Following those lines are instantiations of the binctr as
bin_1 and bin_2:
binctr bin_1 (.reset(RESET),
.get_drink(GET_cola),
.clk(CLK),
.give_drink(GIVE_cola),
.empty(empty_1));
2
binctr bin_2 (.reset(RESET),
.get_drink(GET_diet),
.clk(CLK),
.give_drink(GIVE_diet),
.empty(empty_2));
And finally, the constant assignment logic of the REFILL_BINS signal depending upon
the value of empty_1 and empty_2 is done before the module definition is closed.
assign REFILL_BINS = (empty_1 == 1’b 1 & empty_2 == 1’b 1)
? 1’b 1 : 1’b 0;
The block diagram for ‘refill.v’ is shown in Figure 2-39 and the Verilog code is shown in
Figure 2-40.
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BIN_1
get_diet
get_drink
give_drink
reset
reset
empty
clk
clk
give_diet
logic
2
refill_bins
BIN_2
get_cola
get_drink
give_drink
reset
empty
give_cola
clk
Figure 2-39 Block Diagram for refill.v
Figure 2-40 Final Verilog window for refill.v.
2.4.7
Selecting Files for Compilation
After the files are created, they need to be added to the project. Galaxy has a Preferences
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menu item under the Edit menu that allows you to set the design file extension. These
extensions are used to identify Verilog files. For Verilog projects, the default file name
extensions are: .v and .vlg.
2
2.4.7.1
To add a Verilog file:
1.
Use the menu item Project -> Add Files. This accesses a dialog box (Figure 2-41)
where one or more Verilog files can be selected. Files are added in the order they
are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the binctr.v file and click Add.
4.
Highlight the refill.v file and click Add.
5.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
Figure 2-41 Adding Files to a Verilog project
2.4.8
Compiling and Synthesizing a Top-Level File
In the following pages, you will run Warp to produce a JEDEC file for a specific target
device, in this case, a CY37256 macrocell CPLD.
2.4.8.1
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
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2.4.8.2
Setting Unused Outputs
Warp gives you the option of turning all of your unused output pins that have unused
macrocells into ‘1’s, ‘0’s, or ‘Z’s. This is a global option and cannot be applied on a signalby-signal basis. This option is useful for driving all unused pins to a certain logic level.
=> Under the Unused Outputs options of the Project -> Compiler Options ->
Synthesis tab, choose Z, the default option of leaving all unused I/O pins to be
three-stated.
Note – When using MAX340 EPLDs and FLASH370 CPLDs, it is a
recommended practice to use external pull-ups for unused I/O pins.
2.4.8.3
Choosing Tech Mapping Options
While compiling registered equations, the fitter uses the directive from Choose FF types
to synthesize equations. Leaving the option Opt selected is the best choice. This enables
the fitter to make the choice between a D-FF and a T-FF implementation and then choose
the implementation that uses the least number of product terms.
=> Under Tech Mapping options in the Synthesis tab, select the Optimal option.
There are a few other useful options in the Tech Mapping options, which are explained in
the Galaxy online help, accessible from the Galaxy Help menu.
2.4.8.4
Choosing a Timing Model for Active-HDL Sim (PC Platforms only)
On the PC platforms, Warp Release 6.3 includes the Active-HDL Sim timing simulator.
This section applies only if you want to simulate your design using Active-HDL Sim
installed on your PC. You can verifty the synthesized design using Active-HDL Sim by
creating the Active-HDLSim/Active-VHDL timing model of the design using Warp.
In order to simulate your Verilog file with Active-HDL Sim, you must compile your
refill.v with Active-HDLSim/Active-VHDL, which will generate a refill.vhd file.
=> Select Project -> Compiler Options -> Synthesis tab and click on the Timing
Model drop-down menu in the Simulation area.
=> Select Active-HDLSim/Active-VHDL.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
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2.4.8.5
Setting the Top-Level File
=> Click on refill.v.
=> Select Project -> Set Top or click on the Set Top button available on the project
toolbar.
2
=> Once the top-level file has been set, the file symbol marker in the hierarchy will
be a tree (Figure 2-42).
Figure 2-42 Galaxy window showing refill.v as the top-level design.
2.4.8.6
Compiling and Synthesizing the File
=> In your Galaxy window, select Compile -> Project to begin compilation or click
the Compile Project button on the project toolbar.
Figure 2-43 Galaxy Compile window showing successful compilation.
Warp starts the compilation and synthesis of the design into a 37256 and
prints messages to keep you appraised of its progress in the results sub-
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window. The Compile -> Project option automatically recompiles only
those files which have been modified since the last compilation.
This operation generates two files of particular interest:
•
refill.jed: is used to program the 37256P160-154AC device.
•
refill.rpt: contains pinout and timing information, along with other information about
the final synthesized design. You can see the .rpt file and the output files created by
Warp by clicking on the output view tab in the Project sub-window (Figure 2-44).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
Figure 2-44 Output file in project sub window.
Note – If compilation errors occur, make sure the text of your refill.v
file is entered exactly as shown earlier in this chapter -- or, copy the file
from the <warp path>\examples\wtutor\vlog directory -- and then run
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Warp again.
If compiler error messages appear in the results sub-window:
=> Double click on the error message.
2
=> Go to the Galaxy editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
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2.5
Designing a Parking Garage Monitor (Verilog)
The second Verilog language example is that of a parking garage monitor.
In this section, you will:
•
Write a module declaration for a simple counter circuit using the Warp Verilog editor.
•
Write a top-level module using behavioral Verilog to implement logic functions and to
instantiate the counter circuit, using the Warp Verilog editor.
•
Run Warp to synthesize the design’s Verilog description.
•
Learn the methodology to simulate the behavior of the design.
When you complete this section, you will know how to:
2.5.1
•
Take advantage of Cypress’ UltraGen module generation technology on various
operators.
•
Choose between Area and Speed optimization to obtain results best suited for your
application.
Design Description
This design keeps track of the total number of cars entering a parking lot garage, the total
number of cars that have left the garage, and the number of cars remaining in the garage.
For this exercise, set 32 to be the maximum number of parking lot spaces available. You
also need to alert the parking lot attendant if the parking lot is empty or full. Additionally,
the attendant should also be able to reset the count of the number of cars in the garage to a
zero, at their discretion.
2.5.2
Design Solution
The solution presented in this chapter proceeds as follows:
You are going to create two Verilog files, counter.v and total.v. The counter.v file shows
the implementation of a counter that increments the count by 1 on the rising edge of a
clock (trigger). It also contains an asynchronous reset signal that resets the counter to zero.
This counter is a variable size counter with default size of a 4-bit output data.
The top-level Verilog file, total.v, instantiates the counter twice. The first counter keeps
track of the incoming cars, and the second counter keeps track of the cars exiting the
parking garage. The top-level file takes the output of the second counter and subtracts it
from the output of the first counter to give the attendant the number of cars remaining in
the parking lot. There are two signals, lot_empty and lot_full, to let the attendant know if
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the garage is empty or full. Set both counters to have data width of 5 bits. After that,
synthesize the counter and total Verilog descriptions into a CY7C371 CPLD.
This tutorial reinforces basic Verilog constructs and the concept of hierarchical designs.
This exercise is also intended to make the user more familiar with the Warp tool flow.
2
2.5.3
Getting Started
=> Start Galaxy on your platform. Refer to section Chapter 2.2.3, Starting Warp
Applications for information on starting applications on your platform.
2.5.4
Creating a New Project
Refer to Chapter 2.2.4, Creating A New Project. In Step 4, enter the name of the project as
“parking”.
2.5.5
Creating the Verilog File
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
=> This brings up the text editor and allows you to begin entering your Verilog code.
Note – If you would rather not type the counter.v file yourself, you can
copy it from the Warp directory. The default location for counter.v is
<warp_install_dri>\examples\wtutor\vlog\counter.v. From this
location, copy counter.v to your project directory. Then, read along for
the next few pages to help you understand the purpose of each section of
a Verilog source file.
When using Verilog, only the design files themselves (total.v and counter.v) are entered.
The first file to be coded will be counter.v.
=> Type the following lines into your text editor:
module counter (trigger, reset, count);
parameter counter_size = 4;
input trigger;
input reset;
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inout [counter_size:0] count;
reg [counter_size:0] tmp_count;
always @(posedge reset or posedge trigger)
begin
if (reset == 1'b 1)
tmp_count <= {(counter_size + 1){1'b 0}};
else
tmp_count <= count + 1;
end
2
assign count = tmp_count;
endmodule
=> Save the file as c:\w2tutor\vlog\counter.v on the PC platforms and as
<home_directory>/w2tutor/vlog/counter.v on the UNIX platforms.
2.5.6
Creating a Top-Level Description
At this point, the top-level file must be written. Start another new edit by invoking the text
editor. The top-level design will instantiate the counter.v design that was just finished. In
Verilog, this is not accomplished with packages or libraries, but rather the inclusion of
both designs at the time of compilation.
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
Note – If you would rather not type the total.v file yourself, you can
copy it from the Warp directory. The default location for total.v is
<warp_install_dir>\examples\wtutor\vlog\total.v. From this
location, copy total .v to your project directory. Then, read along for the
next few pages to help you understand the purpose of each section of a
Verilog source file.
This file will become total.v
=> Type the following lines into your text editor:
module total (car_enter,car_exit,reset,lot_empty,lot_full,
count1,count2,total);
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‘define size 5
input car_enter;
input car_exit;
input reset;
inout lot_empty;
inout lot_full;
inout [4:0] count1;
inout [4:0] count2;
inout [4:0] total;
2
wire [4:0] full;
assign full = {(‘size){1'b 1}};
assign lot_empty = total == 4'b 0000 ? 1'b 1 : 1'b 0;
assign lot_full = total == full ? 1'b 1 : 1'b 0;
defparam counter1.counter_size = ‘size - 1;
counter counter1 (.trigger(car_enter),
.reset(reset),
.count(count1));
defparam counter2.counter_size = ‘size - 1;
counter counter2 (.trigger(car_exit),
.reset(reset),
.count(count2));
assign total = count1 - count2;
endmodule
=> Save the file as c:\w2tutor\vlog\total.v on the PC platforms and as
<home_directory>/w2tutor/vlog/total.v on the UNIX platforms.
The block diagram for ‘total.v’ is shown in Figure 2-45.
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reset
reset
car_enter
count1[4:0]
count
car_enter total[4:0]
trigger
car_exit
lot_full
reset
car_exit
trigger
count
logic
lot_empty
count2[4:0]
Figure 2-45 Block Diagram for total.v
2.5.7
Selecting Files for Compilation
After the files are created, they need to be added to the project. Galaxy has a Preferences
menu item under the Edit menu that allows you to set the design file extension. These
extensions are used to identify Verilog files. For Verilog projects, the default file name
extensions are: .v and .vlg.
To add a Verilog file:
1.
Use the menu item Project -> Add Files. This accesses a dialog box (Figure 2-46)
where one or more Verilog files can be selected. Files are added in the order they
are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the counter.v file and click Add.
4.
Highlight the total.v file and click Add.
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5.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
2
Figure 2-46 Adding Files to a Verilog project
2.5.8
Compiling and Synthesizing a Top-Level File
In the following pages, you will run Warp to produce a JEDEC file for a specific target
device, in this case, a CY37256 CPLD.
2.5.9
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
2.5.9.1
Setting Unused Outputs
Warp gives you the option of turning all of your unused output pins that have unused
macrocells into ‘1’s, ‘0’s, or ‘Z’s. This is a global option and cannot be applied on a signalby-signal basis. This option is useful for driving all unused pins to a certain logic level.
=> Under the Unused Outputs options of the Project -> Compiler Options ->
Synthesis tab, choose Z, the default option of leaving all unused I/O pins to be
three-stated.
Note – When using MAX340 EPLDs and FLASH370 CPLDs, it is a
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recommended practice to use external pull-ups for unused I/O pins.
2.5.9.2
Choosing Tech Mapping Options
While compiling registered equations, the fitter uses the directive from Choose FF types
to synthesize equations. Leaving the option Opt selected is the best choice. This enables
the fitter to make the choice between a D-FF and a T-FF implementation and then choose
the implementation that uses the least number of product terms.
=> Under Tech Mapping options in the Synthesis tab, select the Optimal option.
There are a few other useful options in the Tech Mapping options, which are explained in
the Galaxy online help, accessible from the Galaxy Help menu.
2.5.9.3
Choosing a Timing Model for Active-HDL Sim (PC Platforms only)
On the PC platforms, Warp includes the Active-HDL Sim timing simulator. This section
applies only if you want to simulate your design using Active-HDL Sim installed on your
PC. You can verifty the synthesized design using Active-HDL Sim by creating the ActiveHDLSim/Active-VHDL timing model of the design using Warp.
In order to simulate your Verilog file with Active-HDL Sim, you must compile your
refill.v with Active-HDLSim/Active-VHDL, which will generate a refill.vhd file.
=> Select Project -> Compiler Options -> Synthesis tab and click on the Timing
Model drop-down menu in the Simulation area.
=> Select Active-HDLSim/Active-VHDL.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
2.5.10
Setting the Top-Level File
=> Click on total.v.
=> Select Project -> Set Top or click on the Set Top button available on the project
toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will
be changed to a tree. (Figure 2-47).
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Figure 2-47 Galaxy window showing total.v as the top-level design.
2.5.11
Compiling and Synthesizing the File
=> In your Galaxy window, select Compile -> Project to begin compilation or click
the Compile Project button on the project toolbar.
Figure 2-48 Results sub-window showing a successful compilation.
Warp starts the compilation and synthesis of the design into a
CY7C371I and prints messages to keep you appraised of its progress in
the results sub-window. The Compile -> Project option automatically
recompiles only those files which have been modified since the last
compilation.
This operation generates two files of particular interest:
108
•
total.jed: is used to program a CY37256 device.
•
total.rpt: contains pinout and timing information, along with other information about
the final synthesized design. You can see the .rpt file and the output files created by
Warp by clicking on the output view tab in the Project sub-window (Figure 2-49).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
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Figure 2-49 Output view tab in project sub window.
Note – If compilation errors occur, make sure the text of your refill.v
file is entered exactly as shown earlier in this chapter -- or, copy the file
from the <warp path>\examples\wtutor\vlog directory -- and then run
Warp again.
If compiler error messages appear in the results sub-window:
=> Double click on the error message.
=> Go to the Galaxy editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
2.5.12
Simulating the Behavior of the Design
UNIX Customers
Please refer to Chapter 9, Simulation, in the User’s Guide for details on how to simulate
the design after fitting.
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PC Customers
On the PC platforms, the synthesized design can be verified using the Active-HDL Sim
simulator.
See Section 2.3.13 for instructions on how to simulate using Active-HDL Sim.
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3.1
Introduction
The Warp tutorials demonstrate a common sequence of operations in Warp. The tutorials
show the user how to create, compile, synthesize, and simulate designs in Verilog.
This section presents:
•
product description of Warp
•
some conventions about typography, wording, and illustrations used in this tutorial
•
the objectives of the tutorial
•
the contents of the tutorial
The tutorials are organized based on the product.
3.1.1
Product Descriptions
Warp
Warp users describe electronic designs using Verilog and then compile and synthesize
those descriptions to program Cypress devices, such as Delta39K, Quantum38K, PSI,
small PLDs, MAX340 EPLDs, FLASH370, and ULTRA37000 CPLDs.
3
Warp consists of:
112
•
The Warp Verilog IEEE 1364-1995 compliant compiler to translate Verilog text
descriptions into JEDEC files that can be mapped onto programmable devices.
•
On the PC platforms, Warp also contains an FSM editor and Active-HDL Sim, the
post-synthesis timing simulator from Aldec, Inc.
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3.1.2
Conventions
The following conventions are used throughout this manual:
Table 3-1 Notational Conventions
Font Style
Definition
Menu items
Whenever an item from a menu is referenced, the reference
takes the form menu-name->item-name->item-name... The
first entry in the reference is the name of the menu; the second is the name of the menu item; the third and succeeding
entries indicate choices from sub-menus. Example: Select
File->Open... tells you to pull down the File menu and
select the Open... item from it.
Path names
Italics designate path names and file names.
Bold
Bold designates emphasis or draws attention to new terms.
signal
Courier denotes signal names, Verilog constructs, and
system output.
text
Courier denotes the contents of a text file and also indicates the text of typed commands.
File Naming Conventions
Warp runs on many different platforms: IBM PCs and compatible computers and Sun
workstations.
IBM PCs and compatible computers specify file locations by designating a disk drive and
using a backslash (\) character to distinguish directory levels, e.g., c:\level1\level2\myfile.
Sun workstations specify file locations using a forward slash (/) and no disk drive
designator, e.g., /level1/level2/myfile.
For consistency and brevity, this manual uses the same notation as IBM PCs and
compatibles when referring to file locations. UNIX platform users are asked to make
appropriate translations.
Verilog is case-sensitive. When entering anything, make sure case is correct and
consistent.
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Mouse Conventions
The following terms describe common actions you might perform in using this manual:
Table 3-2 Mouse Conventions
Action
3
Definition
Click
Place the mouse cursor over an object, then press and
release the appropriate mouse button.
Double-click
Position the mouse cursor over an object, then press and
release the appropriate mouse button twice in rapid succession.
Drag
Position the mouse cursor over an object or at a specified
location. Press and hold the appropriate mouse button.
While holding down the mouse button, move the cursor to
the new location. Release the mouse button.
Select
Move the cursor over the option to be selected. Click the
appropriate mouse button.
Other Conventions
The following visual indicators denote special situations you may encounter while using
this manual.
Note – This icon indicates a note. This is information you should read
before continuing with a procedure.
Hint – This icon indicates a hint. This is information that could save a
little time, a few keystrokes, or much frustration.
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3.1.3
Differences between Operating Systems
Warp operates identically on both UNIX and Windows systems except for the start-up
procedure and the appearance of some objects in the display.
Naming Restrictions
Keep in mind that some UNIX systems have trouble with spaces embedded in file names.
That can be true for IBM PCs and compatible systems too. Cypress does not allow using
embedded spaces in file names.
If you are working in a system with PCs (running under Windows) and UNIX
workstations connected to the same network, Cypress advises you to name all Verilog files
with lower case characters.
Differences in Display
Although dialog boxes and prompts may differ in appearance between the two platforms,
their functionality is identical. Screen captures in this manual are taken from the Windows
version of Warp. Differences in the UNIX version are identified when necessary. In most
cases, any adjustments needed to go from Windows to UNIX versions of Warp displays
are obvious.
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Delta39K and Quantum38K Design Tutorials
(VHDL)
This is a series of step-by-step examples illustrating the new tools added to Warp in the
transition from Warp2 Release 5 to Warp Release 6 and utilizing the features available in
the new Delta39K and Quantum38K device families.
3
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•
Section 3.2, Designing a Dual-Port Memory Circuit (VHDL): Instantiate a dual-port
RAM memory from the LPM template library, write the entity and architecture
declarations for the VHDL behavioral description of its arbitration, and use the I/O
Properties tool to configure device pins to meet various I/O standards.
•
Section 3.3, Designing a Single-Port ROM memory circuit (VHDL): Instantiate a
single-port RAM with separate data in and data out, a single-port RAM with bidirectional data in and data out, and a single-port ROM memory from the LPM
template library, including a pre-generated ROM file for initialization.
•
Section 3.4, Designing a Synchronous FIFO memory (VHDL): Instantiate a FIFO
RAM memory where the write clock comes from either a divided down input pin or
from an output of an instantiated PLL. Then, compare the device timing results in the
Timing Analyzer.
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3.2
Designing a Dual-Port Memory Circuit (VHDL)
In this design, you’ll complete the following tasks:
3.2.1
•
Instantiate a dual-port RAM memory from the LPM template library.
•
Write the entity and architecture declarations for the VHDL behavioral description of
its arbitration.
•
Use the I/O Properties tool to configure device pins to meet various I/O standards.
•
Target a Delta39K device.
•
Leave all other compiler option settings configured at the default settings.
Design Description
This design describes a dual-port memory circuit which includes arbitration for a
Delta39K device.
3.2.2
Design Solution
Each of the memory's two ports ('porta' and 'portb') should be configured with a 16-bit
data bus and have its own 8-bit address bus, clock signal, write enable, and arbitration
flag. When the write enable for a given port is driven high, the memory contents at the
location stored on the port's address bus will become overwritten with the data stored on
the port's data bus, once a rising edge on the port's clock is detected and the arbitration flag
is not being driven high. In the event that both ports attempt to simultaneously write to the
memory contents stored at the same address, the access should be arbitrated so that only
'porta' is allowed to write. This is achieved by driving the arbitration flag for 'portb' high,
while leaving the arbitration flag for 'porta' low. It is left to the user to respond to the
cancellation of access by 'portb'.
3.2.3
Starting Warp Applications
=> On Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 ->
Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as
galaxy<CR>, from within a shell window.
3.2.4
Creating A New Project
Start Galaxy. Refer to Section 3.2.3 for information on starting applications on your
platform.
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1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown in Figure 3-1 below.
Figure 3-1 New text file and project dialog box.
3
3.
Select VHDL as the Project Type.
4.
Enter the name of the project as dual_port.
5.
Enter the project path as follows.
=> On the PC, enter c:\wtutor\vhdl\dual_port.
=> On UNIX systems, enter <user_home_directory_path>/wtutor/vhdl/dual_port.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device family (SPLD, CPLD, etc.), device subfamily (Delta39K, Quantum38K, Ultra37000, Flash, MAX, etc.), device name and
package type. The user can traverse the device tree. On the left frame of the dialog box are
the Devices available and on the right frame are the Packages available for the device
selected.
Each of the designs in Chapter 3 may be targeted to the Delta39K family. Since the
Quantum38K family is a subset of the Delta39K family of CPLDs, some features
illustrated by each of the designs are not available for the Quantum38K family. The
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design description for each section lists the applicable CPLD family that may be targeted
for that design.
Note – When selecting a device for each design project, do not select
an Quantum38K device unless the design description specifies the
Quantum38K family.
3
Figure 3-2 Select Target Device dialog box with Cypress PLDs in
tree form.
7.
Navigate the tree to CPLD -> Delta39K -> c39k100 in the left frame.
8.
Highlight the CY39100V676-200MBC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
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You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
dual_port.pfg which is now located in the c:\wtutor\vhdl\dual_port directory.
3.2.5
Creating the VHDL File
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
Note – You can also create a new text file by clicking on the "New
Text File" button on the project toolbar (
).
This brings up the Galaxy editor (Figure 3-3) where you enter your
VHDL code.
3
4.
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Select File -> Save and save the file as dual_port.vhd. Saving the file at this point
shows the color coding of keywords in the editor window.
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Figure 3-3 Blank Galaxy editor window.
3.2.6
The dual_port VHDL description
The dual_port VHDL description is written in three parts:
•
a library section which lists the libraries that can be used by the entity and architecture
•
the entity declaration declares the name, direction, and data type of each port of the
component
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•
the architecture describes the behavior of the component
The following pages briefly discuss the contents of each of these sections of the VHDL
description. For a detailed explanation on these VHDL constructs, refer to the text book
VHDL for Programmable Logic included in your software kit.
3.2.6.1
3
Including the Libraries
=> Type these lines at the beginning of the VHDL document:
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.lpmpkg.all;
These lines advise the compiler to link to the IEEE 1164 VHDL library, and the Cypress
LPM module library. These libraries define the various types, modes, and VHDL
constructs used in the VHDL code. The library and use VHDL reserved words
instruct the compiler to include pre-defined libraries in compiling the selected VHDL
code. For details on the std_logic_1164 and std_arith packages, see the VHDL book in the
Warp 6.3 online help.
3.2.6.2
Writing the Entity Declaration
=> Type the following lines into your VHDL text editor:
entity dual_port is port (
porta: inout std_logic_vector(15 downto 0); -- Port A
portb: inout std_logic_vector(15 downto 0); -- Port B
adda: in std_logic_vector(7 downto 0); -- Port A address
bus
addb: in std_logic_vector(7 downto 0); -- Port B address
bus
wena: in std_logic; -- Port A write enable
wenb: in std_logic; -- Port B write enable
clka: in std_logic; -- Port A clock
clkb: in std_logic; -- Port B clock
inva: out std_logic; -- Port A invalid flag (used for
arbitration)
invb: out std_logic -- Port B invalid flag (used for
arbitration)
);
end dual_port;
The entity declaration declares the name, direction, and data type of each port of the
component. The entity declaration declares that entity dual_port has ten external
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interfaces, or ports. It has four input ports of type std_logic, named wena, wenb,
clka, and clkb, respectively. It has two input ports of type std_logic_vector,
named adda and addb, respectively. It has two input/output (inout) ports, of type
std_logic_vector, named porta and portb, respectively. It has two output ports,
of type std_logic, named inva and invb, respectively
3.2.6.3
Writing the Architecture
=> Type the following lines into your VHDL text editor after your entity
declaration:
architecture dual_port_arch of dual_port is
The architecture portion of a VHDL description describes the behavior of the component
and always appears after the entity description. The first line declares an architecture
named arch_dual_port of entity dual_port.
Now, create two signals, 'a_out' and 'b_out', of 16-bit wide std_logic_vector type, to
represent the output data of each port of the instantiated dual-port memory. Also, create a
signal, called 'match', of std_logic type to represent the condition when addresses of both
ports match each other. After the last signal declaration, type in 'begin'. The begin that
follows the signal declaration marks the start of the architecture body. All constant and
signal declarations in the architecture of the VHDL code should precede the begin
statement. The resulting text should be as follows:
signal a_out:std_logic_vector (15 downto 0);
signal b_out:std_logic_vector (15 downto 0);
signal match:std_logic;
begin
Once this has been done, paste in the dual-port memory instantiation by selecting the
'CY_RAM_DP' LPM module from the "Templates" menu located on the toolbar. For
more information about how to instantiate LPM modules, please refer to Chapter 5, LPM
& RTL Modules, in the User’s Guide.
Once pasted, you will need to fill in the appropriate actuals for each of the locals. The
generic map locals should be mapped so that 'lpm_width' is 16 and 'lpm_widthad' is 8.
This configures each memory port to use 16-bit data bus widths and 8-bit address bus
widths, respectively. The port map locals should be mapped so that data_a and data_b are
mapped to porta and portb, respectively. Likewise, 'address_a' and 'address_b' should be
mapped to 'adda' and 'addb', respectively. Outputs 'q_a' and 'q_b' should be mapped to
'a_out' and 'b_out', respectively. The actual 'address_match' should be mapped to 'match'.
The write enables, 'wea' and 'web' should get mapped to 'wena' and wenb', respectively.
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Both the input and output clocks for port a should be mapped to 'clka'. Both the input and
output clocks for port b should be mapped to 'clkb'. The remaining values for each of the
actuals are default values and should not be edited for this exercise. The resulting text
should be as follows:
U1: cy_ram_dp-- Dual-port RAM
generic map(
lpm_width
=> 16,
lpm_widthad
=> 8,
lpm_numwords
=> 0,-- optional
lpm_indata
=> LPM_REGISTERED,-- optional
lpm_address_control
=> LPM_REGISTERED,-- optional
lpm_outdata_a
=> LPM_REGISTERED,-- optional
lpm_outdata_b
=> LPM_REGISTERED,-- optional
lpm_file
=> "",-- optional
lpm_hint
=> speed-- optional
)
port map(
data_a
=>
porta,
data_b
=>
portb,
address_a
=>
adda,
address_b
=>
addb,
q_a
=>
a_out,
q_b
=>
b_out,
addr_matchb
=> match,
wea
=> wena,
web
=> wenb,
inclock_a
=> clka,-- optional
inclock_b
=> clkb,-- optional
outclock_a
=> clka,-- optional
outclock_b
=> clkb,-- optional
outrega_ar
=> '0',-- optional
outregb_ar
=> '0'-- optional
);
3
For a description of this LPM module, please refer to Section 5.2.22 in Chapter 5 of the
User’s Guide.
Create two when else statements that arbitrate that between the two ports when they are
simultaneously attempting to write data to the same address, or when one port is
attempting to read data from an address while the other is attempting to write data to the
same address. Arbitration should result in either 'inva' or 'invb' being driven high to
indicate that data on either 'porta' or 'portb' may be invalid, respectively. The convention
should be as follows:
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•
The output 'inva' should be driven high only when 'match' is high, 'wena' is low , and
'wenb' is high.
•
In all other cases, 'inva' should be driven low.
•
The output 'invb' should be driven high only when 'match' is high and 'wena' is high.
•
In all other cases, 'invb' should be driven low.
The resulting text should be as follows:
inva <= '1'-- porta write access is invalid
when ((match = '1')-- when both port addresses match
and (wena = '0')-- if porta is write disabled
and (wenb = '1'))-- and if portb is write enabled
else '0';-- else porta write access is valid
invb <= '1'-- portb write access is invalid
when ((match = '1')-- when both port addresses match
and (wena = '1'))-- if porta is write enabled
else '0';-- else portb write access is valid
Also, create source code that assigns the outputs of the dual-port, 'a_out' and 'b_out', to the
output pins, 'porta' and 'portb', respectively. The resulting text should be as follows:
porta <= a_out when wena = '1' else (others => 'Z');
portb <= b_out when wenb = '1' else (others => 'Z');
Finally, add end dual_port_arch; to the last line, to denote the end of the
architecture declaration.
=> Select File -> Save.
3.2.7
Selecting Files for Compilation
After the file is created, it needs to be added to the project. Galaxy has a Preferences menu
item under the Edit menu that allows you to set the design file extensions. These
extensions are used to identify VHDL files. For VHDL projects, the default file name
extensions are: .vhd and .vh.
3.2.7.1
To add a VHDL file:
1.
Use the menu item Project -> Add Files.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the dual_port.vhd file and click Add.
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4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
3
Figure 3-4 Dialog box to select files to compile.
3.2.8
Setting the Top-Level File
Once dual_port.vhd has been added into the project, a top level file can be set. Only the
top-level files is actually synthesized, and only one top-level file is allowed in a project.
=> Click on dual_port.vhd.
=> Select Project -> Set Top or click on the Set Top button available on the project
toolbar.
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=> Once the top-level file has been set, the file symbol marker in the hierarchy will
have a tree symbol (Figure 3-5).
Figure 3-5 Galaxy window showing dual_port.vhd as the top-level
design.
3
Note – In order to set the top-level file, you must select the file in the
Source tab in the Project sub-window, as shown in Figure 3-5.
3.2.9
Compiling and Synthesizing a Top-Level File
In the following pages, you will run Warp to produce a .HEX file for a specific target
device, in this case, a CY39100 macrocell CPLD.
3.2.10
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
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3
Figure 3-6 The Compiler Options dialog box for Delta39K devices.
3.2.10.1
Setting Unused Outputs
All unused output pins that have unused I/Os are hardwired to high 'Z', leaving all unused
I/O pins to be three-stated. The ability to choose '1' or '0' will be incorporated in a future
release.
3.2.10.2
Choosing Tech Mapping Options
=> Under the Logic to Memory Mapping options in the Synthesis tab, one of three
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options is available: Disabled, Area, and Speed.
Warp can optionally pack logic into memory and optimize for either area or speed. There
are a few other useful options in the Tech Mapping options, which are explained in the
Galaxy online help, accessible from the Galaxy Help menu.
3.2.10.3
Choosing a Timing Model
On the PC platforms, Warp includes the Active-HDL Sim timing simulator. This section
applies only if you want to simulate your design using Active-HDL Sim. You can verify
the synthesized design using Active-HDL Sim by creating the Active-HDL Sim timing
model of the design using Warp.
The dual_port.vhd file should be compiled with the Active-HDL Sim timing model before
using Active-HDL Sim.
=> Click on the Timing Model drop-down menu in the Simulation area.
=> Select Active-HDL Sim.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
3.2.11
Compiling and Synthesizing the File
=> In your Galaxy window, select Compile -> Project to begin compilation click
the Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a CY39100
and prints messages to keep you appraised of its progress in the results
sub-window. The Compile - > Project option automatically recompiles
only those files which have been modified since the last compilation.
This operation generates two files of particular interest:
•
dual_port.hex: is used to program a CY39100 device.
•
dual_port.rpt: contains pinout and timing information, along with other information
about the final synthesized design. You can see the .rpt file and the output files created
by Warp by clicking on the output view tab in the Project sub-window (Figure 3-7).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
Figure 3-7 View of the output files in the Project sub-window.
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For more information on what is contained in a report file, refer to the Report File book
located in the Warp 6.3 online help.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
Go to the VHDL editor window. The cursor should be positioned on the line that caused
the error. Use the Next and Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
dual_port.vhd file is entered exactly as shown earlier in this chapter -or, copy the file from the <warp path>\examples\wtutor\vhdl directory - and then run Warp again.
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3.2.12
Modifying the I/O Standards
After successfully compiling the tutorial, you can modify the I/O standards within Warp.
=> Select Project -> Configure I/O Standards.
3
Figure 3-8 Default I/O Properties tab with I/O Type selected.
=> Select the LVTTL 12mA from the I/O Type drop down menu, as shown in Figure
3-8.
=> Click on Set Defaults.
=> Select the I/O Bank Properties tab.
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Figure 3-9 I/O Bank Properties with Voltage specified.
=> In Bank 1, select the CUSTOM I/O type.
=> Assign a VCC of 2.5V and a Vref of 1.25V, to allow it to support the SSTL2
Class I I/O standard, as shown in Figure 3-9.
=> Select the I/O Signal Properties tab.
Note – The I/O Signal Properties tab (shown in Figure 3-10) will not
be visible unless the tutorial is successfully compiled.
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3
Figure 3-10 I/O Signal Properties tab with I/O Type selected.
=> Click on signal name adda(0) from the signal name list, then press the Shift
key and select adda(7). All the signals between adda(0) and adda(7)
should be selected.
=> Select the I/O Standard SSTL2 Class I by selecting SSTL2 I from the I/O Type
drop-down box, shown in Figure 3-10.
=> Click on the Update Signals button to update the design control file.
=> Exit the I/O Standards dialog by clicking OK.
=> View the design control file by selecting View -> Control File. Note that even
though the control file has been modified, the changes have not taken effect since
the design has not been recompiled.
=> Compile the design to complete changing the I/O Standards of the design.
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3.2.13
Final code for dual_port.vhd
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.lpmpkg.all;
entity dual_port is port (
porta: inout std_logic_vector
portb: inout std_logic_vector
adda: in std_logic_vector ( 7
address bus
addb: in std_logic_vector ( 7
address bus
wena: in std_logic; -- Port A
wenb: in std_logic; -- Port B
clka: in std_logic; -- Port A
clkb: in std_logic; -- Port B
inva: outstd_logic; -- Port A
arbitration)
invb: outstd_logic -- Port B
arbitration)
);
end dual_port;
3
(15 downto 0);-- Port A
(15 downto 0);-- Port B
downto 0); -- Port A
downto 0); -- Port B
write enable
write enable
clock
clock
invalid flag (used for
invalid flag (used for
architecture dual_port_arch of dual_port is
signal a_out:std_logic_vector (15 downto 0);
signal b_out:std_logic_vector (15 downto 0);
signal match:std_logic;
begin
U1: cy_ram_dp-- Dual-port RAM
generic map(
lpm_width
=> 16,
lpm_widthad
=> 8,
lpm_numwords
=> 0,-- optional
lpm_indata
=> LPM_REGISTERED,-lpm_address_control
=> LPM_REGISTERED,-lpm_outdata_a
=> LPM_REGISTERED,-lpm_outdata_b
=> LPM_REGISTERED,-lpm_file
=> "",-- optional
lpm_hint
=> speed-- optional
)
port map(
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optional
optional
optional
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data_a
data_b
address_a
address_b
q_a
q_b
addr_matchb
wea
web
inclock_a
inclock_b
outclock_a
outclock_b
outrega_ar
outregb_ar
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
porta,
portb,
adda,
addb,
a_out,
b_out,
match,
wena,
wenb,
clka,-- optional
clkb,-- optional
clka,-- optional
clkb,-- optional
'0',-- optional
'0'-- optional
);
inva <= '1'-- Port A becomes invalid
when ((match = '1')-- when both port addresses match
and (wena = '0')-- if Port A is write disabled
and (wenb = '1'))-- and if Port B is write enabled
else '0';
-- else Port A remains valid
invb <= '1
'-- Port B becomes invalid
when ((match = '1')-- when both port addresses match
and (wena = '1'))-- if Port A is write enabled
else '0';
-- else Port B becomes valid
porta <= a_out when wena = '1' else (others => 'Z');
portb <= b_out when wenb = '1' else (others => 'Z');
end dual_port_arch;
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3.3
Designing a Single-Port ROM memory circuit (VHDL)
3.3.1
Design Description
This design describes a single-port ROM memory circuit, which is initialized with a ROM
lookup table. The source of the ROM lookup table is an Intel Hex format file containing
the actual ROM data. All reads to the memory table are asynchronous and operate without
enables. The lookup function will describe the following table.
Table 3-3 ROM Lookup Table
Address Bus Bits
3
136
Data Bus Bits
a
b
c
d
x
y
z
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
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Table 3-3 ROM Lookup Table
Address Bus Bits
1
3.3.2
1
1
Data Bus Bits
1
1
1
1
Starting Warp Applications
=> For Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 -> Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as galaxy<CR>,
from within a shell window.
3.3.3
Creating the Design Project
Start Galaxy. Refer to Section 3.3.2, Starting Warp Applications for information on
starting applications on your platform.
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown below in Figure 3-11.
3
Figure 3-11 New File and Project type dialog box.
The Project Information wizard
3.
Select VHDL as the Project Type.
4.
Enter the name of the project as single_port.
5.
Enter the project path as follows.
On the PC, enter c:\wtutor\vhdl\single_port.
On UNIX systems, enter <user_home_directory_path>/wtutor/vhdl/single_port.
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6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Closing the Project Information wizard creates the project with no files or devices
selected. You will be able to add files and select devices from the Project menu later. The
Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form which
shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device sub-family
(Delta39K, Quantum38K, Ultra37000, Flash370I, etc.), device name and package type.
The user can traverse the device tree. On the left side of the dialog box are the Devices
available and on the right side are the Packages available for the device selected.
3
Figure 3-12 Select Target Device dialog box with Cypress PLDs in
tree form.
Each of the designs in Chapter 3 may be targeted to the Delta39K family. Since the
Quantum38K family is a subset of the Delta39K family of CPLDs, some features
illustrated by each of the designs are not available for the Quantum38K family. The
design description for each section lists the applicable CPLD family that may be targeted
for that design.
138
7.
Navigate the tree to CPLD -> Delta39K -> c39k100.
8.
Highlight the CY39100V676-200MBC package on the right side.
9.
Click Finish to create the project.
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10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
single_port.pfg which is now located in the c:\wtutor\vhdl\single_port directory.
3.3.4
Creating the VHDL File
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
This brings up the Galaxy editor (Figure 3-13) where you enter your VHDL code.
Note – You can also create a new text file by clicking on the "New Text
File" button on the project toolbar (
).
4.
Select File -> Save and save the file as single_port.vhd. Saving the file at this
point shows the color coding of keywords in the editor window.
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3
Figure 3-13 Blank Galaxy editor window.
3.3.5
The single_port VHDL description
The single_port VHDL description is written in three parts:
•
a library section which lists the libraries that can be used by the entity and architecture
•
an entity section which declares the name, direction, and data type of each port in the
design
•
an architecture section declaring the behavior of the design
For a detailed explanation of these VHDL constructs in general, please refer to Chapter 1,
VHDL, in the HDL Reference Manual.
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3.3.5.1
Including the Libraries
=> Type the following lines into your VHDL text editor:
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.lpmpkg.all;
3.3.5.2
Writing the Entity
=> Type the following lines into your VHDL text editor:
entity single_port is port (
a, b, c, d:in std_logic; -- Single Port Address bus bits
x, y, z: out
std_logic -- Single Port Data bus bits
);
end single_port;
3.3.5.3
Writing the Architecture
3
=> Type the following lines into your VHDL text editor after your entity declaration:
architecture single_port_arch OF single_port is
The architecture portion of a VHDL description describes the behavior of the component
and always appears after the entity description. The first line declares an architecture
named arch_single_port of entity single_port.
Now, create a 4-bit signal named 'address', of std_logic_vector type, to represent the
address of the data to be retrieved from the single port ROM table. Also, create a 3-bit
signal named 'result', of std_logic_vector type, to represent the output data of the same.
After the last signal declaration, type in 'begin'. The begin that follows the signal
declaration marks the start of the architecture body. All constant and signal declarations in
the architecture of the VHDL code should precede the begin statement. The resulting text
should be as follows:
signal address:std_logic_vector ( 3 downto 0);
signal result:std_logic_vector ( 2 downto 0);
begin
Once this has been done, paste in the single-port ROM instantiation by selecting the
'LPM_ROM' LPM module from the "Templates" menu located on the toolbar. For more
information about how to instantiate LPM modules, please refer to Chapter 5, LPM & RTL
Modules, in the User’s Guide.
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Once pasted, you will need to fill in the appropriate actuals for each of the locals. The
generic map locals should be mapped so that 'lpm_width' is 3 and 'lpm_widthad' is 4. This
configures the ROM table to use a 3-bit data bus and a 4-bit address bus, respectively. The
generic map locals should be mapped so that 'lpm_address_control' is
`LPM_UNREGISTERED and 'lpm_outdata' is `LPM_UNREGISTERED for
asynchronous operation. A ROM file named 'single_port.rom' using Intel Hex format
must be created and have 'lpm_file' mapped to it.
The port map locals should be mapped so that 'address' and 'q' are mapped to 'address' and
'result', respectively. The remaining values for each of the actuals are default values and
should not be edited for this exercise. The resulting instantiation text should be as
follows:
U1: mrom-- Read-only Memory
generic map(
lpm_width
=> 3,
lpm_widthad
=> 4,
lpm_numwords
=> 0,-- optional
lpm_address_control
=> LPM_UNREGISTERED,-- optional
lpm_outdata
=> LPM_UNREGISTERED,-- optional
lpm_file
=> "single_port.rom",-optional
lpm_hint
=> speed-- optional
)
port map(
address
=> address,
q
=> result,
inclock
=> '0',-- optional
outclock
=> '0', -- optional
memenab
=> '1', -- optional
outreg_ar
=> '0'-- optional
);
For a description of this LPM module, please refer to section Section 5.2.20 in Chapter 5
of the User’s Guide..
3
•
Create two assign statements that connect the address bits 'a', 'b', 'c', and 'd' to 'address'
and 'result' to data bus bits 'x', 'y', 'z'.
The resulting text should be as follows:
address
<= a & b & c & d;
x
<= result(2);
y
<= result(1);
z
<= result(0);
end single_port_arch;
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A text file named 'single_port.rom' should be created and added to the project as a ROM
file. This file should contain the following text:
:080000000407060205040301D8
:080008000103070006070007D1
:00000001FF
This text represents three records that make up a single lookup table and can be separated
into 6 fields, each of which is described in the table below.
Table 3-4 Lookup Table
RECORD
MARK ‘:’
RECLEN
LOAD
OFFSET
RECTYPE
1-byte
1-byte
2-bytes
1-byte
n-bytes
1-byte
:
08
00 00
00
04 07 06
02 05 04
03 01
D8
:
08
00 08
00
01 03 07
00 06 07
00 07
D1
:
00
00 00
01
DATA
CHECKSUM
3
FF
All records start with a ':'. Every 2 ASCII characters represent 1 byte of the record.
RECLEN represents the length in bytes of the data portion of the record. LOAD OFFSET
is a two-byte starting load offset of the data bytes, and determines where in the memory
that the record data will be placed. RECTYPE represents the type of record, where '00' and
'01' means record contains data or record is at the end of the file, respectively. The DATA
field represents an n-byte entry of data bytes. For our example both data records represent
8 bytes of data. Each byte in this field from left to right maps directly a single ROM
address. Therefore, '07' in the second record, maps to the contents of the third address
following offset '0008', which is at address '1010'. The data contents in this example are
composed of 3-bits, not 8. However, each must be represented in the record as one byte
(in hex). This address can be used to retrieve data from a lookup table. The lookup table,
below, represents the ROM file just explained. The checksum is just the two's
complement of the 8-bit addition of the bytes that are in RECLEN, LOAD OFFSET,
RECTYPE, and DATA.
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You can add comment lines to your VHDL code by placing "--" before the comment text.
All of the characters on a line that appear after the comment characters are ignored and
considered to be part of the commented text.
=> Select File -> Save.
3.3.6
Adding the File to the Project
After the design file is created, it must be added to the project, before it can be compiled.
Galaxy has a Preferences menu item under the Edit menu that allows you to set the design
file extension. These extensions are used to identify VHDL files. For VHDL projects, the
default file name extensions are: .vhd and .vh.
3.3.6.1
3
To add a VHDL file:
1.
Use the menu item Project -> Add Files. This accesses a dialog box (Figure 3-14)
where one or more VHDL files can be selected. Files are added in the order they
are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the single_port.vhd file and click OK.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
Figure 3-14 Dialog box to select files to compile
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3.3.6.2
3.3.7
To add a ROM file:
1.
Use the menu item Project -> Add ROM Files. This accesses a dialog box where
one or more ROM files can be selected. Files are added in the order they are
selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the single_port.rom file and click OK.
Setting the File as Top-Level
Once single_port.vhd has been added into the project, it can be set to be the top level file.
When projects contain multiple files, only the top-level file is actually synthesized, and
only one top-level file is allowed in a project.
=> Click on single_port.vhd.
=> Select Project -> Set Top or click on the Set Top button available on the project toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will have a
hierarchy symbol (
).
3.3.8
Configuring Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
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3
Figure 3-15 Compiler Options dialog box with Synthesis tab
chosen.
3.3.8.1
Choosing Tech Mapping Options
=> Under Logic to Memory Mapping in the Synthesis tab, one of the following options
can be selected: Disabled, Area, Speed.
Warp can optionally pack logic into memory and optimize for either area or speed. For an
explanation of the other compiler options please refer to the Galaxy online help, accessible
from the Galaxy Help menu.
3.3.8.2
Choosing Messaging Options
=> Under Messaging in the Messaging tab, select the Detailed Report File option.
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Figure 3-16 The Compiler Options dialog box with the Messaging
tab chosen.
Warp will not print signal equations into the Delta39K or Quantum38K report file, unless
this setting is selected, as this information is available from the Architecture Explorer.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
3.3.9
Design Compilation and Synthesis
=> In your Galaxy window, select Compile -> Project to begin compilation or click the
Compile Project button on the project toolbar. Warp starts the compilation and synthesis
of the design into a CY39100 and prints messages to keep you appraised of its progress in
the results sub-window. The Compile - > Project option automatically recompiles only
those files which have been modified since the last compilation.
This operation generates two files of particular interest:
•
single_port.hex: is used to program a CY39100 device.
•
single_port.rpt: contains pinout and timing information, along with other information
about the final synthesized design. You can see the .rpt file and the output files created
by Warp by clicking on the output view tab in the Project sub-window (Figure 3-17).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
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3
Figure 3-17 View of the output files in the Project sub-window.
For more information on what is contained in a report file, refer to Chapter 6,
Understanding Delta39K & PSI in the User’s Guide.
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
=> Go to the VHDL editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
single_port.vhd file is entered exactly as shown earlier in this chapter -or, copy the file from the <warp path>\examples\wtutor\vhdl directory - and then run Warp again.
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3.3.10
The final code for single_port.vhd
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.lpmpkg.all;
entity single_port is port (
a, b, c, d:in std_logic; -- Single Port Address bus bits
x, y, z: out
std_logic -- Single Port Data bus bits
);
end single_port;
architecture single_port_arch OF single_port IS
signal address : std_logic_vector(3 downto 0);
signal result : std_logic_vector(2 downto 0);
begin
U1: mrom-- Read-only Memory
generic map(
lpm_width
=> 3,
lpm_widthad
=> 4,
lpm_numwords
=> 0,-- optional
lpm_address_control
=> LPM_UNREGISTERED,-- optional
lpm_outdata
=> LPM_UNREGISTERED,-- optional
lpm_file
=> "single_port.rom",-optional
lpm_hint
=> speed-- optional
)
port map(
address
=> address,
q
=> result,
inclock
=> '0',-- optional
outclock
=> '0', -- optional
memenab
=> '1', -- optional
outreg_ar
=> '0'-- optional
);
address <= a & b & c & d;
x
<= result(2);
y
<= result(1);
z
<= result(0);
end arch_single_port;
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3.4
3.4.1
Designing a Synchronous FIFO memory (VHDL)
•
Load Warp R6.3, create a VHDL project targeting a Delta39K device, add a blank
VHDL file to the project, and set it as top.
•
Set the Logic to Memory Mapping feature to disabled.
•
Leave all other compiler option settings configured at the default settings.
Design Description
This design describes a synchronous FIFO memory that performs bus matching between a
32-bit input bus and an 8-bit output bus.
3.4.2
3
Design Description
The design should have a separate clock for writes to and reads from the FIFO. The write
clock is generated from a pin input, while the read clock is generated by an on-board
Phase-Locked-Loop (PLL). A third clock, running at 4x the speed of the read clock,
synchronizes the reads from each of the four bytes of the 32-bit FIFO output.
3.4.3
Starting Warp Applications
=> For Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 -> Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as galaxy<CR>,
from within a shell window.
3.4.4
Creating the Design Project
Start Galaxy. Refer to Section 2.2.2, Starting Warp Applications for information on
starting applications on your platform.
150
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown below in Figure 3-18.
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Figure 3-18 New text file and project type dialog box.
3.
Select VHDL as the Project Type.
4.
Enter the name of the project as pll_clocked_fifo.
5.
Enter the project path as follows.
On the PC, enter c:\wtutor\vhdl\pll_clocked_fifo.
On UNIX systems, enter <user_home_directory_path>/wtutor/vhdl/pll_clocked_fifo.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device subfamily (Delta39K, Quantum38K, Ultra37000, Flash370I, etc.), device name and package
type. The user can traverse the device tree. On the left side of the dialog box are the
Devices available and on the right side are the Packages available for the device selected.
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Figure 3-19 Select Target Device dialog box with Cypress PLDs in
tree form.
3
Each of the designs in Chapter 3 may be targeted to the Delta39K family. Since the
Quantum38K family is a subset of the Delta39K family of CPLDs, some features
illustrated by each of the designs are not available for the Quantum38K family. The
design description for each section lists the applicable CPLD family that may be targeted
for that design.
7.
Navigate the tree to CPLD -> Delta39K -> c39k100 in the left frame.
8.
Highlight the CY39100V676-200MBC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
pll_clocked_fifo.pfg which is now located in the c:\wtutor\vhdl\pll_clocked_fifo
directory.
3.4.5
152
Creating the VHDL File
1.
Select File -> New.
2.
Select "Text File".
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3.
Click OK.
Note – You can also create a new text file by clicking on the "New Text
File" button on the project toolbar.
4.
Select File -> Save and save the file as pll_clocked_fifo.vhd. Saving the file at this
point shows the color coding of keywords in the editor window.
This brings up the Galaxy editor (Figure 3-20) where you enter your VHDL code.
3
Figure 3-20 Blank Galaxy editor window.
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3.4.6
The pll_clocked_fifo VHDL description
Each design's VHDL description is written in three parts:
•
a library section which lists the libraries that can be used by the entity and architecture
•
an entity section which declares the name, direction, and data type of each port in the
design
•
an architecture section declaring the behavior of the design
For a detailed explanation of these VHDL constructs in general, please refer to the text
book VHDL for Programmable Logic included in your software kit.
3.4.6.1
Including the Libraries
=> Insert these lines before the declaration for module pll_clocked_fifo:
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.lpmpkg.all;
use cypress.std_arith.all;
use cypress.rtlpkg.all;
3
These lines advise the compiler to link to the Cypress LPM module library. These libraries
define the various types, modes, and VHDL constructs used in the VHDL code. For
details on the VHDL language, see the VHDL book in the Warp 6.3 online help.
3.4.6.2
Writing the Entity
=> Type the following lines into your VHDL text editor:
entity pll_clocked_fifo is port (
-- write clock and faster clock
writeclk, byteclk:in std_logic;
-- read and write enables
read, write:in std_logic;
--FIFO output byte
byte: out std_logic_vector ( 7 downto 0);
-- data to write
indata: in std_logic_vector (31 downto 0);
-- Flag for empty / full
empty_full:buffer std_logic;
-- Offchip clock
offclk: buffer std_logic;
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-- Flag for half full
half: out std_logic;
-- Reset for FIFO
fifo_reset: in std_logic;
-- PLL lock detection output
lock: out std_logic
);
end pll_clocked_fifo;
The entity declaration declares the name, direction, and data type of each port of the
component. The entity pll_clocked_fifo has ten external interfaces, or ports. It has four
input ports named writeclk, byteclk, read, and write, respectively. It has one 32-bit input
port indata. It has four output ports named empty_full, half, lock , and offclk, respectively.
It has one 8-bit output named byte.
3.4.6.3
Writing the Architecture
Now, create one 32-bit signal named 'outdata', one 2-bit signal named 'selection' for
selecting a byte of the FIFO's output, and one single-bit signal named 'int_byteclk' to
represent the output data of the instantiated FIFO memory and phase adjusted 'byteclk',
respectively. The resulting text should be as follows:
architecture pll_clocked_fifo_arch of pll_clocked_fifo is
signal readclk:std_logic;-- read clock
signal int_byteclk: std_logic;-- phase adjusted byteclk
signal t_empty_full: std_logic;-- temporary empty_full flag
signal selection: std_logic_vector ( 1 downto 0);-- byte
selector
signal outdata:std_logic_vector (31 downto 0);-- FIFO output
begin
Once this has been done, paste in the FIFO memory instantiation by selecting the
'CY_Fifo' LPM module from the "Templates" menu located on the toolbar. For more
information about how to instantiate LPM modules, please refer to Chapter 5, LPM & RTL
Modules in the User’s Guide.
Once pasted, you will need to fill in the appropriate values for each of the generics and
ports. The generics should be mapped so that 'lpm_width' is 32 and 'lpm_numwords' is
512. This configures the FIFO to use 32-bit data bus widths and to store up to 512 fourbyte words, respectively. The remaining values for each of the generics will not be used
for this exercise, and these lines should be deleted. The ports should be mapped so that
'data' and 'q' are mapped to 'indata' and 'outdata', respectively. Likewise, 'enr' and 'enw'
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should be mapped to 'read' and 'write', respectively. Outputs 'readclock' and 'writeclock'
should be mapped to 'readclk' and 'writeclk', respectively. Flags 'efb' and 'hfb' should be
mapped to 'empty_full' and 'half', respectively. Port 'mrb' should be mapped to the value
of one so that it is permanently disabled. Ports 'outreg_ar' and 'pafeb' will not be used for
this exercise, and these lines may be deleted, provided that there are no characters such as
a ','or ';' between the last generic listed and the ');' that closes the generic map. The
resulting text should be as follows:
U1: cy_fifo-- Clocked FIFO
generic map(
lpm_width
=> 32,
lpm_numwords
=> 512,
lpm_pafe_length
=> 0, -- optional
lpm_hint
=> speed-- optional
)
port map(
data
=> indata,
q
=> outdata,
enr
=> read,
enw
=> write,
readclock
=> readclk,
writeclock
=> writeclk,
mrb
=> fifo_reset,
efb
=> t_empty_full, -- optional
hfb
=> half
);
3
For a description of this LPM module, please refer to Section 5.2.21 in Chapter 5 of the
User’s Guide.
Once this has been done, paste in the PLL instantiation by selecting the 'CY_C39KPLL'
LPM module from the "Templates" menu located on the toolbar. For more information
about how to instantiate LPM modules, please refer to Chapter 5, LPM & RTL Modules in
the User’s Guide.
Once pasted, you will need to fill in the appropriate values for each of the ports and
generics. The generics should be mapped so that 'multiply' is 1, 'gclk2_divide'is 4, and
'gclk3_phase' is 0. This configures the PLL to bypass multiplication of the incoming
clock, generate a single clock that is one fourth as fastas the incoming clock, and generate
a single clock at the same rate as the incomingclock without PLL phase adjustment,
respectively. The remaining values for each of the parameters are default values and may
be deleted for this exercise. The ports should be mapped so that 'pll_in' is mapped to
'byteclk'. Likewise, 'lock_detect' should be mapped to 'lock', respectively. Outputs 'gclk2'
and 'gclk3' should be mapped to 'readclk' and 'int_byteclk', respectively. Generics
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'gclk0_phase', 'gclk0_divide', 'gclk1_phase', 'gclk1_divide', and 'feedback' will not be used
for this exercise, and these lines may be deleted. Ports 'ext_fdbk', 'gclk0', and 'gclk1' will
not be used for this exercise, and these lines may be deleted. Be sure to rename the label of
this instantiation to something other than "U1". A suggested name is "U2". The resulting
text should be as follows:
U2: cy_c39kpll
generic map(
multiply
gclk2_phase
gclk2_divide
gclk3_phase
gclk3_divide
input_freq
)
port map (
pll_in
lock_detect
gclk2
gclk3
);
=>
=>
=>
=>
=>
=>
=>
=>
=>
=> 1,-- optional
0,-- optional
4,-- optional
0,-- optional
1,-- optional
133000000
byteclk,
lock,-- optional
readclk,-- optional
int_byteclk-- optional
For a description of this LPM module, please refer to Section 5.3.19 in Chapter 5 of the
User’s Guide.
Create a process statement that is activated upon each rising edge of 'in_byteclk' and uses
a case statement to select one byte of the 'outdata' word that is read for output. The
convention should be as follows:
•
If 'selection' equals 2'b00, then 'byte' is assigned the most significant byte of outdata.
•
If 'selection' equals 2'b01, then 'byte' is assigned the second most significant byte of
outdata.
•
If 'selection' equals 2'b10, then 'byte' is assigned the second least significant byte of
outdata.
•
If 'selection' equals anything else, then 'byte' is assigned the least significant byte of
outdata.
In addition, the always block should increment 'selection' and toggle 'offclk'.
The resulting text should be as follows:
mux:process (int_byteclk)
begin
if (int_byteclk'event and int_byteclk = '1') then
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if (empty_full = '0') then
-- if FIFO is empty
case selection is
-- and if selection equals
when "00" => byte
-- 0, then byte is MSB
<= outdata(31 downto 24);
when "01" => byte
-- 1, then byte is 2nd
byte
<= outdata(23 downto 16);
when "10" => byte
-- 2, then byte is 3rd
byte
<= outdata(15 downto
when others => byte
8);
-- other, then byte is
LSB
<= outdata(7 downto 0);
end case;
selection <= selection + 1;-- increment selection
offclk<= not(offclk);-- Off-chip clock generated at
int_byteclk
end if;
end if;
end process;
empty_full <= t_empty_full;
end pll_clocked_fifo_arch;
3
=> Select File -> Save.
3.4.7
Adding the File to the Project
After the design file is created, it must be added to the project, before it can be compiled.
Galaxy has a Preferences menu item under the Edit menu that allows you to set the design
file extension. These extensions are used to identify VHDL files. For VHDL projects, the
default file name extensions are: .vhd and .vh.
To add a VHDL file:
1.
Use the menu item Project -> Add Files. This accesses a dialog box (Figure 2-5)
where one or more VHDL files can be selected. Files are added in the order they
are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the pll_clocked_fifo.vhd file and click Add.
4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
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to navigate to the project directory.
Figure 3-21 Dialog box to select files to compile
3.4.7.1
Setting the File as Top-Level
Once pll_clocked_fifo.vhd has been added into the project, it can be set to be the top level
file. When projects contain multiple files, only the top-level file is actually synthesized,
and only one top-level file is allowed in a project.
=> Click on pll_clocked_fifo.vhd.
=> Select Project -> Set Top or click on the Set Top button available on the project toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will have a
hierarchy symbol (
).
3.4.8
Configuring Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
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Options and select the Synthesis tab.
Figure 3-22 Compiler Options dialog box Synthesis tab.
3
=> Under Logic to Memory Mapping in the Synthesis tab, one of the following options
can be selected: Disabled, Area, Speed.
Warp can optionally pack logic into memory and optimize for either area or speed. For an
explanation of the other compiler options please refer to the Galaxy online help, accessible
from the Galaxy Help menu.
=> Under Messaging in the Messaging tab, select the Detailed Report File option.
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Figure 3-23 Compiler Options dialog box Messaging tab.
Warp will not print signal equations into the Delta39K or Quantum38K report file, unless
this setting is selected, as this information is available from the Architecture Explorer.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
3.4.9
Design Compilation and Synthesis
=> In your Galaxy window, select Compile -> Project to begin compilation or click the
Compile Project button on the project toolbar. Warp starts the compilation and synthesis
of the design into a CY39100 and prints messages to keep you appraised of its progress in
the results sub-window. The Compile - > Project option automatically recompiles only
those files which have been modified since the last compilation.
This operation generates two files of particular interest:
•
pll_clocked_fifo.hex: is used to program a CY39100 device.
•
pll_clocked_fifo.rpt: contains pinout and timing information, along with other
information about the final synthesized design. You can see the .rpt file and the output
files created by Warp by clicking on the output view tab in the Project sub-window,
shown in Figure 3-24. Different sections of the report file can be accessed by clicking
on the plus sign and selecting the available sections.
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For more information on what is contained in a report file, refer to Chapter 6,
Understanding Delta39K & PSI in the User’s Guide.
3
Figure 3-24 View of the output files in the Project sub-window.
Note – If compilation errors occur, make sure the text of your
pll_clocked_fifo.vhd file is entered exactly as shown earlier in this
chapter -- or, copy the file from the <warp path>\examples\wtutor\vhdl
directory -- and then run Warp again.
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
=> Go to the VHDL editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
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3.4.10
The final code for pll_clocked_fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.lpmpkg.all;
use cypress.std_arith.all;
use cypress.rtlpkg.all;
entity pll_clocked_fifo is port (
writeclk, byteclk:in std_logic; -- write clock and faster
clock
read, write:in std_logic; -- read and write enables
byte: out std_logic_vector ( 7 downto 0);--FIFO output
byte
indata: in
std_logic_vector (31 downto 0); -- data to
write
empty_full:buffer std_logic; -- Flag for empty / full
offclk:
buffer std_logic; -- Offchip clock
half:
out std_logic; -- Flag for half full
fifo_reset: in std_logic; -- Reset for FIFO
lock:
out std_logic -- PLL lock detection output
);
end pll_clocked_fifo;
architecture pll_clocked_fifo_arch of pll_clocked_fifo is
signal readclk:std_logic;-- read clock
signal int_byteclk: std_logic;-- phase adjusted byteclk
signal t_empty_full: std_logic;-- temporary empty_full flag
signal selection: std_logic_vector ( 1 downto 0);-- byte
selector
signal outdata:std_logic_vector (31 downto 0);-- FIFO output
begin
U1: cy_fifo-- Clocked FIFO
generic map(
lpm_width
=>
lpm_numwords
=>
lpm_pafe_length
=>
lpm_hint
=>
)
port map(
data
=> indata,
q
=> outdata,
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32,
512,
0,-- optional
speed-- optional
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enr
enw
readclock
writeclock
mrb
efb
hfb
U2: cy_c39kpll
generic map(
multiply
gclk2_phase
gclk2_divide
gclk3_phase
gclk3_divide
input_freq
=>
=>
=>
=>
=>
=>
=>
read,
write,
readclk,
writeclk,
'1',
t_empty_full,-- optional
half
=>
=>
=>
=>
=>
=>
1,-- optional
0,-- optional
4,-- optional
0,-- optional
1,-- optional
133000000
=>
=>
=>
=>
byteclk,
lock,-- optional
readclk,-- optional
int_byteclk -- optional
)
port map (
pll_in
lock_detect
gclk2
gclk3
);
3
mux:process (int_byteclk)
begin
if (int_byteclk'event and int_byteclk = '1') then
if (empty_full = '0') then-- if FIFO is empty
case selection is
-- and if selection equals
when "00" => byte -- 0, then byte is MSB
<= outdata(31 downto 24);
when "01" => byte -- 1, then byte is 2nd byte
<= outdata(23 downto 16);
when "10" => byte -- 2, then byte is 3rd byte
<= outdata(15 downto 8);
when others => byte -- other, then byte is LSB
<= outdata( 7 downto 0);
end case;
selection <= selection + 1;-- increment selection
offclk<= not(offclk);-- Off-chip clock generated at
int_byteclk
end if;
end if;
end process;
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empty_full <= t_empty_full;-- assign empty_full output
end pll_clocked_fifo_arch;
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Delta39K and Quantum38K Tutorials (Verilog)
This is a series of step-by-step examples illustrating the new tools added to Warp in the
transition from Warp2 Release 5.x to Warp Release 6.3 and utilizing the features available
in the new Delta39K and Quantum38K families of CPLDs.
•
Section 3.5, Designing a Dual Port Memory (Verilog): Instantiate a dual-port RAM
memory from the LPM template library, and write the module declarations for the
Verilog behavioral description of its arbitration.
•
Section 3.6, Designing a single-port ROM memory circuit (Verilog): Instantiate a
single-port ROM memory from the LPM template library, and generate a ROM file for
initialization.
•
Section 3.7, Designing a synchronous FIFO memory (Verilog): Instantiate a FIFO
RAM memory where the write clock comes from either a divided down input pin or
from an output of an instantiated PLL. Then, compare the device timing results in the
Timing Analyzer.
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3.5
Designing a Dual Port Memory (Verilog)
In this section, you’ll do the following tasks:
3.5.1
•
Instantiate a dual-port RAM memory from the LPM template library
•
Write the module declarations for the Verilog behavioral description of its arbitration
Design Description
This design describes a dual-port memory circuit which includes arbitration for a
Delta39K device.
3.5.2
Design Solution
Each of the memory's two ports, Port A and Port B, should be configured with a 16-bit
data bus and have its own 8-bit address bus, clock signal, write enable, and arbitration
flag. When the write enable for a given port is driven high, the memory contents at the
location stored on the port's address bus will become overwritten with the data stored on
the port's data bus, once a rising edge on the port's clock is detected and the arbitration flag
is not being driven high. In the event that both ports attempt to simultaneously write to the
memory contents stored at the same address, the access should be arbitrated so that only
port B data is flagged as invalid. This is achieved by driving the arbitration flag for Port B
high, while leaving the arbitration flag for Port A low. The reverse should occur when
Port A is attempting to read while Port B is writing. It is left to the user to respond to the
flags that are generated.
3.5.3
Starting Warp Applications
=> For Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 -> Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as galaxy<CR>,
from within a shell window.
3.5.4
Creating the Design Project
Start Galaxy. Refer to Section 3.5.3, Starting Warp Applications for information on
starting applications on your platform.
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown below in Figure 3-25.
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Figure 3-25 New file and project dialog box.
3.
Select Verilog as the Project Type.
4.
Enter the name of the project as dual_port.
5.
Enter the project path as follows.
=> On the PC, enter c:\wtutor\vlog\dual_port.
3
=> On UNIX systems, enter <user_home_directory_path>/wtutor/vlog/dual_port.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of Verilog files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device subfamily (Delta39K, Quantum38K, Ultra37000, Flash370I, etc.), device name and package
type. The user can traverse the device tree. On the left side of the dialog box are the
Devices available and on the right side are the Packages available for the device selected.
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3
Figure 3-26 Select Target Device dialog box with Cypress PLDs in
tree form.
Each of the designs in Chapter 3 may be targeted to the Delta39K family. Since the
Quantum38K family is a subset of the Delta39K family of CPLDs, some features
illustrated by each of the designs are not available for the Quantum38K family. The
design description for each section lists the applicable CPLD family that may be targeted
for that design.
7.
Navigate the tree to CPLD -> Delta39K -> c39k100 in the left frame.
8.
Highlight the CY39100V676-200MBC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
dual_port.pfg which is now located in the c:\wtutor\vlog\dual_port directory.
3.5.5
Creating the Verilog File
1.
Select File -> New.
2.
Select "Text File".
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3.
Click OK.
Note - You can also create a new text file by clicking on the "New Text File" button on the
project toolbar (
). This brings up the Galaxy editor (Figure 3-27) where you enter your
Verilog code.
3
Figure 3-27 Blank Galaxy editor window.
Each design's Verilog description is described by:
•
an include section which includes the libraries that can be used by the module
•
a module section which declares the name, direction, and data type of each port in the
design
For a detailed explanation of Verilog constructs in general, please refer to Chapter 2,
Verilog in the HDL Reference Manual.
3.5.5.1
Including Relevant Libraries
=> Insert this line before the declaration for module dual_port:
`include "lpm.v"
These lines advise the compiler to link to the Cypress LPM module library. These libraries
define the various types, modes, and Verilog constructs used in the Verilog code. For
details on the Verilog language, see the Verilog book in the Warp 6.3 online help.
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3.5.5.2
Writing the Module
=> Type the following lines into your Verilog text editor:
module dual_port (porta, portb, adda,
addb, wena, wenb,
clka, clkb, inva,
invb);
inout [15:0] porta, portb; // Port A and Port B data busses
input [ 7:0] adda, addb;
// Port A and Port B address busses
input wena, wenb;
// Port A and Port B write enables
input clka, clkb;
// Port A and Port B clocks
output inva, invb;
// Port A and Port B invalid flags
// (used for arbitration)
Now, create two 16 bit wires, 'a_out' and 'b_out', to represent the output data of each port
of the instantiated dual-port memory. Also, create a wire, called 'match' to represent the
condition when addresses of both ports match each other. The text should look like the
following:
wire [15:0] a_out,b_out;
wire match, inva, invb;
wire 1'b0 = 0;
// internal data busses
// constant for use with LPM
Once this has been done, paste in the dual-port memory instantiation by selecting the
'CY_RAM_DP' LPM module from the "Templates" menu located on the toolbar. For
more information about how to instantiate LPM modules, please refer to Chapter 5, LPM
& RTL Modules, in the User’s Guide.
Once pasted, you will need to fill in the appropriate values for each of the ports and
parameters. The parameters should be mapped so that 'lpm_width' is 16 and
'lpm_widthad' is 8. This configures each memory port to use 16-bit data bus widths and 8bit address bus widths, respectively. A memory instantiation file will not be used for this
excercise, so the line containing the mapping of 'LPM_file' should be commented out or
deleted. The ports should be mapped so that 'data_a' and 'data_b' are mapped to 'porta' and
'portb', respectively. Likewise, 'address_a' and 'address_b' should be mapped to 'adda' and
'addb', respectively. Outputs 'q_a' and 'q_b' should be mapped to 'a_out' and 'b_out',
respectively. The port 'address_match' should be mapped to 'match'. The write enables,
'wea' and 'web' should be mapped to 'wena' and 'wenb', respectively. Both the input and
output clocks for Port A should be mapped to 'clka'. Both the input and output clocks for
Port B should be mapped to 'clkb'. The remaining values for each of the ports and
parameters are default values and should not be edited for this exercise. The text should
look like the following:
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defparam U0.lpm_width= 16;
defparam U0.lpm_widthad= 8;
defparam U0.lpm_numwords= 0;// optional
defparam U0.lpm_indata= `LPM_REGISTERED;// optional
defparam U0.lpm_address_control= `LPM_REGISTERED;// optional
defparam U0.lpm_outdata_a= `LPM_REGISTERED;// optional
defparam U0.lpm_outdata_b= `LPM_REGISTERED;// optional
//defparam U0.lpm_file= "NULL";// optional
defparam U0.lpm_hint= `SPEED;// optional
cy_ram_dp U0(
.data_a( porta ),
.data_b( portb ),
.address_a( adda ),
.address_b( addb ),
.q_a
( a_out ),
.q_b
( b_out ),
.addr_matchb( match ),
.wea ( wena ),
.web ( wenb ),
.inclock_a(clka),// optional
.inclock_b(clkb),// optional
.outclock_a(clka),// optional
.outclock_b(clkb),// optional
.outrega_ar(1'b0),// optional
.outregb_ar(1'b0));// optional
3
For a description of this LPM module, please refer to Section 5.2.22 in Chapter 5 of the
User’s Guide.
Create two when else statements that arbitrate that between the two ports when they are
simultaneously attempting to write data to the same address, or when one port is
attempting to read data from an address while the other is attempting to write data to the
same address. Arbitration should result in either 'inva' or 'invb' being driven high to
indicate that data on either 'porta' or 'portb' may be invalid, respectively. The convention
should be as follows:
•
The output 'inva' should be driven high only when 'match' is high, 'wena' is low, and
'wenb' is high.
•
In all other cases, 'inva' should be driven low.
•
The output 'invb' should be driven high only when 'match' is high and 'wena' is high.
•
In all other cases, 'invb' should be driven low.
The text should look like the following:
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assign inva = (match// if both port addresses match
&& !wena// and if Port A is write disabled
&& wenb) ?// and if Port B is write enabled
1'b1 :// Port A becomes invalid
1'b0; // else Port A remains valid
assign invb = (match// if both port addresses match
&& wena) ?// and if Port A is write enabled
1'b1 :// Port B becomes invalid
1'b0; // else Port B remains valid
Also, create source code that assigns the outputs of the dual-port, 'a_out' and 'b_out', to the
output pins, 'porta' and 'portb', respectively. The text should look like the following:
assign porta = (wena == 1) ? a_out : 'bz;
assign portb = (wenb == 1) ? b_out : 'bz;
endmodule
You can add comment lines to your Verilog code by placing "//" before the comment text.
All of the characters on a line that appear after the comment characters are ignored and
considered to be part of the commented text. Optionally, you can comment out blocks of
text by beginning the commented section with "/*" and ending the commented section
with "*/".
3.5.6
Adding the File to the Project
After the design file is created, it must be added to the project, before it can be compiled.
Galaxy has a Preferences menu item under the Edit menu that allows you to set the design
file extension. These extensions are used to identify Verilog files. For Verilog projects, the
default file name extensions are: .v, .vlg, .ver, .vl.
3.5.6.1
To add a Verilog file:
1. Use the menu item Project -> Add Files. This accesses a dialog box where one or more
Verilog files can be selected. Files are added in the order they are selected.
2. Click the browse button to navigate to the project directory.
3. Highlight the dual_port.v file and click Add.
4. Click OK in the Add Files to Project dialog box.
Note - To add files from a different directory, click the browse button to navigate to the
project directory.
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Figure 3-28 Dialog box to select files to compile
3.5.6.2
3
Setting the File as Top-Level
Once dual_port.v has been added into the project, it can be set to be the top level file. A
top-level file must be specified in order to fit the design to a device. Only one top-level
file is allowed in a project.
=> Click on dual_port.v.
=> Select Project -> Set Top or click on the Set Top button available on the project toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will have a
hierarchy symbol (Figure 3-29).
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3
Figure 3-29 Galaxy window showing dual_port.v as the top-level
file
3.5.7
Configuring Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
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Figure 3-30 Compile Options dialog box with Synthesis tab chosen.
3
=> Under Logic to Memory Mapping in the Synthesis tab, one of the following options
can be selected: Disabled, Area, Speed.
Warp can optionally pack logic into memory and optimize for either area or speed. For an
explanation of the other compiler options please refer to the Galaxy online help, accessible
from the Galaxy Help menu.
=> Under Messaging in the Messaging tab, select the Detailed Report File option.
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Figure 3-31 Compiler Options dialog box with Messaging tab
chosen.
Warp will not print signal equations into the Delta39K or Quantum38K report file, unless
this setting is selected, as this information is available from the Architecture Explorer.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
3.5.8
Design Compilation and Synthesis
=> In your Galaxy window, select Compile -> Project to begin compilation or click the
Compile Project button on the project toolbar. Warp starts the compilation and synthesis
of the design into a CY39100 and prints messages to keep you appraised of its progress in
the results sub-window. The Compile - > Project option automatically recompiles only
those files which have been modified since the last compilation.
This operation generates one file of interest:
•
dual_port.rpt: contains pinout and timing information, along with other information
about the final synthesized design. You can see the .rpt file and the output files created
by Warp by clicking on the output view tab in the Project sub-window (Figure 3-32).
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
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3
Figure 3-32 View of the output files in the Project sub-window.
For more information on what is contained in a report file, refer to the Report File book
located in the Warp 6.3 online help.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
=> Go to the Verilog editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
dual_port.v file is entered exactly as shown earlier in this chapter -- or,
copy the file from the <warp path>\examples\wtutor\vlog directory -and then run Warp again.
3.5.9
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Final code for dual_port.v
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`include "lpm.v"
module dual_port (porta, portb, adda, addb, wena, wenb,
clka, clkb, inva, invb);
inout [15:0] porta, portb; // Port A and Port B data busses
input [ 7:0] adda, addb;// Port A and Port B address busses
input wena, wenb;// Port A and Port B write enables
input clka, clkb;// Port A and Port B clocks
output inva, invb;// Port A and Port B invalid flags
// (used for arbitration)
wire [15:0] a_out,b_out;
wire match, inva, invb;
wire 1'b0 = 0;
// internal data busses
// constant for use with LPM
defparam U0.lpm_width= 16;
defparam U0.lpm_widthad= 8;
defparam U0.lpm_numwords= 0;// optional
defparam U0.lpm_indata= `LPM_REGISTERED;// optional
defparam U0.lpm_address_control= `LPM_REGISTERED;// optional
defparam U0.lpm_outdata_a= `LPM_REGISTERED;// optional
defparam U0.lpm_outdata_b= `LPM_REGISTERED;// optional
//defparam U0.lpm_file= "NULL";// optional
defparam U0.lpm_hint= `SPEED;// optional
cy_ram_dp U0(
.data_a( porta ),
.data_b( portb ),
.address_a( adda ),
.address_b( addb ),
.q_a
( a_out ),
.q_b
( b_out ),
.addr_matchb( match ),
.wea ( wena ),
.web ( wenb ),
.inclock_a(clka),// optional
.inclock_b(clkb),// optional
.outclock_a(clka),// optional
.outclock_b(clkb),// optional
.outrega_ar(1'b0),// optional
.outregb_ar(1'b0));// optional
assign inva = (match// if both port addresses match
&& !wena// and if Port A is write disabled
&& wenb) ?// and if Port B is write enabled
1'b1 :// Port A becomes invalid
1'b0; // else Port A remains valid
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assign invb = (match// if both port addresses match
&& wena) ?// and if Port A is write enabled
1'b1 :// Port B becomes invalid
1'b0; // else Port B remains valid
assign porta = (wena == 1) ? a_out : 'bz;
assign portb = (wenb == 1) ? b_out : 'bz;
endmodule
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3.6
ilog)
Designing a single-port ROM memory circuit (VerIn this section, you’ll do the following tasks:
•
Instantiate a single-port ROM memory from the LPM template library
•
Generate a ROM file for initialization.
3.6.1
Design Description
This design describes a single-port ROM memory circuit, which is initialized with a ROM
lookup table. The source of the ROM lookup table is a Intel Hex format file containing
the actual ROM data. All reads to the memory table are asynchronous and operate without
enables. The lookup function is described in the following table.
Address Bus Bits
Data Bus Bits
a
b
c
d
x
y
z
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
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Address Bus Bits
1
3.6.2
1
1
Data Bus Bits
1
1
1
1
Starting Warp Applications
=> For Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 ->
Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as galaxy<CR>,
from within a shell window.
3.6.3
Creating the Design Project
Start Galaxy. Refer to Section 3.6.2, Starting Warp Applications for information on
starting applications on your platform.
3
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown below in Chapter 3-33.
Figure 3-33 New file and project dialog box.
3.
Select Verilog as the Project Type.
4.
Enter the name of the project as single_port.
5.
Enter the project path as follows.
=> On the PC, enter c:\wtutor\vlog\single_port.
=> On UNIX systems, enter <user_home_directory_path>/wtutor/vlog/single_port.
6.
182
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of Verilog files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
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Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device subfamily (Delta39K, Quantum38K, Ultra37000, Flash370I, etc.), device name and package
type. The user can traverse the device tree. On the left side of the dialog box are the
Devices available and on the right side are the Packages available for the device selected.
3
Figure 3-34 Select Target Device dialog box with Cypress PLDs in
tree form.
Each of the designs in Chapter 3 may be targeted to the Delta39K family. Since the
Quantum38K family is a subset of the Delta39K family of CPLDs, some features
illustrated by each of the designs are not available for the Quantum38K family. The
design description for each section lists the applicable CPLD family that may be targeted
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for that design.
7.
Navigate the tree to CPLD -> Delta39K -> c39k100.
8.
Highlight the CY39100V676-200MBC package on the right side.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
single_port.pfg which is now located in the c:\wtutor\vlog\single_port directory.
3.6.4
Creating the Verilog File
3
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
Note – You can also create a new text file by clicking on the "New Text
File" button on the project toolbar (
).
This brings up the Galaxy editor where you enter your Verilog code.
3.6.5
The single_port Verilog description
Each design's Verilog description is described by:
•
an include section which includes the libraries that can be used by the module
•
a module section which declares the name, direction, and data type of each port in the
design
For a detailed explanation of Verilog constructs in general, please refer to Chapter 2,
Verilog, in the HDL Reference Manual.
3.6.5.1
Including the Libraries
=> Insert this lines before the declaration for module single_port:
`include "lpm.v"
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These lines advise the compiler to link to the Cypress LPM module library. These
libraries define the various types, modes, and Verilog constructs used in the Verilog code.
For details on the Verilog language, see the Verilog section of the Warp 6.3 online help.
3.6.5.2
Writing the Module
=> Type the following lines into your Verilog text editor:
module single_port (a, b, c, d, x, y, z);
input a, b, c, d;// Single Port ROM address bus bits
output x, y, z;// Single Port ROM data bus bits
Now, create a 4-bit wire named 'address' to represent the address of the data to be retrieved
from the single port ROM table. Also, create a 3-bit wire named 'result' to represent the
output data of the same.
wire [3:0]address;
wire [2:0]result;
Once this has been done, paste in the single-port ROM instantiation by selecting the
'LPM_ROM' LPM module from the "Templates" menu located on the toolbar. For more
information about how to instantiate LPM modules, please refer to Chapter 5, LPM & RTL
Modules, in the User’s Guide.
Once pasted, you will need to fill in the appropriate actuals for each of the locals. The
generic map locals should be mapped so that 'lpm_width' is 3 and 'lpm_widthad' is 4. This
configures the ROM table to use a 3-bit data bus and a 4-bit address bus, respectively. The
generic map locals should be mapped so that 'lpm_address_control' is
`LPM_UNREGISTERED and 'lpm_outdata' is `LPM_UNREGISTERED for
asynchronous operation. A ROM file named 'single_port.rom' using Intel Hex format
must be created and have 'lpm_file' mapped to it.
The port map locals should be mapped so that 'address' and 'q' are mapped to 'address' and
'result', respectively. The remaining values for each of the actuals are default values and
should not be edited for this exercise. The resulting instantiation text should be as
follows:
defparam
defparam
defparam
defparam
optional
defparam
defparam
defparam
U0.lpm_width= 3;
U0.lpm_widthad= 4;
U0.lpm_numwords= 0;// optional
U0.lpm_address_control= `LPM_UNREGISTERED;//
U0.lpm_outdata= `LPM_UNREGISTERED;// optional
U0.lpm_file= "single_port.rom";// optional
U0.lpm_hint= `SPEED;// optional
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mrom
U0(
.address( address ),
.q
( result ),
.inclock(1'b0),// optional
.outclock(1'b0),// optional
.memenab(1'b1),// optional
.outreg_ar(1'b0));// optional
For a description of this LPM module, please refer to Section 5.2.20 in the Chapter 5 of
the User’s Guide.
•
Create two assign statements that connect the address bits 'a', 'b', 'c', and 'd' to 'address'
and 'result' to data bus bits 'x', 'y', 'z'.
The text should look like the following:
3
assign address = {a,b,c,d};
assign x = result[2];
assign y = result[1];
assign z = result[0];
endmodule
3.6.5.3
Writing the ROM file
A text file named 'single_port.rom' should be created and added to the project as a ROM
file. This file should contain the following text:
:080000000407060205040301D8
:080008000103070006070007D1
:00000001FF
This text represents three records that make up a single lookup table and can be separated
into 6 fields, each of which is described in the table below.
186
RECORD
MARK ‘:’
RECLEN
LOAD
OFFSET
RECTYPE
1-byte
1-byte
2-bytes
1-byte
DATA
n-bytes
CHECKSUM
1-byte
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RECORD
MARK ‘:’
RECLEN
LOAD
OFFSET
RECTYPE
:
08
00 00
00
04 07 06
02 05 04
03 01
D8
:
08
00 08
00
01 03 07
00 06 07
00 07
D1
:
00
00 00
01
DATA
CHECKSUM
FF
All records start with a ':'. Every 2 ASCII characters represent 1 byte of the record.
RECLEN represents the length in bytes of the data portion of the record. LOAD OFFSET
is a two-byte starting load offset of the data bytes, and determines where in the memory
that the record data will be placed. RECTYPE represents the type of record, where '00' and
'01' means record contains data or record is at the end of the file, respectively. The DATA
field represents an n-byte entry of data bytes. For our example both data records represent
8 bytes of data. Each byte in this field from left to right maps directly a single ROM
address. Therefore, '07' in the second record, maps to the contents of the third address
following offset '0008', which is at address '1010'. The data contents in this example are
composed of 3-bits, not 8. However, each must be represented in the record as one byte
(in hex). This address can be used to retrieve data from a lookup table. The lookup table,
below, represents the ROM file just explained. The checksum is just the two's
complement of the 8-bit addition of the bytes that are in RECLEN, LOAD OFFSET,
RECTYPE, and DATA.
You can add comment lines to your Verilog code by placing "//" before the comment text.
All of the characters on a line that appear after the comment characters are ignored and
considered to be part of the commented text. Optionally, you can comment out blocks of
text by beginning the commented section with "/*" and ending the commented section
with "*/".
3.6.6
Adding the Files to the Project
After the design file is created, it must be added to the project, before it can be compiled.
Galaxy has a Preferences menu item under the Edit menu that allows you to set the design
file extension. These extensions are used to identify Verilog files. For Verilog projects, the
default file name extensions are: .v, .vlg, .ver, .vl.
3.6.6.1
To add a Verilog file:
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1.
Use the menu item Project -> Add Files. This accesses a dialog box where one or
more Verilog files can be selected. Files are added in the order they are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the single_port.v file and click Add.
4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
3.6.6.2
3
3.6.7
To add a ROM file:
1.
Use the menu item Project -> Add ROM File(s). This accesses a dialog box where
one or more ROM files can be selected. Files are added in the order they are
selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the single_port.rom file and click OK.
Setting the File as Top-Level
Once single_port.v has been added into the project, it can be set to be the top level file. A
top-level file must be specified in order to fit the design to a device. Only one top-level
file is allowed in a project.
=> Click on single_port.v.
=> Select Project -> Set Top or click on the Set Top button available on the project toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will have a
hierarchy symbol (Figure 2-6).
3.6.8
Configuring Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
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Figure 3-35 Compile Options dialog box with Synthesis tab chosen.
=> Under Logic to Memory Mapping in the Synthesis tab, one of the following options
can be selected: Disabled, Area, Speed.
Warp can optionally pack logic into memory and optimize for either area or speed. For an
explanation of the other compiler options please refer to the Galaxy online help, accessible
from the Galaxy Help menu.
=> Under Messaging in the Messaging tab, select the Detailed Report File option.
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Figure 3-36 The Compiler Options dialog box with Messaging tab.
3
Warp will not print signal equations into the Delta39K or Quantum38K report file, unless
this setting is selected, as this information is available from the Architecture Explorer.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
3.6.9
Design Compilation and Synthesis
=> In your Galaxy window, select Compile -> Project to begin compilation or click the
Compile Project button on the project toolbar. Warp starts the compilation and synthesis
of the design into a CY39100 and prints messages to keep you appraised of its progress in
the results sub-window. The Compile - > Project option automatically recompiles only
those files which have been modified since the last compilation.
This operation generates two files of particular interest:
•
single_port.hex: is used to program a CY39100 device.
•
single_port.rpt: contains pinout and timing information, along with other information
about the final synthesized design.
You can see the .rpt file and the output files created by Warp by clicking on the output
view tab in the Project sub-window (Figure 3-37). Different sections of the report file can
be accessed by clicking on the plus sign and selecting the available sections.
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3
Figure 3-37 View of the output files in the Project sub-window.
For more information on what is contained in a report file, refer to the Report File book
located in the Warp 6.3 online help.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
=> Go to the Verilog editor window. The cursor should be positioned on the line that
caused the error. Use the Next and Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
single_port.v file is entered exactly as shown earlier in this chapter -- or,
copy the file from the <warp path>\examples\wtutor\vlog directory -and then run Warp again.
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3.6.10
Final code for single_port.v
`include "lpm.v"
module single_port (a, b, c, d, x, y, z);
input a, b, c, d;// Single Port ROM address bus bits
output x, y, z;// Single Port ROM data bus bits
wire [3:0]address;
wire [2:0]result;
defparam U0.lpm_width= 3;
defparam U0.lpm_widthad= 4;
defparam U0.lpm_numwords= 0;// optional
defparam U0.lpm_address_control= `LPM_UNREGISTERED;//
optional
defparam U0.lpm_outdata= `LPM_UNREGISTERED;// optional
defparam U0.lpm_file= "single_port.rom";// optional
defparam U0.lpm_hint= `SPEED;// optional
mrom
U0(
.address( address ),
.q
( result ),
.inclock(1'b0),// optional
.outclock(1'b0),// optional
.memenab(1'b1),// optional
.outreg_ar(1'b0));// optional
3
assign
assign
assign
assign
address = {a,b,c,d};
x = result[2];
y = result[1];
z = result[0];
endmodule
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3.7
Designing a synchronous FIFO memory (Verilog)
In this section, you’ll do the following tasks:
•
3.7.1
Instantiate a FIFO RAM memory where the write clock comes from either a divided
down input pin or from an output of an instantiated PLL.
Design Description
This design describes a synchronous FIFO memory that performs bus matching between a
32-bit input bus and an 8-bit output bus.
3.7.2
Design Solution
The design should have a separate clock for writes to and reads from the FIFO. The write
clock is generated from a pin input, while the read clock is generated by an on-board
Phase-Locked-Loop (PLL). A third clock, running at 4x the speed of the read clock,
synchronizes the reads from each of the four bytes of the 32-bit FIFO output.
3.7.3
3
Starting Warp Applications
=> For Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 ->
Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as galaxy<CR>,
from within a shell window.
3.7.4
Creating the Design Project
Start Galaxy. Refer to Section 3.7.3, Starting Warp Applications for information on
starting applications on your platform.
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown below in Figure 3-38.
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Figure 3-38 New file and project dialog box.
3.
Select Verilog as the Project Type.
4.
Enter the name of the project as pll_clocked_fifo.
5.
Enter the project path as follows.
=> On the PC, enter c:\wtutor\vlog\pll_clocked_fifo.
3
=> On UNIX systems, enter <user_home_directory_path>/wtutor/vlog/
pll_clocked_fifo.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of Verilog files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device Family (SPLD, CPLD, etc.), device subfamily (Delta39K, Quantum38K, Ultra37000, Flash370I, etc.), device name and package
type. The user can traverse the device tree. On the left side of the dialog box are the
Devices available and on the right side are the Packages available for the device selected.
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3
Figure 3-39 Select Target Device dialog box with Cypress PLDs in
tree form.
Each of the designs in Chapter 3 may be targeted to the Delta39K family. Since the
Quantum38K family is a subset of the Delta39K family of CPLDs, some features
illustrated by each of the designs are not available for the Quantum38K family. The
design description for each section lists the applicable CPLD family that may be targeted
for that design.
7.
Navigate the tree to CPLD -> Delta39K -> c39k100 in the left frame.
8.
Highlight the CY39100V676-200MBC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
pll_clocked_fifo.pfg which is now located in the c:\wtutor\vlog\pll_clocked_fifo
directory.
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3.7.5
Creating the Verilog File
1.
Select File -> New.
2.
Select "Text File".
3.
Click OK.
Note – You can also create a new text file by clicking on the "New Text
File" button on the project toolbar (
).
This brings up the Galaxy editor where you enter your Verilog code.
3
Figure 3-40 Blank Galaxy editor window.
3.7.6
The pll_clocked_fifo Verilog description
Each design's Verilog description is described by:
•
an include section which includes the libraries that can be used by the module
•
a module section which declares the name, direction, and data type of each port in the
design
For a detailed explanation of these Verilog constructs in general, please refer to Chapter 2,
Verilog, in the HDL Reference Manual.
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3.7.6.1
Including Relevant Libraries
=> Insert these lines before the declaration for module 'pll_clocked_fifo':
`include "<cypress_dir>\lib\common\lpm.v"
`include "<cypress_dir>\lib\common\rtl.v"
These lines advise the compiler to link to the Cypress LPM module library. These libraries
define the various types, modes, and Verilog constructs used in the Verilog code. For
details on the Verilog language, see the Verilog book in the Warp 6.3 online help.
3.7.6.2
Writing the Module
=> Type the following lines into your Verilog text editor:
module pll_clocked_fifo (indata, byte, writeclk,
byteclk, offclk, read, write, empty_full, half,
fifo_reset, lock);
input
writeclk, byteclk; // write clock and faster clock
input
read, write;
// read and write enables
input [31:0] indata;
// data to write
input
fifo_reset;
// Reset for FIFO
output
empty_full, half;
// Flags for empty/full and half
full
output
lock, offclk;
// PLL lock detection output and
offchip clock
output [ 7:0] byte;
// FIFO output byte
Now, create one 32-bit wire named 'outdata', one 2-bit reg named 'selection' for selecting a
byte of the FIFO's output, and one single-bit wire named 'int_byteclk' to represent the
output data of the instantiated FIFO memory and internal PLL output of 'byteclk',
respectively. The text should look like the following:
reg [1:0] selection;// byte selector
reg [7:0] byte;
reg offclk;
wire readclk;// read clock
wire int_byteclk;// internal PLL output of 'byteclk'
wire [31:0] outdata;// FIFO output"
Once this has been done, paste in the FIFO memory instantiation by selecting the
'CY_Fifo' LPM module from the "Templates" menu located on the toolbar. For more
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information about how to instantiate LPM modules, please refer to Chapter 5, LPM & RTL
Modules, in the User’s Guide.
Once pasted, you will need to fill in the appropriate values for each of the ports and
parameters. The parameters should be mapped so that 'width' is 32 and 'numwords' is 512.
This configures the FIFO to use 32-bit data bus widths and to store up to 512 four-byte
words, respectively. The remaining values for each of the parameters will not be used for
this exercise, and these lines should be deleted. The ports should be mapped so that 'data'
and 'q' are mapped to 'indata' and 'outdata', respectively. Likewise, 'enr' and 'enw' should
be mapped to 'read' and 'write', respectively. Outputs 'readclock' and 'writeclock' should be
mapped to 'readclk' and 'writeclk', respectively. Flags 'efb' and 'hfb' should be mapped to
'empty_full' and 'half', respectively. Port 'mrb' should be mapped to the value of '1'b1' so
that it is permanently disabled. Ports 'outreg_ar', and 'pafeb' will not be used for this
exercise, and these lines may be deleted, provided that there are no characters such as a
','or ';' between the last generic listed and the ');' that closes the parameter map. The
resulting text should be as follows:
defparam U0.lpm_width= 32;
defparam U0.lpm_numwords= 512;
cy_fifo U0(
.data (indata),
.q
(outdata),
.enr (read),
.enw (write),
.readclock(readclk),
.writeclock(writeclk),
.mrb (fifo_reset),
.efb (empty_full),// optional
.hfb (half));// optional
3
For a description of this LPM module, please refer to Section 5.2.21 in Chapter 5 of the
User’s Guide.
Once this has been done, paste in the PLL instantiation by selecting the 'CY_C39KPLL'
LPM module from the "Templates" menu located on the toolbar. For more information
about how to instantiate LPM modules, please refer to Chapter 5, LPM & RTL Modules, in
the User’s Guide.
Once pasted, you will need to fill in the appropriate values for each of the ports and
parameters. The parameters should be mapped so that 'multiply' is 2, 'gclk2_divide' is 4,
and 'gclk3_phase' is 45. This configures the PLL to multiply the incoming clock by a
factor of two, generates a single clock that is half of the rate of the incoming clock,
generates a single clock that is the same rate as the incoming clock, and generates a single
clock that lags the incoming clock by 450, respectively. The remaining values for each of
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the parameters are default values and should not be edited for this exercise. The ports
should be mapped so that 'pll_in' is mapped to 'byteclk'. Likewise, 'lock_detect' should be
mapped to 'lock', respectively. Outputs 'gclk2' and 'gclk3' should be mapped to 'readclk'
and 'int_byteclk', respectively. Parameters 'gclk0_phase', 'gclk0_divide', 'gclk1_phase',
'gclk1_divide', and 'feedback' will not be used for this exercise, and these lines should be
deleted. Ports 'ext_fdbk', 'gclk0', and 'gclk1' will not be used for this exercise, and these
lines should be deleted. Be sure to rename the label of this instantiation to become "U1".
The text should look like the following:
defparam U1.multiply
= 1;// optional
defparam U1.gclk2_phase
= 0;// optional
defparam U1.gclk2_divide = 4;// optional
defparam U1.gclk3_phase
= 0;// optional
defparam U1.gclk3_divide = 1;// optional
defparam U1.input_freq
= 133000000;// optional
cy_c39kpll U1(
.pll_in(byteclk),
.lock_detect(lock),// optional
.gclk2
(readclk),// optional
.gclk3
(int_byteclk));// optional
For a description of this LPM module, please refer to Section 5.3.19.
Create an always block that is activated upon each rising edge of 'int_byteclk' and uses a
case statement to select one byte of the 'outdata' word that is read for output. The
convention should be as follows:
•
If 'selection' equals 2'b00, then 'byte' is assigned the most significant byte of 'outdata'.
•
If 'selection' equals 2'b01, then 'byte' is assigned the second most significant byte of
'outdata'.
•
If 'selection' equals 2'b10, then 'byte' is assigned the second least significant byte of
'outdata'.
•
If 'selection' equals anything else, then 'byte' is assigned the least significant byte of
'outdata'.
In addition, the always block should increment 'selection' and toggle 'offclk'.
The text should look like the following:
always @(posedge int_byteclk)
begin
if (empty_full == 0)// if FIFO is empty
case (selection)// and if selection equals
2'b00:// 0 then
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byte <= outdata[31:24];// byte is MSB
2'b01:// if 1 then
byte <= outdata[23:16];// byte is 2nd byte
2'b10:// if 2 then
byte <= outdata[15: 8];// byte is 3rd byte
default:// otherwise
byte <= outdata[ 7: 0];// byte is LSB
endcase
selection <=
selection + 1;// increment selection
offclock<=
~(offclk);//toggle offchip clock
end
endmodule
You can add comment lines to your Verilog code by placing "//" before the comment text.
All of the characters on a line that appear after the comment characters are ignored and
considered to be part of the commented text. Optionally, you can comment out blocks of
text by beginning the commented section with "/*" and ending the commented section
with "*/".
3
3.7.7
Adding the File to the Project
After the design file is created, it must be added to the project, before it can be compiled.
Galaxy has a Preferences menu item under the Edit menu that allows you to set the design
file extension. These extensions are used to identify Verilog files. For Verilog projects, the
default file name extensions are: .v, .vlg, .ver, .vl.
3.7.7.1
To add a Verilog file:
1.
Use the menu item Project -> Add Files. This accesses a dialog box where one or
more Verilog files can be selected. Files are added in the order they are selected.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the pll_clocked_fifo.v file and click Add.
4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
3.7.8
Setting the File as Top-Level
Once pll_clocked_fifo.v has been added into the project, it can be set to be the top level
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file. A top-level file must be specified in order to fit the design to a device. Only one toplevel file is allowed in a project.
=> Click on pll_clocked_fifo.v.
=> Select Project -> Set Top or click on the Set Top button available on the project toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will have a
hierarchy symbol.
3.7.9
Configuring Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
3
Figure 3-41 Compiler Options dialog box with Synthesis tab.
=> Under Logic to Memory Mapping in the Synthesis tab, one of the following options
can be selected: Disabled, Area, Speed.
Warp can optionally pack logic into memory and optimize for either area or speed. For an
explanation of the other compiler options please refer to the Galaxy online help, accessible
from the Galaxy Help menu.
=> Under Messaging in the Messaging tab, select the Detailed Report File option.
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Figure 3-42 Compiler Options dialog box with Messaging tab.
3
Warp will not print signal equations into the Delta39K or Quantum38K report file, unless
this setting is selected, as this information is available from the Architecture Explorer.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
3.7.10
Design Compilation and Synthesis
=> In your Galaxy window, select Compile -> Project to begin compilation or click the
Compile Project button on the project toolbar. Warp starts the compilation and synthesis
of the design into a CY39100 and prints messages to keep you appraised of its progress in
the results sub-window. The Compile - > Project option automatically recompiles only
those files which have been modified since the last compilation.
This operation generates two files of particular interest:
202
•
pll_clocked_fifo.hex: is used to program a CY39100 device.
•
pll_clocked_fifo.rpt: contains pinout and timing information, along with other
information about the final synthesized design. You can see the .rpt file and the output
files created by Warp by clicking on the output view tab in the Project sub-window
Figure 3-43. Different sections of the report file can be accessed by clicking on the
plus sign and selecting the available sections.
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3
Figure 3-43 View of the output files in the Project sub-window.
For more information on what is contained in a report file, refer to the Report File book
located in the Warp 6.3 online help.
Note – If compilation errors occur, make sure the text of your
pll_clocked_fifo.v file is entered exactly as shown earlier in this chapter
and then run Warp again. You can also copy the file from the
<warp_path>\examples\wtutor\vlog directory.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it.
=> Go to the Verilog editor window. The cursor should be positioned on the line that
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caused the error. Use the Next and Previous Error buttons to locate other errors.
3.7.11
Final code for pll_clocked_fifo.v
`include "lpm.v"
`include "rtl.v"
module pll_clocked_fifo (indata, byte, writeclk, byteclk,
offclk, read, write, empty_full, half, fifo_reset, lock);
input
writeclk, byteclk;// write clock and faster clock
input
read, write;// read and write enables
input [31:0] indata;// data to write
input
fifo_reset;// Reset for FIFO
output
empty_full, half;// Flags for empty / full and half
full
output
lock, offclk;// PLL lock detection output and offchip clock
output [ 7:0]byte;// FIFO output byte
3
reg [1:0] selection;// byte selector
reg [7:0] byte;
reg
offclk;
wire readclk;// read clock
wire int_byteclk;// internal byteclk
wire [31:0] outdata;// FIFO output
defparam U0.lpm_width= 32;
defparam U0.lpm_numwords= 512;
cy_fifo U0(
.data(indata),
.q
(outdata),
.enr(read),
.enw(write),
.readclock(readclk),
.writeclock(writeclk),
.mrb (fifo_reset),
.efb(empty_full),// optional
.hfb(half));// optional
defparam
defparam
defparam
defparam
defparam
204
U1.multiply
U1.gclk2_phase
U1.gclk2_divide
U1.gclk3_phase
U1.gclk3_divide
=
=
=
=
=
1;//
0;//
4;//
0;//
1;//
optional
optional
optional
optional
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defparam U1.input_freq
= 133000000;// optional
cy_c39kpll U1(
.pll_in(byteclk),
.lock_detect(lock),// optional
.gclk2
(readclk),// optional
.gclk3
(int_byteclk));// optional
always @(posedge int_byteclk)
begin
if (empty_full == 0)// if FIFO is empty
case (selection)// and if selection equals
2'b00:
// 0 then
byte <= outdata[31:24];// byte is MSB
2'b01:
// if 1 then
byte <= outdata[23:16];// byte is 2nd byte
2'b10:
// if 2 then
byte <= outdata[15: 8];// byte is 3rd byte
default:
// otherwise
byte <= outdata[ 7: 0];// byte is LSB
endcase
selection <=
selection + 1;// increment selection
offclk <= ~(offclk);//toggle offchip clock
end
endmodule
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Choosing a Timing Model for Active-HDL Sim
(PC only)
On the PC platforms, Warp includes the Active-HDL Sim timing simulator. This section
applies only if you Active-HDL Sim installed on your PC. You can verifty the synthesized
design using Active-HDL Sim by creating the 1164/VHDL timing model of the design
using Warp.
In order to simulate your Verilog file with Active-HDL Sim, you must compile your
refill.v with 1164/VHDL, which will generate a refill.vhd file.
=> Select Project -> Compiler Options -> Synthesis tab and click on the Timing
Model drop-down menu in the Simulation area.
=> Select 1164/VHDL.
3.7.12
3
Simulating the Behavior of the Design
UNIX Customers
Please refer to Chapter 9, Simulation, in the User’s Guide for details on how to simulate
the design after fitting.
PC Customers
On the PC platforms, the synthesized design can be verified using the Active-HDL Sim
simulator.
In section of the tutorial, you will perform the following steps:
•
Start Active-HDL Sim.
•
Open the refill.vhd file in the w2tutor/vhd/vhd folder.
•
Set the values of the stimulus signals in the simulation.
•
Simulate the design.
•
Examine results to figure out what happened.
3.7.12.1
Starting Active-HDL Sim
=> Start Active-HDL Sim by selecting Tools -> Active-HDL Sim in Galaxy.
=> Open the refill.vhd file by choosing File -> Open VHDL and browse to w2tutor/
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vlog/vhd.
Note – Active-HDL Sim is not a Verilog simulator and requires the
refill.v file be compiled with the 1164/VHDL timing model for postsynthesis simulation. In order to simulate your Verilog file with ActiveHDL Sim, you must compile refill.v (a Verilog file) with the 1164/
VHDL timing model in Galaxy, which generates a file called refill.vhd
(a VHDL file). For information on how to compile refill.v with the
1164/VHDL timing model, see Section 3.7.12.
=> Click on refill.vhd.
=> Click on OK. The Active-HDL Sim window should resemble Figure 3-44.
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Figure 3-44 The initial Active-HDL Sim window for refill.vhd.
3.7.12.2
Creating a View
=> Select Waveform -> Add Signals.
=> Double click on clk in the right pane of the Add Signals dialog box, shown
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below in Figure 3-45.
Figure 3-45 Add Signals dialog box with available signals for
creating a view.
3
=> Double click on the following signals to add them to your new view in the
following order: reset, get_cola, get_diet, give_cola,
give_diet, refill_bins.
=> Click on Add.
=> Your new view should look like Figure 3-46.
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Figure 3-46 Active-HDL Sim screen of your new view.
3.7.12.3
Setting Stimulus Signal Values
You need to set the values of the following input signals for your simulation: clk,
reset, get_cola, and get_diet.
Set the clock signal for equally spaced alternating highs and lows.
=> Select the clock signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Clock” as the Stimulator type from the pull-down menu.
=> In the clock diagram, click on the 1 at the left side of the pane. The box with 1
should turn light grey to indicate it is selected. See Figure 3-47 below.
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Figure 3-47 Clock diagram with 1 selected.
3
=> Click on the Apply button and then click on Close.
Set reset to high for one rising clock edge. To do so:
=> Select the reset signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following in the “Enter Formula” field:
=> 0 0, 1 75 ns, 0 125 ns
=> Click on the Apply button and then click on Close.
Set get_cola high for four non-consecutive rising clock edges.
=> Select the get_cola signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following in the “Enter Formula” field:
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=> 0 0, 1 175 ns, 0 225 ns, 1 375 ns, 0 425 ns, 1 575 ns,
0 625 ns, 1 775 ns, 0 825 ns
=> Click on the Apply button and then click on Close.
Set get_diet high for four non-consecutive rising clock edges. These four pulses
should come after the four pulses created for the get_cola signal. The first pulse of the
get_diet signal comes no sooner than the tenth rising clock edge. One clock edge for
reset and 8 edges for get_cola (you need four non-consecutive rising clock edges).
=> Select the get_diet signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Type in the following in the “Enter Formula” field:
=> 0 0, 1 975 ns, 0 1025 ns, 1 1175 ns, 0 1225 ns, 1 1375
ns, 0 1425 ns, 1 1575 ns, 0 1625 ns
3
=> Click on the Apply button and then click on Close.
Set reset high for one rising clock edge after the last get_diet request.
=> Select the reset signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Select “Formula” as the Stimulator type from the pull-down menu.
=> Add the following text to the formula after 0 125 ns:
=> , 1 1675 ns, 0 1725 ns
=> Click on the Apply button and then click on Close.
Set get_cola and get_diet high for one rising clock edge, respectively, after the
second reset.
=> Select the get_cola signal in the left pane of the waveform window.
=> Right click on the signal and select the Stimulators option.
=> Add the following text to the formula after 0 825 ns:
=> , 1 1775 ns, 0 1825 ns
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=> Click on the Apply button.
=> Highlight get_diet in the left pane of the Stimulators dialog.
=> Add the following text to the formula after 0 1625 ns:
=> , 1 1875 ns, 0 1925 ns
=> Click on the Apply button and then click on Close.
The result, when complete, should look like Figure 3-48.
3
Figure 3-48 Active-HDL Sim stimulators dialog box for refill.awf
with all the signals set
3.7.12.4
Running the Simulation
=> To simulate the design, click on the drop-down menu next to the 100ns field on
the toolbar and click on the Run For button in the toolbar.
Note – To re-initialize the simulation, click on the Restart Simulation
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button on the Toolbar or select it from the Simulation -> Restart Simulation menu and select Waveforms -> Clear all Waveforms.
Note – You may wish to change the screen resolution in order to fit all
activity in the waveforms on one screen. Select View -> Zoom -> Out.
The results should look similar to Figure 3-49:
3
Figure 3-49 Results of the refill.vhd Active-HDL Sim simulation
The simulation starts with the drink machine empty. Notice the state of
the refill_bins signal at the start of the simulation.
When the reset signal goes high at the start of the simulation, the
refill_bins signal is set low. The drink machine is now ready to
dispense drinks.
The drink machine dispenses three colas in response to the first three
requests for a cola. Note the relationship between the pulses in the
get_cola and give_cola signals. After the next request for a cola,
however, the machine does not dispense a drink; the cola bin is empty.
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Similarly, the drink machine dispenses three diets in response to the first
three requests for a diet. After the fourth request for a diet, the machine
does not dispense one; the diet bin is empty.
With both bins empty, the refill_bins signal goes high. It stays
high until the reset signal goes high again, telling the machine that
the bins have been replenished. The next two requests, for a cola and a
diet respectively, are honored.
If the output of your simulation does not register correctly, make sure that your signals
begin and end halfway between rising and falling clock edges.
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4
Warp Professional &
Enterprise Tutorials
4
Warp Professional & Enterprise Tutorials
Professional and Enterprise Tutorials
This tutorial will walk through the drink machine tutorial and give an explicit example of
the actual design flow using Aldec Professional/Enterprise.
To run this tutorial, Warp 6.3 Professional or Enterprise must be installed. Throughout
this tutorial, Warp 6.3 Professional/Enterprise will be referred to as Warp P/E.
4.1
4.1.1
Designing a Drink Machine in Warp P/E (VHDL)
Launch the Warp P/E tool
=> To start Warp P/E, select Start -> Programs -> Cypress -> Warp Professional/
Enterprise R6.3 -> Active-HDL 4.1CY.
4.1.2
Creating the Project
=> Select “Create new design” in the Getting Started Wizard (Figure 4-1) and click
OK.
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Figure 4-1 Getting Started Wizard for Warp P/E.
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=> Select Create an empty design and click Next (Figure 4-2).
4
Figure 4-2 Creating an empty design dialog box.
=> The next dialog box (Figure 4-3) displays the synthesis and implementation
setup. Do not change anything and click Next.
Figure 4-3
Synthesis and Implementation location dialog box.
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Note – Make sure the default HDL language is VHDL in the Default
HDL Language pull-down menu.
=> Enter the design name drink_machine and leave the design directory as the
default (Figure 4-4). Warp P/E automatically creates a default working directory
with the same name as the design name.
=> Click Next to continue.
4
Figure 4-4 Entering design name dialog box.
=> Click Finish.
4.1.3
Starting the Tutorial
The opening window (Figure 4-5) shows the standard design environment with the design
flow tab selected. The design flow provides you a flow chart of the steps required to
complete a design and target a Cypress device.
Figure 4-5 Opening window with design flow tab selected.
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4.1.3.1
Adding Existing Files
Since we are using existing design files (refill.vhd and binctr.vhd), we will be double
clicking on the Add New File entry in the Design Browser section. This will bring up a
file selection dialog where you select add existing files (Figure 4-6).
=> Double click on “Add New File”.
4
Figure 4-6 Add New File dialog box.
=> Click on the “Add Existing File” button to navigate to the <warp path>/
examples/wtutor/vhdl directory of your Warp P/E installation and double click on
the binctr.vhd file.
=> Double click on “Add New File”.
=> Click on the “Add Existing File” button to navigate to the <warp path>/
examples/wtutor/vhdl directory of your Warp P/E installation and select the
refill.vhd file as well.
If you are using Warp Professional or do not intend to perform functional simulation in
Warp Enterprise on this design, skip Section 4.1.3.2, Functional Simulation in Warp
Enterprise.
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4.1.3.2
Functional Simulation in Warp Enterprise
If you are performing functional simulation, you will need to make a few modifications to
the files. These modifications result from some differences in how Warp handles some
libraries and how Aldec handles vendor specific attributes in source code.
=> Double click on the file binctr.vhd, which will open it in the editor window.
=> Locate the line "use cypress.std_arith.all;" in the file. There should
be one occurrence immediately above the package declaration and one above the
entity declaration.
=> Replace that line with the following two lines in both places:
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Note – The reason you need to make these changes is that Warp
originally had its own library for arithmetic functions. Warp now
supports the Synopsys "ieee.std_logic_arith" libraries, but to maintain
compatibility with previous versions the tutorial files have been left as
is. Either version of libraries will compile fine through Warp, but Aldec
does not recognize the Cypress specific libraries. This means for
existing designs, which use the "work.std_arith" library, you will need
to modify your source if you want to perform functional simulation.
You can comment out the "work.std_arith" library for clarity, but it can
simply be deleted as well.
4
=> Save the binctr.vhd file.
=> Double click on the refill.vhd file and locate the section with the line "Attribute
pin_numbers".
=> Comment out all attribute related statements.
Note – Aldec does not support vendor specific attributes in the source
files. To remedy this situation, you will need to copy any vendor
specific attributes into a control file. A control file is a text file with the
same root name as the top-level file and the file extension "ctl". For this
example, it would be refill.ctl. All vendor specific attributes can be
placed in this file.
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=> Save the refill.vhd file.
=> Select the Design Flow tab.
=> Click the functional simulation button on the Design Flow Manager and perform
pre-synthesis, functional simulation.
4.1.3.3
Device Selection in Warp P/E
Performing device selection is accomplished by clicking on the Device button on the
Design Flow manager.
This will bring up the Warp Select Device dialog box (Figure 4-7).
4
Figure 4-7 Cypress Select Device dialog box.
=> In the left frame, navigate to Ultra37000 and select c37032.
=> In the right frame, select 37032P44-125AC.
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=> Click OK.
4.1.3.4
Setting Compiler Options in Warp P/E
You can set the synthesis options by clicking on the synthesis options button in the Design
Flow manager. This brings up the Warp Compiler Options dialog box (Figure 4-8 and
Figure 4-9), used to set synthesis goals and options, plus control the amount of
information that Warp presents in the report file.
4
Figure 4-8 Compiler Options dialog box with Synthesis tab
selected.
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Figure 4-9 Compiler Options dialog box with Messaging tab
selected.
4.1.3.5
4
Compiling the Design
After setting the synthesis options, the design can be compiled and targeted by clicking the
Implementation button. This will bring up the Select top-level file and design unit dialog
box (Figure 4-10), where you select refill.v as the top-level entity.
Figure 4-10 Select top level file and design unit dialog box.
=> Select refill.vhd as the top-level file.
=> Type in refill.vhd as the top-level unit.
=> Click OK.
You can watch the progress of the compilation in the Console window. A successful
compilation is shown in Figure 4-11.
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Figure 4-11 Successful compilation result in the Console window.
4
Note – If any errors occur, you can double-click on the error message
in the console window and the source file will open with the relevant
line highlighted.
4.1.3.6
Viewing the Report File
To access the report file, click on the Reports button in the Design Flow Manager. This
will open the report file in the Editor window. You can than examine the design
implementation in detail.
4.1.3.7
Timing Simulation in Warp P/E
To perform post-fit simulation of the design, click on the Timing Simulation button in the
Design Flow manager. This will launch the Aldec simulator and allow you to perform
post-fit simulation as outlined in Section 2.2.14, Setting Stimulus Signal Values.
4.1.3.8
Additional Information
For additional tutorials, see Chapter 3, Delta39K and Quantum38K Tutorials.
For further information on the Cypress Design Flow Manager, see the online documentation included with Warp P/E.
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4.2
4.2.1
Designing a Drink Machine in Warp P/E (Verilog)
Launch the Warp P/E tool
=> To start Warp P/E, select Start -> Programs -> Cypress -> Warp Professional/
Enterprise R 6.3 -> Active-HDL 4.1CY.
4.2.2
Creating the Project
=> Select “Create new design” in the Getting Started Wizard (Figure 4-12) and click
OK.
4
Figure 4-12 Getting Started Wizard for Warp P/E.
=> Select Create an empty design and click Next (Figure 4-13).
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Figure 4-13 Creating an empty design dialog box.
4
=> The next dialog box (Figure 4-14) displays the synthesis and implementation
setup. Do not change anything and click Next.
Figure 4-14
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Synthesis and Implementation location dialog box.
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Note – Make sure the default HDL language is Verilog in the Default
HDL Language pull-down menu.
=> Enter the design name drink_machine and leave the design directory as the
default (Figure 4-15). Warp P/E automatically creates a default working
directory with the same name as the design name.
=> Click Next to continue.
4
Figure 4-15 Entering design name dialog box.
=> Click Finish.
4.2.3
Starting the Tutorial
The opening window (Figure 4-16) shows the standard design environment with the
design flow tab selected. The design flow provides you a flow chart of the steps required
to complete a design and target a Cypress device.
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Figure 4-16 Opening window with design flow tab selected.
4.2.3.1
Adding Existing Files
Since we will be using existing design files (refill.v and binctr.v), we will be clicking on
the Add New File entry in the Design Browser section. This will bring up a file selection
dialog where you select add existing files.
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=> Double click on Add New File.
4
Figure 4-17 Add New File dialog box.
=> Click on the “Add Existing File” button to navigate to the <warp path>/
examples/wtutor/vlog directory of your Warp P/E installation and select the
binctr.v file.
=> Click on the “Add Existing File” button to navigate to the <warp path>/
examples/wtutor/vlog directory of your Warp P/E installation and select the
refill.v file as well.
If you are using Warp Professional or do not intend to perform functional simulation in
Warp Enterprise on this design, skip Section 4.2.3.2, Functional Simulation in Warp
Enterprise.
4.2.3.2
Functional Simulation in Warp Enterprise
If you are using Warp Enterprise and desire to perform functional simulation, click the
Functional Simulation button on the Design Flow Manager to launch the Aldec Simulator.
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4.2.3.3
Device Selection in Warp P/E
Performing device selection is accomplished by clicking on the Device button on the
Design Flow manager.
This will bring up the Warp Select Device dialog box (Figure 4-18).
4
Figure 4-18 Cypress Select Device dialog box.
=> In the left frame, navigate to Ultra37000 and select c37032.
=> In the right frame, select 37032P44-125AC.
4.2.3.4
Setting Compiler Options in Warp P/E
You can set the synthesis options by clicking on the synthesis options button in the Design
Flow manager. This brings up the Warp Compiler Options dialog box (Figure 4-19 and
Figure 4-20), used to set synthesis goals and options, plus control the amount of
information that Warp presents in the report file.
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Figure 4-19 Compiler Options dialog box with Synthesis tab
selected.
4
Figure 4-20 Compiler Options dialog box with Messaging tab
selected.
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4.2.3.5
Compiling the Design
After setting the synthesis options, the design can be compiled and targeted by clicking the
Implementation button. This will bring up the Select top-level file and design unit dialog
box, where you select refill.v as the top-level entity.
4
Figure 4-21 Select top level file and design unit dialog box.
=> Select refill.v as the top-level file.
=> Type in refill.v as the top-level unit.
=> Click OK.
You can watch the progress of the compilation in the Console window. A successful
compilation is shown in Figure 4-22.
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Figure 4-22 Successful compilation result in the Console window.
4
Note – If any errors occur, you can double-click on the error message
in the console window and the source file will open with the relevant
line highlighted.
4.2.3.6
Viewing the Report File
To access the report file, click on the Reports button in the Design Flow Manager. This
will open the report file in the Editor window. You can than examine the design
implementation in detail.
4.2.3.7
Timing Simulation in Warp P/E
To perform post-fit simulation of the design, click on the Timing Simulation button in the
Design Flow manager. This will launch the Aldec simulator and allow you to perform
post-fit simulation as outlined in Section 2.2.14, Setting Stimulus Signal Values.
4.2.3.8
Additional Information
For additional tutorials, see Chapter 3, Delta39K and Quantum38K Tutorials.
For further information on the Cypress Design Flow Manager, see the online
documentation included with Warp P/E.
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Chapter
5
PSI Device Tutorial
5
PSI Device Tutorial
VHDL PSI Device (CYP25G01K100) Tutorial
The following tutorials will guide you through the steps in instantiating the SERDES
component of the 25G01 PSI device using VHDL or Verilog in Warp Release 6.3. The
tutorial will also show how the SERDES input signals can be used to control the operation
of the SERDES and how to obtain and process the data received from or transmitted by
the SERDES.
The tutorials are fit into a 25G01 PSI device, but the tasks are applicable for all PSI
devices (25G01, 15G04). For the PSI devices not targeted in this chapter, instantiate the
appropriate template from the Templates menu. More information on the LPM and RTL
packages can be found in User’s Guide, Chapter 5, LPM & RTL Modules.
To run this tutorial, Warp 6.3 must be installed.
5.1
5
Designing with the 25G01 PSI Device (VHDL)
In this design, you will complete the following tasks:
238
•
Instantiate a SERDES component using VHDL
•
Create a set of counters to provide the inputs to the 16-bit transmit side of the SERDES
•
Create a signal that will control the data output to the PSI device pins
•
Fit the design into a 25G01 PSI device
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5
Figure 5-1 Block Diagram of the 25G01 PSI Device
5.1.1
Design Description
This design describes a simple SERDES application for a PSI device that transmits the
output of four side-by-side 4-bit counters as an input to the SERDES. At the SERDES
receiving end, the received data may be output externally or cleared. Both the inputs to the
SERDES and the outputs from the SERDES will be registered.
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5.1.2
Design Solution
Counter
block
FIFO_RSTB
RESETB
PWRDNB
LOCKREFB
FIFO_ERR
RXD[15:0]
RESET_RXD
LOOPA
LOOP_TIME
LINELOOP_EN
DIAGLOOP_EN
TEST_EN
REFCLK_N
REFCLK_P
5
TXD[15:0]
TXCLK
LFIB
FIFO_RSTB
RESETB
POWERDNB
LOCKREFB
FIFO_ERR
Rxdata
register
Lineloop
Diagloop
Control
RXD[15:0]
RXCLK
SERDES
block
SERIAL_IN_P
SERIAL_IN_N
SD
SERIAL_OUT_P
SERIAL_OUT_N
SERIAL_IN_P
SERIAL_IN_N
SD
SERIAL_OUT_P
SERIAL_OUT_N
LOOPA
LOOP_TIME
LINELOOP
DIAGLOOP
REFCLK_N
REFCLK_P
Figure 5-2 Block diagram of the design.
The 16-bit transmit data is generated by four 4-bit counters. The 4-bit counters are
incremented at every transmit clock cycle and wraps around to "0000" after reaching the
maximum count value of "1111". When a line fault is detected on the receiver, the
SERDES output signal lfib is set to '0' and the data sequence "1111111100000000" is
transmitted instead of the counter outputs.
On the receive side, the design input signal reset_rxd controls whether the received data
bits are reset. When reset_rxd is '1', all 16-bits of received data are set to '0'. Otherwise, it
is left as is. The received data is then passed to the output pins of the PSI device.
Also, when test mode is enabled (test_en = '1'), both line loopback and diagnostic
loopback are enabled. The user may also specify these two loopback modes externally
through the lineloop_en and diagloop_en input ports.
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5.1.3
Starting Warp Applications
=> On Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 ->
Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as
galaxy<CR>, from within a shell window.
5.1.4
Creating A New Project
Start Galaxy. Refer to Section 5.1.3 for information on starting applications on your
platform.
1.
Select File -> New.
2.
Select Project [Target-Device] and click on OK, shown in Figure 5-3 below.
5
Figure 5-3 New text file and project dialog box.
3.
Select VHDL as the Project Type.
4.
Enter the name of the project as psi_serdes.
5.
Enter the project path as follows.
=> On the PC, enter c:\wtutor\vhdl\psi_serdes.
=> On UNIX systems, enter <user_home_directory_path>/wtutor/vhdl/psi_serdes.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
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devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which shows the following hierarchy: Device family (SPLD, CPLD, etc.), device subfamily (PSI, Delta39K, Quantum38K, Ultra37000, Flash, MAX, etc.), device name and
package type. The user can traverse the device tree. On the left frame of the dialog box are
the Devices available and on the right frame are the Packages available for the device
selected.
5
Figure 5-4 Select Target Device dialog box with Cypress PLDs in
tree form.
7.
Navigate the tree to CPLD -> PSI -> c25g01k100 in the left frame.
8.
Highlight the CYP25G01K100V1-MGC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
psi_serdes.pfg which is now located in the c:\wtutor\vhdl\psi_serdes directory.
5.1.5
Creating the VHDL File
1.
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Select File -> New.
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2.
Select "Text File".
3.
Click OK.
4.
Select File -> Save and save the file as psi_serdes.vhd. Saving the file now allows
you to see the color coding of the keywords in the Galaxy editor.
Note – You can also create a new text file by clicking on the "New
Text File" button on the project toolbar (
).
This brings up the Galaxy editor (Figure 5-5) where you enter your
VHDL code.
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Figure 5-5 Blank Galaxy editor window.
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5.1.6
The psi_serdes VHDL description
The psi_serdes VHDL description is written in three parts:
•
A library section which lists the libraries that can be used by the entity and architecture
•
The entity declaration declares the name, ports, and data type of each port of the
component
•
The architecture declaration describes the behavior of the component
The following pages briefly discuss the contents of these sections of the VHDL
description. For a detailed explanation on these VHDL constructs, please refer to the
textbook VHDL for Programmable Logic included in your software kit.
5.1.6.1
Including the Libraries
=> Type these lines at the beginning of the VHDL document:
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.rtlpkg.all;
use cypress.std_arith.all;
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These lines advise the compiler to link to the IEEE 1164 VHDL library and the default
work library in Warp. These libraries define the various types, modes, and VHDL
constructs used in the VHDL code. The library and use VHDL reserved words instruct the
compiler to include pre-defined libraries in compiling the selected VHDL code. For
details on the std_logic_1164 and std_arith packages, see the VHDL book in the Warp
online help.
5.1.6.2
Writing the Entity Declaration
=> Type the following lines into your VHDL text editor:
entity PSI is port(
-- reference differential clock
refclk_p, refclk_n: in std_logic;
-- serial differential input
serial_inn, serial_inp: in std_logic;
-- signal detect
sd: in std_logic;
-- synchronous reset for 16-bit receive data
reset_rxd: in std_logic;
-- control signal, enables test mode
test_en: in std_logic;
-- enables line loop on serial transmit data
lineloop_en: in std_logic;
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-- enables diagnostic loopback of transmit data
diagloop_en: in std_logic;
-- Lock to Reference clock select
lockrefb: in std_logic;
-- FIFO reset
fifo_rstb: in std_logic;
-- Loop Timing mode select
loop_time: in std_logic;
-- line loopback mode (non-retimed data) enable
loopa: in std_logic;
-- all logic circuit reset
resetb: in std_logic;
-- Power down enable
pwrdnb: in std_logic;
-- FIFO error status
fifo_err: out std_logic;
-- serial differential output
serial_outn, serial_outp: out std_logic;
-- 16-bit receive data output to pins
rxdata_out: out std_logic_vector (15 downto 0)
);
end PSI;
The entity declaration declares the name, direction, and data type of each port of the
component. The entity declaration declares that entity PSI has nineteen external
interfaces, or ports. It has fifteen input ports of type std_logic, named refclk_p, refclk_n,
serial_inn, serial_inp, sd, reset_rxd, test_en, lineloop_en , diagloop_en, lockrefb,
fifo_rstb, loop_time, loopa, resetb, and pwrdnb. It has three output ports of type
std_logic, named serial_outn, serial_outp and fifo_err. It has one output port of type
std_logic_vector, named rxdata_out.
5.1.6.3
Writing the Architecture
=> Type the following lines into your VHDL text editor after your entity
declaration:
architecture PSI_arch of PSI is
The architecture portion of a VHDL description describes the behavior of the component
and always appears after the entity description. The first line declares an architecture
named PSI_arch of entity PSI.
Create fivesignals (txdata, txdata_out, rxdata_in, rxdata, rxdata_reg) of 16-bit wide
std_logic_vector type to represent the values of the transmitted and received data at
different stages of processing in the programmable logic. Then create two signals (txclk,
rxclk) of type std_logic to represent the transmit and receive clocks respectively. Also
create three signals (linedown, diagloop_sel, lineloop_sel) of type std_logic to represent
three control signals to be used. After the last signal declaration, type in 'begin'. The begin
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that follows the signal declaration marks the start of the architecture body. All constant
and signal declarations in the architecture of the VHDL code should precede the begin
statement.
The resulting text should be as follows:
-- 16-bit transmit data generated by counters in macrocell register
signal txdata: std_logic_vector (15 downto 0);
-- 16-bit transmit data registered output to SERDES
signal txdata_out: std_logic_vector (15 downto 0);
-- 16-bit receive data registered input from the SERDES
signal rxdata_in: std_logic_vector (15 downto 0);
-- 16-bit receive data input to macrocell register
signal rxdata: std_logic_vector (15 downto 0);
-- 16-bit processed receive data output from macrocell register
signal rxdata_reg: std_logic_vector (15 downto 0);
-- transmit and receive clocks
signal txclk, rxclk: std_logic;
-- diagloop control signal
signal diagloop_sel: std_logic;
-- lineloop control signal
signal lineloop_sel: std_logic;
-- line fault indicator signal
signal linedown:std_logic;
begin
5
Once this is completed, paste in the SERDES instantiation by selecting
'CYPSI2GSERDES' from the "Templates" menu located on the toolbar. For more
information about how to instantiate LPM modules, please refer to Chapter 5, LPM in the
User's Guide.
Once pasted, you will need to connect the various SERDES ports to your own signals in
your design. An example mapping is as follows:
U1: cy_2gserdes
port map(
txd
fifo_rstb
loop_time
diagloop
loopa
lineloop
resetb
pwrdnb
lockrefb
refclk_n
refclk_p
serial_in_n
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=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
txdata_out,
fifo_rstb,
loop_time,
diagloop_sel,
loopa,
lineloop_sel,
resetb,
pwrdnb,
lockrefb,
refclk_n,
refclk_p,
serial_inn,
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serial_in_p
sd
serial_out_n
serial_out_p
fifo_err
txclk
rxd
rxclk
lfib
=>
=>
=>
=>
=>
=>
=>
=>
=>
serial_inp,
sd,
serial_outn,
serial_outp,
fifo_err,
txclk,
rxdata_in,
rxclk,
linedown
);
Input signals to the SERDES may be generated by logic configured into the PSI device. To
illustrate this, we create logic to generate the signals controlling the line loopback and
diagnostic loopback modes. Line loopback mode is enabled when the device is in test
mode (test_en = '1') or when the user specifically requests the line loopback mode
(lineloop_en = '1'). Likewise, diagnostic loopback mode is enabled when the device is in
test mode (test_en = '1') or when the user specifically requests the diagnostic loopback
mode (diagloop_en = '1').
The resulting code should be as follows:
lineloop_sel <= lineloop_en or test_en;
diagloop_sel <= diagloop_en or test_en;
Next, we create a process that generates the transmit data to the SERDES at every rising
transmit clock edge. We use an if-then-else statement to describe the selection. If a line
fault is detected (linedown = '0'), the transmitted data is set to
"1111111100000000". Otherwise, the value of each of the four 4-bit counters represented
by txdata is incremented by 1. The resulting code listing should appear as follows:
process (txclk)
begin
if (txclk'event and txclk='1') then
if (linedown = '0') then
txdata <= "1111111100000000";
else
txdata(15 downto 12) <= txdata(15 downto 12)+1;
txdata(11 downto 8) <= txdata(11 downto 8)+1;
txdata(7 downto 4) <= txdata(7 downto 4)+1;
txdata(3 downto 0) <= txdata(3 downto 0)+1;
end if;
end if;
end process;
Next, we create a process that passes txdata when a rising edge appears on the transmit
clock. The code should appear as follows:
process (txclk)
begin
if (txclk'event and txclk='1') then
txdata_out <= txdata;
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end if;
end process;
Similarly, we create a process that registers the SERDES output rxdata when a rising edge
appears on the receive clock. The code should appear as follows:
process (rxclk)
begin
if (rxclk'event and rxclk='1') then
rxdata <= rxdata_in;
end if;
end process;
Next, we create a process the allows the data received from the SERDES to be reset before
output to the PSI device pins. A synchronous reset signal reset_rxd is accessible to the
user through the entity declaration. When a rising clock edge is detected on the receive
clock, we use an if-then-else statement to set the output to all zeroes when reset_rxd = '1'.
Otherwise, pass the received data to the output. The code should appear as follows:
process (rxclk)
begin
if (rxclk'event and rxclk='1') then
if (reset_rxd = '1') then
rxdata_reg <= (others => '0');
else
rxdata_reg <= rxdata;
end if;
end if;
end process;
5
Lastly, we create a process to register the receive data output on the PSI device output
pins. The code should appear as follows:
process (rxclk)
begin
if (rxclk'event and rxclk='1') then
rxdata_out <= rxdata_reg;
end if;
end process;
Finally, add end arch PSI_arch; to the last line to denote the end of the architecture
declaration.
Select File -> Save and save the file as psi_serdes.vhd.
5.1.7
Selecting Files for Compilation
After the file is created, it needs to be added to the project. Galaxy has a Preferences menu
item under the Edit menu that allows you to set the design file extensions. These
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extensions are used to identify VHDL files. For VHDL projects, the default file name
extensions are: .vhd and .vh.
5.1.7.1
To add a VHDL file:
1.
Use the menu item Project -> Add Files.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the psi_serdes.vhd file and click Add.
4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
5
Figure 5-6 Dialog box to select files to compile.
5.1.8
Setting the Top-Level File
Once psi_serdes.vhd has been added into the project, a top level file can be set. Only the
top-level files is actually synthesized, and only one top-level file is allowed in a project.
=> Click on psi_serdes.vhd.
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=> Select Project -> Set Top or click on the Set Top button available on the project
toolbar.
=> Once the top-level file has been set, the file symbol marker in the hierarchy will
have a tree symbol (Figure 5-7).
5
Figure 5-7 Galaxy window showing psi_serdes.vhd as the top-level
design.
Note – In order to set the top-level file, you must select the file in the
Source tab in the Project sub-window, as shown in Figure 5-7.
5.1.9
Creating the Control File
A designer may write a set of instructions for the place and route tool to follow during
synthesis. These instructions are written in a control file that contains synthesis directives.
The control file contains instructions (or directives) for the fitter to optimize the speed of
the PSI design.
250
1.
From the main menu, select File -> New.
2.
Select "Text File".
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3.
Click OK.
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Note – You can also create a new text file by clicking on the "New Text
File" button on the project toolbar (
).
Note – A detailed description of synthesis directives and the control
file is available in Chapter 3 and Chapter 4 of the Warp User’s Guide.
An application note entitled “Designing with the Programmable Serial
Interface (PSI) for High-Speed Solutions” is available on the Cypress
CD in the doc folder. The application note contains information on
using synthesis directives specifically for high-speed PSI designs.
This brings up the Galaxy editor where you can enter your synthesis directives.
Enter the following lines in the Galaxy editor.
-- These lines instruct the Warp fitter to register
-- the txdata_out, rxdata_out, and rxdata_in signals
-- at I/O or standard datapath cells.
attribute output_reg of txdata_out:signal is ioreg_duplicate;
attribute output_reg of rxdata_out:signal is ioreg_duplicate;
attribute input_reg of rxdata_in:signal is ioreg_iocell ;
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-- These lines instruct the Warp fitter to place
-- the txdata and rxdata_reg signals in specific
-- clusters in the PSI architecture.
attribute lab_force of txdata(*):signal is "C(0,3)A" ;
attribute lab_force of rxdata_reg(*):signal is "C(0,1)A" ;
-- These lines assign
-- pin numbers in the
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
rxdata_out(0 to 15) to specific
PSI architecture.
of rxdata_out(0) is "C1";
of rxdata_out(1) is "D1";
of rxdata_out(2) is "E1";
of rxdata_out(3) is "F1";
of rxdata_out(4) is "G1";
of rxdata_out(5) is "H1";
of rxdata_out(6) is "J1";
of rxdata_out(7) is "K1";
of rxdata_out(8) is "L1";
of rxdata_out(9) is "M1";
of rxdata_out(10) is "D2";
of rxdata_out(11) is "E2";
of rxdata_out(12) is "F2";
of rxdata_out(13) is "G2";
of rxdata_out(14) is "H2";
of rxdata_out(15) is "J2";
Now, save the file as psi_serdes.ctl and place it in the project directory.
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Note – The design control file needs to have the same name as the toplevel file, with a .ctl extension for the Warp fitter to locate it during
compilation.
5.1.10
Compiling and Synthesizing a Top-Level File
The next sequence of steps will guide you through the process of producing a HEX file for
a specific target device, in this case, a CYP25G01K100.
5.1.11
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
5
Figure 5-8 The Compiler Options dialog box for Delta39K devices.
5.1.11.1
Setting Unused Outputs
All unused output pins that have unused I/Os are hardwired to high 'Z', leaving all unused
I/O pins to be three-stated. The ability to choose '1' or '0' will be incorporated in a future
release.
5.1.11.2
Choosing Tech Mapping Options
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=> Under the Logic to Memory Mapping options in the Synthesis tab, one of three
options is available: Disable, Area, and Speed. Use the default option Disable,
with a Node Cost of 3.
Warp can optionally pack logic into memory and optimize for either area or speed. Use the
default option, optimize for Speed. There are a few other useful options in the Tech
Mapping options, which are explained in the Galaxy online help, accessible from the
Galaxy Help menu.
5.1.11.3
Choosing a Timing Model
On the PC platforms, Warp includes the Active-HDL Sim timing simulator. You can verify
the synthesized design using Active-HDL Sim by creating the Active-HDL Sim timing
model of the design using Warp.
The psi_serdes.vhd file should be compiled with the Active-HDL Sim timing model
before using Active-HDL Sim.
=> Click on the Timing Model drop-down menu in the Simulation area.
5
=> Select Active-HDL Sim.
=> Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
5.1.12
Compiling and Synthesizing the File
=> In your Galaxy window, select Compile -> Project to begin compilation click
the Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a CYP25G01K100 and prints
messages to keep you appraised of its progress in the Results sub-window. The Compile > Project option automatically recompiles only those files which have been modified since
the last compilation. During compilation, Warp locates the control file (if it exists) in the
project directory and interprets the synthesis directives.
This operation generates two files of particular interest:
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•
psi_serdes.hex: This file is used to program a CYP25G01K100 device.
•
psi_serdes.rpt: This text file contains pinout and timing information, along with other
information about the final synthesized design. You can see the .rpt file and the output
files created by Warp by clicking on the output view tab in the Project sub-window.
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Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
For more information on what is contained in a report file, refer to the Report File book
located in the Warp online help.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it. Go to the VHDL editor window.
The cursor should be positioned on the line that caused the error. Use the Next
and Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
psi_serdes.vhd file is entered exactly as shown earlier in this chapter, or
copy the file from the <warp path>\examples\wtutor\vhdl directory, and
then run the Warp compiler again.
5
Figure 5-9 View of the output files in the Project sub-window.
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5.1.13
Final code for psi_serdes.vhd
library ieee;
use ieee.std_logic_1164.all;
library cypress;
use cypress.rtlpkg.all;
use cypress.std_arith.all;
entity PSI is port(
-- reference differential clock
refclk_p, refclk_n: in std_logic;
-- serial differential input
serial_inn, serial_inp: in std_logic;
-- signal detect
sd: in std_logic;
-- synchronous reset for 16-bit receive data
reset_rxd: in std_logic;
-- control signal, enables test mode
test_en: in std_logic;
-- enables line loop on serial transmit data
lineloop_en: in std_logic;
-- enables diagnostic loopback of transmit data
diagloop_en: in std_logic;
-- Lock to Reference clock select
lockrefb: in std_logic;
-- FIFO reset
fifo_rstb: in std_logic;
-- Loop Timing mode select
loop_time: in std_logic;
-- line loopback mode (non-retimed data) enable
loopa: in std_logic;
-- all logic circuit reset
resetb: in std_logic;
-- Power down enable
pwrdnb: in std_logic;
-- FIFO error status
fifo_err: out std_logic;
-- serial differential output
serial_outn, serial_outp: out std_logic;
-- 16-bit receive data output to pins
rxdata_out: out std_logic_vector (15 downto 0)
5
);
end PSI;
architecture PSI_arch of PSI is
-- 16-bit transmit data generated by counters in macrocell register
signal txdata: std_logic_vector (15 downto 0);
-- 16-bit transmit data registered input to SERDES
signal txdata_out: std_logic_vector (15 downto 0);
-- 16-bit receive data registered at I/O cell
signal rxdata_in: std_logic_vector (15 downto 0);
-- 16-bit receive data input to macrocell register
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signal rxdata: std_logic_vector (15 downto 0);
-- 16-bit processed receive dataoutput from macrocell register
signal rxdata_reg: std_logic_vector (15 downto 0);
-- transmit and receive clocks
signal txclk, rxclk: std_logic;
-- diagloop control signal
signal diagloop_sel: std_logic;
-- lineloop control signal
signal lineloop_sel: std_logic;
-- line fault indicator signal
signal linedown:std_logic;
begin
-- instantiate the SERDES
U1: cy_2gserdes
port map(
txd
=> txdata_out,
fifo_rstb
=> fifo_rstb,
loop_time
=> loop_time,
diagloop
=> diagloop_sel,
loopa
=> loopa,
lineloop
=> lineloop_sel,
resetb
=> resetb,
pwrdnb
=> pwrdnb,
lockrefb
=> lockrefb,
refclk_n
=> refclk_n,
refclk_p
=> refclk_p,
serial_in_n => serial_inn,
serial_in_p => serial_inp,
sd
=> sd,
serial_out_n => serial_outn,
serial_out_p => serial_outp,
fifo_err
=> fifo_err,
txclk
=> txclk,
rxd
=> rxdata_in,
rxclk
=> rxclk,
lfib
=> linedown
);
5
-- process the diagloop and lineloop control signals
lineloop_sel <= lineloop_en or test_en;
diagloop_sel <= diagloop_en or test_en;
-- Generate transmit data from counter output when rising transmit clock edge occurs
process (txclk)
begin
if (txclk'event and txclk='1') then
if (linedown = '0') then
txdata <= "1111111100000000";
else
txdata(15 downto 12) <= txdata(15 downto 12) + 1;
txdata(11 downto 8) <= txdata(11 downto 8) + 1;
txdata(7 downto 4) <= txdata(7 downto 4) + 1;
txdata(3 downto 0) <= txdata(3 downto 0) + 1;
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end if;
end if;
end process;
-- register transmit data before output to SERDES
process (txclk)
begin
if (txclk'event and txclk='1') then
txdata_out <= txdata;
end if;
end process;
-- register receive data input from SERDES
process (rxclk)
begin
if (rxclk'event and rxclk='1') then
rxdata <= rxdata_in;
end if;
end process;
-- register and process receive data at a macrocell
process (rxclk)
begin
if (rxclk'event and rxclk='1') then
if (reset_rxd = '1') then
rxdata_reg <= (others => '0');
else
rxdata_reg <= rxdata;
end if;
end if;
end process;
5
-- register processed receive data before output to PSI pins
process (rxclk)
begin
if (rxclk'event and rxclk='1') then
rxdata_out <= rxdata_reg;
end if;
end process;
end PSI_arch;
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Verilog PSI Device (CYP25G01K100) Tutorial
This tutorial will guide you through the steps in instantiating the SERDES component of
the PSI device using Verilog in Warp. The tutorial will also show how the SERDES input
signals can be used to control the operation of the SERDES and how to obtain and process
the data received from or transmitted by the SERDES.
5
Figure 5-10 Block Diagram of a SERDES
5.2
Designing with the 25G01 PSI Device (Verilog)
In this design, you will complete the following tasks:
260
•
Instantiate a SERDES component using Verilog
•
Create a set of counters to provide the inputs to the 16-bit transmit side of the SERDES
•
Create a signal that will control the data output to the PSI device pins
•
Fit the design into a CYP25G01K100
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5.2.1
Design Description
This design describes a simple SERDES application for a PSI device that transmits the
output of four side-by-side 4-bit counters as an input to the SERDES. At the SERDES
receiving end, the received data may be output externally or cleared. Both the inputs to
the SERDES and the outputs from the SERDES will be registered.
5.2.2
Design Solution
Counter
block
FIFO_RSTB
RESETB
PWRDNB
LOCKREFB
FIFO_ERR
RXD[15:0]
RESET_RXD
LOOPA
LOOP_TIME
LINELOOP_EN
DIAGLOOP_EN
TEST_EN
REFCLK_N
REFCLK_P
TXD[15:0]
TXCLK
LFIB
FIFO_RSTB
RESETB
POWERDNB
LOCKREFB
FIFO_ERR
Rxdata
register
Lineloop
Diagloop
Control
RXD[15:0]
RXCLK
SERDES
block
SERIAL_IN_P
SERIAL_IN_N
SD
SERIAL_OUT_P
SERIAL_OUT_N
SERIAL_IN_P
SERIAL_IN_N
SD
SERIAL_OUT_P
SERIAL_OUT_N
5
LOOPA
LOOP_TIME
LINELOOP
DIAGLOOP
REFCLK_N
REFCLK_P
Figure 5-11 Block diagram of the design.
The 16-bit transmit data is generated by four 4-bit counters. The 4-bit counters are
incremented at every transmit clock cycle and wraps around to "0000" after reaching the
maximum count value of "1111". When a line fault is detected on the receiver, the
SERDES output signal lfib is set to '0' and the data sequence "1111111100000000" is
transmitted instead of the counter outputs.
On the receive side, the design input signal reset_rxd controls whether the received data
bits are reset. When reset_rxd is '1', all 16-bits of received data are set to '0'. Otherwise, it
is left as is. The received data is then passed to the output pins of the PSI device.
Also, when test mode is enabled (test_en = '1'), both line loopback and diagnostic
loopback are enabled. The user may also specify these two loopback modes externally
through the lineloop_en and diagloop_en input ports.
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5.2.3
Starting Warp Applications
=> On Windows platforms, start Warp by clicking on Start -> Programs -> Cypress
-> Warp R6.3 -> Galaxy.
=> On UNIX systems, start Warp by typing the application name, such as galaxy
<CR>, from within a shell window.
5.2.4
Creating a New Project
1.
From the menu, select File -> New.
2.
Select Project [Target - Device] and click on OK.
5
Figure 5-12 New text file and project dialog box.
3.
Select Verilog as the Project Type.
4.
Enter the name of the project as psi_serdes.
5.
Enter the project path as follows
=> On the PC, enter c:\wtutor\vlog\psi_serdes
=> On UNIX systems, enter <user_home_directory_path>/wtutor/vlog/psi_serdes
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of Verilog files into the current project. Skip this dialog box and click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
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The Select Target Device wizard dialog box displays all the cypress PLDs in a tree form
which shows the following hierarchy: Device family (PSI, CPLD, etc.) device sub-family
(Delta 39K, Quantum 38K, etc.), device name and package type. The user can traverse the
device tree. On the left frame of the dialog box are the Devices available and on the right
frame are the packages available for the device selected.
5
Figure 5-13 Select Target Device dialog box with Cypress PLDs in
tree form.
7.
In the Device list of the dialog box, navigate the tree to PSI ->c25g01k100.
8.
In the Package list of the dialog box, highlight CYP25G01K100V1-MGC.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
psi_serdes.pfg which is now located in the c:\wtutor\vlog\psi_serdes directory.
5.2.5
Creating the Verilog file
1.
From the menu, select File -> New.
2.
Select "Text File".
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3.
Click OK.
Note – You can also create a new text file by clicking on the "New Text
File" button on the project toolbar.
This brings up the Galaxy editor where you enter your Verilog code.
5
Figure 5-14 Blank Galaxy window.
5.2.6
The psi_serdes Verilog Description
The psi_serdes Verilog description begins with the module definition. The module
definition names the design and identifies the I/O ports used. This is followed by an
assignment of the direction of the ports defined in the module definition. After the module
definition is the body of the Verilog code where the behavior of the module is detailed.
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5.2.6.1
Module Definition
Enter these lines at the beginning of the Verilog document:
module PSI (refclk_p, refclk_n, serial_inn, serial_inp, sd,
serial_outn, serial_outp,
rxdata_out, reset_rxd, test_en, lineloop_en, diagloop_en, lockrefb, fifo_rstb,
loop_time, loopa, resetb, pwrdnb, fifo_err);
// reference differential clock
input refclk_p,refclk_n;
// serial differential input
input serial_inn, serial_inp;
// signal detect
input sd;
// synchronous reset for receive data output
input reset_rxd;
// test mode enable
input test_en;
// line loopback mode enable
input lineloop_en;
// diagnostic loopback mode enable
input diagloop_en;
// lock to reference clock select
input lockrefb;
// FIFO reset
input fifo_rstb;
// Loop timing mode select
input loop_time;
// line loopback mode (non-retimed data) select
input loopa;
// all logic circuit reset
input resetb;
// power down enable
input pwrdnb;
// FIFO error status
output fifo_err;
// differential serial output
output serial_outn, serial_outp;
// 16-bit receive data output to pins
output [15:0] rxdata_out;
// 16-bit receive data output to pins
5
These lines define the PSI module as having nineteen ports. Following the module
declaration, each of the ports are defined as an input, output or inout port. The module
called PSI has fifteen input ports of type std_logic, named refclk_p, refclk_n, serial_inn,
serial_inp, sd, reset_rxd, test_en, lineloop_en , diagloop_en, lockrefb, fifo_rstb,
loop_time, loopa, resetb, and pwrdnb. It has three output ports of type std_logic, named
serial_outn, serial_outp and fifo_err. It has one output port of type std_logic_vector,
named rxdata_out.
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5.2.6.2
Writing the Behavior of the PSI module
First, we create six 16-bit regs (txdata, txdata_out, rxdata_in, rxdata, rxdata_reg,
rxdata_out) to represent the values of the transmitted and received data at different stages
of processing in the programmable logic. Regs are temporary variables used to keep track
of signals used in the always procedural block.
// 16-bit transmit data generated by counters in macrocell register
reg [15:0] txdata;
// 16-bit registered transmit data input to SERDES
reg [15:0] txdata_out;
// 16-bit receive data input from SERDES, registered at I/O cell
reg [15:0] rxdata_in;
// 16-bit receive data, input to macrocell register
reg [15:0] rxdata;
// 16-bit receive data, output from macrocell register
reg [15:0] rxdata_reg;
// 16-bit receive data output to pins
reg [15:0] rxdata_out;
Then, declare the wires. Wires represent a physical connection (or a signal) between
components. First, create two wires (txclk, rxclk) to represent the transmit and
receive clocks respectively. Then create three more wires (linedown,
diagloop_sel, lineloop_sel) to represent three control signals to be used.
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// line fault indicator
wire linedown;
// transmit and receive clocks
wire txclk, rxclk;
// external select for diagnostic loopback mode
wire diagloop_sel;
// external select for line loopback mode
wire lineloop_sel;
Now, instantiate the SERDES. To instantiate the SERDES, paste in the SERDES
instantiation by selecting 'CY2GSERDES' from the "Templates" menu located on the
toolbar. For more information about how to instantiate LPM modules, please refer to
Chapter 5, LPM in the User's Guide.
Once pasted, you will need to connect the various SERDES ports to your own signals in
your design. An example mapping is as follows:
cy_2gserdes U0(
.txd
.fifo_rstb
.loop_time
.diagloop
.loopa
.lineloop
.resetb
.pwrdnb
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(txdata_out),
(fifo_rstb),
(loop_time),
(diagloop_sel),
(loopa),
(lineloop_sel),
(resetb),
(pwrdnb),
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.lockrefb
.refclk_n
.refclk_p
.serial_in_n
.serial_in_p
.sd
.serial_out_n
.serial_out_p
.fifo_err
.txclk
.rxd
.rxclk
.lfib
(lockrefb),
(refclk_n),
(refclk_p),
(serial_inn),
(serial_inp),
(sd),
(serial_outn),
(serial_outp),
(fifo_err),
(txclk),
(rxdata_in),
(rxclk),
(linedown));
Input signals to the SERDES may be generated by logic configured into the PSI device.
To illustrate this, we create logic to generate the signals controlling the line loopback and
diagnostic loopback modes. Line loopback mode is enabled when the device is in test
mode (test_en = '1') or when the user specifically requests the line loopback mode
(lineloop_en = '1'). Likewise, diagnostic loopback mode is enabled when the
device is in test mode (test_en = '1') or when the user specifically requests the
diagnostic loopback mode (diagloop_en = '1').
To describe this logic, we use the assign statement. All logic equations declared by an
assign statement are executed concurrently and their order is not important. The Verilog
code should be as follows:
assign lineloop_sel = lineloop_en | test_en;
assign diagloop_sel = diagloop_en | test_en;
Next, we create sequential blocks to generate or process the transmit and receive data.
This is done using an always procedural block. The always procedural block describes the
action of the design in response to certain stimuli. These stimuli are declared in the
sensitivity list enclosed in the parentheses following the @ symbol of the always
declaration.
First, we want to generate the transmit data to the SERDES at every rising transmit clock
edge. We use an if-else statement to describe the selection. If a line fault is detected
(linedown = '0'), the transmitted data is set to "1111111100000000". Otherwise, the
value of each of the four 4-bit counters represented by txdata is incremented by 1. The
resulting code listing should appear as follows:
always @(posedge txclk)
if (!linedown)
txdata <= 16'b111111100000000;
else
begin
txdata[15:12] <= txdata[15:12] + 1;
txdata[11:8] <= txdata[11:8] + 1;
txdata[7:4] <= txdata[7:4] + 1;
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txdata[3:0] <= txdata[3:0] + 1;
end
Secondly, we create an always block that registers the transmit data input to the SERDES
when a rising edge appears on the transmit clock. The code should appear as follows:
always @(posedge txclk)
txdata_out <= txdata;
On the receive side, first we create an always procedural block that registers the SERDES
received data output rxdata_in when a rising edge appears on the receive clock. The code
should appear as follows:
always @(posedge rxclk)
rxdata <= rxdata_in;
Next, we create another always procedural block that allows the data received from the
SERDES to be reset before output to the PSI pins. A synchronous reset signal reset_rxd is
accessible to the user through the module input declaration. When a rising clock edge is
detected on the receive clock, we use an if-then-else statement to set the output to all
zeroes when reset_rxd = '1'. Otherwise, pass the received data to the output. The code
should appear as follows:
5
always @(posedge rxclk)
if (reset_rxd)
rxdata_reg <= 16'h0000;
else
rxdata_reg <= rxdata;
Lastly, we create an always procedural block to register the receive data output on the PSI
output pins. The code should appear as follows:
always @(posedge rxclk)
rxdata_out <= rxdata_reg;
Finally, add endmodule to the last line to denote the end of the Verilog module.
endmodule
Select File -> Save and save the file as psi_serdes.v.
5.2.7
Selecting Files for Compilation
After the file is created, it needs to be added to the project.
5.2.7.1
To add a Verilog file:
1.
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Use the menu item Project -> Add Files.
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2.
Click the browse button to navigate the project directory.
3.
Highlight the psi_serdes.v file and click Add.
4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
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Figure 5-15 Dialog box to select files to add to project.
5.2.8
Setting the Top-Level File
Once psi_serdes.v has been added into the project, a top level file can be set. Only one
top-level file is allowed in a project and only the top-level file is synthesized.
1.
Click on psi_serdes.v.
2.
Select Project -> Set Top or click the Set Top button available on the project
toolbar.
3.
Once the top-level file has been set, the file symbol marker in the hierarchy will
have a tree symbol.
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Figure 5-16 Galaxy window showing psi_serdes.vhd as the top-level
in tree form.
5.2.9
Creating the Control File
A designer may write a set of instructions for the place and route tool to follow during
synthesis. These instructions are written in a control file that contains synthesis directives.
The control file contains instructions (or directives) for the fitter to optimize the speed of
the PSI design.
1.
From the main menu, select File -> New.
2.
Select "Text File".
3.
Click OK.
Note – You can also create a new text file by clicking on the "New
Text File" button on the project toolbar (
).
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Note – A detailed description of synthesis directives and the control
file is available in Chapters 3 and 4 of the Warp User’s Guide. An
application note entitled “Designing with the Programmable Serial
Interface (PSI) for High-Speed Solutions” is also available on the
Cypress CD in the doc folder. The application note contains information
on using synthesis directives specifically for high-speed PSI designs.
This brings up the Galaxy editor where you can enter your synthesis directives.
Enter the following lines in the Galaxy editor.
-- These lines instruct the Warp fitter to register
-- the txdata_out, rxdata_out, and rxdata_in signals
-- at I/O or standard datapath cells.
attribute output_reg of txdata_out:signal is ioreg_duplicate;
attribute output_reg of rxdata_out:signal is ioreg_duplicate;
attribute input_reg of rxdata_in:signal is ioreg_iocell ;
-- These lines instruct the Warp fitter to place
-- the txdata and rxdata_reg signals in specific
-- clusters in the PSI architecture.
attribute lab_force of txdata(*):signal is "C(0,3)A" ;
attribute lab_force of rxdata_reg(*):signal is "C(0,1)A" ;
-- These lines assign
-- pin numbers in the
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
attribute pin_numbers
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rxdata_out(0 to 16) to specific
PSI architecture.
of rxdata_out(0) is "C1";
of rxdata_out(1) is "D1";
of rxdata_out(2) is "E1";
of rxdata_out(3) is "F1";
of rxdata_out(4) is "G1";
of rxdata_out(5) is "H1";
of rxdata_out(6) is "J1";
of rxdata_out(7) is "K1";
of rxdata_out(8) is "L1";
of rxdata_out(9) is "M1";
of rxdata_out(10) is "D2";
of rxdata_out(11) is "E2";
of rxdata_out(12) is "F2";
of rxdata_out(13) is "G2";
of rxdata_out(14) is "H2";
of rxdata_out(15) is "J2";
Now, save the file as psi_serdes.ctl in the project directory.
Note – The design control file needs to have the same name as the toplevel file, with a .ctl extension for the Warp fitter to locate it during
compilation.
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5.2.10
Compiling and Synthesizing a Top-Level File
The next sequence of steps will guide you through the process of producing a JEDEC file
for a specific target device, in this case, a CYP25G01K100.
5.2.11
Choosing Compiler Options
Compiler options are available under the Project menu. Select Project -> Compiler
Options and select the Synthesis tab.
5
Figure 5-17 Compiler Options dialog box with Synthesis tab
selected.
5.2.11.1
Setting Unused Outputs
All unused output pins that have unused I/Os are hardwired to high 'Z', leaving all unused
I/O pins to be three-stated. The ability to choose '1' or '0' will be incorporated in a future
release.
5.2.11.2
Choosing Tech Mapping Options
Under the Logic to Memory Mapping options in the Synthesis tab, three options are
available: Disable, Area, and Speed. Use Disable, with a Node Cost of 3.
Warp can optionally pack logic into memory and optimize for either area or speed. Use
the default option, optimize for Speed. There are a few other useful options in the Tech
Mapping options, which are explained in the Galaxy online help, accessible from the
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Galaxy Help menu.
5.2.11.3
Choosing a Timing Model
On the PC platforms, Warp includes the Active-HDL Sim timing simulator. You can
verify the synthesized design using Active-HDL Sim by creating the Active-HDL Sim
timing model of the design using Warp.
The psi_serdes.v file should be compiled with the Active-HDL Sim timing model before
using Active-HDL Sim.
5.2.12
1.
Click on the Timing Model drop-down mneu in the Simulation area.
2.
Select Active-HDL Sim.
3.
Click on the OK button to accept the above selections and dismiss the Compiler
Options dialog box.
Compiling and Synthesizing the File
In your Galaxy window, select Compile -> Project to begin compilation or click on the
Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a C25G01K100 and prints
messages to keep you appraised of its progress in the Results sub-window. The Compile > Project option automatically recompiles only those files which have been modified since
the last compilation. During compilation, Warp locates the control file (if it exists) in the
project directory and interprets the synthesis directives.
This operation generates two files of particular interest:
•
psi_serdes.hex: This file is used to program a C25G01K100 device.
•
psi_serdes.rpt: This text file contains pinout and timing information, along with other
information about the final synthesized design. You can see the .rpt file and the output
files created by Warp by clicking on the output view tab in the Project sub-window.
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
For more information on what is contained in a report file, refer to the Report File book
located in the Warp online help.
If compiler error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
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window.
=> Double click on the error message to select it. Go to the Verilog editor window.
The cursor should be positioned on the line that caused the error. Use the Next
and Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of you
psi_serdes.v file is entered exactly as shown earlier in this chapter, or
copy the file from the <warp path>\examples\wtutor\vlog directory, and
then run the Warp compiler again.
5
Figure 5-18 View of the output files in the Project sub-window.
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5.2.13
Final code for psi_serdes.v.
module PSI (refclk_p, refclk_n, serial_inn, serial_inp, sd,
serial_outn, serial_outp, rxdata_out, reset_rxd, test_en,
lineloop_en, diagloop_en, lockrefb, fifo_rstb, loop_time, loopa,
resetb, pwrdnb, fifo_err);
// reference differential clock
input refclk_p,refclk_n;
// serial differential input
input serial_inn, serial_inp;
// signal detect
input sd;
// synchronous reset for receive data output
input reset_rxd;
// test mode enable
input test_en;
// line loopback mode enable
input lineloop_en;
// diagnostic loopback mode enable
input diagloop_en;
// lock to reference clock select
input lockrefb;
// FIFO reset
input fifo_rstb;
// Loop timing mode select
input loop_time;
// line loopback mode (non-retimed data) select
input loopa;
// all logic circuit reset
input resetb;
// power down enable
input pwrdnb;
// FIFO error status
output fifo_err;
// differential serial output
output serial_outn, serial_outp;
// 16-bit receive data output to pins
output [15:0] rxdata_out;
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// 16-bit transmit data generated by counters in macrocell register
reg [15:0] txdata;
// 16-bit registered transmit data input to SERDES
reg [15:0] txdata_out;
// 16-bit receive data input from SERDES, registered at I/O cell
reg [15:0] rxdata_in;
// 16-bit receive data, input to macrocell register
reg [15:0] rxdata;
// 16-bit receive data, output from macrocell register
reg [15:0] rxdata_reg;
// 16-bit receive data output to pins
reg [15:0] rxdata_out;
// line fault indicator
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wire linedown;
// transmit and receive clocks
wire txclk, rxclk;
// external select for diagnostic loopback mode
wire diagloop_sel;
// external select for line loopback mode
wire lineloop_sel;
// SERDES instantiation
cy_2gserdes U0(
.txd
.fifo_rstb
.loop_time
.diagloop
.loopa
.lineloop
.resetb
.pwrdnb
.lockrefb
.refclk_n
.refclk_p
.serial_in_n
.serial_in_p
.sd
.serial_out_n
.serial_out_p
.fifo_err
.txclk
.rxd
.rxclk
.lfib
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(txdata_out),
(fifo_rstb),
(loop_time),
(diagloop_sel),
(loopa),
(lineloop_sel),
(resetb),
(pwrdnb),
(lockrefb),
(refclk_n),
(refclk_p),
(serial_inn),
(serial_inp),
(sd),
(serial_outn),
(serial_outp),
(fifo_err),
(txclk),
(rxdata_in),
(rxclk),
(linedown));
// process the line loop and diagnostic loop control signals
assign lineloop_sel = lineloop_en | test_en;
assign diagloop_sel = diagloop_en | test_en;
// Generate transmit data from counter output when rising transmit
clock edge occurs
always @(posedge txclk)
if (!linedown)
txdata <= 16'b111111100000000;
else
begin
txdata[15:12] <= txdata[15:12] + 1;
txdata[11:8] <= txdata[11:8] + 1;
txdata[7:4] <= txdata[7:4] + 1;
txdata[3:0] <= txdata[3:0] + 1;
end
// register transmit data before output to SERDES
always @(posedge txclk)
txdata_out <= txdata;
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// register receive data input from SERDES
always @(posedge rxclk)
rxdata <= rxdata_in;
// register and process receive data at a macrocell
always @(posedge rxclk)
if (reset_rxd)
rxdata_reg <= 16'h0000;
else
rxdata_reg <= rxdata;
// register processed receive data before output to PSI pins
always @(posedge rxclk)
rxdata_out <= rxdata_reg;
endmodule
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VHDL PSI Device (CYP15G04K100) Tutorial
This tutorial will guide you through the steps of instantiating and using the SERDES
component of Cypress's Frequency Agile PSI - CYP15G04K100. The tutorial walks the
designer, step by step, through the design, implementation, and simulation of a simple
design in PSI. The entire design phase of this tutorial can be completed in Warp Release
6.3. Customers wishing to perform the simulation portion of this tutorial must have
Release 6.3 of Warp Professional or Warp Enterprise, or a third party simulator.
Brief Overview of the CYP15G04K100 Device
The PSI15G04K100 is a point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links (optical fiber, balanced,
and unbalanced copper transmission lines) at signaling speeds ranging from 200-to-1500
MBaud per serial link. The multiple channels in each device may be combined to allow
transport of wide buses across significant distances with minimal concern for offsets in
clock phase or link delay.
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Figure 5-19 PSI Diagram
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Each transmit channel accepts parallel characters in an input register, encodes each
character for transport, and converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into characters, and presents these
characters to an output register. This is shown in Figure 5-20 below.
The mode demonstrated in this tutorial is:
Tx & Rx clocked by REFCLK with encoding turned off.
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Figure 5-20 PSI Tutorial Overview Diagram
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5.3
Designing with Frequency Agile PSI
This tutorial is applicable to all Frequency Agile PSI devices, and provides an example
using the CYP15G04K100 device.
In this design, you will complete the following tasks:
•
Instantiate a SERDES in Cypress Warp software.
•
Create a set of counters to provide inputs to the Transmit side of the SERDES.
•
Fit the design to the CYP15G04K100.
•
Simulate the Control Signals.
•
Observe the output waveforms.
5.3.1
Design Description
This design describes a simple application that uses the SERDES in the CYP15G04K100.
The design transmits the output of four counters from the programmable logic portion of
the chip to the Tx side of the SERDES. This unencoded data is then serialized and output
on serial out. The serial out is then deactivated and internally looped back to the Rx side.
The received, unencoded data is then output externally.
5
5.3.2
Design Solution
5.3.2.1
Programmable Logic
The design created within the programmable logic provides stimulus for the Tx logic. For
the purposes of this Tutorial, we must create a design whose data source will guarantee
enough serial data transition density for the SERDES Receive Phase Lock Loops to
maintain lock and thus assure accurate clock data recovery. This is accomplished by
creating four counters (Txcounters 1 - 4 ). When the counters are reset, each counter is
initialized to a specific value. These values are loaded in as follows:
280
•
“111”,”00”,”111”,”00” where each set of bits correspond to each counter ( 1 - 4 ).
•
Each set of ‘1’s are counted down and each set of ‘0’s are counted up.
•
This received data is then passed to the output pins of the PSI device.
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Figure 5-21 Counter Diagram
5.3.2.2
SERDES
The SERDES function in PSI is where the unencoded data passed from the programmable
logic portion of the chip is serialized. In real world designs, this serial data would then be
passed off chip for communication purposes. For the purposes of the tutorial, however, we
will use an internal loopback of the data between the transmit and receive channels of our
chip; we will use the same data we create and transmit on our transmit channel as the input
data on our receive channel. We accomplish this by internally looping back the
SERIAL_OUT data to the SERIAL_IN signals. This loopback is enabled when the LPEN
control signal is set high. This methodology will simplify the tutorial and will eliminate
the need to create a testbench.
5.3.3
Starting Warp Applications
5.3.3.1
For Warp Users
•
On Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 -> Galaxy.
•
On UNIX systems, start Galaxy by typing the application name such, as Galaxy<CR>,
from within a shell window.
5.3.3.2
For Warp Professional Users
For information on starting Warp Professional, see Section 5.3.7, Starting Warp
Professional or Enterprise Applications.
5.3.3.3
For Warp Enterprise Users
For information on starting Warp Enterprise, see Section 5.3.7, Starting Warp Professional
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or Enterprise Applications.
5.3.4
Creating a New Design
Start Galaxy. Refer to Section 5.3.3 for information on starting applications on your
platform.
5
1.
Select File => New.
2.
Select Project [Target-Device] and click on OK, shown in Figure 5-22.
Figure 5-22 New text file and project dialog box.
3.
Select VHDL as the Project type.
4.
Enter the name of the project as PSI_15G04.
5.
Enter the project path as follows.
=> On the PC,enter c:\wtutor\vhdl\PSI_15G04.
=> On the UNIX systems, enter <user_home_directory_path>/wtutor/vhdl/
PSI_15G04.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of VHDL files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
with the following hierarchy: Device Family (SPLD, CPLD, etc), device sub-family (PSI,
Delta39K, Quantum38K, Ultra37000, Flash, MAX,etc), device name and package
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type.The user can traverse the device tree. On the left frame of the dialog box are the
devices available. On the right frame are the packages available for the device selected.
5
Figure 5-23 Select Target Device dialog box with Cypress PLDs in
tree form.
7.
Navigate the tree to CPLD => PSI => c15g04k100 in the left frame.
8.
Highlight the CYP15G04K100V1-MGC package in the right frame.
9.
Click finish to create the project.
10. Click Yes to save the project
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
PSI_15G04.pfg which is now located in the c:\wtutor\vhdl\PSI_15G04 directory.
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5.3.5
Creating the VHDL File
1.
Select File => New.
2.
Select “Text File”.
3.
Click OK.This brings up the Galaxy editor (Figure 5-24) where the VHDL code is
entered.
5
Figure 5-24 Galaxy Editor window.
Note – You can also create a new text file by clicking on the “New Text
File” button on the project toolbar.
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Note – If you would rather not type the PSI_15G04.vhd file yourself,
you can copy it from the Warp directory. The location for the
PSI_15G04.vhd file is <warp path>\examples\wtutor\vhdl. From
this location, copy PSI_15G04.vhd to your project directory. Then,
read along for the next several pages to help understand the purpose of
each section of a VHDL source file.
5.3.6
The Code Description
The PSI VHDL file is written in three parts:
•
A library section which lists the libraries that will be used by the entity and
architecture.
•
The entity declaration declares the name, ports, and data type of each port of the
design.
•
The architecture declaration describes the behavior of the design.
The following pages briefly discuss the contents of these sections of the VHDL
description. For a detailed explanation on these VHDL constructs, please refer to the
textbook VHDL for Programmable Logic included in your software kit.
5.3.6.1
5
Including the libraries
=> Type these lines at the beginning of the VHDL document
library IEEE;
use IEEE.std_logic_1164.all;
library cypress;
use cypress.rtlpkg.all;
use cypress.std_arith.all;
These lines enable the compiler to link the above libraries to a default work directory.
These libraries define the various types, modes, and VHDL constructs used in the VHDL
code. For details on the std_1164, RTL and std_arith packages, see Chapter 1, VHDL in
the Language Reference Manual.
5.3.6.2
Writing the Entity Declaration
The entity declaration declares the name, direction, and data type of each port of the
design.
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Figure 5-25 SERDES Overview Diagram
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The following code should be placed directly after the library declarations.
entity psi is
port (
--To LOGIC, Optional, as needed by design
txpera
:out std_logic;
txperb
:out std_logic;
txperc
:out std_logic;
txperd
:out std_logic;
--Top level, Required
txclka
:in std_logic;
txclko_p
:out std_logic;
txrate
:in std_logic;
--Top level, Required, 3 level input
txmode
:in std_logic_vector(1 downto 0);
txcksel
:in std_logic;
--Top level, Required
txrstb
:in std_logic;
--To LOGIC, Optional, as needed by design
ch_a_txdata_out :out std_logic_vector(9 downto 0);
ch_b_txdata_out :out std_logic_vector(9 downto 0);
ch_c_txdata_out :out std_logic_vector(9 downto 0);
ch_d_txdata_out :out std_logic_vector(9 downto 0);
ch_a_rxdata_out :out std_logic_vector(10 downto 0);
ch_b_rxdata_out :out std_logic_vector(10 downto 0);
ch_c_rxdata_out :out std_logic_vector(10 downto 0);
ch_d_rxdata_out :out std_logic_vector(10 downto 0);
5
--Top level, Required
rxrate
:in std_logic;
rfen
:in std_logic;
--Top level, Required, 3 level input
rxmode
:in std_logic_vector(1 downto 0);
rxcksel
:in std_logic;
framchar
:in std_logic;
rfmode
:in std_logic;
decmode
:in std_logic;
--Top level, Required
spdsel
:in std_logic;
rxclka_p
:out std_logic;
rxclkb_p
:inout std_logic;
rxclkc_p
:out std_logic;
rxclkd_p
:inout std_logic;
refclk_p
:in std_logic;
refclk_n
:in std_logic;
serial_outa1_p
:out std_logic;
serial_outb1_p
:out std_logic;
serial_outc1_p
:out std_logic;
serial_outd1_p
:out std_logic;
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serial_outa2_p
serial_outb2_p
serial_outc2_p
serial_outd2_p
serial_ina1_p
serial_inb1_p
serial_inc1_p
serial_ind1_p
serial_ina2_p
serial_inb2_p
serial_inc2_p
serial_ind2_p
serial_outa1_n
serial_outb1_n
serial_outc1_n
serial_outd1_n
serial_outa2_n
serial_outb2_n
serial_outc2_n
serial_outd2_n
serial_ina1_n
serial_inb1_n
serial_inc1_n
serial_ind1_n
serial_ina2_n
serial_inb2_n
serial_inc2_n
serial_ind2_n
insela
inselb
inselc
inseld
5
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
--Top level, Required, 3 level input
sdasel
:in std_logic;
--Top level, Required
lpen
:in std_logic;
oele
:in std_logic;
bistle
:in std_logic;
rxle
:in std_logic;
boe
:in std_logic_vector(7 downto 0);
bondst
:inout std_logic_vector(1 downto 0);
masterb
:in std_logic;
bond_all
:inout std_logic;
bond_inhb
:in std_logic;
lfiab
:out std_logic;
lfibb
:out std_logic;
lficb
:out std_logic;
lfidb
:out std_logic;
trstzb
:in std_logic;
main_clock
:in std_logic;
reset_counter
:in std_logic
);
end psi;
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5.3.6.3
Writing the Architecture
The architecture portion of a VHDL description describes the behavior of:
•
The internal signal declarations.
•
Component Declaration
•
Behavior of the Entity
The first line declares an architecture named psi_arch of entity psi.
Create 10 bit wide signals of std_logic_vector type to represent the values of the
transmitted and received data.
All constant and signal declarations in the architecture of the VHDL code should precede
the begin statement.
The resulting text should be as follows:
architecture psi_arch of psi is
signal ch_a_txdata_in
signal ch_b_txdata_in
signal ch_c_txdata_in
signal ch_d_txdata_in
signal ch_a_txdata_reg
signal ch_b_txdata_reg
signal ch_c_txdata_reg
signal ch_d_txdata_reg
signal ch_a_rxdata_reg
signal ch_b_rxdata_reg
signal ch_c_rxdata_reg
signal ch_d_rxdata_reg
signal Txcounter1
signal Txcounter2
signal Txcounter3
signal Txcounter4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(2
std_logic_vector(4
std_logic_vector(7
std_logic_vector(9
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
3);
5);
8);
After the last signal declaration, type in ‘begin’, marking the start of the architecture
body.
Once this is completed, paste in the LPM module for the 15G04 SERDES by selecting
‘CY15g04serdes’ from the “Templates” menu located on the toolbar. For more
information about how to instantiate LPM modules, please refer to Chapter 5, LPM, in the
User’s Guide.
Once pasted, the various SERDES ports need to be connected to the signals in the design.
An example mapping is as follows:
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begin
U0: cy_15g04serdes
port map(
--Main Clocks and Controls
refclk_p
=> refclk_p,
refclk_n
=> refclk_n,
bistle
=> bistle,
boe
=> boe,
trstzb
=> trstzb
--Transmit Data Parallel Channels
txrstb
=> txrstb,
txrate
=> txrate,
spdsel
=>spdsel,
txclka
=> txclka,
txcksel
=> txcksel,
txmode
=> txmode,
txclko_p
=> txclko_p,
txda
=> ch_a_txdata_reg(7
txcta
=> ch_a_txdata_reg(9
txpera
=> txpera,
txdb
=> ch_b_txdata_reg(7
txctb
=> ch_b_txdata_reg(9
txperb
=> txperb,
txdc
=> ch_c_txdata_reg(7
txctc
=> ch_c_txdata_reg(9
txperc
=> txperc,
txdd
=> ch_d_txdata_reg(7
txctd
=> ch_d_txdata_reg(9
txperd
=> txperd,
5
downto 0),
downto 8),
downto 0),
downto 8),
downto 0),
downto 8),
downto 0),
downto 8),
--Transmit Data Serial Channels
oele
=> oele,
serial_outa1_p
=> serial_outa1_p,
serial_outa1_n
=> serial_outa1_n,
serial_outa2_p
=> serial_outa2_p,
serial_outa2_n
=> serial_outa2_n,
serial_outb1_p
=> serial_outb1_p,
serial_outb1_n
=> serial_outb1_n,
serial_outb2_p
=> serial_outb2_p,
serial_outb2_n
=> serial_outb2_n,
serial_outc1_p
=> serial_outc1_p,
serial_outc1_n
=> serial_outc1_n,
serial_outc2_p
=> serial_outc2_p,
serial_outc2_n
=> serial_outc2_n,
serial_outd1_p
=> serial_outd1_p,
serial_outd1_n
=> serial_outd1_n,
serial_outd2_p
=> serial_outd2_p,
serial_outd2_n
=> serial_outd2_n,
--Receive Data Serial Channels
sdasel
=> sdasel,
lpen
=> lpen,
rxle
=> rxle,
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insela
inselb
inselc
inseld
serial_ina1_p
serial_ina1_n
serial_ina2_p
serial_ina2_n
serial_inb1_p
serial_inb1_n
serial_inb2_p
serial_inb2_n
serial_inc1_p
serial_inc1_n
serial_inc2_p
serial_inc2_n
serial_ind1_p
serial_ind1_n
serial_ind2_p
serial_ind2_n
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
insela,
inselb,
inselc,
inseld,
serial_ina1_p,
serial_ina1_n,
serial_ina2_p,
serial_ina2_n,
serial_inb1_p,
serial_inb1_n,
serial_inb2_p,
serial_inb2_n,
serial_inc1_p,
serial_inc1_n,
serial_inc2_p,
serial_inc2_n,
serial_ind1_p,
serial_ind1_n,
serial_ind2_p,
serial_ind2_n,
--Receive Data Parallel Channels
rxrate
=> rxrate,
rfen
=> rfen,
framchar
=> framchar,
rfmode
=> rfmode,
rxmode
=> rxmode,
rxcksel
=> rxcksel,
decmode
=> decmode,
rxda
=> ch_a_rxdata_out( 10 downto 3
rxsta
=> ch_a_rxdata_out(2 downto 0),
rxclka_p
=> rxclka_p,
lfiab
=> lfiab,
rxdb
=> ch_b_rxdata_out( 10 downto 3
rxstb
=> ch_b_rxdata_out(2 downto 0),
rxclkb_p
=> rxclkb_p,
lfibb
=> lfibb,
rxdc
=> ch_c_rxdata_out( 10 downto 3
rxstc
=> ch_c_rxdata_out(2 downto 0),
rxclkc_p
=> rxclkc_p,
lficb
=> lficb,
rxdd
=> ch_d_rxdata_out( 10 downto 3
rxstd
=> ch_d_rxdata_out(2 downto 0),
rxclkd_p
=> rxclkd_p,
lfidb
=> lfidb,
bondst
=> bondst,
bond_all
=> bond_all,
bond_inhb
=> bond_inhb,
masterb
=> masterb,
5
),
),
),
),
);
TX input signals to the SERDES are generated by programmable logic implemented
within the PSI device. In this design, 4 counters are created that transmit data to the
SERDES at every rising transmit clock edge. The if-then-else statements are used to reset
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the counters and place specific values in the counters from which they can count up and
down respectively. The resulting code listing is as follows:
--Counters to generate input transmit data and data fed to
--SERDES channels A, B, C and D
process(main_clock,reset_counter)
begin
if (reset_counter = '1' ) then
Txcounter1 <= "111";
Txcounter2 <= "00";
Txcounter3 <= "111";
Txcounter4 <= "00";
elsif (main_clock'event and main_clock='1') then
Txcounter1 <= Txcounter1 - 1;
Txcounter2 <= Txcounter2 + 1;
Txcounter3 <= Txcounter3 - 1;
Txcounter4 <= Txcounter4 + 1;
end if;
end process;
-- Assignment for data that is shifted in to SERDES
-- channel A
ch_a_txdata_in( 2 downto 0 ) <= Txcounter1;
ch_a_txdata_in( 4 downto 3 ) <= Txcounter2;
ch_a_txdata_in( 7 downto 5) <= Txcounter3;
ch_a_txdata_in( 9 downto 8) <= Txcounter4;
5
-- channel B
ch_b_txdata_in(
ch_b_txdata_in(
ch_b_txdata_in(
ch_b_txdata_in(
2
4
7
9
downto
downto
downto
downto
0 )
3 )
5)
8)
<=
<=
<=
<=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
-- channel C
ch_c_txdata_in(
ch_c_txdata_in(
ch_c_txdata_in(
ch_c_txdata_in(
2
4
7
9
downto
downto
downto
downto
0 )
3 )
5)
8)
<=
<=
<=
<=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
-- channel D
ch_d_txdata_in(
ch_d_txdata_in(
ch_d_txdata_in(
ch_d_txdata_in(
2
4
7
9
downto
downto
downto
downto
0 )
3 )
5)
8)
<=
<=
<=
<=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
Next, a process is created that registers txdata and passes it on to the SERDES anytime a
rising_edge appears on the receive clock. The code should appear as follows:
process(main_clock)
begin
if (main_clock'event and
ch_a_txdata_reg <=
ch_b_txdata_reg <=
ch_c_txdata_reg <=
ch_d_txdata_reg <=
292
main_clock = '1')then
ch_a_txdata_in;
ch_b_txdata_in;
ch_c_txdata_in;
ch_d_txdata_in;
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ch_a_txdata_out
ch_b_txdata_out
ch_c_txdata_out
ch_d_txdata_out
end if;
end process;
<=
<=
<=
<=
ch_a_txdata_reg;
ch_b_txdata_reg;
ch_c_txdata_reg;
ch_d_txdata_reg;
Finally add the last line to denote the end of the architecture declaration.
end psi_arch;
Select File -> Save and save file as PSI_15G04.vhd.
5.3.6.4
Selecting Files for Compilation
After the file is created, it needs to be added to the project.
5.3.6.4.1
To add a VHDL file:
1.
Use the menu item Project => Add files.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the PSI_15G04.vhd file and click Add.
4.
Click OK in the Add Files to Project dialog box.
5
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
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Figure 5-26 Dialog box to select files to compile.
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5.3.6.5
Setting the Top-Level File
Once PSI_15G04.vhd has been added into the project, a top level file can be set. Only the
top-level file is actually synthesized, and only one top-level file is allowed in a project.
=> Right click on PSI_15G04.vhd and select Project => Set Top
Once the top-level file has been set, the file symbol marker in the hierarchy will have a
tree symbol (Figure 5-27).
5
Figure 5-27 Galaxy window showing psi15g04.vhd as the top-level
design.
Note – In order to set the top-level file, you must select the file in the
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Source tab in the Project sub-window, as shown in Figure 5-27.
5.3.6.6
Compiling and Synthesizing a Top-Level File
The next sequence of steps will guide you through the process of compiling, synthesizing,
and producing a HEX programming file for a specific target device, in this case, a
CYP15G04K100.
5.3.6.7
Choosing Compiler Options
The compiler options are available under the Project menu. Select Project => Compiler
Options. Two tabs are available: Synthesis and Messaging.
5
Figure 5-28 The Compiler Options dialog box for PSI devices.
=> Select the Messaging tab.
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=> Click on Detailed Report File, if not already selected (Figure 5-28).
This report file will be available for review following successful compilation. No changes
are necessary on the Synthesis tab. For more information on setting compiler options in
the Synthesis tab, see Section 5.1.11, Choosing Compiler Options.
5.3.6.8
Compiling and Synthesizing the File.
In your Galaxy window, select Compile => Project to begin compilation or click the
Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a CYP15G04K100 and prints
messages to keep you appraised of its progress in the Results sub-window. The Compile
=> Project option automatically recompiles only those files which have been modified
since the last compilation. During compilation, Warp locates the control file (if it exists)
in the project directory and interprets the synthesis directives.
This operation generates two files of particular interest:
•
PSI_15G04.hex: This file is used to program a CYP15G04K100 device. This file is
automatically placed in the project directory.
•
PSI_15G04.rpt: This text file contains pinout and timing information, along with other
information about the final synthesized design. You can see the .rpt file and the output
files created by Warp by clicking on the output view tab in the Project sub-window.
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
For more information on what is contained in a report file, refer to Section 6.2,
Understanding the Delta39K Report File in the Warp User’s Guide.
If compile error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it. Go to the VHDL editor window.
The cursor should be positoned on the line that caused the error. Use the Next and
Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
PSI_15G04.vhd file is entered exactly as shown earlier in this chapter,
or copy the file from the <warp path>\examples\wtutor\vhdl directory,
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and then run the Warp compiler again.
Upon successful compilation, you have completed the PSI design portion of this tutorial.
Specific technical details about the PSI device can be found in the Frequency Agile PSI
datasheet and related application notes found on the Cypress website. Software related
issues are addressed in the online help topics or can be addressed by Cypress Applications
Hotline.
The next portion of this tutorial will briefly highlight the use of Warp Professional VHDL
and Warp Enterprise VHDL for design entry and compilation. In addition, the tutorial will
provide an illustrative simulation using the Frequency Agile PSI in Warp Professional
VHDL.
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5.3.7
Starting Warp Professional or Enterprise Applications
=> On Windows platform, select Start -> Programs -> Cypress -> Warp
Professional/Enterprise R6.3 -> Active HDL 4.1CY .
5.3.8
Creating a New Design
The following flow will be identical in either Warp Professional or Warp Enterprise.
Start Warp Release 6.3 Professional or Warp Enterprise. Refer to Section 5.3.7 for
information on starting applications on your platform.
1.
Select File => New Design.
2.
Select Create an Empty Design and click Next (Figure 5-29).
5
Figure 5-29 Creating a New Design In Warp Professional or
Enterprise
3.
The next dialog box (Figure 5-30) displays the synthesis and implementation
setup. Do not change the default values presented and click Next.
Note – The path for your Synthesis tool and Implementation tool may
differ from the example in Figure 5-30.
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Figure 5-30
5
Synthesis and Implementation location dialog box.
Note – Make sure the default HDL language is VHDL in the Default
HDL Language pull-down menu.
4.
300
Enter the design name PSI_15G04 and leave the design directory as the default
(Figure 5-31). Warp Professional or Enterprise automatically creates a default
working directory with the same name as the design name.
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Figure 5-31 Entering design name dialog box.
5.
Click Next.
6.
Click Finish.
5.3.8.1
5
Adding a Design Resource
We need to add the existing design file to the project generated from Warp in the
previous design section of this tutorial.
1.
Click on Add New File in the left frame.
2.
Click on the “Add Existing File” button in the Add New File dialog box.
3.
Browse to your original PSI_15G04.vhd file and click Open to add this file to the
design.
5.3.8.2
Compiling and Synthesizing the Design
The next sequence of steps will guide you through the process of compiling, synthesizing
and producing a HEX file for a specific device, in this case, a CYPSI1504K100.
In order to set your compiler options correctly you must access the Design Flow menu
1.
Select View => Flow.
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You will be presented with the design flow window shown in Figure 5-32.
5
Figure 5-32 Design flow window.
5.3.8.2.1
Selecting a Device
Click on the Device button in the Design Flow and select the CYP15G04K100 device.
The Select Target Device dialog box displays all the Cypress PLDs in a tree form with the
following hierarchy: Device Family (SPLD, CPLD, etc), device sub-family (PSI,
Delta39K, Quantum38K, Ultra37000, Flash, MAX,etc), device name and package
type.The user can traverse the device tree. On the left frame of the dialog box are the
devices available and on the right frame are the packages available for the device selected.
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Figure 5-33 Select Target Device dialog box with Cypress PLDs in
tree form.
5
=> Navigate the tree to CPLD => PSI => c15g04k100 in the left frame.
=> Highlight the CYP15G04K100V1-MGC package in the right frame.
=> Click OK.
5.3.8.2.2
Setting Synthesis Options
From there click on the Synthesis Options button.This gives access to the compiler
options. For more information on setting the synthesis options, see Section 5.3.6.7,
Choosing Compiler Options.
5.3.8.2.3
Synthesizing (Implementation)
In order for simulation to work correctly, some settings must be invidually set. Select
Design => Settings to view this dialog box, shown in Figure 5-34.
=> Select the Simulator Resolution tab and choose 1fs from the combo box.
=> Click Apply.
=> Click OK.
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Figure 5-34 Design Settings dialog box with Simulator Resolution
tab.
5
After setting the simulator resolution option, the design can be compiled and fit to the
device by clicking the Implementation button. This will bring up the Select top-level file
and design unit dialog box (Figure 5-35), where you select psi15g04.vhd as the top-level
entity.
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5
Figure 5-35 Select top level file and design unit dialog box.
=> Select psi15g04.vhd as the top-level file.
=> Click OK.
You can watch the progress of the compilation in the Console window.
Figure 5-36 Successful compilation in Console window.
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Note – If any errors occur, you can double-click on the error message
in the console window and the source file will open with the relevant
line highlighted.
Note – In the Design Browser window, you’ll notice a question mark
next to the PSI_15G04.vhd file. This question mark is present because
we have not done pre-synthesis compilation in this tutorial.
5.3.8.2.4
Simulating the Design (Post-Synthesis) in Active-HDL Sim
=> Select View => Flow if your Design Flow window is not present.
=> In the Design Flow window, select Timing Simulation options.
=> Select the input file (synthesis\vhd\PSI_15G04.vhd) and click on the Recompile
File button.
5
=> Click on the combo box for Top-Level Unit and select PSI.
=> Click OK.
=> Start simulation by clicking on the Timing Simulation button shown in Figure 532.
5.3.8.3
Accessing the Example Waveform
In order to simulate the design, access the waveform in the “examples” folder of the
Cypress install directory. This file has all the control signals previously defined.
=> Select File => Open.
=> Browse to <warp path>/examples/wtutor/vhdl and select the PSI_15G04.awf
waveform file.
=> Click Open.
Use of this waveform file is necessary for simulation because numerous waveform
stimulators have been included. It identifies key signals used to illustrate operation of the
SERDES channels.
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5.3.8.4
Output WaveForms
In order to simulate the design correctly, please follow these instructions carefully:
=> Select Simulation -> Run Until.
=> Type in 600ns in the Run Until dialog box.
=> Click on OK to perform simulation.
5
Figure 5-37 Serial Out present on the Output Pins
Because this simulation uses waveform stimulators instead of a testbench, illustration of
SERDES operation is accomplished in 2 stages. The first stage, shown in Figure 5-37,
shows the parallel to serial conversion ability of the SERDES. The second stage, shown in
Figure 5-38, shows the result of de-serialization by the SERDES. Though the serial data
source for such de-serialization will usually be separate received serial data streams, to
simplify illustration this aspect of the SERDES operation is accomplished via a diagnostic
mode internal direct feedback path from the transmit channel’s serial output to the receive
channel’s serial inputs. When such a path is used, the external serial paths are made
inactive, as can be seen in Figure 5-38.
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5
Figure 5-38
Receive Data visible When LPEN is set LOW
The preceeding simulation example was developed to show the power of serial signal
simulation in Warp Professional. Customers desiring to use testbenches for stimulus input
must use Warp Enterprise or a third party simulator capable of accomodating testbenches.
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5.3.9
Final Code for 15G04.vhd
library IEEE;
use IEEE.std_logic_1164.all;
library cypress;
use cypress.rtlpkg.all;
use cypress.std_arith.all;
entity psi is
port (
--To LOGIC, Optional, as needed by design
txpera
:out std_logic;
txperb
:out std_logic;
txperc
:out std_logic;
txperd
:out std_logic;
--Top level, Required
txclka
:in std_logic;
txclko_p
:out std_logic;
txrate
:in std_logic;
--Top level, Required, 3 level input
txmode
:in std_logic_vector(1 downto 0);
txcksel
:in std_logic;
5
--Top level, Required
txrstb
:in std_logic;
--To LOGIC, Optional, as needed by design
ch_a_txdata_out :out std_logic_vector(9 downto 0);
ch_b_txdata_out :out std_logic_vector(9 downto 0);
ch_c_txdata_out :out std_logic_vector(9 downto 0);
ch_d_txdata_out :out std_logic_vector(9 downto 0);
ch_a_rxdata_out :out std_logic_vector(10 downto 0);
ch_b_rxdata_out :out std_logic_vector(10 downto 0);
ch_c_rxdata_out :out std_logic_vector(10 downto 0);
ch_d_rxdata_out :out std_logic_vector(10 downto 0);
--Top level, Required
rxrate
:in std_logic;
rfen
:in std_logic;
--Top level, Required, 3 level input
rxmode
:in std_logic_vector(1 downto 0);
rxcksel
:in std_logic;
framchar
:in std_logic;
rfmode
:in std_logic;
decmode
:in std_logic;
--Top level, Required
spdsel
:in std_logic;
rxclka_p
:out std_logic;
rxclkb_p
:inout std_logic;
rxclkc_p
:out std_logic;
rxclkd_p
:inout std_logic;
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refclk_p
refclk_n
serial_outa1_p
serial_outb1_p
serial_outc1_p
serial_outd1_p
serial_outa2_p
serial_outb2_p
serial_outc2_p
serial_outd2_p
serial_ina1_p
serial_inb1_p
serial_inc1_p
serial_ind1_p
serial_ina2_p
serial_inb2_p
serial_inc2_p
serial_ind2_p
serial_outa1_n
serial_outb1_n
serial_outc1_n
serial_outd1_n
serial_outa2_n
serial_outb2_n
serial_outc2_n
serial_outd2_n
serial_ina1_n
serial_inb1_n
serial_inc1_n
serial_ind1_n
serial_ina2_n
serial_inb2_n
serial_inc2_n
serial_ind2_n
insela
inselb
inselc
inseld
5
:in std_logic;
:in std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:out std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
:in std_logic;
--Top level, Required, 3 level input
sdasel
:in std_logic;
--Top level, Required
lpen
:in std_logic;
oele
:in std_logic;
bistle
:in std_logic;
rxle
:in std_logic;
boe
:in std_logic_vector(7 downto 0);
bondst
:inout std_logic_vector(1 downto 0);
masterb
:in std_logic;
bond_all
:inout std_logic;
bond_inhb
:in std_logic;
lfiab
:out std_logic;
lfibb
:out std_logic;
lficb
:out std_logic;
lfidb
:out std_logic;
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trstzb
main_clock
reset_counter
:in std_logic;
:in std_logic;
:in std_logic
);
end psi;
architecture psi_arch of psi is
signal ch_a_txdata_in
signal ch_b_txdata_in
signal ch_c_txdata_in
signal ch_d_txdata_in
signal ch_a_txdata_reg
signal ch_b_txdata_reg
signal ch_c_txdata_reg
signal ch_d_txdata_reg
signal ch_a_rxdata_reg
signal ch_b_rxdata_reg
signal ch_c_rxdata_reg
signal ch_d_rxdata_reg
signal Txcounter1
signal Txcounter2
signal Txcounter3
signal Txcounter4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(9
std_logic_vector(2
std_logic_vector(4
std_logic_vector(7
std_logic_vector(9
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
3);
5);
8);
begin
5
U0: cy_15g04serdes
port map(
--Main Clocks and Controls
refclk_p
=> refclk_p,
refclk_n
=> refclk_n,
bistle
=> bistle,
boe
=> boe,
trstzb
=> trstzb
--Transmit Data Parallel Channels
txrstb
=> txrstb,
txrate
=> txrate,
spdsel
=>spdsel,
txclka
=> txclka,
txcksel
=> txcksel,
txmode
=> txmode,
txclko_p
=> txclko_p,
txda
=> ch_a_txdata_reg(7
txcta
=> ch_a_txdata_reg(9
txpera
=> txpera,
txdb
=> ch_b_txdata_reg(7
txctb
=> ch_b_txdata_reg(9
txperb
=> txperb,
txdc
=> ch_c_txdata_reg(7
txctc
=> ch_c_txdata_reg(9
txperc
=> txperc,
txdd
=> ch_d_txdata_reg(7
txctd
=> ch_d_txdata_reg(9
txperd
=> txperd,
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downto 0),
downto 8),
downto 0),
downto 8),
downto 0),
downto 8),
downto 0),
downto 8),
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--Transmit Data Serial Channels
oele
=> oele,
serial_outa1_p
=> serial_outa1_p,
serial_outa1_n
=> serial_outa1_n,
serial_outa2_p
=> serial_outa2_p,
serial_outa2_n
=> serial_outa2_n,
serial_outb1_p
=> serial_outb1_p,
serial_outb1_n
=> serial_outb1_n,
serial_outb2_p
=> serial_outb2_p,
serial_outb2_n
=> serial_outb2_n,
serial_outc1_p
=> serial_outc1_p,
serial_outc1_n
=> serial_outc1_n,
serial_outc2_p
=> serial_outc2_p,
serial_outc2_n
=> serial_outc2_n,
serial_outd1_p
=> serial_outd1_p,
serial_outd1_n
=> serial_outd1_n,
serial_outd2_p
=> serial_outd2_p,
serial_outd2_n
=> serial_outd2_n,
--Receive Data Serial Channels
sdasel
=> sdasel,
lpen
=> lpen,
rxle
=> rxle,
insela
=> insela,
inselb
=> inselb,
inselc
=> inselc,
inseld
=> inseld,
serial_ina1_p
=> serial_ina1_p,
serial_ina1_n
=> serial_ina1_n,
serial_ina2_p
=> serial_ina2_p,
serial_ina2_n
=> serial_ina2_n,
serial_inb1_p
=> serial_inb1_p,
serial_inb1_n
=> serial_inb1_n,
serial_inb2_p
=> serial_inb2_p,
serial_inb2_n
=> serial_inb2_n,
serial_inc1_p
=> serial_inc1_p,
serial_inc1_n
=> serial_inc1_n,
serial_inc2_p
=> serial_inc2_p,
serial_inc2_n
=> serial_inc2_n,
serial_ind1_p
=> serial_ind1_p,
serial_ind1_n
=> serial_ind1_n,
serial_ind2_p
=> serial_ind2_p,
serial_ind2_n
=> serial_ind2_n,
5
--Receive Data Parallel Channels
rxrate
=> rxrate,
rfen
=> rfen,
framchar
=> framchar,
rfmode
=> rfmode,
rxmode
=> rxmode,
rxcksel
=> rxcksel,
decmode
=> decmode,
rxda
=> ch_a_rxdata_out( 10 downto 3 ),
rxsta
=> ch_a_rxdata_out(2 downto 0),
rxclka_p
=> rxclka_p,
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lfiab
rxdb
rxstb
rxclkb_p
lfibb
rxdc
rxstc
rxclkc_p
lficb
rxdd
rxstd
rxclkd_p
lfidb
bondst
bond_all
bond_inhb
masterb
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
lfiab,
ch_b_rxdata_out( 10 downto 3 ),
ch_b_rxdata_out(2 downto 0),
rxclkb_p,
lfibb,
ch_c_rxdata_out( 10 downto 3 ),
ch_c_rxdata_out(2 downto 0),
rxclkc_p,
lficb,
ch_d_rxdata_out( 10 downto 3 ),
ch_d_rxdata_out(2 downto 0),
rxclkd_p,
lfidb,
bondst,
bond_all,
bond_inhb,
masterb,
);
--Counters to generate input transmit data and data fed to
--SERDES channels A, B, C and D
process(main_clock,reset_counter)
begin
if (reset_counter = '1' ) then
Txcounter1 <= "111";
Txcounter2 <= "00";
Txcounter3 <= "111";
Txcounter4 <= "00";
elsif (main_clock'event and main_clock='1') then
Txcounter1 <= Txcounter1 - 1;
Txcounter2 <= Txcounter2 + 1;
Txcounter3 <= Txcounter3 - 1;
Txcounter4 <= Txcounter4 + 1;
end if;
end process;
-- Assignment for data that is shifted in to SERDES
-- channel A
ch_a_txdata_in( 2 downto 0 ) <= Txcounter1;
ch_a_txdata_in( 4 downto 3 ) <= Txcounter2;
ch_a_txdata_in( 7 downto 5) <= Txcounter3;
ch_a_txdata_in( 9 downto 8) <= Txcounter4;
-- channel B
ch_b_txdata_in(
ch_b_txdata_in(
ch_b_txdata_in(
ch_b_txdata_in(
2
4
7
9
downto
downto
downto
downto
0 )
3 )
5)
8)
<=
<=
<=
<=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
-- channel C
ch_c_txdata_in(
ch_c_txdata_in(
ch_c_txdata_in(
ch_c_txdata_in(
2
4
7
9
downto
downto
downto
downto
0 )
3 )
5)
8)
<=
<=
<=
<=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
-- channel
5
D
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ch_d_txdata_in(
ch_d_txdata_in(
ch_d_txdata_in(
ch_d_txdata_in(
2
4
7
9
downto
downto
downto
downto
process(main_clock)
begin
if (main_clock'event and
ch_a_txdata_reg <=
ch_b_txdata_reg <=
ch_c_txdata_reg <=
ch_d_txdata_reg <=
ch_a_txdata_out <=
ch_b_txdata_out <=
ch_c_txdata_out <=
ch_d_txdata_out <=
end if;
end process;
0 )
3 )
5)
8)
<=
<=
<=
<=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
main_clock = '1')then
ch_a_txdata_in;
ch_b_txdata_in;
ch_c_txdata_in;
ch_d_txdata_in;
ch_a_txdata_reg;
ch_b_txdata_reg;
ch_c_txdata_reg;
ch_d_txdata_reg;
end psi_arch;
5
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Verilog PSI Device (CYP15G04K100) Tutorial
This tutorial will guide you through the steps of instantiating and using the SERDES
component of Cypress's Frequency Agile PSI - CYP15G04K100. The tutorial walks the
designer, step by step, through the design, implementation, and simulation of a simple
design in PSI. The entire design phase of this tutorial can be completed in Warp Release
6.3. Customers wishing to perform the simulation portion of this tutorial must have
Release 6.3 of Warp Professional or Warp Enterprise, or a third party simulator.
Brief Overview of the CYP_15G04K100 Device
The PSI15G04K100 is a point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links (optical fiber, balanced,
and unbalanced copper transmission lines) at signaling speeds ranging from 200-to-1500
MBaud per serial link.The multiple channels in each device may be combined to allow
transport of wide buses across significant distances with minimal concern for offsets in
clock phase or link delay.
5
Figure 5-39 PSI Diagram
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Each transmit channel accepts parallel characters in an Input Register, encodes each
character for transport, and converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into characters, and presents these
characters to an output register. This is shown in Figure 5-40 below.
The mode demonstrated in this tutorial is:
Tx & Rx clocked by REFCLK with encoding turned off.
5
Figure 5-40 PSI Tutorial Overview Diagram
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5.4
Designing with Frequency Agile PSI
This tutorial is applicable to using all Frequency Agile PSI devices, and provides an
example using the CYP15G04K100 device.
In this design, you will complete the following tasks:
•
Instantiate a SERDES in Cypress Warp Design software.
•
Create a set of counters to provide inputs to the Transmit side of the SERDES.
•
Fit the design to the CYP15G04K100.
•
Simulate the Control Signals.
•
Observe the output waveforms.
5.4.1
Design Description
This design describes a simple application that uses the SERDES in CYP15G04K100. The
design transmits the output of four counters from the programmable logic portion of the
chip to the Tx side of the SERDES. This unencoded data is then serialized and output on
serial out.The serial out is then deactivated and internally looped back to the Rxside.The
received, unencoded data is then output externally.
5.4.2
Design Solution
5.4.2.1
Programmable Logic
The design created within the programmable logic provides stimulus for the Tx logic. For
the purposes of this Tutorial we must create a design that will guarantee enough transition
density for the data to be seen on the receive side. This is accomplished by creating four
counters (Txcounters 1 - 4 ). When the counters are reset, each counter has a specific value
loaded in to it so as to guarantee transition density. These values are loaded in as follows:
•
“111”,”00”,”111”,”00” where each set of bits correspond to each Counter ( 1 - 4 ).
•
Each set of ‘1’s are counted down and each set of ‘0’s are counted up thus producing
enough transition density on the data being fed out to enable the data to be seen on the
receive side.
•
This received data is then passed to the output pins of the PSI device.
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Figure 5-41 Counter Diagram
5.4.2.2
SERDES
The SERDES function in PSI is where the unencoded data passed from the programmable
logic portion of the chip is serialized. In real world designs, this serial data would then be
passed off chip for communication purposes. For the purposes of the tutorial, however, we
will create an internal loopback of the data between the transmit and receive channels of
our chip; we will use the same data we create and transmit on our transmit channel as the
input data on our receive channel. We accomplish this by internally looping back the
SERIAL_OUT data to the SERIAL_IN signals. This loopback is enabled when the LPEN
control signal is set high. This methodology will simplify the tutorial and will eliminate
the need to create a testbench.
5
5.4.3
Starting Warp Applications
5.4.3.1
For Warp Users
•
On Windows platforms, select Start -> Programs -> Cypress -> Warp R6.3 -> Galaxy.
•
On UNIX systems, start Galaxy by typing the application name such, as Galaxy<CR>,
from within a shell window.
5.4.3.2
For Warp Professional Users
For information on starting Warp Professional, see Section 5.4.6, Starting Warp
Professional or Enterprise Applications.
5.4.3.3
For Warp Enterprise Users
For information on starting Warp Enterprise, see Section 5.4.6, Starting Warp Professional
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or Enterprise Applications.
5.4.4
Creating a New Design
Start Galaxy. Refer to Section 5.4.3 for information on starting applications on your
platform.
1.
Select File => New.
2.
Select Project [Target-Device] and click on OK, shown in Figure 5-42.
5
Figure 5-42 New text file and project dialog box.
3.
Select Verilog as the Project type.
4.
Enter the name of the project as PSI_15G04.
5.
Enter the project path as follows.
=> On the PC,enter c:\wtutor\vlog\PSI_15G04.
=> On the UNIX systems, enter <user_home_directory_path>/wtutor/vlog/
PSI_15G04.
6.
Click Next to invoke the Add Files wizard. The Add Files wizard is used to copy a
set of Verilog files into the current project. Skip this dialog box and Click Next to
invoke the Target Device wizard.
Note – Closing the Project Information wizard creates the project with
no files or devices selected. You will be able to add files and select
devices from the Project menu later.
The Select Target Device wizard dialog box displays all the Cypress PLDs in a tree form
which the following hierarchy: Device Family (SPLD, CPLD, etc), device sub-family
(PSI, Delta39K, Quantum38K, Ultra37000, Flash, MAX,etc), device name and package
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type.The user can traverse the device tree. On the left frame of the dialog box are the
devices available and on the right frame are the packages available for the device selected.
5
Figure 5-43 Select Target Device dialog box with Cypress PLDs in
tree form.
7.
Navigate the tree to CPLD => PSI => c15g04k100 in the left frame.
8.
Highlight the CYP15G04K100V1-MGC package in the right frame.
9.
Click Finish to create the project.
10. Click Yes to save the project.
You have now created a project directory for a design. All files pertinent to this tutorial
need to be placed in this project directory. You have also created a project file called
PSI_15G04.pfg which is now located in the c:\wtutor\vlog\PSI_15G04 directory.
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5.4.5
Creating the Verilog File
1.
Select File => New.
2.
Select “Text File”.
3.
Click OK.This brings up the Galaxy editor (Figure 5-44) where the Verilog code is
entered.
5
Figure 5-44 Galaxy Editor window.
Note – You can also create a new text file by clicking on the “New Text
File” button on the project toolbar.
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Note – If you would rather not type the PSI_15G04.v file yourself,
you can copy it from the Warp directory. The location for the
PSI_15G04.v file is <warp path>\examples\wtutor\vlog. From this
location, copy PSI_15G04.v to your project directory. Then, read along
for the next several pages to help you understand the purpose of each
section of a Verilog source file. Change ‘include “<your warp
installation directory>/lib/common/rtl.v” to the absolute
path of your Cypress installation.
5.4.5.1
Writing the Include Statement
Enter these lines at the beginning of the Verilog document:
‘include “<your warp installation directory>/lib/common/rtl.v”
Where <your warp installation directory> is the absolute path of your
Cypress installation.
5
5.4.5.2
Writing the Module Definition
Enter these lines after the include statement in the Verilog document:
module psi (
txpera, txperb, txperc, txperd,
txclka,
txclko_p,
txrate, txmode, txcksel,
ch_a_rxdata_out, ch_b_rxdata_out,
ch_c_rxdata_out, ch_d_rxdata_out,
rxrate, rfen, rxmode, rxcksel,
framchar, rfmode, decmode, spdsel,
rxclka_p, rxclkc_p,
rxclkb_p, rxclkd_p,
refclk_p, refclk_n,
serial_outa1_p, serial_outb1_p,
serial_outc1_p, serial_outd1_p,
serial_outa2_p, serial_outb2_p,
serial_outc2_p, serial_outd2_p,
serial_ina1_p, serial_inb1_p,
serial_inc1_p, serial_ind1_p,
serial_ina2_p, serial_inb2_p,
serial_inc2_p, serial_ind2_p,
serial_outa1_n, serial_outb1_n,
serial_outc1_n, serial_outd1_n,
serial_outa2_n, serial_outb2_n,
serial_outc2_n, serial_outd2_n,
serial_ina1_n, serial_inb1_n,
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serial_inc1_n, serial_ind1_n,
serial_ina2_n, serial_inb2_n,
serial_inc2_n, serial_ind2_n,
insela, inselb, inselc, inseld,
sdasel, lpen,
oele, bistle, rxle, boe,
bondst, masterb, bond_all, bond_inhb,
lfiab, lfibb, lficb, lfidb,
trstzb, txrstb,
main_clock, reset_counter) ;
These lines define the PSI module as having 81 ports. Each of the ports are defined as an
input, output or inout port below.
//Parity out from TX channel's A,B,C,D.
output txpera, txperb, txperc, txperd;
//As we clock using Refclk this is left open
input txclka;
//Refclk shifted output used to transmit data from 39K
output txclko_p;
//Set it to 'L' meaning Single Data Rate
input txrate;
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//set it to 'LL' to bypass encoder
input txcksel;
//set it to 'L' use Refclk for transmit clocking
input txrstb;
//set 'L' for 20ns and then set high
input [1:0] txmode;
//Receive data out on Ch_A
output [10:0] ch_a_rxdata_out;
//Receive data out on Ch_B
output [10:0] ch_b_rxdata_out;
//Receive data out on Ch_C
output [10:0] ch_c_rxdata_out;
//Receive data out on Ch_D
output [10:0] ch_d_rxdata_out;
//open since this input is not operated on while using the Ref clk.
input rxrate;
//set it to 'L' to disable framing of received data
input rfen;
//set it to 'L' to receive data using Refclk
input rxcksel;
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//set it to 'LL' to clock independent channels on the receive side
input [1:0] rxmode;
//open since framing is disabled -- characters on which you frame
input framchar;
//open since framing is disabled modes framing
input rfmode;
//set it to 'L' to bypass decoder
input decmode;
//set it to 'H' to select a refclk range of 75 Mhz to 150 MHz
input spdsel;
//open Refclk appears on this pin phase shifted
output rxclka_p, rxclkc_p;
//open --Not used since we use refclk
inout rxclkb_p, rxclkd_p;
//Input reference clock
input refclk_p, refclk_n;
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//Serial Outputs and Inputs
output serial_outa1_p, serial_outb1_p;
output serial_outc1_p, serial_outd1_p;
output serial_outa2_p, serial_outb2_p;
output serial_outc2_p, serial_outd2_p;
input serial_ina1_p, serial_inb1_p;
input serial_inc1_p, serial_ind1_p;
input serial_ina2_p, serial_inb2_p;
input serial_inc2_p, serial_ind2_p;
output serial_outa1_n, serial_outb1_n;
output serial_outc1_n, serial_outd1_n;
output serial_outa2_n, serial_outb2_n;
output serial_outc2_n, serial_outd2_n;
input serial_ina1_n, serial_inb1_n;
input serial_inc1_n, serial_ind1_n;
input serial_ina2_n, serial_inb2_n;
input serial_inc2_n, serial_ind2_n;
//All 4 channels insel are set to 'H' - this selects channel 1
input insela, inselb, inselc, inseld;
//Sets Amplitude at which signal is detected, used to determine LFI
input sdasel;
//Loop Enable set to 'L' to disable internal looping in the SERDES
input lpen;
//Set to 'H' to enable Output enable latch enable
input oele;
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//Set to 'H' to disable BIST generation
input bistle;
//Set to 'H' to activate RxPLL's
input rxle;
//Set to "FF" to enable all serial outand serial in
input [7:0] boe;
//Set to 'L' since Refclk to current device is used
input masterb;
//Set to 'l' to inhibit bonding
input bond_inhb;
//open since we do not bond with another device
inout [1:0] bondst;
//Open to check if Rx channels are bonded
inout bond_all;
output lfiab, lfibb, lficb, lfidb;
//set to 'L' for 130 ns and then set 'H'
input trstzb;
5
//Refclk_p is fed to 39K design using Test bench
input main_clock;
//Feed the same inputs to TxRSTzB and Reset_Counter
input reset_counter;
5.4.5.3
Writing the Behavior of the PSI module
First, we create four 10-bit regs (ch_a_txdata_reg, ch_b_txdata_reg, ch_c_txdata_reg,
ch_d_txdata_reg) and four counters of varying widths (Txcounter1, Txcounter2,
Txcounter3, Txcounter4) to show the data flow. The counters of varying sizes are merged
to create a 10-bit data source that feeds all four SERDES transmit channels. The reason for
the multiple counters is to ensure that the serial transmit data has enough edge transitions.
Regs are temporary variables used to keep track of signals used in the always procedural
block.
//Txdata_reg for channel A
reg [9:0] ch_a_txdata_reg;
//Txdata_reg for channel B
reg [9:0] ch_b_txdata_reg;
//Txdata_reg for channel C
reg [9:0] ch_c_txdata_reg;
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//Txdata_reg for channel D
reg [9:0] ch_d_txdata_reg;
//Lower 3 bits of transmit data
reg [2:0] Txcounter1;
//Next 2 bits of Txdata
reg [4:3] Txcounter2;
//Next 3 bits of Txdata
reg [7:5] Txcounter3;
//Highest 2 bits of Txdata
reg [9:8] Txcounter4;
Then, declare the wires. Wires represent a physical connection (or a signal) between
components.
//Txdata into the SERDES for Channel A
wire [9:0] ch_a_txdata_in;
//Txdata into the SERDES for Channel B
wire [9:0] ch_b_txdata_in;
5
//Txdata into the SERDES for Channel C
wire [9:0] ch_c_txdata_in;
//Txdata into the SERDES for Channel D
wire [9:0] ch_d_txdata_in;
Once this is completed, paste in the SERDES instantiation by selecting ‘CY15g04serdes’
from the “Templates” menu located on the toolbar. for more information about how to
instantiate LPM modules, please refer to Chapter 5, LPM, in the User’s Guide.
Once pasted, the various SERDES ports need to be connected to the signals in the design.
An example mapping is as follows:
cy_15g04serdes U0(
//Main Clocks and Controls
.refclk_p
( refclk_p ),
.refclk_n
( refclk_n ),
.bistle
( bistle ),
.boe
( boe ),
.trstzb
( trstzb ),
//Transmit Data Parallel Channels
.txrstb
( txrstb ),
.txrate
( txrate ),
.spdsel
( spdsel ),
.txclka
( txclka ),
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.txcksel
.txmode
.txclko_p
.txda
.txcta
.txpera
.txdb
.txctb
.txperb
.txdc
.txctc
.txperc
.txdd
.txctd
.txperd
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
txcksel),
txmode ),
txclko_p),
ch_a_txdata_reg
ch_a_txdata_reg
txpera ),
ch_b_txdata_reg
ch_b_txdata_reg
txperb ),
ch_c_txdata_reg
ch_c_txdata_reg
txperc ),
ch_d_txdata_reg
ch_d_txdata_reg
txperd ),
//Transmit Data Serial Channels
.oele
( oele ),
.serial_outa1_p ( serial_outa1_p
.serial_outa1_n ( serial_outa1_n
.serial_outa2_p ( serial_outa2_p
.serial_outa2_n ( serial_outa2_n
.serial_outb1_p ( serial_outb1_p
.serial_outb1_n ( serial_outb1_n
.serial_outb2_p ( serial_outb2_p
.serial_outb2_n ( serial_outb2_n
.serial_outc1_p ( serial_outc1_p
.serial_outc1_n ( serial_outc1_n
.serial_outc2_p ( serial_outc2_p
.serial_outc2_n ( serial_outc2_n
.serial_outd1_p ( serial_outd1_p
.serial_outd1_n ( serial_outd1_n
.serial_outd2_p ( serial_outd2_p
.serial_outd2_n ( serial_outd2_n
//Receive Data Serial Channels
.sdasel
( sdasel ),
.lpen
( lpen ),
.rxle
( rxle ),
.insela
( insela ),
.serial_ina1_p
( serial_ina1_p
.serial_ina1_n
( serial_ina1_n
.serial_ina2_p
( serial_ina2_p
.serial_ina2_n
( serial_ina2_n
.inselb
( inselb ),
.serial_inb1_p
( serial_inb1_p
.serial_inb1_n
( serial_inb1_n
.serial_inb2_p
( serial_inb2_p
.serial_inb2_n
( serial_inb2_n
.inselc
( inselc ),
.serial_inc1_p
( serial_inc1_p
.serial_inc1_n
( serial_inc1_n
.serial_inc2_p
( serial_inc2_p
.serial_inc2_n
( serial_inc2_n
.inseld
( inseld ),
.serial_ind1_p
( serial_ind1_p
Warp Getting Started Manual
[7:0]),
[9:8]),
[7:0]),
[9:8]),
[7:0]),
[9:8]),
[7:0]),
[9:8]),
),
),
),
),
),
),
),
),
),
),
),
),
),
),
),
),
5
),
),
),
),
),
),
),
),
),
),
),
),
),
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.serial_ind1_n
( serial_ind1_n ),
.serial_ind2_p
( serial_ind2_p ),
.serial_ind2_n
( serial_ind2_n ),
//Receive Data Parallel Channels
.rxrate
( rxrate ),
.rfen
( rfen ),
.framchar
( framchar ),
.rfmode
( rfmode ),
.rxmode
( rxmode ),
.rxcksel
( rxcksel ),
.decmode
( decmode ),
.rxda
( ch_a_rxdata_out [10:3]),
.rxsta
( ch_a_rxdata_out [2:0]),
.rxclka_p
( rxclka_p ),
.lfiab
( lfiab ),
.rxdb
( ch_b_rxdata_out [10:3]),
.rxstb
( ch_b_rxdata_out [2:0]),
.rxclkb_p
( rxclkb_p ),
.lfibb
( lfibb ),
.rxdc
( ch_c_rxdata_out [10:3]),
.rxstc
( ch_c_rxdata_out [2:0]),
.rxclkc_p
( rxclkc_p ),
.lficb
( lficb ),
.rxdd
( ch_d_rxdata_out [10:3]),
.rxstd
( ch_d_rxdata_out [2:0]),
.rxclkd_p
( rxclkd_p ),
.lfidb
( lfidb ),
.bond_all
( bond_all ),
.bond_inhb
( bond_inhb ),
.bondst
( bondst ),
.masterb
( masterb )
5
);
Next, we create sequential blocks to generate or process the transmit and receive data.
This is done using an always procedural block. The always procedural block describes the
action of the design in response to certain stimuli. These stimuli are declared in the
sensitivity list enclosed in the parentheses following the @ symbol of the always
declaration.
always @(posedge main_clock)
begin
if (reset_counter == 1'b 1)
begin
Txcounter1 <= 3'b 111;
Txcounter2 <= 2'b 00;
Txcounter3 <= 3'b 111;
Txcounter4 <= 2'b 00;
end
else
begin
Txcounter1 <= Txcounter1
Txcounter2 <= Txcounter2
Txcounter3 <= Txcounter3
Txcounter4 <= Txcounter4
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+
+
1;
1;
1;
1;
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end
end
// Assignment for Data that is shifted into the SERDES
// Channel A
assign
assign
assign
assign
ch_a_txdata_in
ch_a_txdata_in
ch_a_txdata_in
ch_a_txdata_in
[2:0]
[4:3]
[7:5]
[9:8]
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
// Assignment for Data that is shifted into the SERDES
// Channel B
assign
assign
assign
assign
ch_b_txdata_in
ch_b_txdata_in
ch_b_txdata_in
ch_b_txdata_in
[2:0]
[4:3]
[7:5]
[9:8]
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
// Assignment for Data that is
// Channel C
assign
ch_c_txdata_in [2:0]
assign
ch_c_txdata_in [4:3]
assign
ch_c_txdata_in [7:5]
assign
ch_c_txdata_in [9:8]
shifted into the SERDES
// Assignment for Data that is
// Channel D
assign
ch_d_txdata_in [2:0]
assign
ch_d_txdata_in [4:3]
assign
ch_d_txdata_in [7:5]
assign
ch_d_txdata_in [9:8]
shifted into the SERDES
=
=
=
=
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
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Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
Next a process is created that registers txdata and passes it on the SERDES anytime a
rising_edge appears on the receive clock. The code should appear as follows:
always @(posedge main_clock)
begin
ch_a_txdata_reg <= ch_a_txdata_in;
ch_b_txdata_reg <= ch_b_txdata_in;
ch_c_txdata_reg <= ch_c_txdata_in;
ch_d_txdata_reg <= ch_d_txdata_in;
end
Finally add endmodule to the last line to denote the end of the file.
endmodule
Select File -> Save and save file as PSI_15G04.v.
5.4.5.4
Selecting Files for Compilation
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After the file is created, it needs to be added to the project.
5.4.5.4.1
To add a Verilog file:
1.
Use the menu item Project => Add files.
2.
Click the browse button to navigate to the project directory.
3.
Highlight the PSI_15G04.v file and click Add.
4.
Click OK in the Add Files to Project dialog box.
Note – To add files from a different directory, click the browse button
to navigate to the project directory.
5
Figure 5-45 Dialog box to select files to compile.
5.4.5.5
Setting the Top-Level File
Once PSI_15G04.v has been added into the project, a top level file can be set. Only the
top-level file is actually synthesized, and only one top-level file is allowed in a project.
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=> Right click on PSI_15G04.v and select Project => Set Top
Once the top-level file has been set, the file symbol marker in the hierarchy will have a
tree symbol (Figure 5-46).
5
Figure 5-46 Galaxy window showing psi15g04.v as the top-level
design.
Note – In order to set the top-level file, you must select the file in the
Source tab in the Project sub-window, as shown in Figure 5-46.
5.4.5.6
Compiling and Synthesizing a Top-Level File
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The next sequence of steps will guide you through the process of compiling, synthesizing,
and producing a HEX programming file for a specific target device, in this case, a
CYP15G04K100.
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5.4.5.7
Choosing Compiler Options
The compiler options are available under the Project menu. Select Project => Compiler
Options. Two tabs are available: Synthesis and Messaging.
5
Figure 5-47 The Compiler Options dialog box for PSI devices.
=> Select the Messaging tab.
=> Click on Detailed Report File, if not already selected (Figure 5-28).
For more information on setting compiler options in the Synthesis tab, see Section 5.1.11,
Choosing Compiler Options.
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5.4.5.8
Compiling and Synthesizing the File.
In your Galaxy window, select Compile => Project to begin compilation or click the
Compile Project button on the project toolbar.
Warp starts the compilation and synthesis of the design into a CY15g04k100 and prints
messages to keep you appraised of its progress in the Results sub-window. The Compile
=> Project option automatically recompiles only those files which have been modified
since the last compilation. During compilation, Warp locates the control file (if it exists)
in the project directory and interprets the synthesis directives.
This operation generates two files of particular interest:
5
•
PSI_15G04.hex: This file is used to program a CY15G04K100 device. This file is
automatically placed in the project directory.
•
PSI_15G04.rpt: This text file contains pinout and timing information, along with other
information about the final synthesised design. You can see the .rpt file and the output
files created by Warp by clicking on the output view tab in the Project sub-window.
Different sections of the report file can be accessed by clicking on the plus sign and
selecting the available sections.
For more information on what is contained in a report file, refer to Section 6.2,
Understanding the Delta39K Report File in the Warp User’s Guide.
If compile error messages appear in the results sub-window:
=> Click on the Errors and Warnings tab located at the bottom of the Galaxy output
window.
=> Double click on the error message to select it. Go to the editor window. The
cursor should be positoned on the line that caused the error. Use the Next and
Previous Error buttons to locate other errors.
Note – If compilation errors occur, make sure the text of your
PSI_15G04.v file is entered exactly as shown earlier in this chapter, or
copy the file from the <warp path>\examples\wtutor\vlog directory, and
then run the Warp compiler again.
Upon successful compilation, you have completed the PSI design portion of this tutorial.
Specific technical details about the PSI device can be found in the Frequency Agile PSI
datasheet and related application notes found on the Cypress website. Software related
issues are addressed in the online help topics or can be addressed by Cypress Applications
Hotline.
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The next portion of this tutorial will briefly highlight the use of Warp Professional Verilog
and Warp Enterprise Verilog for design entry and compilation. In addition, the tutorial
will provide an illustrative simulation using the Frequency Agile PSI in Warp Professional
Verilog.
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5.4.6
Starting Warp Professional or Enterprise Applications
=> On Windows platform, select Start -> Programs -> Cypress -> Warp
Professional/Enterprise R6.3 -> Active HDL 4.1CY .
5.4.7
Creating a New Design
Start Warp Release 6.3 Professional. Refer to Section 5.3.7 for information on starting
applications on your platform.
1.
Select File => New Design.
2.
Select Create an Empty Design and click Next (Figure 5-48).
5
Figure 5-48 Creating a New Design In Warp Professional
3.
The next dialog box (Figure 5-49) displays the synthesis and implementation
setup. Click Next.
Note – Make sure the default HDL language is Verilog in the Default
HDL Language pull-down menu.
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Figure 5-49
4.
Synthesis and Implementation location dialog box.
Enter the design name PSI_15G04 and leave the design directory as the default
(Figure 5-50). Warp P/E automatically creates a default working directory with the
same name as the design name.
Figure 5-50 Entering design name dialog box.
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5.
Click Next.
6.
Click Finish.
5.4.7.1
Adding a Design Resource
We need to add the existing design file generated from Warp to the project.
1.
Click on Add New File in the left frame.
2.
Click on the “Add Existing File” button in the Add New File dialog box.
3.
Browse to your original PSI_15G04.v file and click Open to add this file to the
design.
5.4.7.2
Compiling and Synthesizing the Design
The next sequence of steps will guide you through the process of producing a HEX file for
a specific device, in this case, a CYP1504K100.
In order to set your compiler options correctly you must access the Design Flow menu
5
1.
338
Select View => Flow.
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5
Figure 5-51 Design flow window.
2.
5.4.7.2.1
Click on Design Flow.
Selecting a Device
Click on the Device button in the Design Flow and select the CYP15G04K100 device.
The Select Target Device dialog box displays all the Cypress PLDs in a tree form which
the following hierarchy: Device Family (SPLD, CPLD, etc), device sub-family (PSI,
Delta39K, Quantum38K, Ultra37000, Flash, MAX,etc), device name and package
type.The user can traverse the device tree. On the left frame of the dialog box are the
devices available and on the right frame are the packages available for the device selected.
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Figure 5-52 Select Target Device dialog box with Cypress PLDs in
tree form.
5
=> Navigate the tree to CPLD => PSI => cy15g04k100 in the left frame.
=> Highlight the CYP15G04K100V1-MGC package in the right frame.
=> Click OK.
5.4.7.2.2
Setting Synthesis Options
From there click on the Synthesis Options button.This gives access to the compiler
options. For more information on setting the synthesis options, see Section 5.3.6.7,
Choosing Compiler Options.
5.4.7.2.3
Synthesizing (Implementation)
In order for simulation to work correctly, some settings must be invidually set. Select
Design => Settings to view this dialog box, shown in Figure 5-53.
=> Select the Simulator Resolution tab and choose 1fs from the combo box.
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Figure 5-53 Design Settings dialog box with Simulator Resolution
tab.
After setting the simulator resolution option, the design can be compiled and targeted by
clicking the Implementation button. This will bring up the Select top-level file and design
unit dialog box (Figure 5-54), where you select psi15g04.v as the top-level entity.
Figure 5-54 Select top level file and design unit dialog box.
=> Select psi15g04.v as the top-level file.
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=> Click OK.
You can watch the progress of the compilation in the Console window.
Figure 5-55 Successful compilation in Console window.
5
Note – If any errors occur, you can double-click on the error message
in the console window and the source file will open with the relevant
line highlighted.
5.4.7.2.4
Simulating the Design (Post-Synthesis) in Active-HDL Sim
=> Select View => Flow if your Design Flow window is not present.
=> Start simulation by clicking on the Timing Simulation button shown in Figure 551.
5.4.7.3
Accessing the Example Waveform
In order to simulate the design, access the waveform in the “examples” folder of the
Cypress install directory. This file has all the control signals previously defined.
=> Select File => Open.
=> Browse to <warp path>/examples/wtutor/vlog/templates and select the
15G04tut.awf file.
=> Click Open.
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5.4.7.4
Output WaveForms
In order to simulate the design correctly, please follow these instructions carefully:
=> Select Simulation -> Run Until.
=> Type in 600ns in the Run Until dialog box.
=> Now simulate the WaveForm.
5
Figure 5-56 Serial Out present on the Output Pins
Because this simulation uses waveform stimulators instead of a testbench, illustration of
SERDES operation is accomplished in 2 stages. The first stage, shown in Figure 5-56,
shows the parallel to serial conversion ability of the SERDES. The second stage, shown in
Figure 5-57, shows the result of de-serialization by the SERDES. Though the serial data
source for such de-serialization will usually be separate received serial data streams, to
simplify illustration this aspect of the SERDES operation is accomplished via a diagnostic
mode internal direct feedback path from the transmit channel’s serial output to the receive
channel’s serial inputs. When such a path is used, the external serial paths are made
inactive, as can be seen in Figure 5-57.
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Figure 5-57
Receive Data visible When LPEN is set LOW
The preceeding simulation example was developed to show the power of serial signal
simulation in Warp Professional. Customers desiring to use testbenches for stimulus input
must use Warp Enterprise or a third party simulator capable of accomodating testbenches.
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5.4.8
Final code for PSI_15G04.v
‘include “<your warp installation directory>/lib/common/lpm.v”
module psi (
//To LOGIC, optional, as needed by design
txpera, txperb, txperc, txperd,
//Top level, Required
txclka,
txclko_p,
txrate,
//Top level, Required, 3 level input
txmode, txcksel,
//To LOGIC, Option, as needed by design
ch_a_rxdata_out, ch_b_rxdata_out,
ch_c_rxdata_out, ch_d_rxdata_out,
//Top level, required
rxrate, rfen,
5
//Top level, Required, 3 level input
rxmode, rxcksel,
framchar, rfmode, decmode,
//Top level, Required
spdsel,
rxclka_p, rxclkc_p,
rxclkb_p, rxclkd_p,
refclk_p, refclk_n,
//Top level, Required
serial_outa1_p, serial_outb1_p,
serial_outc1_p, serial_outd1_p,
serial_outa2_p, serial_outb2_p,
serial_outc2_p, serial_outd2_p,
serial_ina1_p, serial_inb1_p,
serial_inc1_p, serial_ind1_p,
serial_ina2_p, serial_inb2_p,
serial_inc2_p, serial_ind2_p,
serial_outa1_n, serial_outb1_n,
serial_outc1_n, serial_outd1_n,
serial_outa2_n, serial_outb2_n,
serial_outc2_n, serial_outd2_n,
serial_ina1_n, serial_inb1_n,
serial_inc1_n, serial_ind1_n,
serial_ina2_n, serial_inb2_n,
serial_inc2_n, serial_ind2_n,
insela, inselb, inselc, inseld,
//Top level, Required, 3 level input
sdasel,
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PSI Device Tutorial
//Top level, Required
lpen,
oele, bistle, rxle, boe,
bondst, masterb, bond_all, bond_inhb,
lfiab, lfibb, lficb, lfidb,
trstzb, txrstb,
main_clock, reset_counter) ;
5
346
output
input
output
input
input
input
input
output
output
output
output
input
input
input
input
txpera, txperb, txperc, txperd;
txclka;
txclko_p;
txrate;
txcksel;
txrstb;
[1:0] txmode;
[10:0] ch_a_rxdata_out;
[10:0] ch_b_rxdata_out;
[10:0] ch_c_rxdata_out;
[10:0] ch_d_rxdata_out;
rxrate;
rfen;
rxcksel;
[1:0] rxmode;
input
input
input
input
output
inout
input
output
output
output
output
input
input
input
input
output
output
output
output
input
input
input
input
input
input
input
input
input
input
input
framchar;
rfmode;
decmode;
spdsel;
rxclka_p, rxclkc_p;
rxclkb_p, rxclkd_p;
refclk_p, refclk_n;
serial_outa1_p, serial_outb1_p;
serial_outc1_p, serial_outd1_p;
serial_outa2_p, serial_outb2_p;
serial_outc2_p, serial_outd2_p;
serial_ina1_p, serial_inb1_p;
serial_inc1_p, serial_ind1_p;
serial_ina2_p, serial_inb2_p;
serial_inc2_p, serial_ind2_p;
serial_outa1_n, serial_outb1_n;
serial_outc1_n, serial_outd1_n;
serial_outa2_n, serial_outb2_n;
serial_outc2_n, serial_outd2_n;
serial_ina1_n, serial_inb1_n;
serial_inc1_n, serial_ind1_n;
serial_ina2_n, serial_inb2_n;
serial_inc2_n, serial_ind2_n;
insela, inselb, inselc, inseld;
sdasel;
lpen;
oele;
bistle;
rxle;
[7:0] boe;
Warp Getting Started Manual
PSI Device Tutorial
input
input
inout
inout
output
masterb;
bond_inhb;
[1:0] bondst;
bond_all;
lfiab, lfibb, lficb, lfidb;
input
input
input
trstzb;
main_clock;
reset_counter;
wire [9:0] ch_a_txdata_in;
wire [9:0] ch_b_txdata_in;
wire [9:0] ch_c_txdata_in;
wire [9:0] ch_d_txdata_in;
reg [9:0] ch_a_txdata_reg;
reg [9:0] ch_b_txdata_reg;
reg [9:0] ch_c_txdata_reg;
reg [9:0] ch_d_txdata_reg;
reg [2:0] Txcounter1;
reg [4:3] Txcounter2;
reg [7:5] Txcounter3;
reg [9:8] Txcounter4;
cy_15g04serdes U0(
//Main Clocks and Controls
.refclk_p
( refclk_p ),
.refclk_n
( refclk_n ),
.bistle
( bistle ),
.boe
( boe ),
.trstzb
( trstzb ),
//Transmit Data Parallel Channels
.txrstb
( txrstb ),
.txrate
( txrate ),
.spdsel
( spdsel ),
.txclka
( txclka ),
.txcksel
( txcksel),
.txmode
( txmode ),
.txclko_p
( txclko_p),
.txda
( ch_a_txdata_reg
.txcta
( ch_a_txdata_reg
.txpera
( txpera ),
.txdb
( ch_b_txdata_reg
.txctb
( ch_b_txdata_reg
.txperb
( txperb ),
.txdc
( ch_c_txdata_reg
.txctc
( ch_c_txdata_reg
.txperc
( txperc ),
.txdd
( ch_d_txdata_reg
.txctd
( ch_d_txdata_reg
.txperd
( txperd ),
5
[7:0]),
[9:8]),
[7:0]),
[9:8]),
[7:0]),
[9:8]),
[7:0]),
[9:8]),
//Transmit Data Serial Channels
.oele
( oele ),
.serial_outa1_p ( serial_outa1_p ),
.serial_outa1_n ( serial_outa1_n ),
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PSI Device Tutorial
.serial_outa2_p
.serial_outa2_n
.serial_outb1_p
.serial_outb1_n
.serial_outb2_p
.serial_outb2_n
.serial_outc1_p
.serial_outc1_n
.serial_outc2_p
.serial_outc2_n
.serial_outd1_p
.serial_outd1_n
.serial_outd2_p
.serial_outd2_n
(
(
(
(
(
(
(
(
(
(
(
(
(
(
serial_outa2_p
serial_outa2_n
serial_outb1_p
serial_outb1_n
serial_outb2_p
serial_outb2_n
serial_outc1_p
serial_outc1_n
serial_outc2_p
serial_outc2_n
serial_outd1_p
serial_outd1_n
serial_outd2_p
serial_outd2_n
),
),
),
),
),
),
),
),
),
),
),
),
),
),
//Receive Data Serial Channels
.sdasel
( sdasel ),
.lpen
( lpen ),
.rxle
( rxle ),
.insela
( insela ),
.serial_ina1_p
( serial_ina1_p ),
.serial_ina1_n
( serial_ina1_n ),
.serial_ina2_p
( serial_ina2_p ),
.serial_ina2_n
( serial_ina2_n ),
.inselb
( inselb ),
.serial_inb1_p
( serial_inb1_p ),
.serial_inb1_n
( serial_inb1_n ),
.serial_inb2_p
( serial_inb2_p ),
.serial_inb2_n
( serial_inb2_n ),
.inselc
( inselc ),
.serial_inc1_p
( serial_inc1_p ),
.serial_inc1_n
( serial_inc1_n ),
.serial_inc2_p
( serial_inc2_p ),
.serial_inc2_n
( serial_inc2_n ),
.inseld
( inseld ),
.serial_ind1_p
( serial_ind1_p ),
.serial_ind1_n
( serial_ind1_n ),
.serial_ind2_p
( serial_ind2_p ),
.serial_ind2_n
( serial_ind2_n ),
//Receive Data Parallel Channels
.rxrate
( rxrate ),
.rfen
( rfen ),
.framchar
( framchar ),
.rfmode
( rfmode ),
.rxmode
( rxmode ),
.rxcksel
( rxcksel ),
.decmode
( decmode ),
.rxda
( ch_a_rxdata_out [10:3]),
.rxsta
( ch_a_rxdata_out [2:0]),
.rxclka_p
( rxclka_p ),
.lfiab
( lfiab ),
.rxdb
( ch_b_rxdata_out [10:3]),
.rxstb
( ch_b_rxdata_out [2:0]),
.rxclkb_p
( rxclkb_p ),
.lfibb
( lfibb ),
.rxdc
( ch_c_rxdata_out [10:3]),
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PSI Device Tutorial
.rxstc
.rxclkc_p
.lficb
.rxdd
.rxstd
.rxclkd_p
.lfidb
.bond_all
.bond_inhb
.bondst
.masterb
(
(
(
(
(
(
(
(
(
(
(
ch_c_rxdata_out [2:0]),
rxclkc_p ),
lficb ),
ch_d_rxdata_out [10:3]),
ch_d_rxdata_out [2:0]),
rxclkd_p ),
lfidb ),
bond_all ),
bond_inhb ),
bondst ),
masterb )
);
always @(posedge main_clock)
begin
if (reset_counter == 1'b 1)
begin
//Counters are alternately set to 111 and 00
Txcounter1 <= 3'b 111;
//The counters with 111 are counted down
Txcounter2 <= 2'b 00;
//The counters with 00 are counted up
Txcounter3 <= 3'b 111;
Txcounter4 <= 2'b 00;
end
else
begin
Txcounter1 <= Txcounter1 - 1;
Txcounter2 <= Txcounter2 + 1;
Txcounter3 <= Txcounter3 - 1;
Txcounter4 <= Txcounter4 + 1;
end
end
5
// Assignment for Data that is shifted into the SERDES
// Channel A
assign
assign
assign
assign
ch_a_txdata_in
ch_a_txdata_in
ch_a_txdata_in
ch_a_txdata_in
[2:0]
[4:3]
[7:5]
[9:8]
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
// Assignment for Data that is shifted into the SERDES
// Channel B
assign
assign
assign
assign
ch_b_txdata_in
ch_b_txdata_in
ch_b_txdata_in
ch_b_txdata_in
[2:0]
[4:3]
[7:5]
[9:8]
// Assignment for Data that is
// Channel C
assign
ch_c_txdata_in [2:0]
assign
ch_c_txdata_in [4:3]
assign
ch_c_txdata_in [7:5]
assign
ch_c_txdata_in [9:8]
Warp Getting Started Manual
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
shifted into the SERDES
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
349
PSI Device Tutorial
// Assignment for Data that is
// Channel D
assign
ch_d_txdata_in [2:0]
assign
ch_d_txdata_in [4:3]
assign
ch_d_txdata_in [7:5]
assign
ch_d_txdata_in [9:8]
shifted into the SERDES
=
=
=
=
Txcounter1;
Txcounter2;
Txcounter3;
Txcounter4;
always @(posedge main_clock)
begin
ch_a_txdata_reg <= ch_a_txdata_in;
ch_b_txdata_reg <= ch_b_txdata_in;
ch_c_txdata_reg <= ch_c_txdata_in;
ch_d_txdata_reg <= ch_d_txdata_in;
end
endmodule
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Index
A
Active-HDL Sim 36, 78, 206
Adding Existing Files 221
architecture 22, 122
back-annotating
85
N
26, 122, 244
17
P
C
Compiling 30, 76, 106, 129, 131, 254
Conventions 14, 113
Creating A New Project 44, 117, 241
Creating a New Project 60
Creating the State Machine 48
package 23
Package Declaration
67
R
Running the Simulation
I
42, 83
S
D
Delta39K 116
Differences in Display
entity
Including the Libraries
Naming Restrictions
B
E
I
17
22, 121
F
254
Frequency Agile PSI 280, 317
Functional Simulation 222
G
Generating VHDL
Selecting the Libraries 55
SERDES 281, 318
Setting Stimulus Signal Values 39, 81
Simulating 36, 78, 109, 206
Starting Active-HDL FSM 44
Starting the Tutorial 220
Stimulus 210
Syntax Explanation 90, 93
Synthesizing 30, 33, 76, 106, 129,
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Warp Getting Started Manual
131,
T
Tech Mapping 75, 107
tech mapping 32, 128, 253
Tech Mapping Options 97
351
Index
Timing Model
254
32, 75, 97, 107, 129, 206,
Top-Level Description 26, 69,
Top-Level File 75
top-level file 32, 126, 249
U
Ultra37000
V
103
18, 86
Verilog 86, 90,
VHDL 278
315
W
I
Writing the Architecture 23, 64, 123, 245
Writing the Entity Declaration 23, 62, 122, 244
Writing the Package Declaration 25
Writing the VHDL File 60
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