A JCET Company
Integrated Test Solutions
Full Turnkey Services from Bump, Wafer Probe,
Assembly, Final Test, Post Test to Drop Shipment
Bump
Wafer Probe
Assembly
Final Test
Post Test
Drop Ship
As one of the largest test outsourcing providers, STATS ChipPAC offers a full suite of test
platforms and engineering services to support a broad range of mixed signal, RF, analog and
high-performance digital semiconductor devices for the communications, digital consumer
and computing markets. STATS ChipPAC combines operational efficiencies with proven test
capabilities to achieve the lowest cost of test with the highest possible throughput and faster
time-to-market.
Test Platforms
A JCET Company
MIXED
SIGNAL
DIGITAL
RF
MEMORY
Teradyne
Advantest
LTXC
UltraFLEX
FLEX / microFLEX
Tiger
Catalyst
93K PS400, PS800,
PS1600, PS3600
93K C200, C400
P600
T2000
Fusion CX
Teradyne
Advantest
LTXC
UltraFLEX
FLEX / microFLEX
Catalyst J750
93K PS400, PS800,
PS1600, PS3600
93K C200, C400
P600
T2000
Fusion CX
Teradyne
Advantest
LTXC
UltraFLEX
FLEX / microFLEX
Catalyst 93K Portscale
Fusion CX
Teradyne
Advantest
Magnum
Maverick (1PT/1VT/1/2GT)
T5503
Test Engineering Services
STATS ChipPAC’s experienced R&D and test teams have helped customers reduce their engineering burdens and
prepare products for high volume manufacturing in the shortest time possible. Our world class test development
and test program migration services include:
• Test program development, debug, optimization and validation
• Device characterization
• First silicon characterization (Wafer Probe)
• Probe card design, fabrication and qualification (Wafer Probe)
• Load board design, fabrication and qualification
(Final Test)
• Prototype evaluation
• Multi-site migration to higher parallel testing
• Test program conversion to new tester platform
NEW PRODUCT
• Device Test Feasibility Study
• Target Teaser Identification
Definition/ • Test Plan / Documentation
Planning
• Pattern Generation
• Test Hardware Design / Build
Develop- • Test Program Coding
ment
• Test Verification and Debugging
Evaluation
• Customer Acceptance
• Final Spec and Limit Implementation
Validation • Final Test Documentation
PRODUCTION RELEASE
Wafer Probe
A JCET Company
Wafer Probe is a critical step in semiconductor manufacturing due to the need to minimize device throughput,
yield and quality in order to reduce the overall cost of test. STATS ChipPAC operates some of the highest precision
probers available in the industry. Our probe services include, but are not limited to:
• Probe card design, development and maintenance
• Copper pillar bump wafer probe
• Known Good Die (KGD) testing for System-in-Package
• Prober network customization to support real-time data
• Fine-pitch, RF, bump, thin wafer probing
• Multiple site (x32) probing
• 3 row staggered / sample
• 28nm and 40nm fabrication wafer probe
• Direct Docking Technology
• 300mm (12”), 200mm (8”) or 150mm (6”) wafer probing
Final Test and Post Test
Every stage of the manufacturing process is critical and test automation is an important differentiator. STATS
ChipPAC has established a Next Generation Final Test Cell and highly automated Post Test systems to achieve
extremely high throughput while maintaining a zero defects standard of quality.
Whether you require production with minimum or full engineering support, STATS ChipPAC can provide:
• Prototype verification and 1st silicon debug
• Multi-site implementation: x16 (Digital),
x320 (Memory), x8 (Mixed Signal), x8 (RF)
• Film Frame Strip Test
• Testing advanced wafer level packages
• Testing silicon-based Integrated Passive Devices
• Yield enhancement with monitoring and feedback
• Test time optimization
• Wafer sort to final test correlation feedback
• Quick-turn failure analysis
• Reliability services (i.e., ESD testing, latch-up testing and operating life testing)
• Handlers with Active Thermal Control (ATC)
STATS ChipPAC’s Post Test services include Lead Scan, Final Marking, Tape and Reel, Burn-in, Bake and Dry Pack,
System Level Test and drop shipment as well as other custom post test solutions.
STATS ChipPAC’s fully-automated Post Test processes maximize throughput while minimizing manual handling to
ensure that your devices are shipped on time. We offer a single, integrated approach to managing supply chain
logistics so our customers’ product is efficiently manufactured in multiple geographies while meeting cost targets
and aggressive cycle times.
Integrated Test Management System (ITMS)
STATS ChipPAC’s test capabilities include an innovative
Integrated Test Management System (ITMS) that
efficiently and effectively integrates the test systems
and business processes with all of STATS ChipPAC’s
factories to achieve the highest levels of quality and
throughput with a lower cost of test.
ITMS automates test systems and manufacturing
processes in order to eliminate manual steps, reduce
cycle time and provide an automatic closed-loop
control process with real-time data analysis and
monitoring. ITMS helps STATS ChipPAC’s customers
gain significant yield improvements as well as the
design-in flexibility of having their devices tested
in any of our factories while receiving the same
successful results.
Design-in
Flexibility
Reduced
Cycle Time
Improved
Test Quality
Lower Cost
of Test
A JCET Company
System
Integration
• Test Off-load Management
• Forecast and WIP Management
• RFQ and Billing
Process
Automation
• Test Data / Report Management
• Test Program Auto-load
• Test Yield Monitoring
• Test Data Analysis
• Real-time Test Cell Controls
Process
Control
• Testers / Handlers
• Cards / Options / Licenses
• Integrated Dashboard on Inventory
and Utility
Real-time
Utilisation
Tracking
Value-Add to
Our Customers
Current Capabilities
Shanghai, China
SCC : 983K ft2 facility
IFEZ, Korea
SCK3 : 1,210K ft2 facility
Ichon, Korea
SCK2 : 212K ft2 facility
Singapore
Corporate Headquarters
Yishun, Singapore
SCS : 808K ft2 facility
Woodlands, Singapore
SCH-WD : 51K ft2 R&D facility
Customer Support /Sales Office
Manufacturing Facility
Flexible Test Services to Meet Your Needs
STATS ChipPAC specializes in full turnkey test solutions that are supported in multiple geographies. Since 1999,
we have provided world class test development and proven test experience in RF, mixed signal, digital, memory
and integrated system-on-chip (SOC) devices. We also offer Wafer Sort only or Final Test only options to meet your
unique test requirements. If you are looking for a test provider who can deliver a lower cost of test, proven test
quality, design flexibility, higher yields, reduced cycle time and a broad geographic footprint, STATS ChipPAC has
a solution for you.
STATS ChipPAC Pte. Ltd.
Corporate Headquarters: 10 Ang Mo Kio Street 65, #04-08/09 Techpoint, Singapore 569059. Tel: (+65) 6824 7777
US Headquarters: 46429 Landing Parkway, Fremont, CA USA 94538 Tel: (+1) 510 979 8000
www.statschippac.com