Roadmap Semiconductor Equipment
Innovation Agenda 2016-2019
1. Societal and economic relevance
It is difficult to imagine the modern world without electronics. The internet, electronic banking,
mobile telephony, GPS, digital archiving and retrieval, and surveillance, to name a few, rely
on advanced electronic circuitry, particularly integrated circuits (chips). Chips advance at a
rapid pace. The introduction of digital photography, car navigation systems, notebooks, and
3D games, are recent manifestations of progress in microchips. With further microchip
advancements, we anticipate that electronics will enable a more sustainable society in
many ways. Electronics consuming less power, or improving power efficiency in e.g. gsm
base stations and street lighting, are foreseen to contribute to a less power hungry
developed world. Electronics are a key enabler of teleworking. Wireless network systems will
gather and deliver ambient information to foster safety and security, for instance in
automated dike monitoring and airport security; and enable “smart buildings” where climate
control is automatically adjusted to real demand. New electronic systems for point-of-care
medication and diagnosis will contribute to the needs of an ageing society. How electronic
circuits will evolve to contribute to these societal needs is further detailed in the “components
and circuits” roadmap.
The aforementioned rapid advancement of microchips is described by Moore’s Law (1965).
Intel cofounder Gordon Moore recognized that technology progress allows us to double the
number of components on a chip every 18-24 months. Three mechanisms make this
possible: the miniaturization of components, the increasing size of chips and substrates
(wafers), and the advancement of fabrication technology. The roadmap for R&D in
Semiconductor Equipment is dominated by the same three driving forces. The bi-annually
updated International Technology Roadmap of Semiconductors (ITRS – www.itrs.net)
describes the worldwide R&D agenda for this sector.
Of the ~ 30.2 B$ (2012, est VLSI) global Semiconductor Equipment market about one fifth is
delivered from the Netherlands, mostly to Asia. Consequently virtually all State-of-the-Art
chips in the world contain Dutch IP and are manufactured on some Dutch tools. The market
is extremely volatile; recently year-to-year variation has been a factor of three. It is likely that
the total market size over time will grow at least by 50% (2020 – 45 B$) due to the increased
complexity at future nodes. The litho content now at 7 B$ (2015) is likely to double since it is
the most complex equipment defining the critical dimension needed. Moore’s law is from a
technical viewpoint continuing at least five years. The total R&D investment in this sector in
the Netherlands by the industry is less cyclic and estimated over 1 B€, more than one sixth
of the Dutch private R&D. In some areas the Dutch industry is dominant, like in lithography,
where ASML has a market share in excess of 80%, in other areas significant, especially at
the high-end side (high resolution imaging, atomic layer depositions, etc.).
2. Application and technology challenges
2.1 State of the art for industry
The forefront of semiconductor manufacturing, regarding lithography is flash memory, which
is used mainly in portable devices. Currently, double patterning immersion lithography is
used at line widths of 20 nm. The reduction of line widths is a major drive in the industry,
since it reduces production cost and improves the quality of the manufactured products: they
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Roadmap Semiconductor Equipment
Innovation Agenda 2016-2019
can operate at a higher clock rate, while consuming less energy. Continuous shrinking of the
dimension is the first business principle that makes commercial success in the
semiconductor industry possible. Furthermore, the introduction of 3D structures, like
FinFETs, poses new challenges to the industry.
The 14nm technology node is about to be introduced by market leaders. Preparations for
10nm node and beyond are ongoing and demands amongst others the introduction of
several new materials (especially to further increase the speed of reading/writing and to
reduce memory cell size), technologies for low temperature processing (e.g. lowtemperature conformal atomic layer deposition), and introduction of new lithography
technologies like Extreme Ultraviolet (EUV) lithography.
The current mainstream wafer size in the industry is a diameter of 300mm. Each ten to
fifteen years the wafer size is increased by a factor of 1.5, giving a cost reduction of at least
30%. This cost reduction due to increase in wafer size is the second business principle,
however it requires a high investment in totally new factories and a totally new set of
equipment.
Productivity improvement is a constant drive in the industry, the number of wafers that are
processed per hour is constantly pushed upwards to reduce production cost. For instance
lithography machines now run at 250 300mm wafers per hour, next year at 275. This
productivity increase is realized almost without additional investment in the factory.
In the display area a move to flexible substrates is expected in the next 10 years.
Lithography on flexible substrates will give serious challenges, requiring adaptive printing.
Another driving force in the display marketplace is the introduction of displays for improved
display qualities and reduced power consumption. This requires new thin film and deposition
technologies that are compatible with the vulnerable functional layers and smaller feature
sizes and more flexible substrates. In this context the now accelerating evolution of printed
electronics as in smart watches or on stressable foils will require new semicon equipment
(for the backend industry).
2.2 Future outlook, in present and emerging markets
In the next ten years the semiconductor market is likely to continue growing by
approximately 14% per year in silicon area, while the complexity will keep increasing with a
rapid pace. The number of process steps and use of diverse materials will increase. This is
all good news for the equipment industry. While the transition to 450mm wafer sizes is
currently on hold, and fewer “super” semi-conductor companies will continue to control a
larger part of the market, smaller players can be involved in the introduction of EUV or create
new niche markets. These new markets will show a high level of “More than Moore” and a
high package diversification.
2.3 Major industry challenges
Continuous miniaturization
The reduction in feature size as well as the application of 3D structures will continue to be
further pursued by industry for at least the next 10 years. This will drive the development of
production and metrology equipment, but also the synthesis of new materials as well as
atomic deposition control as well as the quality of chip factories. Processes like double
patterning, pitch division or directed self assembly will become more important in the
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Roadmap Semiconductor Equipment
Innovation Agenda 2016-2019
reduction in feature size. But also materials, previously forbidden in a CMOS environment
today become necessary. Practically the complete periodic system appears in the fabs and
all kind of e.g. avoidance of contamination measurements are needed. This has great
consequences for the whole chain of semiconductor equipment from lithography and
processing to inspection. Most obvious is the development in lithography, where in the next
few years the introduction of Extreme UV wavelengths in mass fabrication is scheduled.
Main challenges in the EUV are the availability of high-brightness EUV light sources and
optics and defect free reticles with or without pellicle with high reflectivity and prolonged
lifetimes. Thermal loading and energy usage in future systems also require innovations.
Higher productivity
For economic reasons a high throughput and ease of use and service of the production
machines is needed. This leads to lightweight designs and optimal user interfaces. The
mechatronic control of such constructions demands for new control and measurement
strategies to improve the position accuracy down to the picometer level. It can also be
economically advantageous to use thinner substrates. Due to their fragility, breakthroughs in
substrate handling are a prerequisite. Furthermore, throughout the processing chain, minienvironment control by e.g. FOUP purge for batch systems, increased productivity by higher
load sizes and faster temperature control will be required to meet the productivity demands.
Improving yield with contamination control
With the continuous shrinking nodes and thinner layers used in the industry the need for
Contamination Control becomes more important to keep up yield in the production, which is
a pre requisite for affordable chips. The presence of 10 nm particles on a wafer will result in
bad dies (yield loss) while at the moment it is not possible to detect those particles. The
same goes for molecular contamination at the level of sub monolayer concentrations. There
is a need in the industry for better detection methods, prevention strategies and cleaning
technologies to maintain the necessary yield.
Improving the accuracy of production equipment by minimizing thermal effects
For many years the control of dynamics and disturbances has been the competitive element
in precision equipment. The next limit to performance is caused by temperature-induced
effects on the pattern fidelity and overlay accuracy, which have to be in the range of few nm.
Understanding the flow of energy at the milli-Kelvin level both in time and space is needed to
enable the design of next generation tools. The challenges for lithography is in a lightweight,
but stiff wafer stage, requiring new technology with active dimension control, with increased
light levels and improved wafer handling.
Product metrology
As a result of “more Moore”, metrology and characterization of semiconductor products
become more critical since the features to be observed are becoming so small that imaging
requires new technology like Transmission Electron Microscopy (TEM) or high-throughput
electron beam inspection. Next to that the move to 3D structures and device integration will
lead to the application of new technologies like high-throughput Scanning Probe Microscopy.
Affordable high-end, low volume production.
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Innovation Agenda 2016-2019
The start-up costs for a new chip (design, masks, tool costs) at the high end have become
prohibitively high for small series as required in specialty products and scientific research for
"more than Moore". New tools (such as direct write lithography) and processes (open source
design software) are needed.
Flexible printing
New substrates will require litho machines where the image can be adapted to the
deformation of the substrate.
III-V materials
Given the developments at the Dutch academia also the recent developments regarding III-V
materials are to be mentioned. This development, today on 2-4-6 inch wafers is evolving
towards industrial use. In the context of semiconductor equipment this does not require
specific attention. It is more the broad use of more exotic materials has an impact on new
equipment in general.
2.4 Future technology outlook
The semiconductor equipment roadmap is driven by the developments in semiconductor
technology. In the coming 3 to 15 years, we distinguish two trends:
1. Further miniaturization of integrated circuits with basically the same functionality as
today: processors, memory, logic, etc. At the pace set by Moore’s law, this puts
extreme demands on innovations concerning existing equipment. Often it requires
the use of new materials (e.g. ultra thin Si-On-Insulator (SOI), nickel silicide, hafnium
based dielectrics) or new instrument principles (for example transmission electron
microscopy instead of light microscopy for inspection). Some call this “more Moore”.
2. Introduction of new physical principles in chips and packages: optical and wireless
communication, graphene-based conduction, on-chip sensing, actuation, energy
harvesting, etc. Those chips may be more application-specific, such that smaller
series must be produced with equipment that provides greater manufacturing
flexibility. This requires totally new types of semiconductor equipment. Some call this
“more than Moore”.
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Innovation Agenda 2016-2019
The diagram illustrates three possible approaches towards achieving the necessary
innovations in the area of semiconductor equipment:
1. Understanding and improving existing equipment that has already been introduced
into the market.
2. The development of new fabrication processes and tools motivated and necessitated
by the introduction of new materials and device concepts.
3. Innovations regarding process- and equipment concepts can expand the boundaries
of manufacturability of new devices.
3. Priorities and implementation
The two pillars of the strong position of the Semi-Conductor Equipment industry is the
knowledge base and the excellent and world class supply chain. The knowledge base
includes fields such as light-, electron- and EUV-optics, plasma physics, surface physics and
chemistry, heat- and fluid-transport, precision mechanics, electronics, applied mathematics,
materials science, vacuum technology, contamination control, embedded system technology,
thin film technology, fast data processing, etc. The supply chain has exceptional strength in
complicated electro mechanical assemblies and control. However, the supply chain is not
very strong in initiating its own R&D for the development of products for the future. The goal
of the programs in this roadmap is to strengthen and focus the activities in these fields,
guided by the following priorities:
Involving the supply chain in an integrated R&D and supply position. For instance in
Germany, it is very common, that suppliers perform the necessary R&D for the subsystem
delivered on their own risk, unfortunately much less so in the Netherlands. Involving the
supply chain in International R&D projects will assist them to improve this situation.
Modeling, understanding and controlling the physics, chemistry, mechanics and
electronics of existing types of equipment (Innovating equipment for “more Moore”).
 Control of surface processes in (vacuum) tools.
 Complex equipment components enabling the sub-14 nm and beyond (i.e. 10 en 7
nm) generations of semiconductor equipment and tooling.
 Computational models and algorithms for wafer processing and inspection.
 Higher throughput equipment for the inspection requirements of the sub-22 nm
generations.
 Thermo-mechanical models for interaction of high intensity laser beams with multimaterial composites in dicing and additive manufacturing
 Understanding the interaction between light, EUV or electrons with resist materials.
Understanding, modeling and controlling the processes for volume production of new
materials or functions in chips or in packages
 Processes for further miniaturization, compatible with volume manufacturing
(processes for “more Moore”).
 Processes for the introduction of new functions in volume manufacturing (processes
for “more than Moore”).
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Translating desired processes into principles and architectures of new equipment
and testing the basic functionality of these new instruments.
 New principles in manufacturing equipment necessary for further miniaturization (new
equipment for “more Moore”).
 Equipment for devices with new functionality (new equipment for “more than Moore”).
 New principles in inspection and metrology equipment.
 Pick-and-place e.g. on thin wafers.
A new entity in the Dutch R&D environment is the Advanced Research Center for
Nanolithography (ARCNL) focusing on the fundamental physics involved in current and
future key technologies in nanolithography, primarily for the semiconductor industry. This
novel form of PPP has especially been established to maximize the opportunities in the
longer term for the Dutch industry, in particular for ASML. The initial emphasis of ARCNL’s
research program is on EUV lithography.
3.1 TKI program
The best possible institute should be charged with executing work under the TKI
program, not necessarily the institute that provides the base for the TKI. Application
of the TKI funds as counter financing source for institutes and universities might
improve quality and solve the problem of financing in international programs.
Quite a diverse group of projects take place under the SCE TKI programme, many litho
related: regarding immersion lithography, EUV, mirror technology, E-beam litho technology,
improved and plasma resistant mirrors, alignment technologies to assure an overlay
substantially less than 1 nm and a wafer stage capable of 300 wafers/hour and if feasible the
realisation of a technology demonstrator for a flexible printer. In order to advance the
capabilities in the supply base a major program on 3D printing is underway. Advanced
imaging and power electronics are other subjects.
3.2 European program
Focus in the SCE Roadmap for the International cooperation is on the realisation of enabling
equipment and processes for 10nm and beyond on 300mm wafers is first focus now. The
Dutch supply chain will broadly participate in the Dutch contingent of this large international
project. Project will be submitted in ECSEL. The ultimate goal is to realize a 7nm node pilot
facility, maximally equipped with European generated equipment. Application of TKI
funding for institutes and universities should be promoted.
4. Partners and process
Some thirty Dutch OEMs, like ASM, ASML, Mapper and FIE and smaller companies like
BESI, ALSI, SolMateS and Bronkhorst are all active in the SCE sector, while a very large
number are active in the supply chain. This dynamic group of more than 200 companies is
committed to actively participate in the SCE program. Also Carl Zeiss SMT is a major
investor in Dutch R&D, presently mainly in EUV mirror program at the UTwente.
Prime scientific participants are ARCNL, UT, TUD, TU/e, DIFFER, while RUG, UU, UL, VU,
SRON, ASTRON, Nikhef are also participating. Important institutes are M2I, ESI and TNO.
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5. Investments
The SCE sector is by far the largest private R&D investor in the Netherlands, more than 1 B€
yearly or more than one sixth of the total Dutch private R&D investment and better than
one third of the R&D investment in the HTSM sector. Contributions from RDA and TKI in the
sector appear to be lagging somewhat, so a challenge to bring this to proportional levels,
compared to the total investment.
Roadmap
Industry
TNO
ECN
NWO
Universities
Departments1 and regions2
Grand total
2015
120
4
.5
1
10
23
158.5
2016
120
4
1
1
10
23
159
2017
120
4
1
1
10
23
159
2018
120
3
1
1
10
24
159
2019
120
3
1
1
10
24
159
European agenda within roadmap
Industry
TNO
ECN
NWO
Universities
Co-financing of European programs3
European Commission
2015
100
1
.5
2016
100
2
.5
2017
100
2
.5
2018
100
2
.5
2019
100
2
.5
1
15
15
2
15
15
2
15
15
2
15
15
2
15
15
1
Ministries, excluding contributions to TKI HTSM
Regional and Local Authorities
3
Ministry of Economic Affairs contributions to JU ECSEL and EUREKA clusters
2
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