A Low-Power Multi-band ECoG/EEG Interface IC
Fan Zhang∗ , Apurva Mishra∗ , Andrew G. Richardson† , Stavros Zanos† , and Brian P. Otis∗
∗ Department
† Department
of Electrical Engineering, University of Washington, Seattle, WA 98195-2500
of Physiology and Biophysics, University of Washington, Seattle, WA 98195-2500
Abstract—We present a 6.4 µW electrocorticography
(ECoG)/electroencephalography (EEG) processing integrated
circuit (EPIC) with 0.4 µVrms noise floor intended for
emerging brain-computer interface (BCI) applications. This
chip conditions the signal and simultaneously extracts energy
in four fully-programmable frequency bands. Functionality is
demonstrated by tuning the four bands to important frequency
bands used by ECoG/EEG applications: α (8-12Hz), β (1826Hz), low-γ (30-50Hz) and γ (70-100Hz). Measured results
from in-vivo ECoG recording from the primary motor cortex of
an awake monkey are presented.
I. I NTRODUCTION
Electrocorticography (ECoG) is a method of recording
electrical brain activity using planar electrodes on the surface
of the brain cortex. ECoG electrodes may be more suitable for
long-term recordings than intracortical electrodes, as ECoG
recording quality may be less affected by electrode movement
and the tissue response [1]. ECoG implants, used extensively
in the diagnosis of epilepsy [2], have recently demonstrated
promising results towards potential use in brain-computer
interfaces (BCIs): systems to help people with movement
disorders communicate or operate motor prosthetic devices.
Certain frequency ranges of ECoG signals from motor cortical
areas are found to be associated with movement or movement
intentions, and have been used with BCI systems that allow
subjects to control a cursor on a computer screen [1].
Since ECoG spectral changes in specific frequency ranges
are believed to be markers of cortical neuronal activity, a
recording system that extracts sub-banded energy content in
real time would be useful for ECoG-based BCI applications. In
a wireless system, this would reduce the amount of data that
needs to be transmitted out of the recording chip, resulting
in reduced power dissipation. This is particularly important if
many channels (e.g., 16) are processed on each chip. In this
paper, we present an ECoG/EEG processing integrated circuit
(EPIC) with 6.4 µW core power dissipation primarily designed
for, but not limited to, ECoG-based BCI applications. This
chip conditions the signal and simultaneously extracts energy
from four independently tunable bands. The outputs will be
digitized and transmitted to a body-worn device or a remote
station for further processing. Classifiers can then be applied
to the transmitted spectral information to decode movement
intentions. This work focuses on the ultra-low power real-time
energy detection of four frequency bands.
II. S YSTEM AND C IRCUIT D ESIGN
EPIC functions as a computational interface between brain
electrodes and A/D converter in a neural-recording system.
Fig. 1. System block diagram of the ECoG/EEG processing IC (EPIC) to
be used in BCI applications.
Fig. 1 shows the system block diagram, comprising four main
blocks: a low-noise analog front-end (AFE) that amplifies the
input waveforms, four configurable band energy extractors,
clock generation, and control logic. All four band energy
extractors are power- and clock-gated so that any or all of
the bands can be enabled at a time. Fully-differential design
is used throughout EPIC to ensure sufficient output swing and
improve the CMRR/PSRR for low supply voltages (1.2V).
A. Analog Front-End (AFE)
ECoG/EEG-recording applications demand a low noise floor
(<5 µVrms input-referred) and a relatively low bandwidth
(<500Hz). We employ a chopper-stabilized topology to suppress offsets and 1/f noise that dominates in low-frequency
designs. A fully-differential chopper-stabilized closed-loop
amplifier [3] is used to provide 40 dB of gain. A programmable
Gm-C filter is used to reduce switching ripple to below the
noise floor. The outputs are then fed into a variable-gain
amplifier (VGA) with 6 programmable gain settings from 0
to 34 dB and 7 variable high-pass corners, including a sub-Hz
corner formed by pseudoresistors.
B. Band Energy Extractor
Simultaneously calculating signal energy in multiple bands
is necessary to decode neuronal activities [1][4]. To accomodate subject variation and various classification algorithms, the
frequency band selection, integration gain, integration duration
should be fully programmable. Previous implementations of
energy estimators have been reported in [5][6]. In [5], heterodyning dual-nested chopping architecture enables selectability
of the center frequency (fo ) and bandwidth (BW), while
eliminating offsets and low-frequency noise. However, the heterodyne chopping architecture requires two relatively powerhungry front-end low-noise amplifiers to extract spectral power
from one frequency band. In addition, the fo trim step size
(5Hz) is too coarse to realize stagger tuning [6] especially
in α and β bands. In [6], Gm-C filters are used to realize
a stagger-tuned fourth-order bandpass filter, followed by a
squaring circuit and a leaky integrator. However, the fo and Q
of the band-pass filter (BPF) can not be independently tuned.
In addition, the precise location of fo requires trimming due
to process variation in the bias current. Here we present the
design of a 2.6µW band energy extractor that simultaneously
outputs the real-time energy in four independently tunable
frequency bands. Switched-capacitor (SC) techniques are used
here to realize tunable band-pass filter and integrator. Precise
SC frequency responses are obtained without external trimming because frequency response only depends on capacitor
ratios and clock frequency. The band energy extractor consists
of a tunable 4th-order SC BPF, a continuous-time Gilbert-cell
multiplier, and a tunable SC integrator (Fig. 1).
Two stagger-tuned 2nd-order SC biquad sections are used
to realize a programmable 4th-order BPF. Fig. 2 shows the
simplified schematic of one 2nd-order SC biquad section. fo
and Q are determined by:
C3 1
(1)
fc
C2 2π
C2
Q=
(2)
C1
φ1,2 represent two non-overlapping phases. Dual-switch
configurations with minimum-sized switches are used to reduce stray capacitance errors and charge injection [8]. The
switches connecting to the virtual ground nodes near the OTA
inputs are turned off first during φ1a,2a , so that the charge
injected is the same from one clock cycle to the next and can
be considered as a DC offset.
fo =
varying the divided clock frequency fc in octave steps. Fine
tuning varies the fo within each coarse frequency step by
controlling the capacitor banks C3 . Fine tuning provides 16
center frequencies spread logarithmically over each octave of
frequency. This technique provides both a wide tuning range
and fine frequency steps, which is consistent with the common frequency bands used in ECoG/EEG applications, where
smaller frequency steps are desired in the low frequencies to
resolve consecutive bands within a few Hz of each other.
By adjusting the C1 capacitor banks, the Q is tunable from
0.5 to 8 over 16 linear steps. To save area, we use linear
combinations of 7 capacitors to realize 16 Q values (Eqn. 2).
In C1 capacitor banks, unused capacitors are connected to the
output on one end, and virtual ground on the other to reduce
switching glitches in the output [7].
The biquad OTAs are realized with fully-differential telescopic two-stage op-amps. The OTA bandwidth needs to
be at least 5 times fc to reduce the effects of finite OTA
bandwidth on SC operation [9]. When fc is varied to tune
the biquads to different frequencies, the bias currents in the
OTAs are digitally adjusted accordingly to save power. SC
common-mode feedback (CMFB) is used as a convenient and
power-efficient approach to ensure a stable and well-controlled
common-mode operation.
Fig. 3 shows the multiplier circuit that squares the signals
from the BPF. The BPF outputs are AC-coupled into the
multiplier to reject DC offsets. The multiplier consists of a
subthreshold CMOS Gilbert multiplier core that squares the
input voltage, a transimpedance stage, and an output stage
that lowers the output impedance. By sensing the CM voltage
at the output and feeding the CMFB control voltage to the
transimpedance stage, only one CMFB loop is required. Three
bits of current tuning at the outputs of the transimpedance
stage are used to trim the differential DC offsets. This block
also functions as an anti-aliasing filter for the SC BPF.
Fig. 3.
Fig. 2.
Schematic of the 2nd-order SC biquad.
To achieve a wide tuning range and fine tuning steps
for fo , coarse tuning adjusts the center frequency fo by
Schematic of the multiplier and the SC integrator.
We used a SC technique to realize a lossless integrator with
precise and adjustable integration window and gain. An areaefficient approach [10] is employed to realize large integration
time constants (Fig. 3). This operation effectively attenuates
the input voltage by a factor C3 /C2 , then integrating it onto
C2 through C1 . The unity gain frequency of the integrator and
the integration time constant are approximately given by:
fu =
C1 C3
1
fc
2π C1 + C2 C2
(3)
1
2πfu
(4)
τ=
The integration output is reset periodically by a variable
reset clock, divided from its SC clock. Because the gain of the
integration can be approximated as the ratio of the reset time
window and the time constant (Trst /τ ), C2 can be selected to
vary τ , and thus the gain of the integration.
C. Clock Generation
As shown in Fig. 1, four sets of independently programmable SC BPF and integrator clocks are derived from
a 160kHz on-chip crystal oscillator. A 20kHz chopper clock
is chosen to maintain compatility of the chopper-stabilized
amplifier and all the SC blocks. Because discrete-time SC operations are sensitive to the sampling instant, the SC integrator
clocks are shifted by 90 degrees to avoid sampling transients
from the SC BPF. Programmable SC BPF clocks are derived
from in-phase (I) of the 20kHz clock, and programmable SC
integrator and reset clocks are derived from the quadraturephase (Q).
Fig. 5. Measured frequency responses of one biquad: a) coarse fo tuning
when fc is varied; b) fine fo tuning when C3 is changed; c) Q tuning when
C1 is changed.
D. Control Logic
The control logic supplies the synchronization and reset
controls for multiplexing the four integrators in a round-robin
fashion. The synchronization pulses are immediately followed
by the reset pulses.
III. E XPERIMENTAL RESULTS
EPIC was fabricated in a 0.13 µm CMOS process. Systemlevel performance is summarized in Table I. The total current
draw is roughly 9 µA from a 1.2V supply: 2.7µA from the
chopper amplifier/VGA, 2.6 µA from the four energy extractors combined, 2.7µA for bias generation, and approximately 1
µA for the auxilary circuitry such as crystal oscillator, digital
clock generation and logic. The die photo is shown in Fig.
4(a). The total active area is 1400 µm by 2000 µm, and each
energy extractor occupies 0.46 mm2 .
A. Characterization of the BPF
Fig. 5(a) shows the coarse fo tuning from 3.12 to 200Hz,
and Fig. 5(b) shows the fine fo tuning from 200 to 400Hz, both
with logarithmically incremental steps. 16 Q tuning frequency
responses from Q = 0.5 to 8 are illustrated in Fig. 5(c) with
fo set to 200Hz.
B. Multi-band Spectral Analysis
The fo and Q of the 2nd-order biquad sections are tuned to
realize an overall 4th-order Butterworth BPF responses. BPF
responses in four common frequency bands used in ECoG
research (α or 8-12Hz, β or 18-26Hz, low-γ or 30-50Hz, and
γ or 70-100Hz) are synthesized by configuring the two biquads
(Fig. 6(top)). Close resemblance between the measured (solid
Fig. 6. Top: measured frequency response (solid) compared to theoretical
(dotted) of BPF tuned to α, β, low-γ and γ bands; bottom: measured inputreferred noise plots of LNA, VGA and BPF tuned to these four bands.
line) and the theoretical (dotted line) BPF responses were
observed.
Fig. 6(bottom) illustrates the input-referred noise spectrum
at the output of the VGA and BPF when tuned to the four
bands described above. The AFE is set to the maximum gain
in order to characterize the noise √
performance when signal is
weakest. The AFE with a 85nV/ Hz noise floor limits the
resolution. Flicker noise and lower bias currents used in the α
and β bands results in slightly higher noise. The integrated
input-referred noise within the four passbands at the BPF
output are 0.3, 0.29, 0.31, and 0.35µV respectively. The inputreferred noise over the same bands at the output of the LNA
and VGA alone are 0.18, 0.21, 0.31, and 0.34µV respectively.
A 6-second pre-recorded human ECoG waveform [11] was
processed by the chip. Fig. 4(c) compares the measured (solid)
with the modeled (dashed) energy-extractor responses from
four simultaneously recorded freqency bands. Close matching
was observed.
Fig. 4. Left: die photo; middle: performance comparison table with [5]; right: theoretical (dashed) and measured (solid) energy profile in a) signal, b) α, c)
β, d) Low γ, e) γ band for a 6-second ECoG waveform [11].
IV. I N - VIVO EXPERIMENT RESULTS
An in-vivo ECoG recording was performed from the primary motor cortex of a pigtailed macaque monkey (Macaca
nemestrina), through a 32-electrode subdural array (PMT
Corp.). The electrodes were platinum, had an exposed diameter
of 0.075 mm and impedances of 50-100 kΩs measured at 1
kHz. EPIC was connected directly to the ECoG electrodes
through a 0.16 Hz high pass DC blocking RC filter.
To assess the fidelity of the signals recorded using EPIC, we
compared the output of EPIC to the simultaneously-recorded
digitized output of a 24-bit ADC (gUSBamp, Guger Tech.)
sampling at 2.4 ksps/s. Fig. 7 shows two 1-second recording
segments: the first shows activity in the β/low-γ band; the
second shows ECoG activity with no increased frequencyspecific components (baseline). No noticeable difference was
observed between the EPIC (solid) and the gUSBamp (dotted)
recordings. The PSD (power spectral density) illustrates the
increased power in the 15-45Hz range in the first segment
compared to the second.
Fig. 7. Recording of in-vivo ECoG data from an awake monkey with EPIC
and a commercial ADC (gUSBamp). PSD and time-domain representations
of two segments: I. β/low-γ activity; II. baseline activity.
V. C ONCLUSION
We present a four-band EPIC with 6.4 µW core power dissipation and 0.4 µVrms input-referred noise floor integrated over
ECoG/EEG-relevant frequency bands. This chip conditions
the signal and simultaneously extracts energy from four programmable bands. The broad tuning range and logarithmically
incremental fine tuning steps of the band energy extractors are
tailored for ECoG signal characteristics. This work features
programmable multi-band spectral analysis with comparable
power consumption to the state-of-the-art.
VI. ACKNOWLEDGEMENT
The authors gratefully acknowledge Reinhold Scherer and
Felix Darvas for their pre-recorded ECoG data set.
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