FastIRFET™
IRFH4255DPbF
HEXFET® Power MOSFET
Q1
Q2
VDSS
25
25
V
RDS(on) max
(@VGS = 4.5V)
4.60
2.10
m
Qg (typical)
10
23
nC
ID
(@TC = 25°C)
30
30
A
Applications

Control and Synchronous MOSFETs for synchronous buck
converters
DUAL PQFN 5X6 mm
Features
Control and synchronous MOSFETs in one package
Low charge control MOSFET (10nC typical)
Low RDSON synchronous MOSFET (<2.10m)
Intrinsic Schottky Diode with Low Forward Voltage on Q2
RoHS Compliant, Halogen-Free
MSL1, Industrial Qualification
Base part number
Package Type
IRFH4255DPbF
Dual PQFN 5mm x 6mm
Benefits
Increased power density
Lower switching losses
results in Lower conduction losses
Lower Switching Losses

Environmentally friendlier
Increased reliability
Standard Pack
Form
Quantity
Tape and Reel
4000
Orderable Part Number
IRFH4255DTRPbF
Absolute Maximum Ratings
IDM
Parameter
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 4.5V
Continuous Drain Current, VGS @ 4.5V
Continuous Drain Current, VGS @ 4.5V
(Source Bonding Technology Limited)
Pulsed Drain Current
PD @TC = 25°C
PD @TC = 70°C
Power Dissipation
Power Dissipation
TJ
TSTG
Linear Derating Factor
Operating Junction and
Storage Temperature Range
VGS
ID @ TC = 25°C
ID @ TC = 70°C
ID @ TC = 25°C
Q1 Max.
Q2 Max.
± 20
64
105
51
84
Units
V
A
30
30
120
420
31
20
38
24
W
0.25
0.30
W/°C
-55 to + 150
°C
Thermal Resistance
Parameter
RJC (Bottom) Junction-to-Case 
Junction-to-Case 
RJC (Top)
Junction-to-Ambient 
RJA
Junction-to-Ambient 
RJA (<10s)
Q1 Max.
4.0
20
34
Q2 Max.
3.3
12
31
24
19
Units
°C/W
Notes  through  are on page 12
1
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April 14, 2014
IRFH4255DPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
Drain-to-Source Breakdown Voltage
BVDSS/TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
VGS(th)/TJ Gate Threshold Voltage Coefficient
IDSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
IGSS
Gate-to-Source Reverse Leakage
gfs
Forward Transconductance
Qg
Total Gate Charge
Qgs1
Pre-Vth Gate-to-Source Charge
Qgs2
Post-Vth Gate-to-Source Charge
Qgd
Gate-to-Drain Charge
Qgodr
Gate Charge Overdrive
Qsw
Switch Charge (Qgs2 + Qgd)
Qoss
Output Charge
RG
Gate Resistance
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
2
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Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Min. Typ.
25
–––
25
–––
–––
22
–––
23
––– 2.50
––– 1.20
––– 3.70
––– 1.65
1.1
1.6
1.1
1.6
––– -5.7
––– -5.3
––– –––
––– –––
––– –––
––– –––
––– –––
––– –––
131 –––
182 –––
–––
10
–––
23
–––
2.5
–––
4.5
–––
1.6
–––
2.3
–––
3.8
–––
8.4
–––
2.1
–––
7.8
–––
5.4
––– 10.7
–––
10
–––
23
–––
2.4
–––
1.5
–––
10
–––
10
–––
61
–––
43
–––
13
–––
27
–––
15
–––
26
––– 1314
––– 2877
––– 365
––– 907
–––
92
––– 234
Max. Units
–––
V
–––
–––
mV/°C
–––
3.20
1.50
m
4.60
2.10
2.1
V
2.1
–––
mV/°C
–––
1.0
µA
250
100
100
nA
-100
-100
–––
S
–––
15
35
–––
–––
–––
–––
nC
–––
–––
–––
–––
–––
–––
–––
nC
–––
–––

–––
–––
–––
–––
–––
ns
–––
–––
–––
–––
–––
–––
–––
pF
–––
–––
–––
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Conditions
VGS = 0V, ID = 250µA
VGS = 0V, ID = 1.0mA
Reference to 25°C, ID = 1.0mA
Reference to 25°C, ID = 10mA
VGS = 10V, ID = 30A 
VGS = 10V, ID = 30A 
VGS = 4.5V, ID = 30A 
VGS = 4.5V, ID = 30A 
Q1: VDS = VGS, ID = 35µA
Q2: VDS = VGS, ID = 100µA
Q1: VDS = VGS, ID = 35µA
Q2: VDS = VGS, ID = 1mA
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V
VGS = 20V
VGS = 20V
VGS = -20V
VGS = -20V
VDS = 10V, ID = 30A
VDS = 10V, ID = 30A
Q1
VDS = 13V
VGS = 4.5V, ID = 30A
Q2
VDS = 13V
VGS = 4.5V, ID = 30A
VDS = 16V, VGS = 0V
Q1
VDS = 13V VGS = 4.5V
ID = 30A, Rg = 1.8
Q2
VDS = 13V VGS = 4.5V
ID = 30A, Rg = 1.8
VGS = 0V
VDS = 13V
ƒ = 1.0MHz
April 14, 2014
IRFH4255DPbF
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy 
Diode Characteristics
Parameter
IS
Continuous Source Current
(Body Diode)
ISM
Pulsed Source Current
(Body Diode)
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
3
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© 2014 International Rectifier
Typ.
–––
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Min.
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
–––
–––
16
26
13
34
Q1 Max.
61
Q2 Max.
364
Units
mJ
Max. Units
Conditions
30
A MOSFET symbol
30
showing the
120
A integral reverse
p-n junction diode.
420
1.0
V TJ = 25°C, IS = 30A, VGS = 0V
0.75
TJ = 25°C, IS = 30A, VGS = 0V
–––
ns Q1 TJ = 25°C, IF = 30A
–––
VDD = 13V, di/dt = 235A/µs 
––– nC Q2 TJ = 25°C, IF = 30A
VDD = 13V, di/dt = 270A/µs 
–––
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IRFH4255DPbF
Q2 - Synchronous FET
Q1 - Control FET
1000
1000
100
BOTTOM
VGS
10V
5.0V
4.5V
3.5V
3.1V
2.9V
2.7V
2.5V
10
1
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
BOTTOM
10
2.5V
60µs PULSE WIDTH
60µs PULSE WIDTH
2.5V
Tj = 25°C
Tj = 25°C
0.1
1
0.1
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
100
1000
100
BOTTOM
VGS
10V
5.0V
4.5V
3.5V
3.1V
2.9V
2.7V
2.5V
10
2.5V
TOP
ID, Drain-to-Source Current (A)
TOP
BOTTOM
VGS
10V
5.0V
4.5V
3.5V
3.1V
2.9V
2.7V
2.5V
100
2.5V
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 150°C
Tj = 150°C
10
1
0.1
1
10
0.1
100
1
10
100
VDS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 3. Typical Output Characteristics
Fig 4. Typical Output Characteristics
1000
ID, Drain-to-Source Current(A)
1000
ID, Drain-to-Source Current (A)
10
Fig 2. Typical Output Characteristics
1000
ID, Drain-to-Source Current (A)
1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
T J = 150°C
10
T J = 25°C
1
100
TJ = 150°C
10
TJ = 25°C
VDS = 15V
VDS = 15V
60µs PULSE WIDTH
60µs PULSE WIDTH
1.0
0.1
1.5
2.0
2.5
3.0
3.5
4.0
VGS, Gate-to-Source Voltage (V)
Fig 5. Typical Transfer Characteristics
4
VGS
10V
5.0V
4.5V
3.5V
3.1V
2.9V
2.7V
2.5V
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© 2014 International Rectifier
1
2
3
4
VGS, Gate-to-Source Voltage (V)
Fig 6. Typical Transfer Characteristics
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April 14, 2014
IRFH4255DPbF
IRFH4255DPbF
Q2 - Synchronous FET
Q1 - Control FET
100000
100000
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Crss = C gd
Coss = Cds + Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
C, Capacitance (pF)
10000
Ciss
Coss
1000
Crss
10000
Ciss
Coss
1000
100
Crss
10
100
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
VGS, Gate-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
12.0
VDS= 20V
VDS= 13V
10.0
8.0
6.0
4.0
2.0
0.0
ID= 30A
12.0
VDS = 20V
VDS= 13V
10.0
8.0
6.0
4.0
2.0
0.0
0
5
10
15
20
25
30
0
QG, Total Gate Charge (nC)
1000
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
100µsec
Limited by package
1
1msec
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
DC
0.01
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 11. Maximum Safe Operating Area
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20
30
40
50
60
Fig 10. Typical Gate Charge vs. Gate-to-Source Voltage
© 2014 International Rectifier
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
10
QG, Total Gate Charge (nC)
Fig 9. Typical Gate Charge vs. Gate-to-Source Voltage
5
100
14.0
ID= 30A
0.1
10
Fig 8. Typical Capacitance vs. Drain-to-Source Voltage
14.0
10
1
VDS , Drain-to-Source Voltage (V)
OPERATION IN THIS AREA LIMITED BY R
100
DS
(on)
100µsec
10
Limited by Package
1msec
1
10msec
0.1
DC
Tc = 25°C
Tj = 150°C
Single Pulse
0.01
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 12. Maximum Safe Operating Area
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IRFH4255DPbF
Q2 - Synchronous FET
Q1 - Control FET
1.8
ID = 30A
VGS = 4.5V
1.4
RDS(on) , Drain-to-Source On Resistance
(Normalized)
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1.6
1.2
1.0
0.8
0.6
ID = 30A
VGS = 4.5V
1.6
1.4
1.2
1.0
0.8
0.6
-60 -40 -20 0
20 40 60 80 100 120 140 160
-60 -40 -20 0
T J , Junction Temperature (°C)
Fig 13. Normalized On-Resistance vs. Temperature
Fig 14. Normalized On-Resistance vs. Temperature
1000
ISD, Reverse Drain Current (A)
1000
ISD, Reverse Drain Current (A)
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
100
T J = 150°C
10
T J = 25°C
100
TJ = 150°C
TJ = 25°C
10
VGS = 0V
VGS = 0V
1.0
1.0
0.4
0.5
0.6
0.7
0.8
0.9
0.2
1.0
10
ID = 30A
8
6
T J = 125°C
2
T J = 25°C
0
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 17. Typical On-Resistance vs. Gate Voltage
6
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0.8
1.0
1.2
Fig 16. Typical Source-Drain Diode Forward Voltage
RDS(on), Drain-to -Source On Resistance (m)
RDS(on), Drain-to -Source On Resistance (m )
Fig 15. Typical Source-Drain Diode Forward Voltage
2
0.6
VSD , Source-to-Drain Voltage (V)
VSD, Source-to-Drain Voltage (V)
4
0.4
© 2014 International Rectifier
5.0
ID = 30A
4.0
3.0
TJ = 125°C
2.0
1.0
TJ = 25°C
0.0
0
5
10
15
20
VGS, Gate -to -Source Voltage (V)
Fig 18. Typical On-Resistance vs. Gate Voltage
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April 14, 2014
IRFH4255DPbF
Q2 - Synchronous FET
Q1 - Control FET
70
120
Limited By Package
Limited By Package
100
50
ID, Drain Current (A)
ID, Drain Current (A)
60
40
30
20
80
60
40
20
10
0
25
50
75
100
125
0
150
25
TC , Case Temperature (°C)
125
150
2.5
VGS(th), Gate threshold Voltage (V)
2.0
1.8
ID = 35µA
1.6
1.4
1.2
2.0
1.5
ID = 1.0mA
1.0
0.5
0.0
1.0
-75 -50 -25
0
25
50
-75 -50 -25
75 100 125 150
0
25
50
75 100 125 150
TJ , Temperature ( °C )
T J , Temperature ( °C )
Fig 21. Threshold Voltage vs. Temperature
Fig 22. Threshold Voltage vs. Temperature
1600
EAS , Single Pulse Avalanche Energy (mJ)
250
EAS , Single Pulse Avalanche Energy (mJ)
100
Fig 20. Maximum Drain Current vs. Case Temperature
2.2
ID
TOP
7.7A
12A
BOTTOM 30A
200
150
100
50
ID
7.9A
16A
BOTTOM 60A
1400
TOP
1200
1000
800
600
400
200
0
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 23. Maximum Avalanche Energy vs. Drain Current
77
75
TC , Case Temperature (°C)
Fig 19. Maximum Drain Current vs. Case Temperature
VGS(th) , Gate threshold Voltage (V)
50
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© 2013
2014 International
International Rectifier
Rectifier
©
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 24. Maximum Avalanche Energy vs. Drain Current
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April
July14,
31,2014
2013
IRFH4255DPbF
Avalanche Current (A)
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  Tj = 125°C and
Tstart =25°C (Single Pulse)
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 125°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 25. Typical Avalanche Current vs. Pulse Width (Q1)
Avalanche Current (A)
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  Tj = 125°C and
Tstart =25°C (Single Pulse)
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 125°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 26. Typical Avalanche Current vs. Pulse Width (Q2)
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 27. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Q1)
8
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IRFH4255DPbF
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.02
0.01
0.1
0.01
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 28. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Q2)
9
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IRFH4255DPbF
Fig 29. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
A
I AS
0.01
Fig 30a. Unclamped Inductive Test Circuit
Fig 30b. Unclamped Inductive Waveforms
Fig 31a. Switching Time Test Circuit
Fig 31b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Qgs1 Qgs2
Fig 32a. Gate Charge Test Circuit
10
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Qgd
Qgodr
Fig 32b. Gate Charge Waveform
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April 14, 2014
IRFH4255DPbF
Dual PQFN 5x6 Outline “H” Package Details
C
SEATING
PLANE
D
4
A
INDEX AREA
(D/2xE/2)
B
D2
PIN#1 ID
L1
A1
R0.30
E1
E2
e
E
7x L2
8x b
8x K
D1
1.15
0.48
1.21
TOP VIEW
SIDE VIEW
1.08
D im e n s io n T a b le
Th
Sy
ic k
n
m b ess
ol
A
A1
b
D
E
e
D1
E1
D2
E2
K
L1
L2
V : V e r y T h in
M IN IM U M
0 .8 0
0 .0 0
0 .3 0
2 .4 2
4 .4 1
0 .7 8
4 .0 1
0 .2 0
1 .6 7
0 .4 0
NOTE
N O M IN A L M A X IM U M
1 .0 0
0 .9 0
0 .0 5
0 .0 2
0 .5 0
0 .4 0
6 .0 0 B S C
5 .0 0 B S C
1 .2 7 B S C
2 .5 7
2 .6 7
4 .5 6
4 .6 6
1 .0 3
0 .9 3
4 .2 6
4 .1 6
----1 .7 7
0 .5 0
0.94
BOTTOM VIEW
6
1 .8 7
0 .6 0
Dual PQFN 5x6 Outline “H” Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
PIN 1
IDENTIFIER
XXXX
XYWWX
XXXXX
PART NUMBER
(“4 or 5 digits”)
MARKING CODE
(Per Marking Spec)
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
For more information on board mounting, including footprint and stencil recommendation, please refer to
application note AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
11
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IRFH4255DPbF
Dual PQFN 5x6 Outline Tape and Reel
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Qualification Information†
Industrial
(per JEDEC JESD47F †† guidelines )
Qualification level
DUAL PQFN 5mm x 6mm
Moisture Sensitivity Level
Yes
RoHS Compliant
†
††
MSL1
(per JEDEC J-STD-020D††)
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/product-info/reliability
Applicable version of JEDEC standard at the time of product release.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
 Starting TJ = 25°C,
Q1: L = 0.14mH, RG = 50, IAS = 30A;
Q2: L = 0.20mH, RG = 50, IAS = 60A.
 Pulse width ≤ 400µs; duty cycle ≤ 2%.
 R is measured at TJ approximately 90°C.
 When mounted on 1 inch square PCB (FR-4). Please refer to AN-994 for more details:
http://www.irf.com/technical-info/appnotes/an-994.pdf
 Calculated continuous current based on maximum allowable junction temperature.
 Current is limited to Q1 = 30A & Q2 = 30A by source bonding technology.
 Pulsed drain current is limited to 120A by source bonding technology.
Revision History
Date
01/27/2014

Comments
Update the MSL level from MSL2 to MSL1, on page 1 & 12.
04/08/2014

Removed “redundant” information of IDSS Q1 & Q2 on page 2.
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April 14, 2014