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A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM
With Dual-Error Detection and PVT-Tolerant
Data-Fetch Scheme
Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung,
Seokhun Hyun, Hanki Jeoung, Ki-Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun,
Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung,
Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, and Joo Sun Choi
Abstract—A 1.2 V 4 Gb DDR4 SDRAM is presented in a 30 nm
CMOS technology. DDR4 SDRAM is developed to raise memory
bandwidth with lower power consumption compared with DDR3
SDRAM. Various functions and circuit techniques are newly
adopted to reduce power consumption and secure stable transaction. First, dual error detection scheme is proposed to guarantee
the reliability of signals. It is composed of cyclic redundancy
check (CRC) for DQ channel and command-address (CA) parity
for command and address channel. For stable reception of high
speed signals, a gain enhanced buffer and PVT tolerant data fetch
scheme are adopted for CA and DQ respectively. To reduce the
output jitter, the type of delay line is selected depending on data
rate at initial stage. As a result, test measurement shows 3.3 Gb/s
DDR operation at 1.14 V.
TABLE I
COMPARISON TABLE OF DDR3 AND DDR4 SDRAM
Index Terms—CMOS memory integrated circuits, CRC, DDR4
SDRAM, DLL, error detection, parity, PVT-tolerant data-fetch
scheme.
I. INTRODUCTION
C
URRENTLY, DDR3 SDRAM is widely used as a main
memory of PC and server systems. It provides reasonable performance focusing on the reliability of data retention.
However, the explosive growth of mobile devices such as smart
phones and tablet PCs requires a very large number of server
systems [1]. And, higher performance server systems are required due to the advent of high-bandwidth network and the rise
of high-capacity multimedia content. A main memory of server
system also has to have the low power and high performance
features because it is one of the critical components of server
systems [2].
DDR4 SDRAM is regarded as the next generation memory
for the computing and server systems. In comparison with
precedent DDR3 SDRAM, major changes are supply voltage
of 1.2 V, pseudo open drain I/O interface, and high data rate
from 1.6 Gb/s to 3.2 Gb/s.
Table I shows the comparison table of DDR3 and DDR4
SDRAM. First, target data rate is doubled to 3.2 Gb/s/pin which
Manuscript received April 17, 2012; revised June 27, 2012; accepted July 02,
2012. Date of publication September 28, 2012; date of current version December
31, 2012 This paper was approved by Guest Editor Yasuhiro Takai.
The authors are with Samsung Electronics, Gyeonggi-Do 445-701, Korea
(e-mail: Kyomin.sohn@samsung.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2012.2213512
can cause signal integrity problem. And, supply voltages are
lowered from 1.5 V to 1.2 V which is a key factor to reduce
power consumption. VDD and VDDQ are lowered to 1.2 V, but,
VPP is added to reduce the burden of charge pump and its typical value is 2.5 V. A reference voltage for DQ (VREFDQ) is
changed from external to internal which is tightly related with
the change of termination method. Termination method for DQ
is changed from center-tapped-termination (CTT) to pseudoopen-drain (POD). In other words, the termination voltage of
DQ is not the half of VDDQ, but just VDDQ. POD is also
used in Graphics DDR5 (GDDR5) SDRAM and useful to reduce power consumption. Unlike GDDR5, a channel environment of main memory can be varied according to system configuration [3]. It causes variable optimal reference voltage so
that VREFDQ should be generated internally. In view point
of cell array architecture, bank group architecture is actively
used to raise data rate without the increase of core operating
frequency which is described in Section II. Finally, there are
various new functions introduced in DDR4 SDRAM. There are
CA parity, CRC (cyclic redundancy check), DBI (data-bus inversion), gear-down mode, CAL (command address latency),
PDA (per DRAM addressability), MPR (multi-purpose registers), FGREF (fine granularity refresh), and TCAR (temperature
compensated auto refresh). Among them, MPR function is improved from MPR of DDR3 in point of flexibility and quantity.
CA parity, CRC and DBI functions will be explained concretely
in Section II and Section III.
0018-9200/$31.00 © 2012 IEEE
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169
Fig. 2. CCD variation according to bank group operation.
can be applied if different bank group operation occurs. It is only
4, the half of tCCD_L in same frequency.
DDR4 SDRAM has four independent control clock generators to execute bank group operation and power noise from core
operation is managed carefully to guarantee stable core operation between different bank groups.
Fig. 1. Bank group architecture of proposed 4 Gb DDR4 SDRAM.
B. DBI and CRC
In this paper, we present DDR4 SDRAM in 30 nm CMOS
technology with dual error detection and PVT-tolerant data
fetch scheme besides various new functions described previously. As a measurement result, it shows 3.2 Gb/s/pin data
rate in 1.14 V supply voltage. This paper is organized as
follows. Section II provides bank architecture and data bus
system with DBI and CRC functions. Section III describes
command-address path with CA parity scheme. Data-fetch
scheme and adaptive DLL scheme are explained in Section IV.
Section V shows a fabricated chip photo and measurement
result. Section VI summarizes this work.
II. ARCHITECTURE
A. Bank Group Architecture
Fig. 1 shows the bank architecture of proposed DDR4
SDRAM. It has 4 bank-groups and 4 banks per each bank
group. Bank group architecture is very important to enhance
data rate without increasing burst length [4].
Historically, the burst length of DDR SDRAM is always doubled whenever DRAM generation is changed such as DDR to
DDR2 and DDR2 to DDR3. It comes from the fact that core operation period of DRAM is almost fixed as about 5 ns. By doubling the number of fetch data and burst length, the data rate
of DDR3 is improved to 1600 Mbps from 800 Mbps of DDR2.
However, burst length 16 is too long and most systems do not
need as much at one time. Therefore, DDR4 adopted bank group
architecture and if bank group interleaving access is not applied,
the full bandwidth of DDR4 cannot be utilized.
Fig. 2 shows the cases of same bank-group operation and
different bank-group operation. Command to command delay
(CCD) has two type of values. In case of same bank group operation, tCCD_L (l means long) is applied and it is 8 when the
clock frequency is 1.6 GHz. However, tCCD_S (s means short)
To secure stable transaction at even high frequency, dual error
detection scheme is presented. Dual error detection scheme
means cyclic redundancy check (CRC) for DQ channel and CA
parity for command and address channel. In this section, CRC
scheme will be discussed with data bus inversion (DBI).
CRC is used for detecting errors in IO channel. Therefore, in
read operation, DBI operation should precede CRC calculation.
To execute CRC calculation, all bits to be transferred should be
ready. In case of write operation, operation sequence does not
matter. DBI operation for write data can be executed regardless
of the results of CRC calculation. In DDR4 SDRAM, CRC is
based on 72 bits which is composed of 8-burst and 9 bits data.
In case of X16 organization, CRC is executed for each byte, not
for 144 bits data.
DDR4 is not the first DRAM to adopt CRC scheme. It is already used in Graphics DDR DRAM [5]. DBI function is also
used in GDDR5 DRAM, however, detailed specification and requirements are different. As a main memory, area and current
reduction is more important compared with relatively high cost
GDDR SDRAM.
DBI function is used to reduce IO power and enhance signal
integrity by reducing simultaneous switching output (SSO)
noise. Because the termination voltage of DDR4 is VDDQ, to
drive low state consumes more power including direct current
from termination to pull-down transistor.
Fig. 3 shows the data frame to support DBI and CRC function
in case of x8 and burst length 8. Unlike GDDR5 SDRAM, bits
for CRC are located at the 9th burst. It enables to hide CRC
latency in read CRC mode so that read latency is not changed
whether read-DBI function is enabled or not. DBI pin can be
assigned as DM pin according to mode register setting.
Data-bus architecture of proposed DDR4 SDRAM is as
shown in Fig. 4. It supports read-DBI, read-CRC, write-DBI
and write-CRC functions. The major advantages of this architecture are the minimization of area and performance penalty
even when DBI and CRC functions are not used. CRC function
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Fig. 3. Data-frame in case of x8 and burst length 8 with DBI and CRC.
Fig. 4. Data-bus architecture to support DBI and CRC.
Approximate unit location is shown in Fig. 6. According to
the location of DQ pads, units related to lower DQs and upper
DQs are distributed and CRC units are located near the center
of chip in each area to reduce latency.
III. COMMAND AND ADDRESS PATH
A. Gain Enhanced Buffer
Fig. 5. DBI inversion unit in front of output data register.
needs 72 bits for CRC calculation and DBI function needs
8 bits by each burst sequence. When DBI and CRC are enabled simultaneously in read operation, bus inversion for CRC
calculation and bus inversion for DQ transfer are occurred
simultaneously. Bus inversion for CRC happens in front of
CRC calculation block. Bus inversion for DQ transfer happens
in front of each output data register. If bus inversion occurs in
only one place, the number of bussing line should be doubled
in some portion and additional delay is added to read data
path. In case of write operation, write data are transferred
from WRDRV (write driver) to cell array and CRC calculation
block in Fig. 4. Unit for write data inversion are not shown in
Fig. 5. In write operation, DBICAL and DBIINV are bypassed
because CRC should be calculated based on channel data.
Data bus inversion unit in front of output register is as shown
in Fig. 5. In case of DBI off mode, additional delay is reduced to
only 2 gates. When DBI function is enabled, data can be inverted
or pass through-ed by the result of ‘0’ count circuit.
DDR4 CA bus remains unchanged and is center-tapped termination (CTT) compatible. However, as interconnect loss increases with data rate, the eye opening of the signal at the receiver end is not wide enough to meet voltage and timing requirement. Fig. 7 shows the DDR4 CA path. DDR4 CA buffers
are built from conventional DDRx circuitry, but a signal transition detector is added to mitigate the design challenge as shown
in Fig. 8. A small amount of input signal energy is transferred to
the detector which utilizes capacitance coupling, and its output
is superimposed with a fixed bias determined by VREFCA, the
input reference voltage. With this manner, the bias level is then
controlled more dynamically, i.e., larger current is supplied in
accordance with input signal transition, and the receiver sensitivity can be enhanced for a given power consumption at higher
frequencies. Simulation results are as shown in the right side
of Fig. 8. It shows enhanced results by using transition detector
unit.
B. CA Parity Scheme
CA Parity scheme is the second one of dual error detection
scheme. It is implemented in DDR4 SDRAM for improved
RAS where the same functionality exists only in the host
controller and RCD (or memory buffer) interface in previous
DDR SDRAM generations. The CA parity logic comprises
a parity checker, a latency clock generator and a FF-based
shifter. To minimize the delay penalty of the in-line command
SOHN et al.: A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM WITH DUAL-ERROR DETECTION AND PVT-TOLERANT DATA-FETCH SCHEME
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Fig. 6. Approximate position of DBI and CRC circuits.
Fig. 7. Command and address path with CA parity function.
Fig. 8. Gain enhanced buffer for command and address inputs.
decoding path due to the parity function, timing margins are
carefully allocated to each XOR gates and FFs. In Fig. 7, delay
unit tD is implemented to absorb the delay tXOR for satisfying
predefined tPL. It is well-known circuit technique for latency
logic such read latency and write latency. Overall, the latency
adder is N clock cycles of Parity Latency (PL) when this feature is enabled, a few hundred picoseconds when its disabled.
During operation, the DRAM always computes parity and logs
Fig. 9. Wide common mode range DQ buffer using common mode feedback.
erroneous CA frames only qualified by CS. These logic blocks
sit between CA input receivers and command decoders are
gated by CS and only operate for a fixed period time upon
CS assertion to save power consumption. If error is detected
in this scheme, erroneous command is blocked in command
decoder and ALERTB signal is enabled to inform to controller.
To inform error to controller, ALERTB pin is added in DDR4,
it is used in write-CRC and CA parity function.
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Fig. 10. PVT tolerant data fetch scheme by using TDC.
IV. DATA FETCH SCHEME AND DLL
A. PVT-Tolerant Data Fetch Scheme
One notable change in DDR4 data bus is the shift to VDDQreferenced signaling that has been adopted in Graphics DRAMs
[6]. This change has positive effects such as reducing parasitic
pin capacitance and lowering I/O termination power, but downside is that the common-mode of VDDQ-referenced signals depends on transmitter drive strength and receiver ODT resistance.
Therefore, the receiver is required to be able to sense and convert incoming signal to CMOS level for post-processing over
the wide input common-mode range, yet maintaining linearity
with respect to the reference voltage.
Fig. 9 shows the configuration of data input receiver. The receiver frontend is composed of an NMOS differential pair and
a secondary PMOS pair to boost signal gain with low input
common-mode. The main purpose of this first stage buffer is
to deliver stable inputs to the second stage gain amplifier even
under large external input common-mode variation. In addition
to the conventional differential input stage, a feedback network
realized with passive RCs for further reduction of the output
common-mode variation and a compensation capacitor for effective single-ended-to-differential conversion are utilized in
the first stage buffer. The second stage CML comparator followed by a CMOS buffer converts low-swing differential signal
to CMOS logic level. The signal common mode level is readily
shifted to the near half VDD voltage by the first stage buffer,
thus a simple differential amplifier could be used as a differential-to-single ended gain stage. The latter CMOS stage employs shunt feedback for bandwidth extension as well as reducing duty-cycle distortion caused by the mismatch between
the comparator output common-mode and the trip-point of the
succeeding inverter. As a result, high speed operation of the data
input receiver can be achieved with minimal circuit complexity.
Fig. 10 shows high level block diagram of data deserializer including the receiver and data sampling path. First, the buffered
and sampled data received in series must be re-aligned by the
DQS_EN (end of burst) for relaxed domain crossing to be transferred to the core array. However, the data de-serializing and
Fig. 11. Data fetch margin guaranteed by using programmable delay line.
handing over to internal write command synchronized to the internal clock was another design challenge at higher data rates
due to large PVT variation. The phase difference between them
varied too much in low VDD region while the bit time gets
smaller in DDR4 operating frequencies. In this design, Time-toDigital Converter (TDC) and a programmable delay line (PDL)
are adopted to address the above issue. The TDC comprises a
simple supply voltage dependent delay line and multiple FlipFlops. Upon initialization, the TDC measures the clock period
and a thermometer code is generated accordingly. PVT tolerant
data fetching was attained by adaptively adjusting the relative
phase at the second and the third stage latches with decoded
digital codes. In other words, the PDL delay is decreased at
high VDD, and increased at the low VDD to compensate the
phase skew between different domains as shown in Fig. 11. The
DQS_EN timing is not controlled by the TDC code because it
cannot be shifted around arbitrarily after write leveling.
B. Internal VREF Generator
An internal VREF generator configured to generate a DC reference for data receivers is also added for programmable voltage
level over various system environments. The VREF ranges from
45% to 92% of the supply voltage. The generator is realized with
a resistor-based voltage-divider, a decoder and a buffer to drive
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Fig. 12. DLL out jitter feature using analog-type delay and digital-type delay.
Fig. 13. Adaptive DLL scheme.
large capacitive load. The VREF buffer only consumes power
during training mode to minimize the impact of added standby
power consumption.
C. Adaptive DLL Scheme
Generally, analog DLL has good jitter performance but
consumes high power. Inversely, digital DLL consumes lower
power which is under one third of analog DLL, but jitter feature
is not good as analog DLL. When 100 mV noise is injected
to VDD, simulated DLL out jitter of two kinds of DLL at room
temperature is as shown in the right side of Fig. 12. Especially,
in low supply voltage, the jitter of digital DLL increases rapidly.
Therefore, adaptive DLL scheme is adopted in this work. From
the viewpoint of DLL locking time (tDLLK), two kinds of DLL
have similar values, about 500 clock cycles in our design.
To meet the output jitter requirement of DDR4 Tx with
reduced power usage, the DLL, shown in Fig. 13, consists of
two types of digitally controlled delay line (DCDL) sharing a
common control logic to minimize area. The path selector also
employs the TDC concept, and depending on the data rate, it
decides which DCDL to use during initialization process, i.e.,
the CMOS DCDL below a pre-defined threshold frequency
for lower power consumption or the CML DCDL above the
threshold for lower output jitter characteristics at given supply
voltage. At 1.14 V supply voltage, analog delay line is selected
over 2.4 GT/s to satisfy jitter requirements as shown in the
right side of Fig. 13. In addition, after initial DLL locking
and duty cycle correction period expires, the control logic
determines clock division ratio N based on the overall loop
delay. This gives benefits in two aspects. First, the feedback
clock (CLK_R) is geared down to save power consumption.
Secondly, divided clocks to the phase detector can prevent the
DLL control logic from false tracking the external clock phase
when instantaneous timing shift of the feedback clock due to
dynamic IR drop or ground bounce is relatively large at lower
VDD and higher frequencies.
The graph of the right side of Fig. 13 shows the relation between VDD and jitter feature according to choose the type of
delay line. To meet jitter requirement at 3.2 GT/s under 1.2 V,
CML type of delay line is selected at initial stage.
V. MEASUREMENT RESULTS
In this section, implementation and measurement results will
be explained. Fig. 14 shows a chip photo of 4 Gb 30 nm DDR4
SDRAM. Its chip size is 76 mm . IO organization supports 4, 8
and 16. Typical supply voltage is 1.2 V. 1 bank group, 1 bank
and DLL position are shown in Fig. 14. Fig. 15 is the frequency
versus voltage shmoo graph. From the shmoo graph, it is verified that this DRAM operates at 3.3 Gb/s/pin speed with 1.14 V
power supply.
Measured operation current of burst read (IDD4R) is 62 mA
at 1.26 V supply voltage and DDR1600. This figure is selected
for comparing with DDR3. In the same process technology, operation current is slightly higher than DDR3 by 6% which comes
from higher frequency operation and various new functions.
However, VDD power consumption decreases by 15% because
of lowering supply voltage from 1.5 V to 1.2 V. Total system
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Fig. 14. Chip photograph and summary table.
Fig. 15. Measured shmoo plot of tCK versus VDD showing 3.3 Gb/s operation at 1.14 V and measured eye diagram at 2.6 Gb/s.
power consists of core power and I/O power. Considering operation and standby portion of system, system power reduction
reaches to 30% of system with DDR3.
VI. SUMMARY
A 3.2 Gb/s/pin DDR4 SDRAM is implemented in a 30 nm
CMOS 3-metal process. DDR4 SDRAM adopts lower supply
voltage to reduce power consumption compared with previous
DDR3 SDRAM. There are various features to guarantee stable
transaction at higher speed like 3.2 Gb/s. Bank group architecture is adopted and used actively to increase data rate without increasing burst length. DBI and CRC functions are implemented
with data-bus system minimizing area and performance penalty.
CA parity scheme is used to check and inform the error of command and address path. Dual error detection scheme is composed of CRC and CA parity. To enhance the basic receivability
of buffer, gain enhanced buffer for command and address pins,
and wide common mode range buffer for DQ pins are presented.
PVT tolerant data fetch scheme is also implemented to secure
fetch margin in low voltage and high speed operation. Finally,
adaptive DLL scheme is adopted by using analog and digital
delay line according to frequency and voltage. By using this
scheme, the jitter requirement of DDR4 SDRAM can be satisfied at a high frequency and power consumption can be saved
at a low frequency.
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SOHN et al.: A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM WITH DUAL-ERROR DETECTION AND PVT-TOLERANT DATA-FETCH SCHEME
Kyomin Sohn received the B.S. and M.S. degrees in
electrical engineering from Yonsei University, Seoul,
in 1994 and 1996, respectively. From 1996 to 2003,
he was with Samsung Electronics, Korea, involved
in the design of SRAM. He designed various kinds
of high-speed SRAM devices. He received the Ph.D.
degree in electrical engineering and computer science
in 2007 from KAIST, Daejeon, Korea.
He rejoined Samsung Electronics in 2007, where
he has been involved in the design of DDR3 and
DDR4 SDRAM. His interests include high-speed
I/O circuits, robust memory design, and next-generation memory devices.
Taesik Na received the B.S. and M.S. degrees in electrical engineering and computer science from Seoul
National University, Seoul, Korea, in 2006 and 2008,
respectively.
Since 2008, he has been with Samsung Electronics
Semiconductor Memory Division, Korea, involved
in the design of high-speed DRAMs. His current research interests include high-speed CMOS circuit design, and computer-aided design.
Indal Song received the B.S. degree in electronics
engineering from Sungkyunkwan University, Korea,
in 1998, and the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology in 2004.
He joined Samsung Electronics, Korea, in 2005,
and has been involved in the I/O interface circuit
design works for DDR2, DDR3, DDR4 DRAMs
as well as developing DRAM JEDEC standards.
His research interests are in the area of high-speed
low-power digital logic and I/O circuits for future
175
Sanghee Kang received the B.S. degree in electrical
engineering from Korea Univerity, Seoul, Korea, in
1996 and the M.S degree in semiconductor and CAD
from the Graduate School of Korea Univerity, Seoul,
Korea, in 1997.
He joined the DRAM Design Team, Samsung
Electronics, in 2007.
Dongsu Lee received the B.S. degree in electronic
engineering from Busan National University, Busan,
Korea, in 1997 and the M.S. degree in semiconductor and display engineering from Sungkyunkwan
University, Suwon, Korea, in 2002. He is currently
working toward the Ph.D. degree at the Graduate
School of Semiconductor and Display Engineering,
Sungkyunkwan University, Suwon, Korea.
He joined Samsung Electronics in 1997 and is currently with the DRAM Design Team. His research interests include low-power and analog circuit design
for mobile and high-speed DRAMs, especially leakage monitoring and reduction technique.
Hangyun Jung received the B.S. degree in electronics engineering from Hanyang University,
Korea, in 2003.
He joined Samsung Electronics in 2003, where
he has been involved in the design of Synchronous
DRAM such as SDR/DDR, DDR2, DDR3, DDR4.
His current interests are in the area of high speed
digital logic and low power design for memory.
memory.
Yong Shim received the B.S. and M.S. degrees in
electrical and computer engineering from Korea University, Seoul, Korea, in 2004 and 2006, respectively.
He joined Samsung Electronics, Hwasung-city,
Korea, in 2006 as an interface design engineer.
Since then, he has worked on the development and
failure analysis of wide dram generation from DDR1
to DDR4 through the most of dram processes. His
interests include ultra low power interface circuit
design, reconfigurable circuit design for robust operation, and low-power high-speed clock generation.
Wonil Bae received the B.S. and M.S. degrees from
Korea University, Seoul, Korea, in 1994 and 1996,
respectively, both in electrical engineering.
Since 1996, he has been with Samsung Electronics,
working in the area of developement for DRAM, especially in design of DDR3 and DDR4 SDRAM. His
interests include high speed, low power circuits and
improvement of reliability for memory.
Seokhun Hyun received the B.S. degree from
Kwangwoon University, Seoul, Korea, in 1999, and
the Master and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology,
Atlanta, Georgia, in 2001 and 2004.
In 2004, he was with the ultra mixed signal IC research group at Duke University, Durham, North Carolina, where he worked on mixed signal IC design
fo optical interconnect. In 2006, he joined DRAM
design group at Samsung Electronics in Hwasung,
Korea. His current research interests include highspeed and low power IO interface circuits for memory systems.
Hanki Jeoung was born in Korea in 1975. He
received the B.S degree from the School of Electrical Engineering, Chung Nam National University,
Daejeon, Korea, in 2001 and the M.S. degree from
the School of Electrical Engineering, Seoul National
University, Seoul, Korea, in 2008.
From 2001 to 2012, he was with Samsung Electronics Co., Ltd. Hwasung, Gyeonggi, Korea, where
he is involved in developing DDR3 and DDR4
SDRAM.
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Ki-Won Lee was born in Seoul, Korea, in 1977. He
received the B.S. and M.S. degrees in electronics engineering from Korea University, Seoul, in 2001 and
2003, respectively.
In 2003, he joined Hynix Semiconductor Inc.,
Kyungki-do, Korea where he was involved in
graphic memory design team. In 2008, he joined
the Memory Division, Samsung Electronics Inc.,
Kyungki-do, Korea where he was involved in circuit
design, product development, and failure analysis
of DDR3 and DDR4 memory. He has also been in
charge of mixed circuit development for high-speed I/O design. His current
interests include clocking circuit, signal integrity and power integrity for
high-speed digital/analog interface.
Jun-Seok Park was born in Korea in 1979. He received the B.S. degree in electrical engineering and
computer science from Hanyang University, Korea in
2004.
In 2004, he joined Samsung Electronics,
Gyeonggi-do, Korea, where he is involved in
the design of DDR3 and DDR4 SDRAM. His
research interests are high speed and low power
memory.
Jongeun Lee received the B.S. and M.S. degrees in
electrical engineering from Kwangwoon University,
Seoul, Korea, in 2004 and 2006, respectively.
He joined Samsung Electronics in 2006 and is
currently with the DRAM Design Team. His research
interests include low-power and analog circuit design for mobile and high-speed DRAMs, especially,
leakage monitoring and reduction technique.
Byunghyun Lee received the B.S. degrees in electrical engineering in 1998 and 2004, respectively,
from Kwangwoon University, Seoul, Korea.
He joined Samsung Electronics in 2005, where he
has been involved in the design of DDR3 and DDR4
SDRAM. His interests include high speed and low
power, 3Ds circuits for memory.
Inwoo Jun received the B.S. degrees in electrical engineering in 2005 from Kyungpook National University, Daegu, Korea.
He joined Samsung Electronics in 2005, where he
has been involved in the design of DDR3 and DDR4
SDRAM. His interests include high speed and low
power circuits for memory.
Juseop Park received the B.S. and M.S. degrees
in electrical and electronic engineering from Yonsei
University, Seoul, Korea, in 2005 and 2007, respectively.
She joined Samsung Electronics Company, Ltd.,
Korea in 2007, where she is involved in the design of
DDR2, DDR3, and DDR4 SDRAM.
Junghwan Park received the B.S. degree in electrical engineering from Kyungpook National University, Daegu, Korea, in 2006.
In 2006, he joined Samsung Electronics, Korea,
where he has been engaged in the design of highspeed DRAMs such as DDR3 and DDR4 DRAM.
He is currently involved in the development of highspeed LPDDR3 DRAM.
Hundai Choi received the B.S. and M.S. degrees
in electronic engineering from Kookmin University,
Korea, in 2004 and 2006, respectively.
He joined Samsung electronics Corporation,
Korea, in 2006, where he is currently working on
low-power and high-speed DRAM circuits design.
Sanghee Kim received the B.S. degree in electronic
communication engineering from Hanyang University, Seoul, Korea, in 2005.
He joined Samsung Electronics, Korea, in 2005,
where he worked on I/O interface and DLL design for
high-performance DRAM. His current interests are in
the area of high-speed and low-power I/O interface
circuit design for the next generation memory.
Haeyoung Chung received the B.S. degree in electrical engineering in 2005 and M.S. degree in SOC
design in 2007 from Korea University, Korea.
She then joined Samsung Electronics, working in
the design of DDR3 and DDR4 SDRAM, especially
for I/O interface. Her interests include high speed and
low power circuits for memory.
SOHN et al.: A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM WITH DUAL-ERROR DETECTION AND PVT-TOLERANT DATA-FETCH SCHEME
Young Choi received the B.S. and M.S. degrees in
electrical engineering in 2006 and 2008, respectively,
from Sogang University, Seoul, Korea.
He joined Samsung Electronics in 2008, where he
has been involved in the design of DDR3 and DDR4
SDRAM. His interests include RF circuit and DRAM
interface.
Dae-Hee Jung was born in Seoul, Korea, in 1971.
He received the M.S. degree in electronic and electrical and computer engineering from Korea University, Seoul, Korea, in 2004.
In 1997, he joined Samsung Electronics Company,
Ltd., Korea, where he is involved in the design of
Rambus, DDR3, DRR4, and Mobile DRAM. His research interests include high-speed I/O interface circuits and low power memory design.
Byungchul Kim received the B.S. and M.S. degrees
in electronic engineering from Kyungpook National
University, Taegu, Korea, in 1987 and 1989, respectively.
He joined Samsung Electronics in 1992, where
he has been involved in the design of SDRAM,
DDR1/2/3 and DDR4 SDRAM. His work focuses on
high speed and low power circuits for high density
memory.
Jung-Hwan Choi was born in Taegu, Korea, in 1968.
He received the B.S. degree from Kyung-buk National University, Taegu, Korea, in 1990 and the M.S.
and Ph.D. degrees from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon,
Korea, in 1992 and 1997, respectively, all in electrical
engineering.
In 1997, he joined Samsung Electronics Company,
Ltd., Korea, where he is involved in the design of
Rambus, XDR DRAM, SDR, DDR, DDR2, DDR3,
DDR4, and high speed I/O interface circuits for
memory applications. He is now Manager of IODLL design group for DRAM
circuits. His research interests include design of monolithic microwave IC,
high-speed memory, and high frequency measurement.
Dr. Choi received the Outstanding Research Award in 2000 for the design of
high speed DRAM development.
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Seong-Jin Jang received the B.S. degree in electronic engineering from Kyung-Book University,
Daegu, Korea, in 1987, and the M.S. degree in
electrical engineering from the Korea Advanced
Institute of Science and Technology, Seoul, in 1990.
He joined LG Semicon Corporation, Ltd., Seoul, in
1990, where he was engaged in DRAM design division. Since 2000, he has worked for Samsung Electronics as a Vice President of the DRAM Development and Production Division. His research interests
are in high-speed DRAM design and production.
Chiwook Kim received the M.S. degrees in electrical
engineering from Korea University, Seoul, Korea, in
2001.
He joined Samsung Electronics in 1991, where he
has been involved in the design of DDR3 and DDR4
SDRAM. His interests include high speed and low
power circuits for memory.
Jung-Bae Lee was born in Seoul, Korea, in 1967. He
received the B.S., M.S., and Ph.D. degrees in electronics engineering from Seoul National University
in 1989, 1991, and 1995, respectively.
In 1995, he joined Samsung Electronics Company,
Ltd., Gyeonggi-do, Korea, as a Research Engineer,
where he has been working on the circuit design of
high-speed low-power DRAMs. His research interests include design of high-speed low-power memory
and VLSI systems and noise phenomena in electronic
systems and semiconductor devices.
Joo Sun Choi received the B.S. degree in electronics
engineering from Seoul National University, Seoul,
Korea, in 1986, and the M.S. and Ph.D. degrees
in electrical engineering from KAIST (Korea Advanced Institute of Science and Technology) in 1989
and 1995 respectively.
In 1989, he joined Hyundai Electronics Co. Ltd.
(now SK-Hynix Semiconductor), where he has
been involved in device and circuit design for the
high-speed dynamic RAM’s such as Synchronous
DRAM, DDR, DDR2 and Graphic DRAM. From
2002 to 2004, he was with Micron Technology, Boise, Idaho, and worked
in the strategic marketing group for the product definition and enabling of
high-speed memory devices. In late 2004, he joined Samsung Electronics,
Hwasung, Korea, and is now in charge of DRAM technology, design and
product engineering for the computing systems, mobile, consumer and graphics
as an Senior Vice President. He has authored more than 30 papers in the field
of electronic circuits and devices and holds more than 25 U.S. patents. His
current focus includes memory technology scaling, low power memory design,
high speed memory and I/O design and system oriented memory solution.
From 1996 to 2001, Dr. Choi served as a committee member of JEDEC (Joint
Electronic Devices Engineering Council) and contributed the industry standards
of dynamic memories such as SDRAM, DDR, DDR2 and several generation of
SDR, DDR, DDR2 and Graphics DRAMs. He also served as a memory subcommittee member of IEEE ISSCC from 2007 to 2012.