ARM Evaluation Board
(KPI-0041A)
User Guide
ARM DUI 0091A
Open Access
ARM Evaluation Board
User Guide
Change log
Date
Issue
Change
August 1998
A
First release
Proprietary notice
ARM, EmbeddedICE, and Muliti-ICE are trademarks of ARM Limited. All other
products or services mentioned herein may be trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described
in, this document may be adapted or reproduced in any material form except with the
prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and
improvements. All particulars of the product and its use contained in this document are
given by ARM Limited in good faith. However, all warranties implied or expressed,
including but not limited to implied warranties or merchantability, or fitness for
purpose, are excluded.
This document is intended only to assist the reader in the use of the product.
ARM Limited shall not be liable for any loss or damage arising from the use of any
information in this document, or any error or omission in such information, or any
incorrect use of the product.
Confidentiality and information status
This document is:
Open Access
No restriction on distribution
Final
Complete information on a developed product
Electromagnetic compatability
ii
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Preface
ARM Evaluation Board
About this document
This document describes the ARM Evaluation Board (KPI-0041A), which is a simple
means of evaluating an ARM processor and its peripheral technology.
Intended audience
This document has been written for experienced engineers.
Typographical conventions
The following typographical conventions are used in this document:
bold
highlights menu items and signal names within the text
italic
highlights important notes, ARM-specific terminology, cross
references, and references to other publications
monospace
highlights directory names, file names, and code examples
italic monospaced
highlights variables which should be substituted with actual text.
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
iii
Preface
Related publications
The following ARM documents may be useful:
iv
•
the ARM Evaluation Board Welcome Guide (ARM DGI 0005A)
•
the ARM Target Development System User Guide (ARM DUI 0061)
•
the ARM7DI Databook (ARM DDI 0027D)
•
the ARM7DI Test Chip Implementation Guide (ARM DXI 0027B)
•
the ARM SDT User Guide (ARM DUI 0040C)
•
the ARM SDT Reference Guide (ARM DUI 0040C)
•
the Sharp LH77790A Embedded Microcontroller User’s Guide v2.1.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Preface
Feedback on this document
If you have any comments or suggestions about this document, please contact your
supplier giving:
ARM DUI 0091A
•
the document title
•
the document number
•
the page number(s) to which your comments refer
•
a concise explanation of your comments.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
v
Preface
vi
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Contents
ARM Evaluation Board
Preface
Chapter 1
Overview
1.1
1.2
1.3
1.4
1.5
1.6
Chapter 2
Hardware Description
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
ARM DUI 0091A
Kit contents ................................................................................................... 1-2
System requirements .................................................................................... 1-3
Using the evaluation board ........................................................................... 1-4
Precautions ................................................................................................... 1-5
Federal Communications Commission notice............................................... 1-6
CE Declaration of Conformity........................................................................ 1-6
Overview ....................................................................................................... 2-2
The Sharp LH77790A microcontroller........................................................... 2-4
LEDs ............................................................................................................. 2-5
Memory ......................................................................................................... 2-7
JTAG connector .......................................................................................... 2-12
Serial port.................................................................................................... 2-13
5V voltage regulator.................................................................................... 2-14
50 PTH blocks J1 to J4 ............................................................................... 2-14
© Copyright ARM Limited 1998. All rights reserved.
Open Access
vii
Contents
Chapter 3
Bootstrap Loader Setup and Use
3.1
3.2
3.3
3.4
3.5
3.6
Chapter 4
Angel Debug Monitor Setup and Use
4.1
4.2
4.3
Chapter 5
Overview....................................................................................................... 4-2
Basic setup with the Angel Debug Monitor................................................... 4-3
Setting up ARM Debugger for Windows for the Angel Debug Monitor......... 4-4
EmbeddedICE Setup and Use
5.1
5.2
Chapter 6
Overview....................................................................................................... 3-2
Basic setup with the Bootstrap Loader ......................................................... 3-3
Bootstrap Loader command line editor......................................................... 3-7
Bootstrap commands.................................................................................... 3-7
FLASH and module management .............................................................. 3-11
Application downloading and execution ..................................................... 3-14
Overview....................................................................................................... 5-2
Setup with an EmbeddedICE unit................................................................. 5-3
Multi-ICE Setup and Use
6.1
6.2
Overview....................................................................................................... 6-2
Setup with a Multi-ICE unit ........................................................................... 6-3
Appendix A
Evaluation Board Schematics
Appendix B
Evaluation Board Layout
Glossary
viii
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Chapter 1
Overview
This chapter describes:
ARM DUI 0091A
•
the kit contents
•
the system requirements
•
using the evaluation board
•
precautions which should be taken when using the board
•
the requirements of the Federal Communications Commission
•
the CE Declaration of Conformity.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
1-1
Overview
1.1
Kit contents
The ARM Evaluation Board is a simple means of evaluating an ARM processor and its
peripheral technology. The kit includes the following:
1.1.1
•
The ARM Evaluation Board Welcome Guide.
•
A CD-ROM containing installable software and documentation in pdf format.
•
A 9-pin null-modem RS 232 serial cable.
•
The ARM Evaluation Board.
•
A 9V wall-mounted power adapter.
The CD-ROM
The CD-ROM contains the following:
•
A free evaluation copy of the latest version of the ARM Evaluation Software
Development Toolkit (SDT).
•
This manual, as well as the ARM SDT User and Reference guides in pdf format.
•
The Sharp LH77790A Embedded Microcontroller User’s Guide v2.1.
Evaluation ARM Software Development Toolkit
The free evaluation ARM SDT is fully functional but has a 60-day timeout. It runs on
Microsoft Windows NT 4.0 and Microsoft Windows 95. It includes:
1-2
•
an efficient C compiler
•
an assembler
•
a linker
•
a graphical debugger
•
a project manager
•
C libraries
•
example programs.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Overview
1.1.2
The ARM evaluation board
The board conhas the following major components:
1.2
•
Sharp LH77790A microcontroller
•
128KB FLASH EEPROM
•
128KB SRAM memory
•
Four programmable output LEDs and a power indicator LED
•
9-pin D-sub RS232 serial connector
•
JTAG socket
•
24MHz clock
•
5V voltage regulator
•
reset and interrupt switches
•
FCC and European Commission EMC Directive, 89/336.EEC compliant (EN 55
022:1996 Class A equipment).
System requirements
The evaluation board must be connected to a PC running the ARM Evaluation Software
Development Toolkit (SDT) or a terminal application such as Hyperterm, or a UNIX
system running xterm. The host PC requirements are:
ARM DUI 0091A
•
100MHz or faster Pentium or similar PC
•
Microsoft Windows NT 4.0 or Microsoft Windows 95
•
16MB of RAM
•
25MB available hard disk space
•
CD-ROM drive
•
Serial port.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
1-3
Overview
1.3
Using the evaluation board
The ARM Evaluation Board is a complete target ARM development platform. As such,
with the exception of the host PC, the kit includes all the components required to
evaluate a simple ARM system including a representative software development
environment. There are four distinct ways of setting up the ARM Evaluation Kit for use:
•
The first and most primitive configuration involves the use of the Bootstrap Loader.
It connects to a terminal application on the host PC through the serial port
connector P1. The Bootstrap Loader coexists in the FLASH ROM of the
evaluation.
The actual connection is made with an RS-232 null-modem cable. In this
configuration the host PC based software tools can be used to develop, download,
and debug software programs.
•
The second method includes the use of the Angel debug monitor, in the FLASH
ROM of the evaluation board, and connecting the ARM debugger on host PC
through the serial port connector.
Again, the actual connection is made with an RS-232 null-modem cable. In this
configuration the host PC based software tools can be used to develop, download,
and debug software programs.
•
The third method requires an EmbeddedICE unit, which is not supplied with the
evaluation kit. The EmbeddedICE unit is connected to the evaluation board through
the 14-Pin JTAG connector, JP5, using a ribbon cable. The EmbeddedICE unit is
also connected to the the host PC by means of a serial cable. This method does not
require the use of the Angel debug monitor in the FLASH ROM.
•
The fourth method requires a Multi-ICE unit, which is not supplied with the
evaluation kit. The Multi-ICE unit is connected to the 20 to 14-pin JTAG adaptor,
and from there to the JTAG connector on the evaluation board through the 14-Pin
JTAG connector, JP5, using a ribbon cable. The Multi-ICE unit is also connected to
the host PC by means of a serial cable. This method does not require the use of the
Angel debug monitor in the FLASH ROM.
The ARM EmbeddedICE and ARM Multi-ICE units are supported by the ARM
software tools provided in each kit, and which allow you to develop, download and
test your software on the evaluation board.
1-4
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Overview
The EmbeddedICE and Multi-ICE give you the additional capability of monitoring
software on the evaluation board in a non-invasive manner at the hardware register level.
This is unlike using the more invasive Angel ROM monitor in that Angel shares system
resource usage with the downloaded program under test and also modifies it.
Table 1-1 Summary of differences between Angel and EmbeddedICE unit
1.4
EmbeddedICE and
Multi-ICE
Effect
Angel
Run control
Does not halt the processor.
Breakpoints available in
ROM. Hardware
watchpoints at full processor
speed.
System resources
Requires some target system
ROM and RAM, and a
software interrupt.
Requires no system
resources.
Host communication
Only requires the serial port.
Only requires the JTAG
interface to the ARM
processor.
Precautions
The evaluation board is intended for use as a tool within a laboratory or engineering
development environment. As a result the evaluation board is supplied without an
enclosure. The absence of an enclosure leaves the board sensitive to electrostatic
discharges and allows electromagnetic emissions. You should:
ARM DUI 0091A
•
always wear an earth strap when handling the board
•
only hold the board by the edges
•
not use the board near equipment which could be sensitive to electromagnetic
emissions (such as medical equipment) or which is a transmitter of electromagnetic
emissions.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
1-5
Overview
1.5
Federal Communications Commission notice
This equipment has been tested and found to comply with the limits for a class A digital
device, pursuant to part 15 of the FCC rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses, and can radiate radio
frequency energy and, if not installed and used in accordance with the instruction
manual, may cause harmful interference to radio communications. Operation of this
equipment in a residential area is likely to cause harmful interference in which case the
user will be required to correct the interference at his own expense.
1.6
CE Declaration of Conformity
This equipment has been tested according to ISE/IEC Guide 22 and EN 45014. It
conforms to the following product EMC specifications:
•
EN50081-1:1992 (Emissions)
•
EN55022/A1:1995, Class a Radiated and Conducted emissions to CISPR 22
Amend 1:1993
•
EN50082-1:1994 (Immunity)
•
EN61000-4/ENV50140:1995 RF Immunity, 80-1000MHz, 3V/m (before
modulation), 1kHz, 80% AM
•
EN61000-4-4:1995 EFT Immunity, 1kV on AC port, 5/50nSec, 5kHz Rep. Freq.
The product herewith complies with the requirements of EMC Directive 89/336/EEC
as amended.
1-6
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Chapter 2
Hardware Description
This chapter describes
ARM DUI 0091A
•
the SHARP LH77790A microcontroller
•
the LEDs
•
the memory
•
the JTAG connector
•
the serial port
•
the voltage regulator
•
the 50 PTH blocks J1 to J4.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-1
Hardware Description
2.1
Overview
The ARM Evaluation Board is a simple ARM platform that includes very few
input/output (I/O) devices, powerful and flexible enough for evaluation and
experimentation with ARM technology. The board allows;
•
the downloading of software images and the subsequent debugging process
•
the user easy access to all significant connection points, so enabling the attachment
of additional I/O devices and peripheral circuits for experimentation.
Figure 2-1 shows the major functional components of the ARM Evaluation Board.
More detailed diagrams are given in Appendix A and Appendix B.
2-2
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
ARM DUI 0091A
50 PTH array
© Copyright ARM Limited 1998. All rights reserved.
Open Access
JTAG
Clocks
Interrupts
Reset
LCD display
Interrupt switch
Reset switch
Boundary scan
ARM7DI TAP controller
Clock/power management
PWM
82C55 programmable
peripheral interface
16C40 UARTS
Watchdog timer
2KB scratch pad SRAM
INT/RESET controller
82C54 counter/timers
ARM7DI CPU
and cache
Bus controller
128KB FLASH
LCD controller
128KB SRAM
50 PTH array
4 LEDs
24 bits
CH 0/1
CH 2
3 channels
RS232 interface
irDA/DASK
CH 2
CH 1
CH 0
Hardware Description
50 PTH array
JTAG connector
Figure 2-1 Evaluation board architecture
2-3
Hardware Description
2.2
The Sharp LH77790A microcontroller
This is a square, 176-Pin, Thin Quad Flat Pack (TQFP), embedded microcontroller
manufactured by Sharp Electronics Corporation. It provides a wide range of on-board
peripherals and specialized interfaces.
Its principal features are:
•
JTAG port
•
32-bit ARM7DI RISC Core
•
26-bit External Address Bus
•
16-bit External Data Bus
•
2KB Data/Instruction Cache
•
2KB Static RAM
•
programmable clock and power management
•
programmable monochrome LCD controller
•
on-chip interrupt controller
•
three 16450 class UARTS
•
IrDA/DASK IR interface
•
three pulse width modulator channels
•
flexible memory interface
•
on-chip DRAM controller
•
programmable peripheral interface
•
three, 16-Bit counter/timer channels
•
hardware watchdog timer
•
external busmaster support
•
little endian memory format.
The LH77790A microcontroller is powered by a 5V regulator and has a single 24MHz
clock generator. The microcontroller pins are connected to four banks of 50 plated
through holes (PTHs), JP1, JP2, JP3, and JP4. For more details please consult the Sharp
LH77790A Embedded Microcontroller User’s guide V 2.1.
2-4
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Hardware Description
2.3
LEDs
General purpose LEDs
JTAG
connector
.......
.......
D1 D2 D3 D4
Serial
port
connector
JP5
INTERRUPT
P1
SW1
LH77790A
J1
SW2
RESET
Power
connector
D5
Power LED
Figure 2-2 LED Locations
There are five LEDs on the ARM Evaluation Board. Four of them, D1 to D4, are user
controllable and located at the top of the board. They are connected to the high-order
nibble of Port C on the Sharp LH77790A Microcontroller. LED D5 is connected to the
5V output of the LM2937 voltage regulator and is a power indicator light. It is located
in the bottom right area of the board near the power socket.
Table 2-1 LED colors
ARM DUI 0091A
LED
Color
D1
Green
D2
Red
D3
Yellow
D4
Green
D5
Red
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-5
Hardware Description
The Sharp LH77790A Programmable Peripheral Interface has 24 programmable Input/
Output (I/O) pins grouped into three, eigh8-bit ports:
•
PA[7:0]
•
PB[7:0]
•
PC[7:0]
Each port has three modes, 0, 1, or 2. These modes determine which pins can be set as
general purpose outputs that allow software access to the LEDs:
•
MODE 0 provides for simple input and output (no handshaking) for the three ports.
All user controllable LEDs are accessible by software.
•
MODE 1 provides for I/O using strobes or handshaking. In MODE 1, transfers on
Ports A and B use Port C signals for handshaking. Only two of the user controllable
LEDs are software accessible (the particular LED pair is determined by the I/O
direction of Port B).
•
MODE 2 operation on Port A provides bi-directional data transfer on the eight-bit
port with handshaking on Port C as in MODE 1. The user controllable LEDs are
not software accessible in MODE 2.
For complete details refer to the latest version of the Sharp LH77790A Embedded
Microcontroller User’s Guide. See http://www.sharpmeg.com/lh/index.html.
In order for software to have access to the LEDs the corresponding Port C pins must be
configured as general purpose outputs. The initialized state of the evaluation board is
such that the Programmable Peripheral Interface is set to MODE 0 and the upper half
of Port C (the LED control lines) set to general purpose outputs. As a result, on power
up all four user controllable LEDs are software accessible for output.
+5V
47KΩ
47KΩ
Port C6
Port C7
47KΩ
47KΩ
Port C5
Port C4
1KΩ
1KΩ
1KΩ
1KΩ
D1 green
D1 green
D1 green
D1 green
Figure 2-3 Connection of the four output LEDs on Port C
2-6
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Hardware Description
2.4
2.4.1
Memory
FLASH bootROM
The evaluation board contains 128KB of FLASH memory which contains the ROM
monitor/Boot ROM. It can also be programmed to contain any downloaded program.
The FLASH memory is implemented as a single, 8-bit, component, manufactured by
Amtel Corporation. It is decoded by the active low, Chip Select 0 (nCS0) from the
Sharp LH77790A and as such will respond at address 0 within Memory Bank 0.
2.4.2
SRAM
There are three arrays of SRAM memory on the ARM Evaluation Board. Two of these
memory arrays are found on the LH77790A microcontroller itself, and the third,
consisting of two 64K x 8 SRAM parts (U4 and U3), is connected via the external bus.
nCS1
nCE1/nCAS1
nOE
64KB x 8 SRAM
U4
nWE
A[0 – 15]
D[0 – 7]
CS2
nOE
nWE
A[1 – 16]
SHARP
LH77790A
D[0 – 7]
microcontroller
D[8 – 15]
nBW
A0
U1
nCS1
nOE
64KB x 8 SRAM
U3
nWE
A[0 – 15]
D[8 – 15]
CS2
U10
Figure 2-4 External SRAM memory array
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-7
Hardware Description
Of the two, 2KB, memory arrays found on the LH77790A (U1), one can be configured
as a cache or general-purpose SRAM (fast storage) while the other is used solely as fast
storage.
The 128KB memory array connected to the LH77790A via the external 16-bit memory
bus consists of two 64K x 8 SRAM parts (U4 and U3). U4 is connected to the lower
order byte lane (D0 - D7) of the 16-bit data bus while U3 is connected to the higher
order byte lane (D8 - D15). This is shown in Figure 2-4 External SRAM memory array
on page 2-7.
The address bus is shifted down by one to connect to both SRAM parts, thus all
addresses received by the SRAM parts are truncated to a half-word boundary.
Each SRAM part has two Chip Select (CS) inputs, nCS1 and CS2. The nCS1 inputs for
both U4 and U5 are connected together to the active low Chip Enable active LOW
Column Address Select (nCE1/nCAS1) output on the Sharp LH77790A. This means
that the SRAM array will only respond within Memory Bank1 of the microcontroller
physical address space.
The logic circuit connects the CS2 inputs of both SRAM parts to the external address
bus (A0) and the active low, byte wide access (nBW) from the microcontroller. Its
function is to enable the correct SRAM part to drive its respective data byte lane
depending on whether we have a 16-bit or 8-bit access.
The timing diagrams on the following pages show the SRAM read and write access
operations.
2-8
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
nCS2
nWAIT
nBW
nWE
nOE
nCE1/ nCS1
D15 - D0
A25 - A0
XCLK
tXBW
tGD
Cycle 1
tWS
tXOE
tXCE
VALID
Cycle 2
tCO1
Cycle 3
tWtH
VALID
tDS
VALID
Cycle 4
tWTS
tDH
tXA
Cycle 5
tAA
Cycle 6
tWH
VALID
tDS
VALID
Cycle 7
tXBWH
tXOEH
tXCEH
tDH
Hardware Description
Figure 2-5 SRAM read access
2-9
2-10
© Copyright ARM Limited 1998. All rights reserved.
Open Access
CS2
nBW
nWE
nOE
nCE1/ nCS1
D15 - D0
A25 - A0
XCLK
tXBW
tXA
tTGD
VALID
Cycle 1
tXCE
TXD
tXWE
Cycle 2
tCW
VALID
VALID
Cycle 3
Cycle 4
tXDH
tXA
Cycle 5
Cycle 7
VALID
VALID
tWC
Cycle 6
tXBWH
tXWEH
tXCEH
tXAH
Hardware Description
Figure 2-6 SRAM write access
ARM DUI 0091A
Hardware Description
Table 2-2 SRAM timing parameters
ARM DUI 0091A
Parameter
Description
tCO1
Chip Select CS1 access time
70
tXCE
XCLK↓ to nCE Active
22
tXOE
XCLK↓ to nOE Active
20
tXBW
XCLK↓ το nBW valid
23
tGD
Total decoder gate delay
15
tWTS
nWAIT setup relative to XCLK↓
tWTH
nWAIT hold relative to XCLK↓
tDS
Read data setup relative XCLK↓
9
tDH
Read data hold relative XCLK↓
3
tXCEH
nCE Hold relative XCLK↓
8
tAA
Address access time
70
tXA
XCLK↓ to address valid
27
tXD
XCLK↓ to write data valid
28
tXWE
XCLK↑ to nWE Active
19
tXWEH
nWE Hold relative XCLK↓
8
tCW
Chip select to end of write
60
tXDH
Write data hold relative XCLK↓
10
tWC
Write cycle time
70
tXAH
Address hold relative XCLK↓
11
tXBWH
nBW Hold relative to XCLK↓
7
© Copyright ARM Limited 1998. All rights reserved.
Open Access
Min
Max
2-11
Hardware Description
2.5
JTAG connector
The 14-pin connector (JP5) is connected to the JTAG interface of the LH77790A. The
pinout is compatible with the ARM EmbeddedICE interface and as such supports
several ICEBreaker compatible modules. The pinout is shown below.
VSS
VSS
VSS
VSS
2
4
6
8
10
12
14
1
3
5
7
9
11
13
TCK
TDO
SPU
SPU
nTRST
TDI
TMS
VSS
nICERST VSS
Figure 2-7 Pinouts of JTAG/ICE connector (JP5)
Table 2-3 Pinouts of JTAG/ICE connector (JP5)
2-12
Pin(s)
Name
Description
2, 4, 6, 8, 10, 14.
VSS
Substrate Voltage
12.
nICERST
Ice Reset (for tablet unit, active low)
1, 13.
SPU
Safe Power Up
3
nTRST
Test System Reset(JTAG, active low)
5
TDI
Test Data Serial In
7
TMS
Test Mode Select
9
TCK
Test Clock
11
TDO
Test Data Serial Out
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Hardware Description
2.6
Serial port
An RS232 line driver (Maxim Semiconductor part number MAX233) is used between
the microcontroller and the serial port connector. The pinout of the serial port connector
is shown below.
DCD
RxD
1
TxD
DTR
3
4
2
6
7
DSR
RTS
GND
15
8
CTS
9
RI
Figure 2-8 Pinouts of the RS232 serial port connector (P1)
Table 2-4 Pinouts of the RS232 serial port connector (P1)
ARM DUI 0091A
Pin(s)
Name
Description
1
DCD
Data Carrier Detect
2
RxD
Receive Data
3
TxD
Transmit Data
4
DTR
Data Transmit Ready
5
GND
Ground
6
DSR
Data Send Ready
7
RTS
Ready To Send
8
CTS
Clear To send
9
RI
Ringing Indicator
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-13
Hardware Description
2.7
5V voltage regulator
The evaluation board is supplied with power at +5V by a regulator circuit using an
LM2937ES. The circuit operates within an input voltage range of 6 -13 Volts. The LED
D5 indicates the presence of power at the output of the voltage regulator. Reverse power
protection is built into the LM2937ES.
2.8
50 PTH blocks J1 to J4
Table 2-5 JP1
2-14
Description
Name
Pin
Pin
Name
Description
Voltage at Collect
VCC
01
02
GND
Ground
External Clock
XCLK
03
04
NC
No Connect
Address 0
A0
05
06
A1
Address 1
Address 3
A3
07
08
A2
Address 2
No Connect
NC
09
10
NC
No Connect
Address 4
A4
11
12
A5
Address 5
Address 6
A6
13
14
A7
Address 7
Address 8
A8
15
16
A9
Address 9
Address 10
A10
17
18
A11
Address 11
No Connect
NC
19
20
NC
No Connect
Address 12
A12
21
22
A13
Address 13
Address 14
A14
23
24
A15
Address 15
Address 16
A16
25
26
A17
Address 17
Address 18
A18
27
28
A19
Address 19
No Connect
NC
29
30
NC
No Connect
Address 20
A20
31
32
A21
Address 21
Address22
A22
33
34
A23
Address 23
Address 24
A24
35
36
A25
Address 25
Data 0
D0
37
38
D1
Data 1
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Hardware Description
Table 2-5 JP1 (continued)
Description
Name
Pin
Pin
Name
Description
No Connect
NC
39
40
NC
No Connect
Data 2
D2
41
42
D3
Data 3
No Connect
NC
43
44
NC
No Connect
No Connect
NC
45
46
NC
No Connect
No Connect
NC
47
48
NC
No Connect
No Connect
NC
49
50
NC
No Connect
Table 2-6 JP2
ARM DUI 0091A
Description
Name
Pin
Pin
Name
Description
Voltage at Collect
VCC
01
02
GND
Ground
Data 4
D4
03
04
D5
Data 5
Data 6
D6
05
06
D7
Data 7
Data 8
D8
07
08
D9
Data 9
No Connect
NC
09
10
NC
No Connect
Data 10
D10
11
12
D11
Data 11
Data 12
D12
13
14
D13
Data 13
Data 14
D14
15
16
D15
Data 15
Row Address Select 0
RAS0
17
18
RAS1
Row Address Select 1
No Connect
NC
19
20
NC
No Connect
Chip Enable 0 (active
low)
/Column Address
Select 0 (active low)
nCE0/nCAS0
21
22
nCCE1/
NCAS1
Chip Enable 1 (active
low)
/No Connect
Chip Enable 2 (active
low)
/Column Address
Select 2 (active low)
nCE2/nCAS2
23
24
nCCE3/
NCAS3
Chip Enable 3 (active
low)
/No Connect
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-15
Hardware Description
Table 2-6 JP2 (continued)
Description
Name
Pin
Pin
Name
Description
Chip Enable 4 (active
low)
/Column Address
Select 4 (active low)
nCE4/nCAS4
25
26
nCCE5/
NCAS5
Chip Enable 5
(active low)
/No Connect
Write Enable
(active low)
nWE
27
28
nOE
Output Enable
(active low)
Byte Wide Access
(active low)
nBW
29
30
nWAIT
External Memory Wait
(active low)
No Connect
NC
31
32
NC
No Connect
Video Data 0
VD0
33
34
VD1
Video Data 1
Video Data 2
VD2
35
36
VD3
Video Data 3
Video Data 4
VD4
37
38
VD5
Video Data 5
Video Data 6
VD6
39
40
VD7
Video Data 7
No Connect
NC
41
42
NC
No Connect
No Connect
NC
43
44
NC
No Connect
No Connect
NC
45
46
NC
No Connect
No Connect
NC
47
48
NC
No Connect
No Connect
NC
49
50
NC
No Connect
Table 2-7 JP3
2-16
Description
Name
Pin
Pin
Name
Description
Voltage at Collect
VCC
01
02
GND
Ground
Shift/Pixel Clock
CP2
03
04
CP1
Line Pulse/HYSNC
AC Modulation Signal
MCLK
05
06
S
Frame pulse/VSYNC
LCD Control Signal
LCDCNT
07
08
PWM0
Pulse Width Modulator
output signal 0
Pulse Width Modulator
output signal 1
PWM1
09
10
PWM2
Pulse Width Modulator
output signal 2
No Connect
NC
11
12
NC
No Connect
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Hardware Description
Table 2-7 JP3 (continued)
ARM DUI 0091A
Description
Name
Pin
Pin
Name
Description
Chip and JTAG
Controller Reset Input
(active low)
nRESETI
13
14
INT0
External Interrupt
signal 0
External Interrupt
signal 1
INT1
15
16
INT2
External Interrupt
signal 2
External Interrupt
signal 3
INT3
17
18
INT4
External Interrupt
signal 4
External Interrupt
signal 5
INT5
19
20
nRxD0
UART serial data input
signal 0 (active low)
No Connect
NC
21
22
NC
No Connect
UART serial data
output signal 0 (active
low)
nTxD0
23
24
nRxD1
UART serial data input
signal 1 (active low)
UART serial data
output signal 1 (active
low)
nTxD1
25
26
nRxD2
UART serial data input
signal 2 (active low)
UART serial data
output signal 2 (active
low)
nTxD2
27
28
UCLK
UART/DASK clock
Counter/timer control
gate input 0
CTGATE0
29
30
CTOUT0
Counter/timer output
signal 0
Chip and JTAG
Controller Reset
Output (active low)
nRESETO
31
32
NC
No Connect
Counter/timer control
gate input 1
CTGATE1
33
34
CTOUT1
Counter/timer output
signal 1
Counter/timer control
gate input 2
CTGATE2
35
36
CTOUT2
Counter/timer output
signal 2
Counter/timer external
clock input signal
CTCLK
37
38
PA0
I/O port A signal 0
I/O port A signal 1
PA1
39
40
PA2
I/O port A signal 2
No Connect
NC
41
42
NC
No Connect
No Connect
NC
43
44
NC
No Connect
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-17
Hardware Description
Table 2-7 JP3 (continued)
Description
Name
Pin
Pin
Name
Description
No Connect
NC
45
46
NC
No Connect
No Connect
NC
47
48
NC
No Connect
No Connect
NC
49
50
NC
No Connect
Table 2-8 JP4
2-18
Description
Name
Pin
Pin
Name
Description
Voltage at Collect
VCC
01
02
GND
Ground
I/O port A signal 3
PA3
03
04
PA4
I/O port A signal 4
I/O port A signal 5
PA5
05
06
PA6
I/O port A signal 6
I/O port A sigI/Onal 2
PA7
07
08
PB0
I/O port B signal 0
I/O port B signal 1
PB1
09
10
PB2/nRI1
Ring Indicator for
UART1 (active low)
No Connect
NC
11
12
NC
No Connect
I/O port B signal 3/
Clear To Send for
UART1 (active low)
PB3/nCTS1
13
14
PB4/nCTS0
I/O port B signal 4/
Clear To Send for
UART0 (active low)
I/O port B signal 5/
Ring Indicator for
UART1 (active low)
PB5/nRI0
15
16
PB6/nDCD0
I/O port B signal 6/
Data Carrier Detect for
UART0 (active low)
I/O port B signal 7/
Data Set Ready for
UART0 (active low)
PB6/nDSRO
17
18
PC0/nRTS1
I/O port C signal 0
/Request To Send for
UART1 (active low)
I/O port C signal 1
/Request To Send for
UART0 (active low)
PC1/nRTS0
19
20
PC2/nDTR0
I/O port C signal 2
/Data Terminal ready
for UART0 (active
low)
No Connect
NC
21
22
NC
No Connect
I/O port C signal 3
PC3
23
24
PC4
I/O port C signal 4
I/O port C signal 5
PC5
25
26
PC6
I/O port C signal 6
I/O port C signal 7
PC7
27
28
TCK
JTAG Test
EmbeddedICE clock
input signal
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Hardware Description
Table 2-8 JP4 (continued)
ARM DUI 0091A
Description
Name
Pin
Pin
Name
Description
JTAG Test
EmbeddedICE mode
select input signal
TMS
29
30
XCLKDIS
External clock circuitry
disable
No Connect
NC
31
32
NC
No Connect
JTAG Test
EmbeddedICE data
input signal
TD1
33
34
TD0
JTAG Test
EmbeddedICE data
ouput signal
No Connect
NC
35
36
TEST1
Reserved. No Connect
Byte Boot (active low)
nBB
37
38
nADBE
Reserved (active low)
No Connect
NC
39
40
TEST3
Reserved. No Connect
No Connect
NC
41
42
NC
No Connect
No Connect
NC
43
44
NC
No Connect
No Connect
NC
45
46
NC
No Connect
No Connect
NC
47
48
NC
No Connect
No Connect
NC
49
50
NC
No Connect
© Copyright ARM Limited 1998. All rights reserved.
Open Access
2-19
Hardware Description
2-20
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Chapter 3
Bootstrap Loader Setup and Use
This chapter describes:
ARM DDI 0091A
•
the basic setup with the Bootstrap Loader
•
the Bootstrap line command editor
•
the Bootstrap commands
•
FLASH and module management
•
application downloading and execution.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-1
Bootstrap Loader Setup and Use
3.1
Overview
The Bootstrap Loader is located in the first 16K of the FLASH ROM and is the first
code that is executed by the LH77790A processor when it powers up or resets. This
code has four major areas of functionality:
3-2
•
It provides facilities to configure the board and provide user help.
•
It manages the FLASH on the board as a set of executable modules.
•
It allows you to download applications to SRAM and execute them.
•
It provides a basic set of C style input/output (IO) functions which are called using
software interrupt (SWI) calls from executing programs.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
3.2
Basic setup with the Bootstrap Loader
This is the simplest configuration for the ARM Evaluation Board.
Host PC
Serial cable
D1 D2 D3 D4
JP5
INTERRUPT
P1
SW1
LH77790A
J1
SW2
RESET
D5
Power adapter
(to mains power socket)
Figure 3-1 Angel Debug Monitor setup configuration
ARM DDI 0091A
1.
Connect the null modem cable to the evaluation board.
2.
Connect the other end of the cable to the host PC, making a note of the serial port
that is used.
3.
Connect the power adapter to the power connector on the evaluation board.
4.
Connect the power adapter to the mains power socket. The red LED power
indicator D5 lights up.
5.
Press the reset button on the evaluation board. The four general purpose LEDs
should flicker and the green LED D1 should remain on. This indicates the board
has been initialized and is working correctly.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-3
Bootstrap Loader Setup and Use
3.2.1
Configuring the system using Unix terminal
To start tip enter :
tip
-<baud-rate> <device name>
Where baud-rate is one of the baud rates listed in Table 3-1 Supported Bootstrap
Loader serial line settings and device name is the name of the device associated with
the serial port attached to the board (usually /dev/ttya or /dev/ttyb). For example
tip -38400 /dev/ttya
Table 3-1 Supported Bootstrap Loader serial line settings
Baud rate
Data bits
Parity
Stop bits
Flow control
9600
8
none
1
none
19200
8
none
1
none
38400
8
none
1
none
Note
Most UNIX systems do not support baud rates higher than 38400 baud.
3-4
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
3.2.2
Configuring the system using Windows HyperTerminal
1.
Start the Windows HyperTerminal terminal emulator program by selecting Start,
then Programs, then Accessories, and then HyperTerminal. Double click on
Hyper Terminal. The application will start and display a Connection
Description dialog box.
2.
Enter a name in the dialog box (for example ArmEval) and click on OK.
3.
Select the COM port to which you have connected the evaluation board from the
menu Direct to COM1 through Direct to COM4.
4.
In the next dialog box select a baud rate from the list of baud rates shown in
Table 3-2 Supported Bootstrap Loader serial line settings. Older PCs may not
support baud rates in excess of 38400.
Table 3-2 Supported Bootstrap Loader serial line settings
Baud rate
Data bits
Parity
Stop bits
Flow control
9600
8
none
1
none
19200
8
none
1
none
38400
8
none
1
none
57600
8
none
1
none
115200
8
none
1
none
If you are not using a VT100 emulator you must connect initially at 9600 baud as
the board cannot detect what baud rate you are using. You can later configure the
board to use a higher baud rate.
5.
Select None from the Flow Control menu. If you change the serial line
Properties from the File menu within Hyper Terminal you will have to
disconnect the current session and restart before the changes will take effect.
6.
Connect the power adapter to the power connector on the evaluation board.
7.
Connect the power adapter to the power outlet. The red LED D5 on the board
will light to indicate power. Press the reset button on the evaluation board. The
board should display the following message:
ARM Evaluation Board Boot Monitor 0.01 (19 APR 1998)
Press ENTER within 2 seconds to stop autoboot
ARM DDI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-5
Bootstrap Loader Setup and Use
8.
Press ENTER within 2 seconds to prevent the board from autobooting any other
modules which may be present in flash. You will then get the prompt Boot: and
LEDs D3 and D4 will be lit.
If you do not observe the banner described in step 7 above:
1.
Check that you are using one of the supported baud rates shown in Table 3-2
download on page 3-5.
2.
Check that you are using a genuine VT100 emulator.
3.
Try switching to 9600 baud (if the board cannot detect what baud rate you are
using it defaults to 9600 baud).
4.
Regardless of the baud rate you should always configure your terminal emulator
for 8 bits data, No parity, 1 stop bit. You should also disable any flow control on
your terminal emulator (Xon/Xoff or Hardware handshake). If you cannot disable
hardware flow control then you may need to tie some or all of CTS, DSR and CD
high.
5.
Check that you are using the correct serial cable. The cable requires three
connections, Signal Ground, Rx, and Tx. Rx and Tx to be crossed over (i.e. you
should be using a null-modem cable).
The Bootstrap Loader stores environment variables which are used to configure the
board. If you change these values then the board will configure differently. Since the
storage area can be accessed by modules new environmental variables can be added or
existing ones modified, and then used by all modules.
3-6
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
3.3
Bootstrap Loader command line editor
While entering commands in the BootStrap loader you can use the BootStrap loader
command line editor to edit the command. The commands are not case sensitive. These
editing facilities are built into the BootStrap loader Read Line Software Interface (SWI)
so any other module which uses this SWI will be able to use the editing facilities.
Table 3-3 Bootstrap editor commands
3.4
3.4.1
Key
Function
BACKSPACE
Delete the character before the cursor
DEL
Same function as BACKSPACE
CTRL-A
Move the cursor to the start of the current
line.
CTRL-B
Moves the cursor back one character.
CTRL-D
Forward Delete - deletes the character under
the cursor. If entered on an empty line
CTRL-D is treated as End Of File.
CTRL-E
Move the cursor to the end of the current
line.
CTRL-F
Move the cursor forward one character.
CTRL-R
Redraws the current line
CTRL-U
Erases the current line
Bootstrap commands
boot
Usage: boot
The Boot command is used to reboot the system:
Boot: boot
ARM Evaluation Board Boot Monitor 0.01 (19 APR 1998)
Press ENTER within 2 seconds to stop autoboot
ARM DDI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-7
Bootstrap Loader Setup and Use
3.4.2
help
Usage: help <command>
Entering help at the Boot: prompt with no arguments returns a list of commands
supported by the Bootstrap Loader. The help command goes through each module in
FLASH and lists all the commands supported by each module. For example:
Boot: help
Module is BootStrap
0.01 (19 APR 1998)
Help is available on:
Help Modules ROMModules nPlug PlugIn
Kill SetEnv UnSetEnv PrintEnv DownLoad
Go GoS Boot PC FlashWrite
FlashLoad FlashErase
Module is Angel
1.02 (12 MAY 1998)
To get help on a specific command you can enter help <Command>.This will give a brief
one line help on the command. For example:
Boot: help help
Usage: help <command>
Help gives help on the command, if none specified, gives a list of
commands.
You can also specify a module name instead of the <command>. This will list all the
commands supported by that module. For example:
Boot: help bootstrap
Module is BootStrap
0.01 (19 APR 1998)
Help is available on:
Help Modules ROMModule UnPlug PlugIn
Kill SetEnv UnSetEnv PrintEnv DownLoad
Go GoS Boot PC FlashWrite
FlashLoad FlashErase
This only gives help about the Bootstrap module.
3-8
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
3.4.3
setenv
Usage: setenv <variable-name> <value>
Table 3-4 Environment variables used by the basic Bootstrap Loader
Variable
Value
noautoboot
boot
If this variable is set then the BootStrap loader bypasses
the normal autoboot sequence and goes straight to the
Boot: prompt. This can be used to prevent the BootStrap
loader from automatically starting another module stored
in flash.
<bootmodule>
noautobaud
This variable may be set to the name of a module to boot
at startup. If this variable is set the Bootstrap Loader will
boot that module, otherwise the Bootstrap Loader will
boot the last module in the module list which has the
AutoBoot bit set.
If this variable is set then the Bootstrap Loader bypasses
the normal baud rate detection and defaults to the
configured baud rate, or 9600 baud if no baud rate is
configured.
baud
<baud-rate>
Sets the configured baud rate for the board. This may be
one of 9600, 19200, 38400, 57600 or 115200.
The Bootstrap Loader will first perform automatic baud
rate detection (subject to the setting of the noautobaud
variable) and will only use this value if the baud rate
could not be determined or if the noautobaud variable is
set.
ram-base
<base
address>
This variable may be set to configure the base address of
the main RAM segment on the board. The <baseaddress> should be specified in hex and should be
aligned on a 1KB page boundary. The base address
defaults to 0x8000. The base address of the ROM and of
the internal SRAM cannot be configured.
nocache
ARM DDI 0091A
Effect
This variable should always be set.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-9
Bootstrap Loader Setup and Use
SetEnv allows you to set an environment variable which is programmed into flash. You
may program any variable name into flash. However certain variable names are
recognized by different modules in the system to provide for configuration options. If
you are writing your own module you may wish to assign your own variable names to
have specific meaning for your module. For example, the command setenv baud
38400 will tell the BootStrap loader to use a baud rate of 38400. This command will
not take effect until the board is next reset.
You may omit the <value> part to set BOOLEAN type variable which are assumed to
be TRUE the variable exists or FALSE if it does not. For example:
Boot: setenv baud 38400
Boot: setenv noautobaud
The command setenv noautobaud will tell the BootStrap loader not to do autobaud
rate detection on startup. Used in conjunction with the setenv baud 38400, above, a
fixed baud rate of 38400 is set on the board. If you just use the setenv baud 38400
command, the auto baud rate detection will override the configured baud rate and the
configured baud rate will only apply if the board cannot determine what baud rate you
are using. You should enter these commands if you had difficulty getting started with
the board and had to revert to 9600 baud.
Caution
You should not set the baud rate to a baud rate higher than your terminal can support. If
you do, you may not be able to regain control of the board.
3.4.4
unsetenv
Usage: unsetenv <variable-name>
UnSetEnv unsets (removes) an environment variable previously created with setenv.
For example:
Boot: unsetenv noautobaud
Boot: unsetenv baud
3-10
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
3.4.5
printenv
Usage: printenv
PrintEnv lists the variables currently stored in the environment area in the flash ROM.
For example:
Boot: printenv
Variable
Value
========
=====
nocache
noautobaud
baud
3.5
38400
FLASH and module management
The FLASH storage on the evaluation board consists of a number of executable
modules. The basic FLASH which is shipped with the evaluation board contains two
modules. The first is the Bootstrap Loader itself and the other is the Angel Debug
Monitor. By default, the Angel Debug Monitor is automatically run if the Bootstrap
Loader is not interrupted by the user pressing the enter key in the connected terminal
application.
3.5.1
modules
Usage: modules
modules gives a list of all initialized modules. For example:
Boot: modules
Header
Base
Limit
Data
04000004 04000000 040033c0 00000000 BootStrap 0.01 (19 APR 1998)
where
Header is the address of the module header within the module
Base is the first address of the module in flash
Limit is the last address (+1) of the module in flash
Data is the address of the modules data (0 => none).
ARM DDI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-11
Bootstrap Loader Setup and Use
3.5.2
rommodules
Usage: rommodules
rommodules scans the flash memory and prints out a list of all modules in flash, as
opposed to Modules which lists only those modules that have been initialised. With
each module rommodules prints the Header, Base and Limit information as for
modules. It does not print the Data information because an uninitialized module
cannot have any data.
This command gives a list of all modules available in flash along with the version
number, date and base address in flash of each module. For example:
Boot: rommodules
Header
Base
Limit
04000004 04000000 040033c0 BootStrap 0.01 (19 APR 1998)
0400e4f4 04004000 0400e60f Angel 1
3.5.3
modulename
Usage: modulename
You can type just the name of a module to run that module. For example:
Boot: bootstrap
ARM Evaluation Board Boot Monitor 0.01 (19 APR 1998)
Press ENTER within 2 seconds to stop autoboot
This reruns the Bootstrap module thus rebooting the board.
3.5.4
unplug
Usage: unplug <module name>
unplug tells the BootStrap Loader not to try to initialize that module when the board is
next booted. In addition, if the module is currently active (it has been initialised) it will
try to kill the module.
unplug is useful if you have an errant module which is causing the board to crash when
it is booted. In this case, boot the board, press <ENTER> to interrupt the boot, then
unplug the errant module and reboot the board. If you don’t know which module is
causing the problem keep unplugging modules until the problem ceases. You can then
use the plugin command to reinstate the modules which are working satisfactorily.
3-12
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
Caution
It is usually a bad idea to unplug the Bootstrap module itself. However if you do so, all
is not lost. You can still recover by booting the board and interrupting the boot by
pressing <ENTER>. When you interrupt the boot like this the Bootstrap Loader always
initializes itself so you can regain control by using the plugin command.
3.5.5
plugin
Usage: plugin <module name>
The plugin command may be used to reinstate a module which has been unplugged
with the unplug command. The plugin command marks the module so that the
BootStrap loader will find it next time the board is booted. The plugin command also
initializes the module.
The plugin command may also be used to initialize a module which failed to initialize
at boot time.
3.5.6
kill
Usage: kill <module name>
The kill command kills a module by calling its finalization code. Unlike the unplug
command it does not mark the module as unplugged so the module will be initialised
the next time the board is booted. Use kill to remove a module temporarily, and use
unplug to remove it permanently.
ARM DDI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
3-13
Bootstrap Loader Setup and Use
3.6
3.6.1
Application downloading and execution
Preparing an application for downloading into SRAM
To build an application for downloading you may either use the latest ARM Toolkit or
the GNU ProToolkit (available from http://www.cygnus.com/product/).
3.6.2
Example application
#include "module.h"
#include "swis.h"
extern ARMWord Image$$RO$$Base[];
extern ARMWord Image$$RO$$Limit[];
extern ARMWord Image$$RW$$Base[];
extern ARMWord Image$$ZI$$Base[];
extern ARMWord Image$$ZI$$Limit[];
extern void start(char *cmd);
extern ModuleHandle init(void);
extern void final(void);
extern ServiceBlock service(ServiceBlock sb);
extern CallBack swi(unsigned swino, SWIRegs *regs);
extern CallBack command(char *cmd);
static const CmdTable Example_Commands[] = {
{
"ExCommand",
command,
0,
"Usage: ExCommand ",
"A trivial command example"
},
{
0, 0, 0, 0, 0
}
};
3-14
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DDI 0091A
Bootstrap Loader Setup and Use
global_reg(6) unsigned R9;
extern __swi(SWI_PrettyPrint) void PrettyPrint(const char *fmt, ...);
extern __swi(SWI_CLI) void CLI(char *cmd);
extern __swi(SWI_Exit) void Exit(void);
extern __swi(0x100) MySWI(int r0);
void start(char *cmd)
{
unsigned r0;
PrettyPrint("*** In start entry, R0 = %s, R9 = %x", cmd, R9);
PrettyPrint("*** Calling my own SWI (0x100) with R0 = 0x12341234");
r0 = MySWI(0x12341234);
PrettyPrint("*** My SWI returned %x", r0);
PrettyPrint("*** Executing my own command \"ExCommand Hello,
World\"");
CLI("ExCommand Hello, World");
Exit();
}
ModuleHandle init(void)
{
PrettyPrint("*** In init entry, returning R0 = 0x12345678");
return (ModuleHandle)0x12345678;
}
void final(void)
{
PrettyPrint("*** In final entry, R9 = %x", R9);
}
__value_in_regs ServiceBlock service(ServiceBlock sb)
{
PrettyPrint("*** In service entry, R0 = %d, R1 = %x, R2 = %x",
sb.r0, sb.r1, sb.r2);
PrettyPrint("*** ... R3 = %x, R9 = %x", sb.r3, R9);
sb.r0 = 0;
return sb;
}
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Bootstrap Loader Setup and Use
CallBack command(char *cmd)
{
PrettyPrint("*** In command handler, R0 = %s, R9 = %x", cmd, R9);
return 0;
}
CallBack swi(unsigned swino, SWIRegs *regs)
{
PrettyPrint("*** In swi handler, SWI #%d, regs->r[0] = %x, R9 = %x",
swino, regs->r[0], R9);
PrettyPrint("*** Returning R0 = 0xABCDABCD");
regs->r[0] = 0xABCDABCD;
return 0;
}
3.6.3
Compiling your application
If you are using the ARM tools and building a large application you may wish to add
the <-nodebug> option to armlink. This prevents armlink from adding debug info to
the image which can be quite space consuming.
To build your application using the GNU ProToolkit you should use the following
command format to link your program:
arm-coff-gcc -o <output-file> <input object files> -Xlinker -oformat Xlinker binary
For example:
arm-coff-gcc -o dhry dhry_1.o dhry_2.o -Xlinker -oformat -Xlinker binary
This command will invoke the GNU linker (arm-coff-ld) with the correct options and
will also pass the Demon C library to arm-coff-ld for inclusion in the link stage.
3.6.4
Linking your application program
•
To link your application using the ARM STD you should use the following linker
command line format:
armlink -o <output-file> <input object files> <demon library>
For example:
armlink -o dhry dhry_1.o dhry_2.o /work/tools/rel211/common/lib/demon/
armlib.32l
Please note that, as shown above, you must use the Demon C library for applications
which you wish to download to the Bootstrap Loader.
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Bootstrap Loader Setup and Use
3.6.5
Converting your application to uuencoded format
To convert the linked application image to uuencoded format using uuencode use the
following example as a guide:
uuencode dhry dhry > dhry.uue
A link to a source of uuencode for Windows which has been tested to work with the
Bootstrap Loader is
<http://home.swbell.net/ravntree/wuudoall.html
The following procedure needs to be performed;
1. Click on Preferences→Encode. The Encode Preferences dialog will appear.
2. Click on the Write Encoding Table and check the box to disable it.
3. Click on the Write Size Record and check the box to disable it.
4. Click on the Use BackQuote For Spaces and check the box to disable it.
5. Click on the OK button.
3.6.6
Downloading your application
Please refer to download on page 3-27 in order to download your application to SRAM.
ARM DDI 0091A
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Bootstrap Loader Setup and Use
3.6.7
Creating new modules
A module is piece of executable code which contains a module header descriptive
structure embedded somewhere within it. This descriptive structure is not required to be
the first item in the module. The module header structure must take the following form
as described in the C language:
typedef struct ModuleHeader ModuleHeader;
struct ModuleHeader {
unsigned
magic;
unsigned
flags:16;
unsigned
major:8;
unsigned
minor:8;
unsigned
ARMWord
checksum;
*ro_base;
ARMWord
*ro_limit;
ARMWord
*rw_base;
ARMWord
*zi_base;
ARMWord
*zi_limit;
ModuleHeader
*self;
StartCode
start;/* Optional - may be 0 */
InitCode
init;/* Optional - may be 0 */
FinalCode
final;/* Optional - may be 0 */
ServiceCode
service;/* Optional - may be 0 */
TitleString
title;
HelpString
help;
CmdTable
*cmdtbl;/* Optional - may be 0 */
SWIBase
swi_base;/* Optional - may be 0 */
SWICode
swi_handler;/* Optional - may be 0 */
};
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The following is a description of each of the fields within the module. The fields in the
module must be in the order shown in table
Table 3-5 Module fields
Offset
ARM DDI 0091A
Name
Description
0x00
magic
Magic word (value = 0x4d484944) used to identify this
as a module.
0x04
flags
A 16 bit flags field. The individual flags are described below.
0x06
major
A 1b major version number. Currently this should have the value
1.
0x07
minor
A 1b major version number. Currently this should have the value
0.
0x08
checksum
An EOR checksum of the entire module used to validate the
module.
0x0C
ro_base
The linked Read Only base of the module (=Image$$RO$$Base).
0x10
ro_limit
The linked Read Only limit of the module
(=Image$$RO$$Limit).
0x14
rw_base
The linked Read Write base of the module
(=Image$$RW$$Base).
0x18
zi_base
The linked Zero Init base of the module (=Image$$ZI$$Base).
0x1C
zi_limit
The linked Zero Init limit of the module (=Image$$ZI$$Limit).
0x20
self
A pointer to the linked address of the module header.
0x24
start
The linked address of the start code called to boot a module.
0x28
init
The linked address of the init code called to initialise a module.
0x2C
final
The linked address of the final code called to kill a module.
0x30
service
The linked address of the service call entry of a module.
0x34
title
The linked address of the title string of the module.
0x38
help
The linked address of the help string of the module.
© Copyright ARM Limited 1998. All rights reserved.
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Table 3-5 Module fields
Offset
Name
Description
0x3C
cmdtbl
A pointer to the command table for this module.
0x40
swi_base
The base address of the 64 entry SWI chunk handled by this
module.
0x44
swi_handler
A pointer to the SWI handler for this module.
magic
This word identifies a module header. The word should be set to the value
MODULE_MAGIC which has the following definition.
#define MODULE_MAGIC
0x4d484944;
/* ’MHID’ */
The word MAGIC may be used to identify the endianess of a module. Therefore the
above definition should always be used. Other definitions such as
#define MODULE_MAGIC’MHID’
or
#define MODULE_MAGIC *(unsigned *)"MHID"
should not be used as these may not correctly identify the endianness of the module.
When the Bootstrap Loader is booted it searches the ROM(s) for the
MODULE_MAGIC word. Each occurrence of the MODULE_MAGIC word is
identified as a module, provided that the module checksum succeeds.
flags
The following flags are currently defined:
#define UNPLUGGED_FLAG
0x0001
#define AUTOSTART_FLAG
0x0002
All other bits in this field should be set to zero. The UNPLUGGED_FLAG is used to
identify which modules have been unplugged ( removed from the list of modules).
Unplugged modules will be entered into the module list. However, none of their entries
will ever be called. The AUTOSTART_FLAG is used to identify a single module which
should be automatically booted on startup in the absence of a boot module. Usually,
only one module should have the AUTOSTART_FLAG set. In the case that more than
one module has the AUTOSTART_FLAG set the Bootstrap Loader will boot the last
such module found. This will be the last such module found in a ROM. However, in the
case of multiple ROMs the search order of the ROMs is undefined.
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major
minor
These fields identify the major and minor version numbers of the module header. These
may be used to allow future extension of the module header. The current version
number is:
#define MAJOR_VERSION
1
#define MINOR_VERSION
0
checksum
This field is used to validate the module. The checksum is calculated over the range
<real_base> to <real_limit>. The checksum value is set so that the checksum
over this range is equal to 0. The checksum is calculated as the End of Range (EOR) of
each word in the range <real_base> to <real_limit>. Note that the checksum is
included in the range <real_base> to <real_limit> so there is no need to perform
a final EOR of checksum to generate a zero result.
ro_base
ro_limit
rw_base
zi_base
zi_limit
self
These fields are used to identify the extents of the module ROM and RAM regions. The
fields should be set to the linked address of the regions. The following shows how these
fields might be defined in both assembler and C:
IMPORT|Image$$RO$$Base|
IMPORT|Image$$RO$$Limit|
IMPORT|Image$$RW$$Base|
IMPORT|Image$$ZI$$Base|
IMPORT|Image$$ZI$$Limit|
ModuleHeaderDCDMODULE_MAGIC
...
DCD|Image$$RO$$Base|
DCD|Image$$RO$$Limit|
DCD|Image$$RW$$Base|
DCD|Image$$ZI$$Base|
DCD|Image$$ZI$$Limit|
DCDModuleHeader
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Bootstrap Loader Setup and Use
...
extern ARMWord Image$$RO$$Base[];
extern ARMWord Image$$RO$$Limit[];
extern ARMWord Image$$RW$$Base[];
extern ARMWord Image$$ZI$$Base[];
extern ARMWord Image$$ZI$$Limit[];
ModuleHeader module_header = {
...
Image$$RO$$Base,
Image$$RO$$Limit,
Image$$RW$$Base,
Image$$ZI$$Base,
Image$$ZI$$Limit,
&module_header,
...
};
The actual base and limit of the module are calculated as follows (where
<module_address> is the address where the Bootstrap Loader located the
MODULE_MAGIC word):
<real_RO_base> = ro_base + (<module_address> - self)
<real_RO_limit> = ro_limit + (<module_address> - self)
+ (zi_base - rw_base)
The actual base and limit of the modules RAM regions(s) are calculated as follows
(where <static_base> is the static base address of the modules instantiation):
<real_RW_base> = <static_base>
<real_RW_limit> = <static_base> + (zi_limit - rw_base)
If a module is statically linked (it does not support PID (Position Independent Data) or
multiple instantiation) then <static_base> == rw_base. Otherwise <static_base> is
the static base address of the data for the current instantation which is held in R9.
The self entry is also used to calculate the real entry points of the modules various entry
points (start, init, final, service, title, help, cmdtbl, swi_handler) as follows.
<real_start>= start + (<module_address> - self)
<real_init>= init + (<module_address> - self)
<real_final> = final + (<module_address> - self)
<real_service> = service + (<module_address> - self)
<real_title>= title + (<module_address> - self)
<real_help> = help + (<module_address> - self)
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Bootstrap Loader Setup and Use
<real_cmdtbl>= cmdtbl + (<module_address> - self)
<real_swi_handler>= swi_handler + (<module_address> - self)
start
The start entry point is called to execute a module. A module does not have to have a
start entry. In this case the start entry should be 0. The start code is only ever called after
the module has been instantiated by a call to its init entry. A C language definition
of this entry point is as follows:
typedef void (*StartCode)(char *cmd);
Where on entry:
R0 = pointer to static data
R9 = ModuleHandle returned by init
init
The init entry point is called to instantiate a module. The value returned is used to
identify the module instantiation in subsequent calls to other entries. The value returned
is passed in R9 to other entry points. Usually the init entry will allocate memory for its
static data and initialise the static data. It will then return a pointer to its static data in
R0. The init entry may be 0 in which case the init entry is not called. A C language
definition of this entry point is as follows:
typedef struct ModuleInfo *ModuleHandle;
typedef ModuleHandle (*InitCode)(void);
Where on exit:
R0 = Pointer to static data.
R9 = ModuleHandle used in subsequent calls to other entry points.
final
The final entry point is called to finalize a module. The module should free any
resources allocated by it. Usually a module will free its static data which is pointed to
by R0 on entry. The final entry may be 0 in which case the final entry is not called. A
C code definition of this entry point is as follows:
typedef void (*FinalCode)(void);
Where on entry:
R9 = ModuleHandle return by init
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Bootstrap Loader Setup and Use
service
The service entry is called to alert a module of various conditions. The module may use
this to intercept certain conditions. For example, a debugger module might intercept a
GO or DOWNLOAD service call. To intercept a service call the module should return
a service continuation routine pointer in R0. This will then be called when the system
is unthreaded, just before it returns to the original caller. If the module does not want
to intercept the call it should return 0 in R0. If a module does not support any service
the value 0 should be used. The C code definitions for the service entry point as well as
a service continuation routine are shown below:
typedef void (*ServiceCont)(void);
typedef ServiceCont (*ServiceCode)(int service);
Where on entry:
R0 = Service number
R9 = ModuleHandle returned by init
And on exit:
R0 = Address of service continuation routine.
title
The title entry points to the title string for the module. This should be a 0 terminated
string of16 characters or less. A C code definition of this is:
typedef char *TitleString;
help
The help entry points to the help string for the module. A C code definition of this is:
typedef char *HelpString;
The actual help string should use the following format:
<Module Name>
V.VV (DD MMM YYYY) <Comment>
cmdtbl
The command table points to an array of command descriptions each having the format
shown below. The array is terminated by an entry with a command field of 0.
typedef struct CmdTable CmdTable;
typedef void (*CommandCode)(char *cmd);
struct CmdTable {
char
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*command;
© Copyright ARM Limited 1998. All rights reserved.
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ARM DDI 0091A
Bootstrap Loader Setup and Use
CommandCode
code;
unsigned
flags;
char
*syntax;
char
*help;
};
Given that the module may be relocatable the real address of the command, code, syntax
and help entries are calculated using the real address calculations shown below. The
cmdtbl field is optional and may be 0 if no commands are supported.
<real_command> = command + (<module_address> - self)
<real_code> = code + (<module_address> - self)
<real_syntax> = syntax + (<module_address> - self)
<real_help> = help + (<module_address> - self)
command
This points to the name of the command. The command name must be less than 16
characters for command tabulation in the help command to work correctly. The
command may be in any mixture of upper and lower case, though good taste should
prevail. The Command Line Interface (CLI) performs a case insensitive match on
commands.
code
This entry is called when a command matching the command field is entered. If the
command wishes to unthread the system, it should return the address of a continuation
routine in R0. This can be used, for example, by a debugger when a go command is
executed. The debugger will wish to unwind the Supervisor Control (mode) (SVC)
stack before continuing execution of the debugger. The debugger can do this by
returning the address of a continuation routine in R0. The C code definition of both the
continuation and command entry points are shown below:
typedef void (*CommandCont)(void);
typedef CommandCont (*CommandCode)(char *cmd);
Where on entry:
R0 = command tail
And on exit:
R0 = Address of continuation routine.
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Bootstrap Loader Setup and Use
flags
The flags field contains flags for the command. At the moment no flags are defined, so
all bits in this word should be zero.
syntax
This points to a string to give a syntax error message. The syntax message should be of
the form
Usage: <command> <arguments>
help:
This points to help on the command.
swi_base
The swi_base entry gives a SWI chunk base for the module. A chunk is 64 entries so
bits 0 through 5 should be zero in the swi_base. When a SWI occurs which is in a
modules swi_chunk range the swi_handler entry will be called. A value of 0 may be
used if no SWIs are supported.The C code definition of this entry is:
typedef unsigned SWIBase;
swi_handler
The swi_handler entry is called when a SWI is executed in the modules SWI chunk
range. If the handler wishes to intercept the SWI and not return to the caller it should
return the address of a continuation routine in R0. The system will then unwind the SVC
stack and call the continuation routine. A value of 0 may be used if no SWIs are
supported. The C code definition of both the continuation and command entry points
are shown below:
typedef void (*SWICont)(void);
typedef SWICont (*SWICode)(unsigned swino, SWIRegs *regs);
Where on entry:
R0 = The SWI number modulo 64
R1 = Pointer to register R0 through R12 on the stack. These registers may be modified
by the swi_handler.
And on exit:
R0 = Address of continuation routine
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ARM DDI 0091A
Bootstrap Loader Setup and Use
3.6.8
Downloading your module
Please refer to page 3-30 in order to download your application to FLASH.
3.6.9
download
Usage: download [<address>]
The download command downloads an image (for example an application) into
RAM. The image must be converted to uuencoded format before downloading. If no
address is specified the image is downloaded at the address 0x8000, otherwise it is
downloaded at the address specified.
To download an image you must take the following steps:
1.
Convert the image to uuencoded format using uuencode (uuencode is a standard
utility in UNIX). Please see 3.6.5Converting your application to uuencoded
format on page 3-17. For PCs, a copy may be obtained as part of the CYGWIN32
distribution from ftp://ftp.cygnus.com/pub/gnu-win32/gnu-win32/).
2.
Enter the download command at the Boot: prompt.
3.
Transmit the uuencoded file down the serial line using your terminal emulator’s
transmit file option. If you are using HyperTerminal on a PC you should use the
Send Text file option under the Transfer menu, and enter the name of the
uuencoded file you wish to download in the dialog box.
If you are using tip on a UNIX system, use the tip command < ~> > followed by the
name of the uuencoded file you wish to download. Note that you may need to press
<RETURN> before entering < ~> >.
If you are using HyperTerminal on a PC you should use the Send Text file option under
the Transfer menu, and enter the name of the uuencoded file you wish to download in
the dialog box. For example:
Boot: download
Ready to download. Use ’transmit’ option on terminal emulator to
download file.
<Use terminal emulator to download uuencoded filed>
Loaded file dhry at address 0x00008000, size = 0000d79c
The output you get will depend upon the terminal emulator you are using. If the
BootStrap loader detects any errors during downloading, it will print a message similar
to:
Error: 00000001 errors encountered during download.
ARM DDI 0091A
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Bootstrap Loader Setup and Use
If this occurs you should try downloading again. If you are using a higher baud rate
(57600 or 115200) you should ensure that you are using a high-quality cable which is
less than 1.8m (6 feet) long. If you are getting persistent errors you should try using a
lower baud rate.
Note
If after having entered download you want to exit the download function without
downloading an image you should type CTRL-D.
3.6.10
go
Usage: go [<program arguments>]
The go command starts, in user mode, the execution of a program previously
downloaded using the download command. The starting address of the program is set
to the address at which the program was downloaded. Arguments to the program may
be specified after the go command. For example, if you were to build and download
the following program
--- echo.c --#include <stdio.h>
int main(int argc, char **argv)
{
int i;
for (i = 0; i < argc; i++)
puts(argv[i]);
return 0;
}
and then run it with the command
Boot: go 1 2 3 4
you will get the following output:
1
2
3
4
Program terminated with return code 00000000
3-28
© Copyright ARM Limited 1998. All rights reserved.
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ARM DDI 0091A
Bootstrap Loader Setup and Use
For details on how to prepare programs for download you should refer to section 3.6.1
Preparing an application for downloading into SRAM. You should note that on entry to
a program using the go command, the stack pointer is not initialised. You should ensure
that you initialize the stack pointer early in your program initialization code, and
especially before you call any functions written in C. In the case of the program listed
above, it is linked with the C library that performed the initialization prior to calling the
C code.
3.6.11
gos
Usage: gos [<program arguments>]
The gos command is very similar to the go command except that it enters the program
in Supervisor (SVC) mode instead of in User mode. On entry the SVC stack pointer is
initialized to a small (about 1KB) stack.
3.6.12
pc
Usage: pc <address>
The pc command sets the value of the stored Program Counter (PC). This command is
used to set the address before doing a go or gos command. The go and gos commands
read the stored pc into the ARM pc register (r15). If executed without any argument the
pc command prints the current value of the stored pc.
3.6.13
flashwrite
Usage: flashwrite <address><source><length>
This writes the area of memory specified by source and length to the flash, starting at
the address specified by address. The address is the mapped address of the flash
memory on the board. To convert a flash offset to an address, add 0x4000000, which is
the base address of the flash in the board’s memory map.
Caution
Be very careful that you do not overwrite the BootStrap loader when writing the flash.
The BootStrap loader resides in the lower 16KB of the flash (from 0x4000000 to
0x4004000). You should never use the flashwrite command to write an address in
this range. If you do, you will be unable to recover control of the board.
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Bootstrap Loader Setup and Use
3.6.14
flashload
Usage: flashload <address>
Flashload performs a download command and then writes the result of the download
into flash at the specified address.
Caution
As with flashwrite do not attempt to load anything into the lower 16KB of flash
memory.
3.6.15
FlashErase
Usage: flashErase <address length>
FlashErase erases the section of flash specified by address and length by overwriting it
with 0xFF.
Caution
As with flashwrite and flashload do not attempt to erase flash in the lower 16KB
region of the flash.
3-30
© Copyright ARM Limited 1998. All rights reserved.
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ARM DDI 0091A
Chapter 4
Angel Debug Monitor Setup and Use
This chapter describes:
ARM DUI 0091A
•
the basic setup with the Angel Debug Monitor
•
setting up the armsd command line debugger to use the Angel Debug Monitor.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
4-1
Angel Debug Monitor Setup and Use
4.1
Overview
The Angel Debug Monitor is a program that is pre-written in the FLASH ROM of the
Evaluation Board as a Bootstrap Loader module. Angel allows the debug and control of
software running on the Evaluation Board.
When the Evaluation Board is powered on, the Bootstrap Loader eventually executes
the Angel Debug Monitor (unless this default behavior is changed). Angel re-initializes
the board and sets up a communication channel with a debugger on the host PC through
the serial port. It is this interaction between the host-based debugger and Angel that
allows software to be downloaded to the Evaluation board and debugged in place.
In order to control the downloaded software, Angel interacts with it and in some cases
actually modifies it—for instance, to set software breakpoints. For more detailed
information consult the documentation found onthe ARM website at
http://www.arm.com.
4-2
© Copyright ARM Limited 1998. All rights reserved.
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ARM DUI 0091A
Angel Debug Monitor Setup and Use
4.2
Basic setup with the Angel Debug Monitor
Host PC
.......
.......
Null modem cable
D1 D2 D3 D4
JP5
INTERRUPT
P1
SW1
LH77790A
J1
SW2
RESET
D5
Power adapter
(to mains power socket)
Figure 4-1 Angel Debug Monitor setup configuration
ARM DUI 0091A
1.
Connect the null modem cable to the evaluation board.
2.
Connect the other end of the cable to the host PC, making a note of the serial port
that is used. ADW will require this information later.
3.
Connect the power adapter to the power connector on the evaluation board.
4.
Connect the power adapter to the mains power socket. The red LED power
indicator D5 will light up.
5.
Press the reset button on the evaluation board. The four general purpose LEDs
should flicker and the green LED D1should remain on. This indicates the board
has been initialized and is working correctly.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
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Angel Debug Monitor Setup and Use
4.3
4.3.1
4.3.2
Setting up ARM Debugger for Windows for the Angel Debug Monitor
Installing software on the host PC
1.
Install the ARM Software Development Toolkit from the CD-ROM. Instructions
for this installation can be found on the CD-ROM packaging.
2.
If you wish to use the Angel C library you should use the ARM Debugger for
Windows (ADW) and the Angel module on the Evaluation Board to download
your image.
Configuring the ARM Debugger for Windows for the evaluation board
To configure the ARM Debugger for Windows (ADW) to use the correct serial port
when communicating with the evaluation board:
4-4
1.
Run the ADW by clicking on its icon in the Windows Start dialog. Do not run the
debugger through the ARM Project Manager.
2.
Select Options→Configure Debugger.... The Debugger Configuration dialog
box appears.
3.
Select the Target tab, and Remote_A as the target Environment.
4.
Select Configure.... The Angel Remote Configuration dialog box will appear.
© Copyright ARM Limited 1998. All rights reserved.
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ARM DUI 0091A
Angel Debug Monitor Setup and Use
Figure 4-2 The Debugger Configuration dialogue box
ARM DUI 0091A
5.
In the Angel Remote Configuration dialog box select Serial and the COM port
used to connect the Angel to the evaluation board.
6.
Select OK. The Debugger Configuration dialog box will appear.
7.
Select OK. The debugger is now restarted.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
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Angel Debug Monitor Setup and Use
4.3.3
Setting up armsd (Command line debugger) to use the Angel Debug Monitor
1.
2.
Follow the procedure in 4.2 Basic setup with the Angel Debug Monitor.
At the DOS command line type:
armsd -li -adp -port s=1 -linespeed 9600
where
4-6
-li
set the debugger to little endian mode
-adp
set the communication protocol to ARM Debug Protocol for
Angel.
-p s=1
set the serial port to COM1. Use COM2 if that is the port being
used.
-linespeed 9600
sets the Baud rate between the host and the Angel on the
Evaluation board to 9600 Baud.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Chapter 5
EmbeddedICE Setup and Use
This chapter describes setup with an EmbeddedICE unit.
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
5-1
EmbeddedICE Setup and Use
5.1
Overview
An EmbeddedICE unit is effectively a protocol converter. It communicates with the
host PC using the ARM Remote Debug Protocol over a serial cable in the same way as
the Angel Debug Monitor described in Chapter 4, Angel Debug Monitor Setup and Use.
The EmbeddedICE unit converts the ARM Remote Debug Protocol into an equivalent
JTAG type command stream, which it uses to communicate with the evaluation board.
This JTAG communication stream actually controls two components within the
microcontroller itself—the TAP Controller and the EmbeddedICE Macrocell.
The TAP Controller uses scan chains within the microcontroller to insert instructions
directly into the processor core and retrieve the contents of the internal bus. The inserted
instructions may be executed at slow debug speed or full speed. By inserting certain
instructions, the TAP Controller is able to retrieve or change the core or system state.
The EmbeddedICE Macrocell implements breakpoints and watchpoints at full speed.
The instruction or address data of interest is written to the EmbeddedICE Macrocell,
which compares this to the instructions and data the ARM core is issuing and receiving
on the internal bus. When a match is made, the EmbeddedICE Macrocell stops the
processor by putting it into debug mode.
This combination of the EmbeddedICE unit, the TAP Controller and EmbeddedICE
Macrocell provide all the capabilities of the Angel Debug Monitor with a primary
advantage of being unobtrusive. For instance, code in ROM can be debugged using
breakpoints when an EmbeddedICE is used.
For more detailed information about the available EmbeddedICE and compatible
products, visit the ARM web site at http://www.arm.com.
5-2
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
EmbeddedICE Setup and Use
5.2
Setup with an EmbeddedICE unit
EmbeddedICE
power supply
Host PC
EmbeddedICE unit
Serial cable
Optional parallel cable
Ribon cable
D1 D2 D3 D4
JP5
P1
SW1
INTERRUPT
LH77790A
J1
SW2
RESET
D5
Power adapter
(to mains power socket)
Figure 5-1 Angel Debug Monitor setup configuration
ARM DUI 0091A
1.
Connect the EmbeddedICE unit to the host PC using the serial cable.
2.
Connect the power supply to the EmbeddedICE unit.
3.
Connect the evaluation kit power adapter to the power connector on the
evaluation board.
4.
Connect the evaluation kit power adapter to a mains power socket. The red LED
on the board will light to indicate power.
5.
Press the reset button on the evaluation board. The four general-purpose LEDs
will flicker and the green LED will remain ON. This indicates that the board has
been initialized and is working correctly.
6.
Connect the ribbon cable provided with the EmbeddedICE unit to the JTAG
connector on the evaluation board. The other end of this ribbon cable should be
connected to the EmbeddedICE unit.
7.
Install the ARM Software Development Toolkit from the CD-ROM. The specific
instructions for this installation are found on the CD-ROM packaging.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
5-3
EmbeddedICE Setup and Use
5-4
8.
Configure the debugger on the host PC to use the EmbeddedICE unit. Consult the
documentation provided with the EmbeddedICE unit for details.
9.
Select View, then select Debugger internals, then change top-of-memory to
0x20000.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Chapter 6
Multi-ICE Setup and Use
This chapter describes setup with a Multi-ICE unit.
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
6-1
Multi-ICE Setup and Use
6.1
Overview
Multi-ICE is a system for debugging embedded processor cores via a JTAG interface.
It is made up of four elements:
•
Debug hardware within the ASIC—in the case of ARM processors, this is the
EmbeddedICE macrocell.
•
The Multi-ICE interface unit which connects to the JTAG port on the target system
and the parallel port on a host PC.
•
The Multi-ICE Server software running on the Host PC, which manages the
connection between the debug software tools and the Multi-ICE interface unit.
•
The Debug software tools, which communicate with the Server via the Multi-ICE
dll—in the case of ARM processors, this will be MDW (Multi-processor Debugger
for Windows).
The JTAG standard originally described daisy-chaining multiple devices on a PCB.
This concept has now been extended to multiple cores within a single package. If there
are more than one JTAG TAP Controller within your ASIC, then they should be serially
chained so that Multi-ICE can communicate with all of them.
Several configurations of multiple TAP controllers are possible:
6-2
•
The TAP controllers are serially chained within the ASIC. This is the natural
extension of the JTAG board level interconnection, and is the one recommended for
use with Multi-ICE. There is no increase in package pin count.
•
Each set of JTAG connections is pinned out separately. This gives greatest
flexibility on the PCB but at the cost of many pins on the device package. If this
method is chosen to simplify wafer-level testing, then the JTAG ports should be
serially chained on the PCB when it is desired to use Multi-ICE. The separate
JTAG ports could be tracked to separate headers on the PCB, but this then needs
one Multi-ICE Interface Unit per header and is unnecessary.
•
Multiplexing of data signals. It is possible to provide some means of gating TCK
or TMS signals so that only one TAP controller is active at once, and then to
multiplex their data outputs so that the JTAG debug interface sees a single device.
There is no standard definition of how to build or control such circuitry, and this
method is not supported by Multi-ICE.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Multi-ICE Setup and Use
6.2
Setup with a Multi-ICE unit
Host PC
Multi-ICE unit
Parallel cable
Ribon cable
Adaptor
D1 D2 D3 D4
JP5
P1
SW1
INTERRUPT
LH77790A
J1
SW2
RESET
D5
Power adapter
(to mains power socket)
Figure 6-1 Angel Debug Monitor setup configuration
ARM DUI 0091A
1.
Connect the Multi-ICE unit to the host PC using the serial cable.
2.
Connect the evaluation kit power adapter to the power connector on the
evaluation board.
3.
Connect the evaluation kit power adapter to a mains power socket. The red LED
on the board will light to indicate power.
4.
Press the reset button on the evaluation board. The four general-purpose LEDs
will flicker and the green LED will remain ON. This indicates that the board has
been initialized and is working correctly.
5.
Connect the ribbon cable provided with the Multi-ICE unit to the 20 to 14-pin
JTAG adaptor, and from there to the JTAG connector on the evaluation board.
The other end of this ribbon cable should be connected to the Multi-ICE unit.
6.
Install the ARM Software Development Toolkit from the CD-ROM. The specific
instructions for this installation arefound on the CD-ROM packaging.
7.
Install Multi-ICE on the host PC.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
6-3
Multi-ICE Setup and Use
6-4
8.
Configure the debugger on the host PC to use the Multi-ICE unit. Consult the
documentation provided with the Multi-ICE unit for details.
9.
Select View, then select Debugger internals, then change top-of-memory to
0x20000.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Appendix A
Evaluation Board Schematics
This chapter provides:
ARM DUI 0091A
•
the main evaluation board schematic
•
the evaluation board miscellaneous Schematic.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
A-1
© Copyright ARM Limited 1998. All rights reserved.
Open Access
0.1uF
C20
21
20
19
18
17
15
14
13
D9 2
D8 2
64K x 8
21
20
19
18
17
15
14
13
U3
NOE 2
NWAIT 2
D15 2
D4 2
D5 2
D6 2
D7 2
NWE 2
NCE1/NCAS1
NWE
NOE
0.1uF
C18
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
A
31
3
28
4
25
23
26
27
5
6
7
8
9
10
11
12
24
29
22
30
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
31
3
28
4
25
23
26
27
5
6
7
8
9
10
11
12
24
29
22
30
D14 2
D13 2
D12 2
D11 2
D10 2
OE
WE
CS1
CS2
D0
D1
D2
D3
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
WE
CS1
CS2
4
74AC02
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
CS2/UBL
SRAM(Upper 8 data bits)
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
CS2/LBL
2
3
U10B
74AC02
D2
A20
A22
A24
D0
A12
A14
A16
A18
A4
A6
A8
A10
2 D0
2 D1
2 D2
2 D3
XCLK_1
A0
A3
VCC
5
6
8
9
A0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
JP1
HEADER50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NBW
B
CE
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
AT29C020
22
31
24
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
U2
1000pF
C35
1000pF
C34
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
0.1uF
C8
0.1uF
C21
0.1uF
C7
0.1uF
C6
11
12
13
14
15
16
17
18
21
22
23
24
25
26
27
28
31
32
33
34
35
36
37
38
41
42
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
D0
D1
D2
D3
0.1uF
C22
D4
D5
D6
D7
5
6
7
8
A0
A1
A2
A3
3
R11
15
15
R10
8
14
1
XCLK_1
24 Mhz
OUT
OE5V_IN
VCC
C13
D2
D3
A20
A21
A22
A23
A24
A25
D0
D1
A12
A13
A14
A15
A16
A17
A18
A19
A4
A5
A6
A7
A8
A9
A10
A11
A0
A1
A2
A3
XCLK
0.1uF
1000pF
C33
JP4
HEADER50
VCC
VCC
0.1uF
C14
VCC
0.1uF
C11
VCC
0.1uF
C15
VCC
0.1uF
C10
VCC
1000pF
C32
VCC
HEADER50
JP2
0.1uF
C12
C9
0.1uF
PWM2
PWM1
PWM0
LCDCNTL
S
98
97
96
95
94
93
92
91
LH77790
Locate C2 as close
1000pF
D
LM293
as possible to
2
4
6
8
10
12
14
33
1
33
R14
MCLK
VCC
VCC
R13
UCLK
33
CTCLK
0.1uF
1
1
1000pF
C31
HEADER14
1
3
5
7
9
11
13
JP5
2
C5
0.1uF
C4
2
R12
2
NTXD1
Embedded ICE Connector
VCC
SW2
R15
4.7K
R16
33
1000pF
C30
INT0
NRXD1
3
2
1
22 uF
C37 +
13
14
10
17
8
20
VCC
1
OR-LED
D5
R8
1.0K
22 uF
C2 +
3
Date:
Size
C
Title
OUT
U7
LM2937
copper area thermally connected to package.
C2+
C2+
C2C2-
1
100pF
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
HEADER50
SW1
0.1uF
C1
Tact switch
1
4
Reset Switch
Wednesday, May 06, 1998
Document Number
EIO-0041B
ARMLAB-1 Eval Board
IN
R3
4.7K
VCC
PWM2
PWM0
S
CP1
NRXD0
INT4
INT2
INT0
CTOUT0
UCLK
NRXD2
NRXD1
PA2
PA0
CTOUT2
CTOUT1
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
E
E
R1
4.7K
C24
100pF
C26
JP3
12
15
16
11
19
4
18
5
VCC
NRESETI
R2in
C1+
C1VVV+
MAX233
R1in
R2out
T2out
T1out
U8
R1out
T1in
T2in
0.1uF
C23
LM2937 needs to have >=0.5 square inches of
Tact switch
1
4
VCC
Interrupt Switch (INT0)
C36
NRXD0
INT5
INT4
INT3
INT2
INT1
INT0
NRESETI
108
107
106
105
104
103
102
101
CP1
CP2
NTXD2
NRXD2
NTXD1
NRXD1
NTXD0
119
118
117
116
115
114
113
112
111
NRESETO
CTOUT0
CTGATE0
CTOUT2
CTGATE2
CTOUT1
CTGATE1
PA2
PA1
PA0
C3
VCC
VCC
VCC
0.1uF
128
127
126
125
124
123
122
121
VCC
PWM2
PWM1
PWM0
LCDCNTL
S
MCLK
CP1
CP2
NRXD0
INT5
INT4
INT3
INT2
INT1
INT0
NRESETI
NRESETO
CTOUT0
CTGATE0
UCLK
NTXD2
NRXD2
NTXD1
NRXD1
NTXD0
PA2
PA1
PA0
CTCLK
CTOUT2
CTGATE2
CTOUT1
CTGATE1
U1
PC0/NRTS1
PB3/NCTS1
TDI
TMS
TCK
TDO
D
2
C
VCC
C16
0.1uF
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
component
same pad footprint for this
VCC
13
14
15
17
18
19
20
21
VCC
VCC
VCC
VCC
1
U9
GR-LED
D1
R7
1.0K
PC1/NRTS0
PB7/NDSR0
PB5/NRI0
PB3/NCTS1
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
Use surface mount socket with
NCE0/NCAS0
NWE
NOE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
D3
A21
A23
A25
D1
A13
A15
A17
A19
A5
A7
A9
A11
A1
A2
possible to LH77790
Locate as close as
0.1uF
C17
R9
0.1
1
P
D15
D14
D13
D12
D11
D10
D9
D8
VCC
D7
D6
D5
D4
VCC
64K x 8
U4
SRAM(Lower 8 data bits)
74AC02
10
OR-LED
D2
PC7
R6
1.0K
PC6
52
51
50
49
48
47
2
1
NCE1/NCAS1
NWE
NOE
CS2/UBL1
U10A
CS2/LBL
U10C
GR-LED
AMB-LED
VCC
D4
D3
R5
1.0K
2
2 PB4/NCTS0
2 PB3/NCTS1
2 PB2/NRI1
2 PB1
2 PB0
2 PA7
2 PA6
2 PA5
2 PA4
2 PA3
2 PA2
2 PA1
2 PA0
2 NBB
2 TDI
2 TCK
2 NADBE
2 PB0
2 PC0/NRTS1
2 PC1/NRTS0
2 PC2/NDTR0
2 PC7
2 PC6
PC4
R4
1.0K
PC5
2
2
3
4
2
2
PB7/NDSR0
2 PC5
PB6/NDCD0
2
PB5/NRI0
2 PC4
2
D9
D8
D7
D6
D5
D4
2 1
GND
D4
D6
D8
2 PC3
TDI
TDO
BREQ
BGR
NBB
NADBE
XREQ
XACK
62
61
60
59
58
57
56
55
D10
D11
D12
D13
D14
D15
/RAS0
/RAS1
2 TMS
C
TDO
TDI
165
166
167
168
169
170
171
172
/RAS1
/RAS0
D15
D14
D13
D12
D11
D10
74
73
72
71
70
69
68
67
66
65
1
D5
D7
D9
PC3
PC4
PC5
PC6
PC7
TCK
TMS
NTRST
NWAIT
NBW
NOE
NWE
NCE5/NCAS5
NCE4/NCAS4
NCE3/NCAS3
NCE2/NCAS2
NCE1/NCAS1
NCE0/NCAS0
84
83
82
81
80
79
78
77
N
D11
D13
D15
/RAS1
B
XACK
NBB
TDI
XACK
NADBE
BGR
TDO
155
156
157
158
159
160
161
162
D0
D1
D2
D3
NADBE
NBB
BGR
PB1
PA7
PA5
PA3
PB3/NCTS1
PB4/NCTS0
PB5/NRI0
PB6/NDCD0
PB7/NDSR0
PC0/NRTS1
PC1/NRTS0
PC2/NDTR0
P
D10
D12
D14
/RAS0
2
145
146
147
148
149
150
151
152
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
D4
D5
D6
D7
D8
D9
TMS
PC7
PC5
PC3
XCLKDIS
TCK
PC6
PC4
XCLKDIS
TMS
TCK
PC7
PC6
PC5
PC4
PC3
1
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2/NRI1
NCE1/NCAS1
NCE3/NCAS3
NCE5/NCAS5
2
135
136
137
138
139
140
141
142
2
NOE
NWAIT
2
1
NCE0/NCAS0
NCE2/NCAS2
NCE4/NCAS4
NWE
NBW
2
VD1
VD3
VD5
VD7
1
100pF
C25
R2
4.7K
VCC
Sheet
connected to the
3
VCC
of
connector
2
2
CTGATE1
CTGATE2
2
Rev
B
PA2 2
CTCLK 2
UCLK 2
NRXD2 2
NRXD1 2
NRXD0 2
2
CTGATE0
INT5 2
INT4 2
INT3 2
INT2 2
INT1 2
holes of the DB9
PWM1
LCDCNTL
MCLK
CP2
J1
Jack
100pF
C29
GND
RI
DTR
CTS
TXD
RTS
RXD
DSR
DCD
SIGNALS
plated through
INT5
INT3
INT1
NRESETI
1
DB9
P1
100pF
C28
5
9
4
8
3
7
2
6
1
connector
holes of the DB9
plated through
connected to the
This GNDmust be
This GNDmust be
PA1
CTCLK
CTGATE2
CTGATE1
NRESETO
CTGATE0
NTXD2
NTXD1
NTXD0
100pF
C27
2
VD0
VD2
VD4
VD6
1
PC2/NDTR0
PC0/NRTS1
PB6/NDCD0
PB4/NCTS0
1
PB2/NRI1
PB0
PA6
PA4
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
PC2/NDTR0
PC1/NRTS0
PC0/NRTS1
PB7/NDSR0
PB6/NDCD0
PB5/NRI0
PB4/NCTS0
PB3/NCTS1
A-2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
11
NCE0/NCAS0
NCE1/NCAS1
NCE2/NCAS2
NCE3/NCAS3
NCE4/NCAS4
NCE5/NCAS5
NWE
NOE
NBW
NWAIT
1
PB2/NRI1
PB1
PB0
PA7
PA6
PA5
PA4
PA3
1
10
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
A
1
2
3
4
Evaluation Board Schematics
2
N
2
2
ARM DUI 0091A
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
1
2
3
4
1 PC7
1 PB1
1 PB2/NRI1
1 PB3/NCTS1
1 PB4/NCTS0
1 PB5/NRI0
1 PB6/NDCD0
1 PB7/NDSR0
1 PA0
1 PA1
1 PA2
1 PA3
1 PA4
1 PA5
1 PA6
1 PA7
1 TDI
1 TMS
1 TCK
1 NADBE
1 PB0
1 PC0/NRTS1
1 PC1/NRTS0
1 PC2/NDTR0
1 PC3
1 PC4
1 PC5
1 PC6
A
PB1
PB2/NRI1
PB3/NCTS1
PB4/NCTS0
PB5/NRI0
PB6/NDCD0
PB7/NDSR0
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
right onboard
Place near the top
TDI
TMS
TCK
NADBE
PB0
PC0/NRTS1
PC1/NRTS0
PC2/NDTR0
PC3
PC4
PC5
PC6
PC7
left onboard
Place near the top
A
RP4O
15
RP4N
14
RP4M
13
RP4L
12
RP4K
11
RP4J
10
RP4I
9
RP4H
8
RP4G
7
RP4F
6
RP4E
5
RP4D
4
RP4C
3
RP4B
2
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
47K
RP3O
15
RP4A
1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
RP3N
14
RP3M
13
RP3L
12
RP3K
11
RP3J
10
RP3I
9
RP3H
8
RP3G
7
RP3F
6
RP3E
5
RP3D
4
RP3C
3
RP3B
2
RP3A
1
1 NRXD0
1 NRXD1
1 NRXD2
1 UCLK
1 CTCLK
B
1 D15
1 NWE
1 NOE
1 NWAIT
NRXD0
NRXD1
NRXD2
UCLK
CTCLK
NWE
NOE
NWAIT
right on board
Place near the bottom
B
RP2O
15
RP2N
14
RP2M
13
RP2L
12
RP2K
11
RP2J
10
RP2I
9
RP2H
8
RP2G
7
RP2F
6
RP2E
5
RP2D
4
RP2C
3
RP2B
2
RP2A
1
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
C
C
1 D8
1 D9
1 D10
1 D11
1 D12
1 D13
1 D14
1 D7
1 D6
1 D5
1 D4
1 D0
1 D1
1 D2
1 D3
D8
D9
D10
D11
D12
D13
D14
D7
D6
D5
D4
D0
D1
D2
D3
left on board
Place near the bottom
RP5O
15
RP5N
14
RP5M
13
RP5L
12
RP5K
11
RP5J
10
RP5I
9
RP5H
8
RP5G
7
RP5F
6
RP5E
5
RP5D
4
RP5C
3
RP5B
2
RP5A
1
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
D
D
1 NBB
1 INT1
1 INT2
1 INT3
1 INT4
1 INT5
1 CTGATE0
1 CTGATE1
1 CTGATE2
NBB
INT1
INT2
INT3
INT4
INT5
CTGATE0
CTGATE1
CTGATE2
Date:
Size
C
Title
RP1O
15
RP1N
14
RP1M
13
RP1L
12
RP1K
11
RP1J
10
RP1I
9
RP1H
8
RP1G
7
RP1F
6
RP1E
5
RP1D
4
RP1C
3
RP1B
2
RP1A
1
Place near the top right
on board
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
Tuesday, April 21, 1998
Document Number
EIO-0041B
ARMLAB-1 Eval Board
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
E
E
Sheet
2
of
2
Rev
B
1
2
3
4
Evaluation Board Schematics
A-3
Evaluation Board Schematics
A-4
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Appendix B
Evaluation Board Layout
This chapter provides:
ARM DUI 0091A
•
the top routing layer and silk screen
•
the bottom routing layer.
© Copyright ARM Limited 1998. All rights reserved.
Open Access
B-1
Evaluation Board Layout
B-2
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Evaluation Board Layout
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
B-3
Evaluation Board Layout
B-4
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
Glossary
ARM Evaluation Board User Guide
ARM DUI 0091A
© Copyright ARM Limited 1998. All rights reserved.
Open Access
Glossary-1
Abbreviations
The following abbreviations are used in this document:
BB
BW
C
CAS
CE
CH
CLI
CP
CS
CTCLK
CTGATE
CTOUT
CTS
D
DCD
DRAM
DSR
DTR
EEPROM
EmbeddedICE
EMC
EOF
EOR
ESD
FCC
ICE
GND
GNU
INT
I/O
IrDA/DASK
JTAG
LCDCNT
MCLK
n
nBW
NC
Glossary-2
byte boot
byte wide access
the programing language C
column address select
chip enable
channel
command line interface
shift/pixel clock
chip select
counter/timer external clock input signal
counter/timer control gate
counter/timer output
clear to send
external data bus
data carrier detect
dynamic random access memory
data send ready
data transmit ready
electronically erasable programmable read-only memory
This is a debugging system used to provide many functions of an ICE.
electromagnetic compatability
end of file
end of range
electro-static discharge
Federal Communications Commission
in-circuit emulator
ground
GNU’s not UNIX
interrupt
input/output
infra-red data association/digital amplitude key shifting
joint test action group
lcd control signal
ac modulation signal
not (inverted, which means active low)
byte wide (active low)
no connect
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A
nCE
nCS
nICERST
nOE
nTRST
nWAIT
P
PC
PID
PTH
PWM
RAM
RAS
RESETI
RESETO
RI
ROM
RTS
RxD
SDT
SPU
SRAM
SVC
SWI
TAP
TCK
TDI
TDO
TMS
TQFP
TxD
UART
UCLK
VCC
VD
VDD
VSS
WE
XCLK
ARM DUI 0091A
chip enable (active low)
chip select (active low)
ICE reset (for tablet unit, active low)
output enable (active low)
test system (JTAG) reset (active low)
wait state enable (active low)
port
program counter
position independent data
plated through hole
pulse width modulation
random access memory
row address select
reset input
reset output
ringing indicator
read only memory
ready to send
receive data
software development toolkit
safe power up
static random access memory
supervisor control (mode)
software interrupt
test access port
test clock
JTAG test embeddedICE data input
JTAG test embeddedICE data output
JTAG test embeddedICE mode select
thin quad flat pack
transmit data
universal asynchronous receiver/transmitter
UART/DASK clock
voltage at collect
video data
voltage at drain
voltage at substrate (0V, GND)
write enable
external clock
© Copyright ARM Limited 1998. All rights reserved.
Open Access
Glossary-3
Glossary-4
© Copyright ARM Limited 1998. All rights reserved.
Open Access
ARM DUI 0091A