Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Evaluation of different CMOS processes using a
circuit optimization tool.
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Anders Johansson
LiTH-ISY-EX-ET--09/0365--SE
Linköping 2009
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköpings tekniska högskola
Linköpings universitet
581 83 Linköping
Evaluation of different CMOS processes using a
circuit optimization tool.
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Anders Johansson
LiTH-ISY-EX-ET--09/0365--SE
Handledare:
J Jacob Wikner
Examinator:
J Jacob Wikner
Linköping, 22 December, 2009
Avdelning, Institution
Division, Department
Datum
Date
ISY
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Språk
Language
Rapporttyp
Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN
Engelska/English
Examensarbete
C-uppsats
D-uppsats
Övrig rapport
2009-12-22
—
LiTH-ISY-EX-ET--09/0365--SE
Serietitel och serienummer ISSN
Title of series, numbering
—
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52338
Titel
Title
Utvärdering av olika CMOS-processer genom användning av ett kretsoptimeringsverktyg.
Evaluation of different CMOS processes using a circuit optimization tool.
Författare Anders Johansson
Author
Sammanfattning
Abstract
The geometry of CMOS processes has decreased in a steady pace over the years
at the same time as the complexity has increased. Even if there are more
requirements on the designer today, the main goal is still the same: to minimize
the occupied area and power dissipation. This thesis investigates if a prediction
of the costs in future CMOS processes can be made. By implementing several
processes on a test circuit we can see a pattern in area and power dissipation
when we change to smaller processes.
This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the
performance measures and costs. The optimization results from the area and
power dissipation is used to present a diagram that shows the decreasing costs
with smaller processes and also a prediction of how small the costs will be for
future processes. This thesis also presents different optimization tools and a
design hexagon that can be used when we struggle with optimization trade-offs.
Nyckelord
Keywords
CMOS process, Scaling, Operational transcoductance amplifier, Optimization tool
Abstract
The geometry of CMOS processes has decreased in a steady pace over the years
at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the
occupied area and power dissipation. This thesis investigates if a prediction of the
costs in future CMOS processes can be made. By implementing several processes
on a test circuit we can see a pattern in area and power dissipation when we change
to smaller processes.
This is done by optimizing a two-stage operational transconductance amplifier
on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller
processes and also a prediction of how small the costs will be for future processes.
This thesis also presents different optimization tools and a design hexagon that
can be used when we struggle with optimization trade-offs.
v
Acknowledgments
I would like to thank my supervisor Jacob Wikner for his support, engagement
and quick mail-responses. I also like to thank AnSyn AB for their part of this
project, particularly Robert Hägglund for his help. Further I thank my family and
my girlfriend who always supports me whether I am happy or grumpy. Finally I
would like to thank my former teacher Olle Berglund who has been a big influence
and laid the foundation for my studies at Linköping University. Thank you.
vii
Contents
1 Introduction
1.1 BACKGROUND . . . . . . . . . . . . .
1.2 OBJECTIVE & DESCRIPTION . . . .
1.2.1 Overview . . . . . . . . . . . . .
1.2.2 Delimits . . . . . . . . . . . . . .
1.2.3 The problem on a technical level
1.3 ABBREVIATIONS . . . . . . . . . . . .
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2 Before you start
2.1 ELECTRONIC DESIGN AUTOMATION
(EDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 OPTIMIZATION TOOLS . . . . . . . . . . . . . . . . . .
2.3 THE OPERATIONAL AMPLIFIER (OP) . . . . . . . . .
2.3.1 Operational amplifiers in general . . . . . . . . . .
2.3.2 Two-stage operational transconductance amplifier
(OTA) . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 THEORY . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Parameters, general & small-signal . . . . . . . . .
2.4.2 Understanding the design hexagon . . . . . . . . .
2.4.3 The cost-function . . . . . . . . . . . . . . . . . . .
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3 Sizing by hand
3.1 INITIAL STEPS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 BUILDING A TESTBENCH . . . . . . . . . . . . . . . . . . . . .
3.3 SIZING WITH SOME RULES-OF-THUMB . . . . . . . . . . . . .
17
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4 The Optimization Tools
4.1 CADENCE TOOL . . . . . . . . . . . . .
4.1.1 Introduction to Cadence tool . . .
4.1.2 Problems with Cadence tool . . . .
4.2 ASCO TOOL . . . . . . . . . . . . . . . .
4.2.1 Introduction to ASCO tool . . . .
4.2.2 Problems with ASCO tool . . . . .
4.3 ANALOG DIMENSIONS TOOL . . . . .
4.3.1 Introduction to Analog Dimensions
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ix
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x
Contents
4.3.2
Problems with Analog Dimensions tool
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7 Results
7.1 DISCUSSION & FUTURE WORK . . . . . . . . . . . . . . . . . .
39
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References & Sources
41
A The specification
A.1 COMMENTS TO THE SPECIFICATION . . . . . . . . . . . . . .
43
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B The Schematic
45
C The Testbench
47
5 Optimization
5.1 OPTIMIZING IN CADENCE . . . . . . .
5.1.1 Getting the amplifier within target
5.1.2 Comments to the specification . .
5.1.3 Performance measures . . . . . . .
5.1.4 Optimization of each parameter . .
5.1.5 Problems and difficulties . . . . . .
5.2 OPTIMIZATION IN ANALOG
DIMENSIONS . . . . . . . . . . . . . . .
6 Runs
6.1 INITIAL SETUP . . . . . .
6.2 "PROCESS ONE", 350nm .
6.3 "PROCESS TWO", 180nm
6.4 "PROCESS THREE", 90nm
6.5 "PROCESS FOUR", 65nm .
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Chapter 1
Introduction
1.1
BACKGROUND
It all started in the summer of 2009 with an e-mail conversation with Dr. Emil
Hjalmarsson, CEO (see Abbreviations on page 6) at AnSyn AB, about a final
year-project at their company. When fall came the outline for the project had
been settled; the project was to be held at Linköping University with a software
tool, called Analog Dimensions, from AnSyn AB.
Analog Dimensions is an optimization-based analog design automation tool developed by two former Ph.D. students at Linköping University. It started as a
research project at the department of Electronic Systems in the year 2000. Since
2006, the software is developed by AnSyn AB. Analog Dimensions is made for
designing industrial circuits in modern CMOS technologies below 90 nm[1].
The development of electronic devices has gone fast over the years and today
we face other problems with speed, size and design complexity than we did in the
past. Today, shrinking geometries of CMOS processes, increase of complexity and
need for second-stage foundries force the IC integrators to always be prepared to
switch from one foundry process to another, or switch process nodes within the
same foundry. A process node refers to the particular method used to make silicon
chips. These processes have decreased over the years and the 45 nm process were
presented in 2008. Around the turn of the year a 32 nm process is planned to
be released[2]. Since it is vital that the risks and costs are held at a minimum,
the requirements of the manufacturer and designer has increased. They have to
understand how the area, performance and power consumption of the processes
will effect the characteristics, and more importantly: the costs of the process that
in the prolongation means the success of the project.
There are some rules-of-thumb that can be applied on these processes in order
to make your decision easier, but they are not accurate enough. Since these three
parameters are dependent on each other the cost-function will therefor be rather
1
2
Introduction
complex. Other problems you have to solve are, for instance, if it is worth to
increase the area to meet the requirements of the performance or the power consumption. When your constant goal is "faster, smaller, cooler", you always have
to make some sacrifices.
1.2
1.2.1
OBJECTIVE & DESCRIPTION
Overview
The purpose of the project is to, on the basis of a two-stage operational amplifier,
investigate several CMOS processes by implementing the circuit in them. The circuit specifications will be met by using an optimization tool where the main goal
is to minimize the occupied area and power dissipation. Hopefully a prediction of
area and power dissipation for future technologies can be shown.
At first the circuit will be sized by hand in an EDA, Electronic Design Automation, software and later on we will use the optimization tool.
There are several softwares to choose from and some of these will be presented
in chapter two.
Besides minimizing the area and power, the deliverable is to create a graph that
shows the resulting parameters as functions of the process (see Figure 1.1.). Further, a statistical analysis should be performed and hopefully a more accurate
prediction of area and power as function of process node geometry will be concluded, compared with the predictions the rules-of-thumb gives you.
1.2 OBJECTIVE & DESCRIPTION
3
Figure 1.1. A desired result graph with a question mark for the performance of future
processes
1.2.2
Delimits
One delimit is that the layout parasitics will not be considered. Although the
layout is indeed a limiting factor on achievable performance we will not consider
it due to the quantity of manual work that has to be done. Also we will only
have one corner to take in concern. The limited time of this 10-week project also
prevents us from developing it any deeper than this, even if there is a possibility
to improve the results with more time given. From the beginning it was planned
to test ten different processes but due to the time running out we cut down to
four, and these four were only optimized in open-loop configuration.
4
1.2.3
Introduction
The problem on a technical level
Whenever we talk about optimization in analog CMOS design it is always one
word that comes to your mind: trade-offs. You will always have trade-offs to
struggle with no matter how much knowledge you have or how good an optimization tool you have access to. Since each parameter in a specification has its own
ideal desire on how the parameters should be set, one quickly realizes that when
you have somewhat 15 parameters to take in concern (the ones from specification),
the complexity increases rapidly. Now the trade-offs become obvious and the questions starts to hail: do we want a fast system or a very linear one, do we prefer
high gain or large bandwidth, et cetera. This contributes that you have enough
knowledge to know in what direction you are going with the system. There is no
ideal solution and you have to weight the trade-offs. This weighting must in some
cases even be decided by the sales department rather than by the designers.
Figure 1.2. The Design Hexagon where the arrows represent the trade-offs between
parameters.
1.2 OBJECTIVE & DESCRIPTION
5
Figure 1.2. shows a design hexagon that tells us how the parameters affect each
other that can be a good helper. With parameters in each corner and trade-off
arrows represented as the sides the hexagon shows us very clear, yet simple, what
parameters there is trade-offs between. Remember this is just a simplification and
in the reality it is even more complex.
PM is the phase margin, GBP is the gain-bandwidth product, SR is the slewrate and PSRR is the power supply rejection ratio.
In this project we will take a look at, and struggle with, these problems. Since the
specification includes values on all the parameters we know what targets we have
and do not have to think that much about what characterization we want for our
system; the trade-off problems will be more than enough.
6
1.3
Introduction
ABBREVIATIONS
Notation
A
A0
ADE
CC
CL
CAD
CEO
CMOS
dB
EDA
GBW
gds
gm
GRRL
GRRH
HD3
IC
ICMR
IR
MOS
NMOS
OP AMP
OR
OTA
P
PM
PMOS
PSRRL
PSRRH
PSS
ROUT
SR
THD
VN
Description
Area
Open-loop gain
Analog design environment
Compensating capacitance
Load capacitance
Computer-aided design
Chief engineering officer
Complementary metal-oxide semiconductor
Decibels
Electronic design automation
Gain-bandwidth product
Drain-source conductance
Transconductance
Ground rejection ratio
Ground rejection ratio
Third harmonic distortion
Integrated circuit
Input common-mode range
Input range
Metal-oxide semiconductor
Negative metal-oxide semiconductor
Operational amplifier
Output range
Operational transconductance amplifier
Power dissipation
Phase margin
Positive metal-oxide semiconductor
Supply rejection ratio
Supply rejection ratio
Periodic steady state
Output resistance
Slew rate
Linearity (Total harmonic distortion)
Output referred noise
Table 1.1. Abbreviations used in this thesis
Chapter 2
Before you start
2.1
ELECTRONIC DESIGN AUTOMATION
(EDA)
Electronic design automation, EDA, is the category of tools for designing and
producing electronic systems ranging from printed circuit boards to integrated
circuits. This is also referred to as circuit-aided design (CAD) programs. The
growth of EDA programs has rapidly increased in recent years due to the continuous scaling in semiconductor technology. Some of the significant EDA companies
are Synopsys, Cadence Design Systems, Mentor Graphics and Tanner EDA. The
first two were founded in the mid 1980s where Cadence is specialized in physical
IC design and Synopsys in logic synthesis. Both have grown to be the two largest
full-line suppliers of EDA tools[3].
Cadence Design Systems is de-facto the most commonly used EDA software and
it will also be used in this project since it is used at Linköping University by students in Electronic engineering for laboratory work and projects. Cadence was
established in 1988, their main corporate product is software used to design chips
and printed circuit boards. The most common member of their product family is
the Virtuoso Platform. It is a powerful tool for designing full-custom ICs. It includes schematic entry, behavioral modeling, circuit simulation, layout, extraction
et cetera. It is used for analog, mixed-signal and standard-cell design[4, 5].
2.2
OPTIMIZATION TOOLS
The biggest part of this project is to optimize the circuit and for that a powerful
optimization tool will be used. In general the goal for these tools are to minimize
a given cost-function by finding suiting values for the chosen parameters. In our
case the cost-functions two biggest rascals are area and power consumption. Some
of the different tools are the built in Cadence optimizer, ASCO (A Spice Circuit
Optimizer), munEDA and Analog Dimensions where the latter will constitute as
7
8
Before you start
the main optimizer in this project. All these, except munEDA, have been tried
and the opinions about them can be read in chapter four.
2.3
2.3.1
THE OPERATIONAL AMPLIFIER (OP)
Operational amplifiers in general
An operational amplifier is a DC-coupled, high-gain electronic voltage amplifier
with differential inputs and, usually, a single output. Typically, the outputs of the
operational amplifiers are controlled by some sort of feedback, either negative or
positive. High input impedance and output voltage are other typical characteristics.
Operational amplifiers are very common in electronic devices of today and the
standard op amps are very cheap to manufacture. They are most common as
integrated circuits but can also come in the form of macroscopic components[6].
2.3.2
Two-stage operational transconductance amplifier
(OTA)
Our circuit is a type of amplifier called operational transconductance amplifier.
The OTA has some characteristics that contrasts the one of the OP: the output is
of a current and it is constructed only of transistors and diodes i.e. no resistors or
capacitances. Since we do not want to reconsider our architecture as we proceed
towards lower supply voltages in smaller process nodes, this two-stage OTA with
an NMOS input differential pair and Miller-compensation is used because it is
suitable for low-voltage applications. A Miller-compensation is a capacitor (in this
case represented by a transistor) that will make sure that the system is stable in
feedback configurations. It is siutable for low-voltage applications because it only
has three transistors on top of each other and that provides us with an adequate
headroom. Other characteristics of the two-stage OTA is high voltage-gain, high
output impedance and high input impedance.
2.4 THEORY
2.4
2.4.1
9
THEORY
Parameters, general & small-signal
In the Appendix we have a component specification where all the parameters are
listed. Before we go any further some theory and important relationships describing the operational amplifier performance will be presented[7, 8].
Open-loop Gain, A0 ,
A0 =
Vout
Vin
A0 = 20log
Vout
Vin
(2.1)
(dB)
(2.2)
A0 is a measure of the ability of an amplifier to increase the amplitude of a signal.
An ideal open-loop OTA has infinite gain.
The small-signal expression for open-loop gain, A0 , is:
A0 =
-gm1
gds1 + gds3
(2.3)
where gm1 is the transconductance for transistor M1, gds1 and gds3 are the drainsource conductance for transistors M1 and M3 respectively.
Gain-bandwidth product, GBW,
GBW = A0 · BW
(2.4)
GBW is, as the name says, the product of the gain and the -3-dB bandwidth and
allows circuit designers to determine the maximum gain for a given frequency, and
vice versa.
The small-signal expression for gain-bandwidth product, GBW, is:
GBW =
gm1
CC
(2.5)
where gm1 is the transconductance for transistor M1 and CC is the Miller-compensation
capacitance represented by M10 in the circuit in Figure 3.2.
Input common-mode range, ICMR,
ICMR = [Vin,min ; Vin,max ]
(2.6)
ICMR is an interval from the minimum input voltage to the maximum input voltage. The minimum is determined by finding the path from ground to the input
node which gives us the maximum number of transistors (a maximum number of
transistors results in a minimum voltage since it is harder to take a path with
many transistors. Make sure that the negative coefficients is subtracted rather
10
Before you start
than added to the contribution), the maximum voltage is determined by finding
the path from vdd to the input node which gives us the minimum number of transistors.
Slew-rate, SR,
SR = max
dvout
dt
(2.7)
The "small-signal" expression for slew-rate, SR, is:
I5
CC
(2.8)
I7
CC + CL
(2.9)
SR =
or
SR =
where I5 and I7 is the drain current for M5 and M7 respectively, CC is the Millercompensation capacitance (M10) and CL is the load capacitance on 75 fF.
SR is basically a measure of how fast the system is; the quicker the output responds to the input, the faster a system we have. This is easiest measured by
letting the input signal be a square pulse and then measure the responding output
slope. Often you just measure it from 10% to 90% due to overshots and such.
Output range, OR,
OR = [Vout,min ; Vout,max ]
(2.10)
OR is basically the same as ICMR except that you find a path to the output
node instead.
2.4 THEORY
11
Power supply rejection ratio, PSRR,
PSRR = 20log
Adiff
AVdd→Vout
(dB)
(2.11)
PSRR is the ratio between amplification for differential input signals and the amplification for variations in supply from Vdd to Vout. It is often given at various
frequencies or, as in this case, frequency intervals. You can say it is basically a
measure used to describe the amount of noise from a power supply that the OTA
can reject.
The small-signal expression for power supply rejection ratio, PSRR, is:


sCII
sCc
+
1
+
1
gm6
gm1 gm6

 gm1
PSRR =
sgm6 Cc
(gds1 + gds2 )gds6
+1
(2.12)
(gds1 +gds2 )gds6
where the gm -terms are the transconductances and the gds -terms are the drainsource conductances for the corresponding transistors. CII is a parasitic capacitance.
Ground rejection ratio, GRR,
GRR = 20log
Adiff
(dB)
Agnd→Vout
(2.13)
GRR is the same as PSRR except that you measure the amplification for variations in ground from ground to Vout. It is a measure used to describe the amount
of noise from ground that a particular device can reject.
The small-signal expression for ground rejection ratio, GRR, is:


s(Cc CI +CI CII +Cc CII )
sCc
+
1
+
1
gm6 CC
gm1 gm6

 gm1
GRR =
s(CC +CI )
(gds1 + gds2 )gds7
+1
(2.14)
(gds1 +gds3 )
where the gm -terms are the transconductances and the gds -terms are the drainsource conductances for the corresponding transistors. CI and CII are parasitic
capacitances.
Output resistance
Rout
(2.15)
Rout can be referred to as the output resistance, output impedance or sometimes
the internal resistance.
12
Before you start
Output referred noise, VN,
1
2π
Z∞
2
|N(jω)|2 dω = V2noise = E v2noise (t) = σnoise
(2.16)
−∞
Above is the noise power we measure, or: the integral of the square-voltage is
equal to sigma-squared of the noise. Sigma only covers about 70% of the normal
distribution so that is why we multiply it with a factor 3 (see specification on page
29), then it covers about 99%.
Single-side spectral density for thermal noise:
I2d (f) = 4kTγgm
where
2
3
(2.17)
< γ < 2.
Single-side spectral density for flicker noise:
V2g (f) =
K
WLCox f
(2.18)
Noise in CMOS circuits is inherent noise, there are three different types of inherent noise: thermal noise, flicker noise and shot noise. Thermal noise is the
same as white noise and occur due to random thermal motion of the electrons and
is dependent of the DC current flowing in the components.
Flicker noise is associated with carrier traps in semiconductors, which normally
gives the DC-current. The traps hold the carriers for some while and then release
them. (DC-current does not float smooth.)
Shot noise is associated with the DC-current flow across a pn-junction.
Load capacitance
CL
(2.19)
CL is simply a load capacitor used for on-chip use only, that is why it is so small.
If we want we can replace it by dominant-pole compensation but this will hurt the
area.
2.4 THEORY
13
Phase margin, PM,
PM = 90 - arctan
f0dB
f2
(2.20)
where f0dB and f2 are the unity gain frequency and the frequency for where the
second pole is placed respectively. We want the second pole to be placed at a
higher frequency
than the unity gain frequency. If the pole is at a lower frequency,
f0dB
arctan f2 ≤ 45 degrees and if the poles is at a higher frequency arctan f0dB
f2
will be ≥ 45 degrees. If the phase margin decreases below specifications, the system risks to be unstable.
The small-signal expression for phase margin, PM, is:
!
g
m1
PM = 90 - arctan
CC
−gm6
CL
(2.21)
where the gm -terms are the transconductances for M1 and M6, CC and CL are the
Miller-compensation capacitor (M10) and the load capacitor (75 fF) .
Linearity
HD3 = 20log10
harmonic1
harmonic3
(dB)
(2.22)
Linearity is also a measure of how well the output signal follows the input signal. You can check the linearity, for instance by see if the output compresses or
decompresses at the peak of the signal. The system is very sensitive to clipping
and that is why this compression occur.
14
Before you start
Figure 2.1. The Design Hexagon where the arrows represent the trade-offs between
parameters
2.4.2
Understanding the design hexagon
Now that we have seen some theory, and particularly the small-signal parameters,
we can take a look at the design hexagon again and see that the trade-offs mentioned includes either gm1 , CC or both. This means that the parameters are very
dependent on how we size the differential gain-stage and the Miller-compensation
(the Miller-compensation is represented by CC in the small-signal expressions). So
by looking at our small-signal parameters will help us to better understand why
these trade-offs occur.
2.4.3
The cost-function
Theory about the parameters alone is not enough. Another part of this project
that require some theory is the cost-function. We will set up a lot of targets in our
optimization tool and even if we do not exactly see how the cost-function works,
it can be good with some theory that helps us understand the optimization. Remember this is just one of many approaches of the cost-functions.
When a performance measure is set to be optimized in some way the tool uses
2.4 THEORY
15
a cost-function[9] to try to attain the goal. This is because we want to see how
much it will cost us to have a parameter out of target. Is it better to increase
the area or power to get everything within specification or is it better to take the
penalty for the parameter out of specification and keep the small area or power?
Those questions will hopefully be easier to answer with a cost-function that helps
us understand. The cost-function is based on mathematical formulas that, if everything goes as preferred, will approach zero. A simplified equation often used
is
r(x) = rC (x) + rP (x) + rT (x)
(2.23)
where r(x) is the total cost, rC (x) is the penalty cost if the design fails to satisfy basic requirements, rP (x) is the penalty cost if the design of the circuit is not
robust enough and rT (x) defines the trade-offs between the circuits characteristics.
rC (x) is defined as
F(y) =
N
X
f[(yi − Bi )/Ai ] + f[(bi − yi )/Ai ]
(2.24)
i=1
where Ai is the steepness of the penalty function for i-th design requirement, Bi
and bi is the design parameters.
rP (x) is defined as
rP (x) =
KH
X
F[D(x, qi )]
(2.25)
i=1
where Di is an interval function and rT (x) is defined as
rT (x) = C
N
X
i=1
f{[Bi − Di (x, qnom )]/Ti } + C
N
X
f{[Di (x, qnom ) − bi ]/Ti }
(2.26)
i=1
where C is a small constant that makes this function less influential on the total
cost-function, compared to rC (x) and rP (x).
We can see rT (x) as a trade-off plane where the performance constrains, defined
by rP (x), constitutes as the surrounding walls. Then the trade-off coefficients Ti
represents the angles between the trade-off plane and the coordinate axes.
If we apply this on one of our performance measures it would work something
like this. The transistors have a target on them to be saturated. This is fulfilled if
Vgs − Vth > 0, Vds − Vdsat > 0
(2.27)
Then the rC (x) will be zero because the target is met. Although, we want the
transistors to have a safety margin of 1 mV and if
0 < Vgs − Vth < 1mV, 0 < Vds − Vdsat < 1mV
(2.28)
16
Before you start
it still has satisfied the basic requirements but it is not robust enough, then it
will be penalized with a cost determined by rP (x). If the transistor has a great
negative influence on some other parameter, it will get a trade-off cost determined
by rT (x). Remember that
rC (x) rP (x) rT (x)
(2.29)
so the cost will be less hurtful if we fulfill the basic requirements.
If the simulation fails to converge, the optimization cannot determine the costfunction value for a combination of circuit parameters, so we have to make sure
that the simulation converges as it should. Although in some cases the simulator still manages to simulate the circuit even with false convergence we will have
performance measures that is far from the required and that renders in a big cost
that we want to avoid.
Chapter 3
Sizing by hand
3.1
INITIAL STEPS
When you start up a project of this size without the amount of knowledge or
experience needed it is vital that you get a good overview of the task. To size
and measure a circuit properly we need to understand how an ideal operational
amplifier works and how different errors and external signals affect the behavior
of the circuit. Issues like noise, nonlinearity, wrong operational region, et cetera,
will always be a problem for a designer and therefor we need to have the right
knowledge, especially when there are about 15 parameters (see the specification
on page 29) to take into concern. There are a lot of publications and literature
about CMOS technology and circuits that are very helpful. Even so, it takes
some time to get an initial feeling for the circuit and the task. From similar, but
much smaller, laboratory work we know that naming the widths and lengths of
the semiconductor is a good starting point; with variables instead of set values it
is easier to change values. After doing some research, a publication of a method
based on the ratio gIDm [10] made the foundation of the initial values. This method
considers the relationship between the ratio of the transconductance gm over the
ID
as a fundamental
DC drain current ID , and the normalized drain current W/L
design relation. It is also a unified synthesis methodology and is not dependent of
if the transistors are in strong or weak inversion.
3.2
BUILDING A TESTBENCH
To be able to simulate something at all we need a testbench that can perform the
required measurements. According to the component specification the testbench
should be able to measure in open-loop and closed-loop configuration. A hint by
Jacob, the supervisor, was to aim for that all the parameters could be measured
and evaluated in the same testbench (See Figure 3.1.). That would save time and
work in the optimization.
17
18
Sizing by hand
To make both an open-loop and a closed-loop configuration in the same testbench we need feedback from the output net to the negative input voltage net
with a switch on the feedback net. The switch makes it able to enable the feedback for closed-loop, and disable it for open-loop. Since this method was chosen
switches were used wherever we needed to specify which loop that was measured.
Switches were placed: between the DiffSignal and the negative input to prevent
the circuit to be fed from two sources simultaneously, to chose between the square
pulse-signal or the DiffSignal for the slew-rate and on the output to enable/disable
Rout .
For both the PSRR and the GRR a DC voltage source was added on power supply
and ground respectively. The different ranges were set as given in the specification.
An advantage with the switch is that you could choose its position for DC, AC and
transient analysis respectively. This makes it possible to measure the slew-rate or
the THD, total harmonic distortion, (closed-loop measurements) simultaneously
as the open-loop measured parameters. Rout was a bit difficult to find a good way
of measuring but the method used was to add a sinusoidal voltage source in series
with a capacitor to the output net. Then look at the voltage drop across the test
resistor divided by the resistance to get the current. Finally divide the current
with the node voltage of the output net and multiply it with the gain.
After all those modifications were done the testbench was able to measure and
evaluate all the parameters. One nice thing with the Virtuoso Analog Design Environment is that one can choose which of the analyzes that should be enabled;
this saves time and makes it easier to simulate when you get a lot of parameters
to look at.
3.3 SIZING WITH SOME RULES-OF-THUMB
19
Figure 3.1. Testbench of the OTA with capacity to measure all the targets from specification.
3.3
SIZING WITH SOME RULES-OF-THUMB
The first thing was to make sure that all the transistors, except the two in the
Miller-compensation (M9 and M10 in Figure 3.2.), worked in the saturated region.
We want this because the saturated region gives the highest gain per transistor,
and a high output impedance gives you low distortion. This was very frustrating
at the beginning when all the transistors seemed to change operation region with
almost every new simulation. After a while one got a feel for what adjustments
that had to be done by looking at the operation region for a specific transistor.
For instance: if M1 and M2 worked in the subthreshold region it meant that the
widths of those transistors were too big and the current through them became too
small. If the widths of M1 and M2 were instead too small, the tail-transistor (M5)
changed to the linear region and so on.
The easiest parameters to adjust to specifications were gain, gain-bandwidth product and phase margin so it seemed like the best to start with. These parameters
are measured in the open-loop configuration. This was at first just to try different
values and see how they affected the parameters. After a while some observations
were made based on the parameters behavior. The differential gain-stage should
be robust enough so that it gives a high gain. Also, if the scale factor of the nDrive
(M7) is too big, the gain decreases. This went on like this until the specifications
for those three parameters were fulfilled. This is a good way to learn more about
20
Sizing by hand
how the different sizes affects the circuit and its behavior.
The circuit was sized with all the parameters in consideration, both the ones
in open-loop configuration and the ones in closed-loop. In Figure 3.2. you can see
the circuit and how each transistor is sized by different variables. The table shows
the values of each variable that was finally used for the first satisfying sizing.
Figure 3.2. Schematic of the two-stage OTA with bias circuit
3.3 SIZING WITH SOME RULES-OF-THUMB
Variable
gainMult = 42.0
nMult = 4.0
pMult = 1.0
nSF = 4.1
PSF = 10.3
nWidth = 2.0 µm
pWidth = 5.0 µm
nMiller = 47.0 µm
pMiller = 4.0 µm
chLength = 500 nm
bias = 0.2
gain = 5.0
R1 = 200k
Comment
Multiplier for the differential gain stage
Multiplier for the NMOS transistors
Multiplier for the PMOS transistors
Scalefactor for the drive-NMOS
Scalefactor for complementary PMOS
Width of the NMOS transistors
Width of the PMOS transistors
Width of the NMOS Miller-transistor
Width of the PMOS Miller-transitor
Channel-length for all transistors
Multiplier for the bias-NMOS (M8)
Multiplier for the gain stage’s chLength
Resistance in the bias-circuit
Table 3.1. Variables used to size the transistors
M1:
W
L
=
gainMult*nWidth
gain*chLength
M2:
W
L
=
gainMult*nWidth
gain*chLength
M3:
W
L
=
pMult*pWidth
chLength
M4:
W
L
=
pMult*pWidth
chLength
M5:
W
L
=
nMult*nWidth
chLength
M6:
W
L
=
pSF*pMult*pWidth
chLength
M7:
W
L
=
nSF*nMult*nWidth
chLength
M8:
W
L
=
nMult*nWidth*bias
chLength
M9:
W
L
=
pMult*pMiller
chLength
M10:
W
L
=
nMult*nMiller
chLength
21
Chapter 4
The Optimization Tools
4.1
4.1.1
CADENCE TOOL
Introduction to Cadence tool
There is an optimization tool built-in in Cadence that we can use as a starting
point. Cadence analyzes the graphs and curves based on waveforms and hence it
is a more time consuming optimization tool. It has a graphical user interface even
though it is basically some graphs moving in different directions. It works, but it
is not the strongest part of Cadence. Although this may seem like a bad optimizer
we will find out that it is quite good after all, comparing to the other tools used
in this project.
4.1.2
Problems with Cadence tool
Since this is not the tool-of-choice for this project it has to have some drawbacks,
and it certainly has; it is too time consuming. Particularly one main thing that
would be preferable is a way to weight the cost-functions. The weighting had
came in quite handy when the whole circuit was optimized with respect to all
parameters. Then one could have set that it was more important to, for instance,
minimize the area rather than trying to get the PSRRH within target.
We also wanted the operation regions to be in saturated region and at first this did
not seem possible to set. At the end of the time-line it was figured out that this
is possible to do but it is quite lengthy. Also you have to take into consideration
an operation that you only can optimize with the testbench in one configuration
at the time which makes it impossible to optimize with all parameters in concern.
Over all you have to do all the setup yourself and you have no help from the
program so that is a drawback. Beside those main problems it is quite capricious
with sudden crashes and sometimes ignoring its tasks.
23
24
4.2
4.2.1
The Optimization Tools
ASCO TOOL
Introduction to ASCO tool
Since the built-in Cadence optimization tool left a lot to wish for, another tool
was presented: ASCO (A Spice Circuit Optimizer). In ASCO, one must have a
properly formatted input netlist file, and since we use Spectre, the default file
extension is <inputname>.scs. In this netlist file, all the information about the
circuit is gathered; voltages, transistors, parameters, input signals, analyzes et
cetera. Here we can set our design variables from cadence to be design variables
in ASCO as well. Further, we need to have a configuration file, <inputname>.cfg,
where we specify what analysis we want to perform, how conservative or liberal
it should be, what variable we want to alter et cetera. Also, we set up which
parameter to optimize and what targets that are desired. We also need to create a
directory called /extract where we can keep scripts that is necessary for the process
to work, for instance: If we have specified a measurement in the configuration
file called P_SUPPLY to be a certain value, we can call an external script that
performs the calculation. These scripts are stored in the directory /extract.
4.2.2
Problems with ASCO tool
This tool is far from intuitive and does not have a graphical user interface and
therefor the adjustments have to be done using a text editor, and run in a terminal
window. The initial idea to compare the Cadence tool with this tool was to see if
there was a big difference in results, since they have different approaches on how
to calculate the cost-functions. The plan was to optimize an CMOS inverter to
minimize the power consumption with respect to the width of the transistors, the
width should vary from [1mm 10mm]. After comparing these two the mistrust
for the ASCO tool was big. After optimizing in Cadence we got satisfying values,
but when optimizing with ASCO one could not get a descent value. It ignored
the interval [1mm 10mm] and chose the width to 1µm which is 1000 times smaller
than the minimum value. Further you do not get any units for the cryptic numbers shown in the terminal window that the tutorial does not motivate further. So
the ASCO optimizer is, with consideration to time restrains and the non-intuitive
design, not a suiting tool for this project. A result from an ASCO optimization is
seen on the next page and as you can see, it is very cryptic.
4.3 ANALOG DIMENSIONS TOOL
25
best-so-far cost funct. value=0.40609
best[0]=-5.173398086
best[1]=9.592135291
best[2]=9.780050221
best[3]=-8.086606726
best[4]=9.822119535
Generation=51 NFEs=2080 Stategy: DE/rend-to-best/1/exp
NP=40
F=0.7
CR=0.9
cost-variance=0.026777
INFO: de36.c - Maximum number of generations reached (genmax=50)
Ending optimization
INFO: ASCO has ended on ’linux’
4.3
4.3.1
ANALOG DIMENSIONS TOOL
Introduction to Analog Dimensions tool
The big advantage with Analog Dimensions is that it calculates the cost-function
on the basis of equations instead of waveforms like the other tools tried out i.e. it
saves us a lot of time. The other big advantage for less experienced users is the
graphical user interface that makes it a lot easier to understand and set up the
parameters and performance measures correct. Further this tool provides us with
an option to choose and set the operation region and also an option to weight the
performance measures. As you can see this tool is, on the paper, the most suitable
for this project.
4.3.2
Problems with Analog Dimensions tool
During the period this project was ongoing AnSyn launched a new version of their
tool and it contained some bugs that unfortunately slowed down the progress
of the project. one can say that it was the bottleneck of this projects success.
These problems were not related to the tool itself, but we also had problem with
generating netlists, start the optimization, defining analyzes and load old projects
et cetera. Due to this problems the option with setting the operation regions
could not be used and that is why that was solved in Cadence after all and more
important - we had to reduce the number of processes from ten to four. Also, if
you get error-messages, Analog Dimensions leaves a lot to wish for when it comes
to explaining what the problem is.
Chapter 5
Optimization
5.1
OPTIMIZING IN CADENCE
5.1.1
Getting the amplifier within target
After the sizing-by-hand was done we could start to optimize the circuit with
the built-in Cadence tool. Since most of the parameters are to be measured in
open-loop configuration it was a good idea to start with that, just as when the
sizing-by-hand was made. Again start with Gain, A0 , Gain-Bandwidth Product,
GBW, and Phase margin, PM. If all of those suit the specification we would have
a rough template to start from when moving on to closed-loop later on. The
difficulties with this is, above all, that when a satisfying solution has been found
for open-loop you wont be able to vary the variables that much in closed-loop
because it affects the parameters a lot. In Figure 5.1. you see the open-loop
configuration and in Figure 5.2. the closed-loop configuration and a table (Table
5.1.) with the parameters and comments on how they each were set up in the
optimization environment.
27
28
Optimization
Figure 5.1. Testbench of the OTA in open loop configuration
Figure 5.2. Testbench of the OTA in closed loop configuration
5.1 OPTIMIZING IN CADENCE
Specification
Open-loop gain
Gain-bandwidth product
Input common-mode range
Input range
Slew-rate
Power Dissipation
Output range
Supply rejection ratio
Ground rejection ratio
Supply rejection ratio
Ground rejection ratio
Output resistance
Output referred noise
Load capacitance
Phase margin
Area
Linearity
Parameter
A0
GBW
ICMR
IR
SR
P
OR
PSRRL
GRRL
PSRRH
GRRH
Rout
VN
CL
PM
A
THD
29
Target
4000 (72dB)
60 MHz
[0.5 V, 1.5 V]
[0.8 V, 1.8 V]
100 V/µs
- mW
[0.5 V, 1.5 V]
70 dB
70 dB
50 dB
50 dB
250 kOhm
0.5 mV
75 fF
55 degrees
- Sq µm
60 dB
Comment
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Table 5.1. The design specification with all the necessary information
5.1.2
Comments to the specification
1. Notice the relation between IR, OR and ICMR.
2. There is a competing relation between IR, ICMR and OR.
3. The slew-rate is measured in closed-loop configuration.
4. Free optimization target, i.e. minimize power.
5. The output range is measured in closed-loop configuration.
6. Measured from 0 to 50 kHz.
7. Measured from 0 to 50 kHz.
8. Measured from 50 kHz to 1 MHz.
9. Measured from 50 kHz to 1 MHz.
10. Minimum output resistance.
11. +/- 3 sigma.
12. Intended for on-chip use only. Notice that dominant-pole compensation is
possible too, but will obviously hurt area, A.
13. Notice that dominant-pole compensation is possible too.
14. Free optimization target, i.e. minimize area.
15. Closed-loop linearity with unity feedback factor.
30
5.1.3
Optimization
Performance measures
We know the basics of the cost-function and can use that knowledge while setting
up satisfying requirements on the performance measures. We know what value the
parameters are required to have from the specification. Now we set up expressions
that tell the tool how we want to optimize the circuit. For A0 , GBW, PM, THD
and SR it is quite easy since it is basically a value we want to reach and it is not
bound to any intervals or such. In that case we simply fill in the desired target
and the tool will find a solution that is greater than or equal that specified value.
For instance: PM ≥ 55 degrees.
The same is basically done with PSRR and GRR except that we divide them
into two frequency intervals. PSRRL and GRRL is measured from 0-50kHz and
PSRRH and GRRH from 50kHz-1MHz. This is made because it is harder to avoid
the PSRR and GRR to drop at high frequencies.
The area and power dissipation are free optimization targets and should therefor
be minimized; just get a good performance measure and approach zero. As you
can see we can basically choose between maximizing or minimizing the value of a
parameter. If we want the parameter to match a certain value this can be made
by taking the desired value and subtract the formula for measuring the parameter
of interest. This was tried out in this project but the approach from above seemed
to fit better with the specification.
5.1.4
Optimization of each parameter
Below is a list of the performance measures that were set up. As you can see it is
not everyone from the specification, this is because some of the parameters should
not be optimized, only set to a certain value.
1. The open-loop gain,A0 , was measured by taking the value of the output voltage
in decibels at 1 Hz. From the beginning it was measured by hand in the waveform
window, but when the optimization started it was more accurate and easier to
look at the expression instead. This was done by taking the expression
(value(dB20(VF("/vOut"))) 1 ?histoDisplay nil ?noOfHistoBins 1)
Then a permanent expression was in the output box in the ADE Window. Since
it was measured in decibels, a value of 72 dB or higher were desired. After some
unsuccessful simulations a pattern was established showing that the gain is very
much dependent on the channel length of the transistors, i.e. the larger the channel the higher the gain. This was strange though because it should be the other
way around since a larger channel-length should generate in a smaller current and
therefor also the transconductance (see small signal section).
2. The Gain-bandwidth product,GBW, is the product of the gain and the bandwidth. The expression is:
gainBwProd(VF("/vOut"))
5.1 OPTIMIZING IN CADENCE
31
This could be a trade-off between gain and bandwidth. One can keep the gain and
increase the bandwidth though, but this often results in that other targets will be
out of specification. GBW is also dependent on the NMOS Miller-transistor i.e.
the transistor which represents the capacitor in the Miller-compensator. With decreasing values on the NMOS Miller-transistor one will have increasing GBW and
vice versa. This has to do with the pole placement that the Miller-compensation
adjusts.
3. The phase margin
phaseMargin(VF("/vOut"))
also depends a lot on the pole placement i.e the Miller-compensation. In addition to that we also have a PMOS transistor that represents an resistor. If the
dominant pole is on the output, the PMOS does not affect the GBW but is of
the essence for the phase margin. With increasing values of the NMOS, the phase
margin increases, and with decreasing values it decreases.
A0 ·p1
=
90
arctan
and GBW = f0dB = A0 · p1
PM = 90 - arctan f0dB
f2
f2
As you can see from these equations, this generates some trouble when you have to
take both PM and GBW in consideration because of the pole p1 . If the frequency
of the pole increases, the unity gain, i.e. the GBW increases, but at the same time
PM decreases. One must find a balance between those two so that both can meet
the specifications.
4. The power supply rejection ratio, PSRR, for low frequencies was optimized
by starting with the initial values from above and then slightly vary them, but in
a smaller span than before, and mainly take the PSRRL in consideration. The
expression for measuring PSRRL is:
value((db(getData("/Vdiff" ?result "xf")) db(getData("/VsupplyNoise" ?result "xf")))
50000 ?histoDisplay nil ?noOfHistoBins 1)
In other words, it means the difference between the amount of noise from power
supply that a particular device can reject from 1 Hz to 50kHz. Based on the optimization one should increase the width of the PMOS transistors, width of both
the NMOS and PMOS in the Miller-compensation and channel length. Also one
should decrease the width of the NMOS transistors. The hardest part of the optimization was to get the PSRRH within target since the PSRR has a tendency to
drop faster at higher frequencies.
5. The ground rejection ratio, GRR, was measured exactly the same as PSRR
with just a different expression, videlicet:
32
Optimization
value((db(getData("/Vdiff" ?result "xf")) db(getData("/VgroundNoise" ?result "xf")))
50000 ?histoDisplay nil ?noOfHistoBins 1)
for low frequencies.
Unfortunately, the GRR on high frequencies also drops faster and makes it hard
to get within the specification.
6. The THD was the parameter found to be the most difficult to measure. The
idea with this is to make sure that the amplifier is stable, this means basically that
the output signal should follow the input signal and that it does not compress or
dislocates.
This was made by running a periodic steady state analysis (PSS-analysis) and
then make a script that takes the first harmonic wave in decibels subtracted with
the second harmonic wave in decibels. This is the expression from the optimization:
(dB20(harmonic(v("/vOut" ?result "pss-fd.pss") 1))
- dB20(harmonic(v("/vOut" ?result "pss-fd.pss") 2)))
This performance measure was set up to be ≥ 60 dB. Also, an expression for the
third harmonic wave was included to make sure that the amplifier was stable for
both even and odd distortion.
7. Slew-rate was a bit tricky because the testbench configuration had to be adjusted just for this parameter alone. This means that if you have good costfunctions and parameter values for all the other parameters listed here, you can
adjust the testbench for SR-mode and then discover that the SR is far off the
targeted value. This happened more than one time. The expression was:
slewRate(VT("/vOut") 0.5 nil 1.5 nil 10 90 nil nil nil 1)
This performance measure was set up to be ≥ 100M (because it was measured in
V/s).
8. Since we wanted all the transistors (except the ones in the Miller-compensation:
M9 and M10) to work in saturated region we had to make sure that each transistor
fulfilled the requirements for saturation, i.e. Vgs − Vth ≥ 0 and Vds − Vdsat ≥ 0.
The expressions looked like this:
(OP("/Iamplifier/MX" "vgs") - OP("/Iamplifier/MX" "vth"))
(OP("/Iamplifier/MX" "vds") - OP("/Iamplifier/MX" "vdsat"))
5.1 OPTIMIZING IN CADENCE
33
and were set up to be ≥ 1 mV for the NMOS-transistors and ≤ -1 mV for the
PMOS-transistors.
9. The power dissipation were quite hands on, just multiplying the voltage of
the DC source with the current through the DC source.
(OP("/VsupplyNoise" "v") * OP("/VsupplyNoise" "i"))
10. Finally, the area was calculated in a somewhat lengthy way. By adding
every transistors width times length times multiplier one could get one correct
expression.
((VAR("pWidth") * VAR("pMult") * VAR("chLength"))
+ (VAR("pWidth") * VAR("pMult") * VAR("chLength"))
+ (VAR("pWidth") * VAR("pSF") * VAR("pMult")
* VAR("chLength")) + (VAR("pMiller") * VAR("pMult")
* VAR("chLength")) + (VAR("chLength") * VAR("nMult")
* VAR("nMiller")) + (VAR("nWidth") * VAR("gainMult")
* VAR("gain") * VAR("chLength")) + (VAR("nWidth")
* VAR("gainMult") * VAR("gain") * VAR("chLength"))
+ (VAR("nWidth") * VAR("nMult") * VAR("bias")
* VAR("chLength")) + (VAR("nWidth") * VAR("nMult")
* VAR("chLength")) + (VAR("nWidth") * VAR("nMult")
* VAR("nSF") * VAR("chLength")))
34
Optimization
Parameters
gainMult = 42.0 → 60.0
nMult = 4.0 → 8.0
pMult = 1.0 → 12.0
nSF = 4.1
PSF = 10.3
nWidth = 2.0µm → 6.0µm
pWidth = 5.0µm → 6.0µm
nMiller = 47.0µm → 41.0µm
pMiller = 4.0µm → 1.0µm
chLength = 500nm
bias = 0.2
gain = 5.0 → 6.0
R1 = 200k → 60k
Comment
Multiplier for the differential gain stage
Multiplier for the NMOSes
Multiplier for the PMOSes
Scalefactor for the drive-NMOS
Scalefactor for complementary PMOS
Width of the NMOS-transistors
Width of the PMOS-transistors
Width of the NMOS Miller-transistor
Width of the PMOS Miller-transitor
Channel-length for all transistors
Multiplier for the bias-NMOS chLength
Multiplier for the gain stage’s chLength
Resistance in the bias-circuit
Table 5.2. Final variable values
5.1.5
Problems and difficulties
As you can see, the initial values of the variables from the handmade sizing had to
be adjusted. Especially the gain stage had to be more robust and also the widths
of the NMOS transistors increased. This shows just how hard it is to size a circuit
by hand with this scarce experience and even if the solution looks good, it often
turns out that there are one or several better ways of sizing it.
The first big problem was to get the slew-rate within specifications at the same time
as PSRR, GRR because there is a trade-off between these. This was solved eventually when we found satisfying values on the widths and lengths. Also, the input
swing had to be decreased from 1V to 850 mV to get the THD within specification.
Further, one over-night simulation were made with objective to get all the parameters within target and in addition to that also minimize the power dissipation
and area. The anti climax was that the transistors had changed operation region
to subthreshold and not much had improved, actually, the area had increased quite
a lot so that was a disappointment.
5.2 OPTIMIZATION IN ANALOG
DIMENSIONS
5.2
35
OPTIMIZATION IN ANALOG
DIMENSIONS
While the problems with the new generation Analog Dimensions tool were fixed
an old tutorial example provided by AnSyn AB was reused. This was done by
changing the original folded cascode amplifiers structure to the two-stage amplifiers we are using. When we do this we also have to change names in project-file
so that the transistor- and instance names in the modified folded cascode matches
the ones in the two-stage. This is time consuming and not a very good course of
action. This did not really lead to anything interesting in terms of results but it
was a good way to get to know the tool.
We decided to only focus on one testbech configuration in the optimization due
to all the struggle. This meant that the the final performance measures that was
optimized were: A0 , GBW, PM, PSRRL, PSRRH, GRRL, GRRH, Area, Pdiss
and the transistor regions.
The final version that was used included both Analog Dimensions and the use
of ocean scripts. Since this results in that you are not allowed to define any analyzes in Analog Dimensions, all that has to be done in Cadence. You set up
all your analyzes and performance measures in Cadence and check that it is running as it should, then save the state as a ocean script. This script with some
commenting and corrections is then loaded with the project you have created in
Analog Dimensions. By doing this you have basically imported all information
from Cadence and Analog Dimensions interpret these analyzes instead of setting
up own.
Left to do in Analog Dimensions is to set up restrains and weights of the performance measures and start the optimization. When you have started the optimization you also have to paste an initiation file into the ocean terminal so that
both these work simultaneous. With a way of weighting the performance measures
and setting the regions (although not as easy as planned) we now can optimize
with all the restrains we have. Figure 3.5. shows a flow diagram over the strategy
with ocean scripts.
36
Optimization
Figure 5.3. Flow diagram over the use of ocean scripts.
Chapter 6
Runs
6.1
INITIAL SETUP
When Analog Dimensions finally worked properly, the baptism of fire was held:
full optimizing on a first process to make sure all the performance measures were
correct. This was run overnight and when we evaluated it, it seemed like it had not
taken the area and power dissipation in concern, this means that our parameters
fit the specification, but the sizes were larger than they necessary should be. Even
the optimization in Cadence was a lot better if we just look at the area and power
dissipation. The conclusion was to take another look at the performance measures
of those two parameters and try to improve it further. Some slight changes of
the targets for area and power dissipation were made, and also the performance
measures for the rejection ratios had to be modified due to the fact that we have
the testbench set up for open-loop. Finally a decision was made that no more adjustments would be made so that all the processes had the same starting condition.
Since it became quite lengthy with the ocean scripts and setup in Cadence we
tried to improve the procedure so that the runs could be performed easier. With
goal to avoid any copy-pasting in our ocean files we added if-statements and load
commands. Finally the only change that had to be done when switching process
was to change from the old process name to the present in the terminal. Meaning that we had eliminated the manual work for: changing process, changing the
netlist widths, lengths and finger numbers for the different processes, and also to
launch Analog Dimensions faster. By doing this we saved time and manual work
and, most of all, it looked nice. Even if this does not really has to do with the
optimization as such, it is a part of the job description in that sense that the
switching between processes should be as easy as possible.
37
38
6.2
Runs
"PROCESS ONE", 350nm
This process was the biggest one, but even so, the area and power dissipation
were surprisingly big. Even if Analog Dimensions found an optimal solution, all
the performance measures did not fulfill the specification, gain = 70.904 dB and
PSRRH = 48.188 dB.
6.3
"PROCESS TWO", 180nm
This process performed as expected in a sense. Its values was not surprising and
placed in the middle of the processes. In this process, the performance measures
did not reach within specification as well. PSRRL = 61.72 dB and PSRRH =
35.31 dB.
6.4
"PROCESS THREE", 90nm
This process behaves different and require some additional change in setup. In the
netlist file the widths and lengths have to be multiplied with a scale factor 1e6.
This is because "process three" calculate its widths and lengths different compared
to process one and two. Also, the transistors are defined as sub circuits in this
process, meaning that the performance measures for the transistors have to be
re-written as
(get(getData("Iamplifier."transistor name".M1"
?result "dcOpInfo-info") "vgs")
- get(getData("Iamplifier."transistor name".M1"
?result "dcOpInfo-info") "vth"))
Parameters out of specification were: PSRR = 65.115 dB and PSRRH = 39.65
dB.
6.5
"PROCESS FOUR", 65nm
Basically the same conditions and setup as "process three", but instead of "transistor name".M1 it has to be called "transistor name".m1. This process was very
good with all the parameters within specification and both small area and low
power dissipation.
Chapter 7
Results
Figure 7.1. Graph showing the final results of the optimization.
39
40
Results
Process
"Process one", 350 nm
"Process two", 180 nm
"Process three", 90 nm
"Process four", 65 nm
Power dissipation
2.464 mW
649.031 µW
694.956 µW
472.578 µW
Area
2.463 nm2
567.95 pm2
178.2 pm2
44.55 pm2
Table 7.1. The design specification with all the necessary information
7.1
DISCUSSION & FUTURE WORK
As we can see in the graph in Figure 7.1, the pattern reminds us of the desired
one. The area is clearly decreasing when we change process to a smaller one. The
power consumption seems to do that as well, even if "process three" consumed a
bit more than expected. Although, this could perhaps be a result of the fact that
we only optimized four processes. If we have had time for all ten, the conclusion
about the power dissipation would have been easier. Now we do not know if it
just was this process that consumed more than expected or if another pattern had
occurred with all ten processes.
Also, it seemed like the optimizer chose between two methods when optimizing.
Either it decreased the resistance in the bias circuit resulting in a higher power
dissipation or it increased the gain-stage which resulted in a lower power dissipation. Either way, all the processes had the same starting conditions so we can only
assume that the optimization tool uses the same approach every time - but from
experience we do know that it is not to take for granted.
This project will constitute as a base for future work where the optimization will
be brought up and completed. The optimization will run (for all ten processes)
in both open-loop configuration and closed-loop configuration so that as many
parameters as possible can be optimized. This will hopefully lead to a better and
more truthful prediction of future costs.
References & Sources
R
c
[1] AnSyn
AB 2007, “Analog design optimization using ANALOG
TM
DIMENSIONS
tutorial, folded-cascode operational amplifier.”
http://www.ansyn.com.
[2] “Process technology.”
http://encyclopedia2.thefreedictionary.com/process+technology,
Retrieved Novermber 30, 2009.
[3] S. M. Rubin, “Computer aids for VLSI design.”
http://www.rulabinsky.com/cavd/,
Retrieved Novermber 3, 2009.
[4] J. Markoff, “Design on diagonal path in pursuit of a faster chip.”
http://www.nytimes.com/2007/02/26/technology/26chip.html,
Published: February 26, 2007.
[5] Prof. Regan A. Zane, “Mixed-signal IC design.”
http://ecee.colorado.edu/~ecen5007/software.html,
Retrieved Novermber 3, 2009.
[6] “Maxim application note 1108: Understanding single-ended, pseudodifferential and fully-differential adc inputs.”
http://www.maxim-ic.com/appnotes.cfm/an_pk/1108,
Retrieved Novermber 3, 2009.
[7] S. Söderqvist, Properties Basic Amplifiers.
[8] P. E. Allen and D. R. Holberg, “CMOS analog circuit design,”
1987.
[9] A. Burmen, P. Janez, and T. Tuma, “Defining cost funtions for robust IC
design and optimization.”
www.date-conference.com/archive/conference/.../05D_1.PDF,
Retrieved Novermber 3, 2009.
[10] F. Paixão Cortes and S. Bampi, “Miller ota design using a design methodology
based on the gim
and early-voltage characteriristics: design considerations and
d
experimental results.”
41
42
References & Sources
www.iberchip.org/iberchip2006/ponencias/78.pdf,
Retrieved Novermber 3, 2009.
Appendix A
The specification
Specification
Open-loop gain
Gain-bandwidth product
Input common-mode range
Input range
Slew-rate
Power Dissipation
Output range
Supply rejection ratio
Ground rejection ratio
Supply rejection ratio
Ground rejection ratio
Output resistance
Output referred noise
Load capacitance
Phase margin
Area
Linearity
Parameter
A0
GBW
ICMR
IR
SR
P
OR
PSRRL
GRRL
PSRRH
GRRH
Rout
VN
CL
PM
A
THD
Target
4000 (72dB)
60 MHz
[0.5 V, 1.5 V]
[0.8 V, 1.8 V]
100 V/µs
- mW
[0.5 V, 1.5 V]
70 dB
70 dB
50 dB
50 dB
250 kOhm
0.5 mV
75 fF
55 degrees
- Sq µm
60 dB
Comment
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Table A.1. The design specification with all the necessary information
43
44
A.1
The specification
COMMENTS TO THE SPECIFICATION
1. Notice the relation between IR, OR and ICMR.
2. There is a competing relation between IR, ICMR and OR.
3. The slew-rate is measured in closed-loop configuration.
4. Free optimization target, i.e. minimize power.
5. The output range is measured in closed-loop configuration.
6. Measured from 0 to 50 kHz.
7. Measured from 0 to 50 kHz.
8. Measured from 50 kHz to 1 MHz.
9. Measured from 50 kHz to 1 MHz.
10. Minimum output resistance.
11. +/- 3 sigma.
12. Intended for on-chip use only. Notice that dominant-pole compensation is
possible too, but will obviously hurt area, A.
13. Notice that dominant-pole compensation is possible too.
14. Free optimization target, i.e. minimize area.
15. Closed-loop linearity with unity feedback factor.
Appendix B
The Schematic
Figure B.1. Schematic of the two-stage OTA with bias circuit.
45
Appendix C
The Testbench
Figure C.1. Testbench of the OTA with switches.
47