Phototransmitters and receptors abound in
flavors and capabilities
Bill Travis - December 31, 1969
In part 1 of this article I provided the necessary equations to develop your own macro model for a
bipolar input operational amplifier (op amp). In part 2, we looked at a CMOS input and output
topology. Now in part 3 we derive the necessary equations for a purely bipolar process, a rail-to-rail
in and out op amp.
Just as we did in the first two parts, highlighted equations are inserted into the netlist. Equations in
blue are for your own observation purposes, while the red ones may be required in the model
parameters at the end of netlist.
First you need to specify the following specifications: Supply voltage, open loop gain, unity gain
bandwidth, slew rate, input offset voltage, input offset current, phase margin, temperature. Later in
the output section we get to other parameters such as open loop output impedance, short circuit
current, and voltage output swing.
Rail-to-rail input stage
Unlike the non-rail-to-rail input stage, we need two differential pairs PNP and NPN bipolar junction
transistors (BJTs). Just like in the bipolar input stage, we have the option to add an emitter
degeneration, or resistance emitter (RE) at the expense of the gain in the first stage.
Figure 1. Bipolar rail-to-rail input stage
PNP input stage
Set the following device parameters:
I1=1E-3A
VA=130V
IS=1E-16
β1=5000
Next, set the input stage gain as:
Avin=Aol/Avout*Avmiddle
gm1=I1/VT
If you decide to add degeneration, be sure to use the following formula:
Gm=gm/(1+gm1*RE)
With no added degeneration,
Avin=gm*(RC1*ro)/(RC1+ro)
ro=VA/2*I1
rπ=2*β1*VT/I1
RC1=RC2=2*VRC/I1,
where VRC=0.2V
RE1=RE2=[( β*RC1)-( rπ*Avin)]/(gm*RC1+ β*Avin)
Next, compute the additional lag needed to get the proper phase margin dialed in.
ɸ1=90-ɸm-fz, where fz=arctan(GBP/z1),
where z1=1/Cf*(1/gm5+gm6)-Rz
p1=GBP/tan(90- ɸm-2), p1 in Hz
C1=1/2*RC1,2*p1, use radians for p1 here
We will come back to Rz (zero) and show how to derive it in the middle stage.
V1=Vs-Vcm, high; sets the common voltage input range
Input stage noise contribution
Now we turn to the transistors and diodes of the input stage to determine their noise contribution.
This is an important part of the model, especially if you are trying to model a low-noise device.
The total input noise (RTI) is expressed as:
entotal=sqrt(enRC^2+ enRE^2+enID^2+ enPNP^2)
where:
enRC=sqrt(2*4*k*T*RC1,2)/(2*Avin),
enRE=sqrt(2*4*k*T*RE1,2)/(2*Avin),
k is Boltzmann’s constant and T, the temperature in Kelvin
enID=sqrt(2*q*(I1/2)),
where IB is the input bias current from the datasheet
enPNP=sqrt(2*Id*RC1,2)/(2*Avin)
NPN input stage
For the NPN differential pair, device parameters are set to the same PNP values.
I2=1E-3A
VA=130V
IS=1E-16
V2=Vs-Vcm, low;
V2 sets the lower range of the input common mode range:
Gm2=I2/VT
ro=VA/2*I2
rπ=2*β2*VT/I2
RC3=RC4=2*VRC/I2,
where VRC=0.2V
RE3=RE4=[( β2*RC3,4)-( rπ*Avin)]/(gm2*RC3,4+ β2*Avin)
C2=C1
Middle (gain) stage
This represents the second of our three-stage design. Set a voltage-controlled current source in
parallel with a resistor, clamping diodes, capacitor Cf to set the pole, and resistor Rz to set a zero
such that you get the correct phase margin.
The gain Avmid is simply written:
Avmid=2*G1*R1
To determine Cf, set R1 to an arbitrary value. Remember that the larger the value, the higher your
noise will be.
Set R1=10k
Cf=1/2π*fdom*R1*(Avout+1),
where fdom=(GBP/Aol)*sqrt(1+GBP^2/p1^2)
G1=SR*Cf/2*I1*RC1,2
Rz=1/(gm5+gm6)-(1/2π*Cf*fz)
Figure 2. Middle or gain stage