Title
Author(s)
Citation
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Rights
Resonant augmentation circuits for a buck converter achieving
minimum-time voltage recovery from load transients
Shan, ZY; Tan, SC; Tse, CK; Jatskevich, J
The 2014 IEEE Energy Conversion Congress and Exposition
(ECCE), Pittsburgh, PA., 14-18 September 2014. In Conference
Proceedings, 2014, p. 3429-3434
2014
http://hdl.handle.net/10722/210618
IEEE Energy Conversion Congress and Exposition (ECCE)
Proceedings. Copyright © IEEE.
Resonant Augmentation Circuits for a Buck
Converter Achieving Minimum-Time Voltage
Recovery from Load Transients
∗
Zhenyu Shan∗, Siew-Chong Tan†, Chi K. Tse‡ and Juri Jatskevich∗
Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC, Canada
†
Department of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam, Hong Kong
‡
Department of Electronic and Information Engineering, Hong Kong Polytechnic University, Kowloon, Hong Kong
Email: zhenyus@ece.ubc.ca
I. I NTRODUCTION
Low voltage digital intelligent ICs, e.g., digital signal processors or microprocessors, are widely used in industrial and
consumer electronics. To feed high-speed digital electronics
loads, high performance power supplies are needed. The power
converter needs to track high-slew-rate and large-step load
transients to limit voltage deviations within a narrow tolerance
band [1]–[3]. The physical limit to the transient response of
a traditional buck converter is the internal slew rate of the
inductor.
While the time-optimal control scheme can push the dynamic performance to its physical limit [4], augmentation circuits
[5]–[9] (or auxiliary circuits [10]–[17]) for dc–dc converters
have been proposed to break the limit and achieve minimumtime recovery under fast-load-transient conditions. In Fig. 1,
the augmentation circuits provide the short-fall charges of the
filter capacitor Co while the main converter inductor current
is recovering. Therefore, the response of such an augmented
converter is better than that of a fixed-topology converter
which uses a time-optimal control algorithm.
To reduce the converter complexity and the extra space
needed, the augmentation circuits and its control stage should
be as simple and small as possible. Additionally, the trend of
power technology development is moving towards integrating
———————————————————————————————
This project is supported in part by HK RGC GRF grant 5267/12E and
PolyU grant GYJ62.
978-1-4799-5776-7/14/$31.00 ©2014 IEEE
AugHigh
iaA
+ V
i
−
Vo
+
−
iaB
Co
io
Load
iL
AugLo
Abstract—This paper presents the use of a resonant circuit
for fast voltage recovery of power supplies under large-signal
load transients. Previous works have shown that an augmentation
circuit (or auxiliary circuit) for voltage recovery may be used
to improve the dynamic response, while the main converter is
operating for current recovery with load current feedforward
control. A compact, low cost and magnetic-coreless topology with
a simple control algorithm to achieve an augmentation circuit
is presented. In the prototype, the inductors are realized using
printed copper wires. The control algorithm is realized by a low
cost and low density logic device. Simulation and experimental
results validate the feasibility and effectiveness of the circuit.
Fig. 1. A buck converter with two augmentation circuits (“AugHigh” and
“AugLo”) to enhance the dynamic response.
the high performance microprocessor together with its power
supplies on the same wafer [18]. However, it is still a challenge
to implement the augmentation circuits as an IC chip. The
reasons are two folds.
First, the inductor may be operating in non-resonant mode
to regulate the augmentation current. In this circumstance, the
inductance value is in hundreds of nH, which is too large for
IC implementation. Second, some methods use switches with
diverse resistance to achieve current regulation. To enlarge the
current regulation range, the number of switches and the space
occupied by the circuit will be large, which also hinders IC
implementations.
A set of resonant auxiliary circuits serving as augmentation
branches to achieve minimum-time recovery of a converter
is proposed in this paper. The circuit operating in resonant
mode with an event driving control algorithm generates unified
quasi-sinusoidal pulses. Comparing with previous methods
[5]–[17], advantages of the proposed approach are as follows:
• The circuit generates unified discontinuous pulses so that
the controller is easy to design and realize.
• The quasi-sinusoidal current generated by a resonant
circuit has lower di/dt than the sharp-edge current generated by a pure-resistive current path.
• Small capacitors (μF) and inductors (tens of nH, achieved
by stray inductance) are used such that the circuit power
stage will occupy a smaller space.
3429
cycle damped sinusoidal current iai . At the end of T1 , vCa
rises to VCa1 which is slightly under Vi . During T2 , Sao is on
and Ca is discharged, generating a half cycle quasi-sinusoidal
current iao . In Cell A, iao is flowing into Co ; in Cell B, iao
is flowing out of Co . The levels of VCa2 in Cell A and Cell
B are slightly under Vo and Vi − Vo , respectively.
From distributed inductance of wires
Sai
iai
+
− Vi
Sao
Ri L
Lao Ro
ai +
+
vCa
Vo
C
a
−
−
VCa1
vCa
VCa1
VCa2
iao
VCa2
Co
iai
(a)
0
B. Energy Pulses
From distributed inductance of wires
vCa
+ −
iao
Ca
Lai Lao Ro Sao+
+
Vo
Co
− Vi
−
R Sai iai
iao
0
Sai
ON
OFF
Sao
ON
OFF
T1
i
T2
T1
During T2 , the precise iao can be expressed as
T2
(c)
(b)
Fig. 2. Illustration of the basic cells of the proposed auxiliary circuit: (a)
Cell A delivers energy to Co for positive transients; (b) Cell B draws energy
out from Co for negative transients; and (c) the normalized waveforms of the
two cells.
The proposed method takes advantage of a resonant circuit
and gives a paradigm shift in the implementation of augmented
converter, catered for the power-supplies-on-chip trend. In this
work, the small inductors are realized by coreless printed spiral
windings (CPSW).
II. R ESONANT AUXILIARY C IRCUIT
The two basic cells of the proposed auxiliary circuit shown
in Fig. 2 function as the two augmentation branches. “Cell
A” operates as the high-side branch to mitigate the positive
transient; “Cell B” operates as the low-side branch to mitigate the negative transient. Each cell is comprised of three
components: two switches Sai and Sao and a capacitor Ca .
Additionally, two inductors Lai and Lao are realized using
the distributed inductance of wires on a printed circuit board
(PCB) or a silicon wafer. In this analysis, the resistance of all
conducting components are represented by Ri and Ro . The
input voltage source Vi and output capacitor Co of the main
converter are shown in Figs. 2(a) and (b), while other elements
of the main converter are not shown to avoid cluttering figures.
Since capacitance Co is much bigger than Ca , the output
voltage Vo of the converter is assumed to be constant when
the proposed cells are active.
The energy transfer between the cell and Co is achieved
in two phases, i.e., T1 (charging phase) and T2 (discharging
phase). The normalized waveforms of the two cells are shown
in Fig. 2(c). During T1 , Sai is on and Ca is charged by a full
=
1
T2
T2
0
−
iao dt ≈
C
Iaoavg ≈
2
π
Ca
(Vi − Vo ).
Lao
(4)
Similarly, the approximate Iaoavg value of Cell B can be
derived as
A. Overview of Topology and Realization
Iaoavg
e−αt
Vd sin ωd t (0 ≤ t < π/ωd ),
(1)
Lao ωd
√
Ro
,
ω
=
ωo2 − α2 , ωo = 1/ Lao Ca and
where α = 2L
d
ao
Vd = Vca1 − Vo in Cell A or Vd = Vi − Vca1 + Vo in Cell B.
When
4Lao
Co (2)
Ro 2
√
is satisfied, √
it can be assumed that ωd ≈ ω0 = 1/ Lao Co ,
and T2 ≈ π Lao Ca . The average value of iao is derived and
given as (3). Vd can be approximated as either Vi − Vo in Cell
A or Vo in Cell B, as Vca1 ≈ Vi . If Ro is sufficiently small,
Iaoavg can be further simplified as
iao =
1
π Lao Ca
√
a Ro π
Lao
2
1+e
=
2
π[1 + Ro Ca /(4Lao )]
π
Iaoavg ≈
2
π
Ca
Vo .
Lao
(5)
C. Determination of Parameters of Auxiliary Circuits
According to above analysis, the parameters Lao and Ca ,
determine the Iaoavg value and other properties of the energy
pulses. The amount of transferred electrical charge per pulse
is constrained by the voltage tolerance, and the duration of
the pulses is constrained by switching frequency at which the
components can operate. Therefore, the values of Lao and Ca
depend on all the factors mentioned above.
1) ΔVo max Determines Ca : The load will change with
variable-size steps, while the auxiliary circuit generates fixedamplitude pulses. When the load transient is relatively small,
the pulses from the auxiliary circuit may introduce extra
voltage ripples on Vo . Therefore, the amount of transferred
charge per pulse (denoted as Qao ) must be limited by the
tolerance of Vo deviations (assumed to be ΔVo max ), and is
given as
Δvo = Qao /Co = Iaoavg T2 /Co ≤ ΔVo max ,
√
Lao Ca
e
0
Ca
Vd
Lao
3430
R
ao
− 2L o t
Ca /Lao Vd sin √
t
dt
Lao Ca
(6)
(3)
where Vo is assumed to be relatively constant and much larger
than Δvo . After substituting Iaoavg by the result of (4) and (5),
ΔVo max Co
,
the derived constraints on Ca for Cell A is Ca ≤
2(Vi − Vo )
ΔVo max Co
.
and for Cell B is Ca ≤
2Vo
2) ΔIo max Determines Lao : To achieve a voltagedeviation-free response to load transients, the current provided
by the auxiliary circuit should make up the mismatch between
the inductor and the load current [6]. The value of Iaoavg
should be determined by the maximum load transient (assumed
to be ΔIo max ). The limit on inductance Lao can be derived
from
Iaoavg ≥ kiao ΔIo max ,
(7)
where kiao is the scaling factor to cope with the error existing
in the estimated value of Iaoavg . The factor of
C R π
a
o
1 + e− Lao 2
(8)
Ms =
π[1 + Ro2 Ca /(4Lao )]
Cell A is working
P2 does not end
P2
TH = −1
Cell B is working
TH = 0
P2 does not end
TH = 1
Stand by
P1 ends
P2 ends
P1
P2 ends
P1
P1 does not end
P1 does not end
TH =
P2
0: vo is inside the allowed band ( Vthl <vo < Vthh )
1: vo is over the allowed band ( vo ≥ Vthh )
−1: vo is under the allowed band ( vo ≤ Vthl )
Fig. 3. State transition diagram of the proposed resonant augmentation
control.
should be substituted into (11) and (12) to ensure that the
switches are capable of achieving the designed switching
speed.
in (3) is approximated as 2/π in (4) and (5). In a circuit with
a set of general parameters, e.g., Ro = 0.2 Ω, Ca = 2 μF
and Lao = 30 nH, the Ms value drops to 0.6/π which is
one-third of 2/π. As a result, the values of Iaoavg obtained
from (4) and (5) are overestimated. A reasonable kiao should
be in the range from 2 to 4 to compensate the overestimation
of Iaoavg . Finally, the constraints on Lao in Cell A and Cell
B are
2
2(Vi − Vo )
Lao = Ca
(9)
kiao ΔIo max π
Taking advantage of the load feedforward control method,
the control loop of main converter and augmentation circuits
are simplified for design. The main converter achieves the
minimum-time recovery of its inductor current, while the
augmentation circuit is facilitating the voltage recovery. As a
result, the augmented converter recovers from its load transient
in a minimum time.
and
A. Review of Load Feedforward Control for Main Converter
Lao = Ca
2Vo
kiao ΔIo max π
2
,
(10)
respectively.
3) Ro , Ri and Li Effects: In the above guidelines, Ro is not
considered. However, the presence of Ro causes errors in (4)
or (5) such that the actual Iaoavg is lower than its calculated
value. The Iaoavg value should be verified using (3) with the
estimated Ro . Normally, Ro of around 100 mΩ is reasonable.
The existence of Ri and Lai will limit the magnitude and the
slew rate of iai . Values of a few mΩ for Ri and a few nH for
Lai are suitable for most applications where Ca is around 1 μF.
Particularly, the stray inductance from the connection lines
among the elements and the power may achieve a satisfied
Lai . In summary, the constraints on Ri , Ro and Lai are not
strict, but should be considered.
4) Duration of T1 and T2 : In both cells, the precise
duration of T1 and T2 can be calculated by
and
2π
T1 = 1/(Lai Ca ) − Ri 2 /(4Lai 2 )
(11)
π
,
T2 = 1/(Lao Ca ) − Ro 2 /(4Lao 2 )
(12)
respectively. The values of T1/2 are expected to range within
the component-switching-time limits. The chosen parameters
III. C ONTROL S CHEME
FOR
AUGMENTED C ONVERTER
Peak current with load feedforward control applied to
converter with an augmentation scheme has been proposed
by Kapat and Krein [5], [6]. This strategy is capable to make
the inductor current recover to its steady state from large load
transients in minimum time. The load current io feedforward
is functioning as the dominant component of the peak current
reference. The peak current of iL will refer to
ip = io + kp (Vref − Vo ) + ki (Vref − Vo )dt.
(13)
B. Event Driving Control of Augmentation Circuits
The voltage recovery of the system will be achieved by the
augmentation that is controlled by a fast non-linear loop, e.g.,
bang-bang control [5], [6]. Thus, an event driving method is
developed for the control of the proposed auxiliary circuit.
There is only one threshold to start the circuit actions. Cell A
in Fig. 2(a) and the diagram in Fig. 3, for instance, illustrate
the approach. The circuit will be standing by unless vo is lower
than a fixed threshold (Vthl ). When the circuit enters the P2
state, it will stay there with the switch Sao on until a pre-set
time period (T2 ) has elapsed. Then, the circuit will shift to the
P1 state with the switch Sai on and remain as it is until the
time period (T1 ) has elapsed. The control of Cell B is the same
as that of Cell A except for the event (vo becoming higher than
Vthh ) to drive the state turning to P2 from a stand-by state.
3431
vo (V)
v of traditional converter
o
5.1
A. Simulation Results
5
4.9
0
0.05
0.1
0.15
(a)
0.2
0.25
iL
8
io
iL / io (A)
The simulation is implemented in Matlab/Simulink. The
key waveforms in a large time scale is given in Fig. 4.
In both cases (with and without the augmentation) the load
feedforward control is applied and the the inductor current
recovers from large load transients in the minimum time. By
using the proposed circuit, the voltage recovery time has been
shortened from 100 μs to 10 μs which is approaching the
current recovery time. Also the voltage overshoots or dips have
been reduced from 90 mV to 30 mV, which is significant.
The enlarged waveforms of the output current and capacitor
voltage of the two cells are shown in Fig. 5. In discharging
phase T2 , one quasi-sinusoidal current pulse is generated
by the capacitor Ca discharging through the inductor iao .
In charging phase T1 , vCa rises back to the initial level
approaching Vi . The circuit operation is repeated cycle by
cycle providing the required transient energy.
0.3
10
6
4
0
0.05
0.1
0.15
(b)
0.2
0.25
15
iao (A)
two cells are kiao = 3.5, ΔVo max = 0.05 V, Vthl = 4.97 V,
Vthh = 5.03 V , Ri ≈ 50 mΩ and Ro ≈ 160 mΩ.
vo of converter with the augmentation circuits
5.2
0.3
iao of Cell A
10
i
of Cell B
ao
5
0
0
0.05
0.1
0.15
(c)
t (ms)
0.2
0.25
0.3
B. Prototype and Experimental Results
i
The schematic diagram of the prototype is shown in Fig.
6. The main converter is a general sync-buck converter. Two
auxiliary circuits configured as Cell A and Cell B operate
15
10
iao
5
0
0.05
0.052
0.054
t (ms)
0.056
LaiB
iaiB
vCa of Cell A
ao
(A)/ v
Ca
(V)
Fig. 4. The simulated buck converter waveforms of (a) vo , (b) iL , io and
(c) iao of the auxiliary circuits during the 5-to-10 A load transients.
TaiB CaB
LaiA
10
i
+
−
i
ao
0.202
0.204
t (ms)
0.206
LaoA
Cell B
iaoA
Cell A
TaoA
iao
CPSW inductor
io
iL
Tm
+12 V
Ts
vCa of Cell B
0.2
TaoB
TaiA CaA
15
ao
(A)/ v
Ca
(V)
iaiA
0
iaoB
0.058
(a)
5
LaoB
Co
gate drive
0.208
0~10 A
dummy load
gate drive
(b)
R1
R-S
Flip-flop
+
Q R
−
Fig. 5. Enlarged iao and vCa simulation waveforms in Fig. 4 for (a) Cell A
and (b) Cell B.
Q S
C2
C1
−
Σ
R2
+
Vref
IV. S IMULATION AND E XPERIMENTS
Clk
The simulation and experimental measurements based on
a traditional sync-buck converter are performed to verify the
proposed method. The parameters of the main converter are
Vi = 12 V, Vo = 5 V, fsw = 200 kHz, L = 10 μH and
Co = 280 μF. The auxiliary circuit is designed for 5 A load
transients. Parameters of Cell A are Lao ≈ 50 nH, Lai ≈ 5 nH
and Ca = 0.8 μF, and that of Cell B are Lao ≈ 40 nH,
Lai ≈ 5 nH and Ca = 1 μF. Other common parameters of the
3432
Logic
devices
vcs
Load feedforward
loop
−
Event drive control
vcs V V
+
thl
Vref
thh
vo
Vref
Fig. 6. Schematic of the experimental prototype.
the main converter is achieved purely by analog circuits. The
proposed event driving control algorithm for the augmented
circuits is achieved by a low cost complex programmable logic
device (EPM240T100C5) plus analog comparators.
Figs. 8 and 9 are the experimental waveforms obtained from
the prototype. As it can be seen in these figures, the proposed
approach successfully achieves minimum time recovery and
suppresses voltage deviations under fast load transients. Some
high frequency ripples on vo are observed from the waveforms
when the augmentation circuits are operating. This problem
can be improved by tuning the switching dead time or adding
a small capacitor at the connection line between the augmentation and the filter capacitor bank.
/DR%
/DR$
&D$
/DL%
&D%
/DL$
7DL$
7DL%
Fig. 7. Bottom view of the augmentation circuits built on a four-layer standard
PCB.
respectively as “AugHigh” and “AugLo” shown in Fig. 1. The
components comprising Cell A are denoted as LaiA , LaoA ,
CaA , TaiA and TaoA and the components comprising Cell B
are denoted as LaiB , LaoB , CaB , TaiB and TaoB .
The inductor LaoA/B is implemented by a CPSW as shown
in Fig. 7. To reduce the parasitic resistance, the windings
printed on four copper layers are paralleled. The space ratio
of the central hollow and the winding has been optimized
according to the principle given in [19]. The control loop of
V. C ONCLUSION
This work describes the design of a new circuit to achieve
minimum-time recovery from fast load dynamics in the framework of an augmented converter. The compact resonant cells
that generate fixed-width current pulses are used to handle
the voltage recovery. An event driving strategy is developed
to control such cells. The experimental results confirm the
effectiveness of the proposed methodology. It is further envisioned that the proposed approach may lead to a paradigm
shift that the augmentation method based on small inductors
are designed together with the main converter on chip.
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ǻYR P9
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ǻYR P9
7VHWWOH ȝV
L/ $GLY
L/ $GLY
7LPHVFDOHȝVGLY
7LPHVFDOHȝVGLY
(a)
(b)
Fig. 8. Waveforms of the general buck converter under 5 A-size (a) step-up load transients and (b) step-down load transients.
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ǻYR P9
9&D% 9
9&D$ 9
9&D% 9
7VHWWOH ȝV
7VHWWOH ȝV
9&D$ 9
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&+Y&D% 9GLY
&+L/ $GLY
(a)
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&+aYR P9GLY
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Fig. 9. Waveforms of the augmented buck converter with the proposed resonant circuits and the related load feedforward control under 5 A-size (a) step-up
load transients and (b) step-down load transients.
3433
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