Design and Analysis of a Highly Linear Fully
Differential LNA for SOC
Jiming Jiang
David M Holburn
Department of Engineering
University of Cambridge,UK
Email:jj278@cam.ac.uk
Department of Engineering
University of Cambridge,UK
Email:dmh@eng.cam.ac.uk
Abstract— This paper presents the analysis and design of a
highly linear fully differential LNA based on the modification
of active post distortion method. The analysis focuses on both
nonlinearity and noise performance. The linearisation mechanism
is investigated in terms of low frequency and high frequency
theory based on Power and Volterra series respectively. A
prototype LNA has been designed and is to be implemented
in UMC 0.18 µm CMOS technology. Simulation shows the LNA
achieves 9.7 dBm IIP3 with 16.5 dB power gain, 1.97 dB noise
figure and 15.84 mW power consumption.
I. I NTRODUCTION
System-on-Chip (SOC) integrates functions including digital, analogue and RF circuits into a single chip. It is becoming
a more and more promising solution for modern communication system due to its low cost, power consumption and
high integration feature. In the integration of front-ends with
CMOS for SOC, there exist some stringent requirements.
Firstly, since circuits are integrated in the same substrate,
the circuit must have sufficient abilities to reject the digital
circuitry noise that couples from substrate. Secondly, due to
the dramatically increasing demand of integrating different
functions such as GPS, GSM/3G, and DVB-H into a single
device, power consumption is becoming more and more important and must be minimised. Thirdly, linearity is straightly
with the decrease of power consumption. On the other hand,
linearity is a significant parameter which directly affects many
key performances of the entire system. Unfortunately, without
the use of linearisation technique, it is difficult to achieve good
linearity with insufficient power consumption. At present,
many applied linearisation techniques improve the linearity by
severely damaging the gain and noise of circuit simultaneously.
In contract, the modified superposition (MDS) method [1] is
attractive for the linearity enhancement with little power consumption but also suffering the significant noise penalty due
to the sub-threshold biased FET. At the mean time, the active
post-distortion method [2] does not need any sub-threshold
biased device. However, due to the single-ended structure,
it is difficult to provide sufficient common mode rejection
ratio (CMRR) to prevent the digital circuitry interferes. In
order to cope with these limitations, a modified version of
post-distortion circuit is proposed, as it can be seen in Fig
1. The proposed circuit employs two fully differential pair
rather than two single ended FET in the conventional method,
978-1-4244-5795-3/10/$26.00 ©2010 IEEE
300
Fig. 1.
LNA Schematic
thus it will improve the immunity to the digital circuitry
noise. Furthermore, many linearisation techniques suffer from
the nonlinearity degradation due to the parasitic bonding
wire inductance. After applying the differential structure, such
variation can be resolved, thus resulting in good linearity
compensation.
II. P OWER S ERIES A NALYSIS OF N ONLINEAR
C OMPENSATION
Any nonlinear system can be expanded by Power Series.
For the case of the differential pair M1P/N , the small-signal
current can be expressed in terms of the differential voltage
at the gate, as follows:
2
3
iM1 = g1 vgs1 + g2 vgs1
+ g3 vgs1
(1)
where g1 is the small-signal transconductance and g2 , g3
are the second and third order nonlinear coefficients of M1
respectively.
Assuming the cascode transistors M3P/N are linear, the
differential voltage at the drain node of M1P/N and the
differential drain current of the pair M2P/N becomes:
vM3 = −α
iM2 =
iM1
g1
1
2
3
(g1 Vgs2 + g2 Vgs2
+ g3 Vgs2
)
β
(2)
(3)
where α and β are the ratio of transconductance between
M1P/N and M2P/N , M1P/N and M3P/N respectively. Substituting (2) into (3) and combining iM1 and iM2 , the total
output current itotal can be obtained and 1st and 3rd order
power series coefficients can be calculated as follows:
α
(4a)
g1,total = g1 (1 − )
β
2
2g2,M
α2
α α3
1
g3,total = g3 (1 − −
)+
(4b)
β
β
g1,M1 β
As can be seen from (4b), the first term represents the 3rd
order nonlinearity contribution and the second term indicates
a combination of 1st and 2nd order nonlinearity. Practically,
the second term is always positive; therefore, for the given g1 ,
g2 , g3 , an optimum value of α, β can be calculated from (4b)
α3
to make the term g3 (1 − α
β − β ) negative and neutralise the
positive term, thus compensating the entire nonlinearity.
III. VOLTERRA S ERIES A NALYSIS OF N ONLINEAR
C OMPENSATION
Since the power series analysis does not take memory effect
into consideration it is only valid in low frequency case, to
accurately explain the mechanism at high frequencies, the
method of Volterra series is employed for analysis. It is based
on the analysis of the small-signal equivalent circuit shown in
Fig 2.
The small signal equivalent circuit for Volterra series analysis is depicted in Fig 2, where Z1g is the impedance seen
from the gate of M1P/N , which consisting with bias resistance,
source impedance and impedance matching elements; Z2g is
the impedance at the gate of M2P/N , which is the coupling
capacitance in this case; Cgs1 and Cgs2 represent gate to
source capacitance of M1P/N and M2P/N respectively; Vgs1
and Vgs2 are the voltages across Cgs1 and Cgs2 ; Z1 and Z2
are the source degeneration impedance of M1P/N and M2P/N
respectively; Rtail1 and Rtail2 are the resistances of current
mirror of M1P/N and M2P/N respectively.
The first and second order coefficients of the pair M2P/N
are neglected for simplicity. Without losing of generality in
non-linear analysis, gate-drain capacitance Cgd , body effect
transconductance gmb , and source-drain conductance gds are
also neglected. For further simplification, only the nonlinearity
of M1P/N and M2P/N are considered, thus M3P/N are
assumed to be linear.
In contrast with other publications [1], [5], the Volterra
series analysis in this paper considers the current mirror
resistance RT ail of the differential pair, whereas others neglect
it. Such application of Volterra series to the differential pair
has not been used in other publication.
The expression of IIP3 is given by Volterra series analysis
as follows:
IIP3,2ωa −ωb
2
g1 (1 − α
1
β )|Zg1 (s)sCgs1 + 1|
=
2
6[Z1 (sa )] |g3 (1 − α3 ) − 2g2 (ΛA − α23 ΛB )|
β
3
β
(5)
301
Fig. 2.
Equivalent Circuit of Volterra Series Analysis
where
2Z˜1 (Δs) Z˜1 (2s)
2Z˜2 (Δs) Z˜2 (2s)
+
ΛB =
+
ã(Δs)
ã(2s)
b̃(Δs)
b̃(2s)
a(s) = (Z1g (s) + Z1 (s))sCgs1 + 1 + Z1 g1
g1
b(s) = Z2g (s)sCgs2 + 1 + Z2 (s)sCgs2 + Z2 (s)
β
˜
˜
Z1 = Z1 + 2Rtail1 , Z2 = Z2 + 2Rtail2
ΛA =
(6)
(7)
(8)
(9)
As can seen in the above analysis, once g1 , g2 and g3 are
given, equation (5) can be solved for the optimum value of α
and β, thus achieving the optimum IIP3 . It is worth to note
that the optimum solution obtained from the (4b) is no more
optimum at high frequency, Volterra series analysis is more
accurate to investigate and explain the complicated mechanism
due to the memory effect, and interaction of second order
nonlinearities. In our specific example, given the value of α
is 1.8, the optimum value of β is 7.62 while the power series
analysis suggests 9.14, as shown in Fig 3.
Fig. 3.
Example of Compensation at Low and High Frequency
IV. N OISE A NALYSIS OF P ROPOSED LNA
As can be seen in the Fig 4, the additional canceling path
M2P/N consists of two dedicated noise sources: the gateinduced and drain current noise. The gate-induced noise is
partially correlated to the drain current noise with a correlation
Fig. 5.
Fig. 4.
Output Noise Voltage due to M1P /N
Small Signal Equivalent Circuit of Noise Analysis
coefficient defined as
ing .i
C = nd
i2ng .i2nd
(10)
This coefficient is purely imaginary and the value is 0.395j
for the long channel MOSFET in saturation. By applying the
method used in [3], the total noise current at the output due to
gate-induced and drain current of M2P/N can be appropriated
as
gm
i2n,totalM ≈ 4KT γgdoM2 + ( 2 )2 4KT δggM2
(11)
2
g m3
Similarly to the operation in the conventional CS LNA, the
noise from M1P/N generates a noise current and dedicates
to the output. However, due to the existence of M3P/N , the
noise current creates a correlated noise voltage at VP/N with
1
opposite phases, which approximates to ( gm3
)in,totalM1 . This
noise voltage is then converted to a noise current by M2 thus
canceling the noise from M1 at output. Therefore, the total
root mean square noise current due to M1 at output is:
gm2 2 2
i2n,outputM1 = (1 −
) i
(12)
gm3 n,totalM1
Fig. 6.
Total Output Noise Voltage
figure noise, as shown in equation (13), thus increasing α/β
leads to the improvement of NF. This analysis has been verified
by the simulation shown in Fig. 5, 6 and 7. The first two figures
illustrate the output noise voltage due to M1P/N and total
output noise voltage with bias current of main and cancellation
path respectively, in which either decreasing Ibias1 (current
of M1P/N ) or increasing Ibias2 (current of M2P/N ) results
in a decrease of β and brings about a smaller noise. Fig 7
shows the noise figure of LNA with the varying Ibias1 and
Ibias2.
If neglecting the noise due to cascode transistor M3P/N , the
total noise figure of the LNA can be expressed as follows:
δ g m1 2
|1 + sCgs1 (Rs + Z(s))|2
[(1 + |c|
) γgdoM1
F =
2 R
gm1
5γ gdoM1
s
+(
g m1 2
) δggM1 (1 − |c|2 )
ωCgs1
+
2
γgdoM2 + ( α
β ) δggM2
2
1 − (α
β)
]+1
(13)
Equation (12) indicates the output noise due to M1 can be
partly canceled at the output due to the interaction of M2
and M3 . Similar phenomenon was not observed in [2]. The
noise cancellation strength depends on the ratio α/β. However,
cancellation of the M1 noise can not result in a better noise
figure because the output noise i2o,ns , which is due to source
resistance Rs , is decreased by the same attenuation factor
as M1P/N . Furthermore, due to the attenuation of i2o,ns , the
contribution from M2P/N is actually amplified of the total
302
Fig. 7.
Noise Figure with Different Biasing Currents
V. A 2.1GH Z CMOS LNA D ESIGN
The completed schematic of LNA using proposed method
is designed and realised in UMC 0.18μm CMOS (6M1P)
Process using Mentor Graphics IC Flow Suite, as shown in
Fig 8 and Fig 9. The differential pair M1P/N and M2P/N are
interdigitated for better mutual matching and smaller drainbulk capacitance. Although the use of degeneration inductor
could result in a better input noise matching [4], [3], it
significantly increases the die area, the proposed LNA does
not use any degeneration inductors. The LNA is designed
to achieve the best power matching by utilising the external
matching circuitry. The bias and size of the main differential
pair M1P/N are firstly chosen to achieve accepted noise figure
and sufficient power gain with good input power matching
firstly. Afterwards, the optimum α and β values are designed
in terms of the nonlinear compensation, noise and gain based
on the analysis and simulation. The control of α and β are
realised through the selection of the size of M3P/N and the
bias current of M2P/N . The size of M1P/N , M2P/N and
M3P/N are 120μm/0.18μm, 25μm/0.18μm, 50μm/0.18μm
respectively and the bias current for M1P/N and M2P/N are
8.4mA and 0.4mA.
Fig. 10.
Simulated IIP3 with various input power level
Fig. 11.
Fig. 8.
Simulated performance with bias current
Fig 11 summarises the complete post-layout simulation
results, in which the proposed LNA achieves 9.7dBm IIP3,
16.5dB power gain, 1.97dB noise figure, and 15.84mW power
dissipation.
Schematic of 2.1 GHz LNA
VII. C ONCLUSION
A LNA using modified version of active post-distortion
method is proposed. The nonlinearity and noise performance
of the designed LNA have been investigated in this work. The
linearisation mechanism is explored by using Power series and
Volterra series respectively and an optimised performance is
achieved. A highly linear, low power differential LNA suitable
for SOC has been designed and implemented in UMC 0.18 μm
CMOS technology. Simulation result shows the improvement
of linearity is more than 12dB with 0.72 mW extra power
consumption.
Fig. 9.
R EFERENCES
Layout of 2.1 GHz LNA
VI. S IMULATION R ESULTS
Simulation shows this LNA can achieve significant linearity
improvement. In Fig 10, it illustrates IIP3 simulation under
two bias conditions: in one, the cancellation path is biased
into operation; in the other, only a single differential pair
is in operation, in effect grounding the sub differential pair
(M2P/N ). Fig 10 shows that IIP3 is improved by this means
from -2.3 dBm to 9.7dBm, which achieves 12 dB improvement
with limited additional power consumption.
303
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