Pin, Differential Pair and Sub-Part Swapping
Related Training Videos
How do I use FPGA Pin Swapping during PCB layout?
Contents
Configuring Swap Groups
Pin Groups
Part Groups and Sequence IDs
Pair Groups
Controlling How the Swaps are Performed on the Schematic
Enabling Pin, Pair and Part Swapping on the PCB
Swap Manager Dialog
Performing Pin, Pair and Part Swaps
Interactive Pin, Pair and Part Swapping
Automatic Pin/Net Optimizer
Passing the Changes Back to the Schematic
Pushing the Changes from the PCB to the Schematic
Taking Advantage of the New Pin/Part Swap System with FPGA Designs
Working in harmony with Altium Designer's interactive routing and BGA escape routing capabilities is the pin, pair
and part swapping system. This feature provides all the benefits of traditional pin-swapping systems, but takes
advantage of Altium Designer's intimate understanding of the net assignments in the design to lift pin swapping to a
new level. During a pin swap operation Altium Designer analyses the net assigned to the chosen pin, and
dynamically reassigns the net on the pin and any connected copper.
This level of functionality means that partially routed nets and pre-routed multilayer escapes from complex BGA
devices can be swapped. Differential pairs can also be swapped, taking advantage of the knowledge about
differential pin-pairs on FPGAs.
At the PCB level the system includes a powerful automatic optimizer that uses this information to dynamically
re-assign nets to improve routability. For example, the system can perform a reconnect on multiple devices that
have been escape routed on multiple layers. It will assign these based on matching escape route layers, shortest
Manhattan routing distance, and minimum number of crossovers on each layer.
The addition of partial routed net swapping, along with the automatic optimizer gives you the ability to adopt a
hierarchical and iterative routing strategy, escape routing devices first, then routing to the edge of a given area, and
then finally connecting these sections together. At any time, the automatic swapper can be re-run to re-optimize,
based on the updated information provided by the partially routed nets.
There are three categories of swapping: Pin Swapping, Differential Pair Swapping and Subpart Swapping.
Configuring Swap Groups
For each category of swapping swap groups dictate what can be and what can not be swapped within a component.
In the case of pin swapping, pins within a component that share a common pin group are able to be swapped with
one another. Similarly for pair swapping and part swapping it is the pair group and part group values that determine
that a differential pair or sub part can be swapped respectively.
The swap groups for a component are configured in the 'Configure Pin Swapping' dialog, shown in Figure 2. It is
accessible by right clicking on the component in the Schematic or PCB editors and selecting the Part
Actions->Configure Pin Swapping.. or Component Actions->Configure Pin/Part Swapping menu items respectively.
The Configure Pin Swapping dialog can also be accessed through the Swap Manager Dialog.
Figure 2. Setting up the pin swap groups in the Configure Pin Swapping dialog for a Dual 5-Input NOR Gate component.
Pin Groups
A component pin is swappable with another pin in that component when it belongs to the same pin group (has the
same pin group value). The pin group is an attribute of each pin in the component and its value can be any
alphanumeric string. The pin groups for the entire component are set up in the Configure Pin Swapping dialog, as
shown in Figure 2.
Figure 3. Schematic containing a Dual 5-Input Positive-NOR Gate component. Each of the input pins for either sub parts are
logically equivalent and presenting an ideal situation for pin swapping.
Considering the schematic of Figure 3 which contains the two 5-Input NOR Gates for the SNJ54S260 component
(the component can be found in the TI Logic Gate 2.IntLib library that ships with Altium Designer), each of the nets
INA0 to INA4 can be swapped with each other due to the nature of the NOR Gate. Similarly each of the nets INB0 to
INB4 can be swapped, however a INAx net can not be swapped with a INBx net.
The swapping constraints for the NOR gate are defined in the Configure Pin Swapping dialog shown in Figure 2.
Giving the nets INAx the swap group 1, and the nets INBx the swap group 2 ensures that swapping will only be
preformed by the system in such a way that it is consistent with the component logic.
Leaving the Pin Group value for a pin empty means it is unavailable for swapping. In the case of Figure 2 it does not
make sense to interchange the output and power pins (Designators 5,6,7 and 14) with each other and so the pin
group is left blank.
Part Groups and Sequence IDs
It is common for a component to consist of multiple functionally equivalent subparts. Part swapping allows the nets
of such equivalent sub-parts to be swapped. Consider again the component of Figure 3. Both NOR gates offer
identical functionality and the nets (INA0, INA1, INA2, INA3, INA4, OUTA) are able to be swapped with nets (INB0,
INB1, INB2, INB3, INB4, OUTB).
Part swapping for a component is configured with the part group and sequence ID attributes. These are both text
attributes and are accessible in the Part tab of the Pin Swapping dialog. Figure 4. displays the part group and seque
nce ID settings corresponding to the component in Figure 3. The part group indicates which sub-parts are able to be
swapped with one another. The two sub-parts in Figure 3 are able to be swapped and consequently in Figure 4 their
part groups are given the same value of 1.
The sequence ID attribute determines equivalence of the pins between swappable sub-parts. In the NOR gate
example it is important that the input pins are not interchanged with the output pins when a part swap occurs. Figure
4 shows the sequence ID are set so that OUTA swaps with OUTB, INA0 swaps with INB0, INA1 swaps with INB1
and so on.
Figure 4. Setting up part swap groups in the Configure Pin Swapping dialog for a Dual 5-Input NOR Gate component.
Note that Part Swapping is only available for components designed as sub-parts as it is based upon swapping all
the nets between two sub-parts.
Pair Groups
The swapping of differential pairs is governed by the value of the pair group for a differential pair. The pair group attri
bute is accessed in the 'Differential Pair Swapping' tab of the Configure Pin Swapping dialog. There are three modes
in the 'Differential Pair Swapping' tab that can be set by the drop down box in the lower left corner.
Show Pairs From Directives - The system will use differential pair directives placed on the schematic to
populate the differential pairs in the table.
Show Pairs From FPGA - The system will use differential pair data obtained from FPGA information avaiable
to the component to pair up the pins. Note that this mode is available when the component is an FPGA.
Show All Pins - The system will display all the component pins.
Figure 5. Setting up Pair Swap groups in the Configure Pin Swapping dialog
Controlling How the Swaps are Performed on the Schematic
In the PCB editor pin, pair and part swaps are performed by exchanging nets on component pads and
corresponding copper. When the changes are merged into the schematics there are two ways that a pin swap can
be handled, either by swapping the pins on the component symbol, or by swapping net labels on the wires attached
to the pins. Each approach has its advantages and disadvantages.
Swapping the pins will always work on the schematic, but it may mean that this instance of the component symbol is
no longer the same as it was defined in the library. In this situation it means the symbol cannot be updated from the
library, and it also means that other instances of the same component in this design will have a different pin
arrangement, a possible source of confusion to someone reading the schematic. This approach is ideal for simple
components, such as a resistor arrays.
Performing the swap on the schematic by swapping net labels can only be done if the connectivity is established
through the net labels, that is, if the pins are not hard-wired together. The advantage of this approach is that the
component symbol does not change, and can be updated from the library at a later date. This approach is the best
choice for a complex component, such as an FPGA, where physically moving two pins on the symbol could result in
an I/O bank-based symbol presenting incorrectly.
Selecting which of these two approaches is used is determined by the Allow Pin Swapping Using these Methods
options in the Options for Project dialog, as shown in Figure 6.
Figure 6. Project options governing how pin swaps are updated in the schematic documents. Found in the menu item
Project->Project Options under the Options tab.
Enabling Pin, Pair and Part Swapping on the PCB
The swap group attributes needed to setup pin, pair and part swapping within a component are stored in the
Schematic components. However it is the PCB editor where this information is used and each PCB component has
an option to allow pin swapping of its pins.
The swapping options for each PCB component can be configured in the component properties dialog (accessible
by double clicking on the component or right clicking and selecting properties) under the 'Swapping options section'.
These options can also be found in the PCB Inspector Panel.
Swap Manager Dialog
The Swap Manager lists all components used in the design (or library), with their current swap settings. The PCB
editor Swap Manager includes additional columns for enabling/disabling swapping on each component on the board.
The swap manager dialog is found in the tools menu of the Schematic, Schematic Library and PCB editors under
the 'Configure Pin Swapping' command.
Figure 7. Swap Manager dialog
The Swap Manager includes a powerful right-click menu, making it very easy to quickly copy the settings from one
component to another, or enable/disable multiple components in a single click.
Double clicking on a component in the Swap Manager will open the Configure Pin Swapping dialog for that
component, where you can define the swap group settings for pins, differential pairs and subparts.
Performing Pin, Pair and Part Swaps
Interactive Pin, Pair and Part Swapping
Interactive swapping allow pins, differential pairs or subparts to be swapped one at a time in the PCB editor. The
interactive swapping commands are found in the Tools » Pin/Part Swapping sub-menu. Once the command is
selected from the menu the pins that are available for swapping are highlighted. The steps required to preform a
swap are displayed on the Status line;
1. The first step is to select one of the highlighted pins that will become the source of the pin swap. In the case
of pair or part swapping the differential pair or sub-part that the pin belongs to will be subsequently swapped.
2. The second step is to select the target pin for the swap. For pair or part swapping this pin will be
representative of a differential pair or a sub-part.
Continuing with the example of Figure 4 the stages of interactively part swapping the Dual 5-input NOR gate
component are shown in Figures 8 and 9. There are two subparts that can be swapped and so each of their five pins
can be selected in Figure 7. Pin 8 is selected corresponding to the subpart U2B. The system then highlights the pins
of subpart U2A that can be swapped.
Figure 8. The first step in using the interactive pin swapper is to select a pin to be swapped. The pins that are available to be swapped are
highlighed
Figure 9. The second step in using the interactive pin swapper is to select a pin to be the target of the pin swap.
Automatic Pin/Net Optimizer
The Automatic Pin/Net Optimizer is a two-stage tool. Select Tools » Pin/Part Swapping » Automatic Pin/Net
Optimizer from the PCB editor menu to perform an automatic optimization.
The Automatic Pin/Net Optimizer first runs a fast single-pass optimizer that attempts to minimize cross overs and
connection lengths, but may actually increase them. When this is complete you will be asked if you want to run the
iterative optimizer. The iterative optimizer will perform multiple passes in an attempt to reduce the number of cross
overs and connection lengths.
Passing the Changes Back to the Schematic
When you configure the swap groups in the Configure Pin Swapping dialog the edits you make are immediately
applied to the schematic components, regardless of which editor was active when the command was launched.
However design changes that are a result of you performing a pin, differential pair or subpart swap in the PCB editor
are propagated back to the schematic using the standard Design Update process.
Pushing the Changes from the PCB to the Schematic
Pin, pair and part swaps are passed back to the schematic in the same way that other design changes are
transferred - by selecting Design » Update from the menus. Depending on how the Allow Pin Swapping options are
configured, pin swaps will be performed as:
Change Pin Names - this change will move the pins on the symbol. The pins are not actually moved on the
symbol, internally the definition of the two pins are swapped over, however, visually it will appear that the two
pins have moved, swapping locations.
Move Pins to Different Nets - this change will swap the net labels on the attached wires
Change Sub-Part ID - this change will simply change the sub-part index when a part swap is performed.
Figure 10. The image above shows a pin swap resolved in the schematic by changing net names.
Figure 11. The image above shows a pin swap resolved in the schematic changing the pin names. This is not always the best
solution, for an FPGA moving the pins to a different net by moving the net labels is a better solution, as shown in the image below.
If the schematic does not udpate to show swapped pins or parts, press the END key to refresh the display.
Taking Advantage of the New Pin/Part Swap System with FPGA Designs
Other than the obvious advantages that intelligent pin, pair and part swapping provides, the ability to swap partially
routed sub-nets brings a new dimension to swapping, that is ideal for working with large capacity FPGAs. The
dynamic net re-assignment allows you to use a multi-stage design process, with progressively refined pin/net
assignments.
Initial I/O Assignment
In this stage the FPGA's and other device pins have their net assignments setup in whatever way is easiest at the
schematic level. Usually this means just adding net labels in numeric bus order to the pins on the FPGA. The Smart
Paste feature in the Schematic Editor is ideal for doing this.
Initial Connection Optimization
The design can be transferred to PCB layout, where there will be a lot of connection crossovers because of the
random assignment at the schematic level. Running the Automatic Net/Pin Optimizer command will quickly provide
a large reduction in the number of crossovers. The result does not need to be ideal yet, it is just to make things a
more visually manageable at the PCB level.
Escape Routing
Fanout and Escape routing can now be performed on large devices on the PCB (right-click on the component to
selectively perform fanout/escape routing). This may worsen the previously optimized assignments, but that does
not matter at this point.
Escaped Connection Optimization
Run the automatic optimizer again, this time it will take advantage of the pre-routed sections of fanout/escape
routing.
Manual Routing
You can now treat the ends of the escape routes as 'targets' to route towards. Ignoring the actual connection lines,
you can route from the other ends of the nets toward the nearest escaped I/O route (spatially and by layer) on the
PCB, rather than the one that is on the same net. The connections will not line up, instead you will end up with a
series of small gaps between the escape routing from the FPGA I/O pins and your routing coming from other parts
of the PCB. Figure 14 shows a simple example of this.
Final optimization
Run the automatic optimizer again and it will assign the routed subnets to the closest possible escaped I/O pin. This
will leave you with a set of very short connections to complete. The automatic optimizer has special routines to
produce a good result in this case. These can now be interactively or automatically routed.
Manual Pin Swaps
Use the interactive swapper to perform any specific pin swap changes that you need.
Propagate Changes Back to Schematic
When you are ready to propagate these pin assignments back to the schematic, it is a good idea to disable pin
changes on the schematic symbols. This is because FPGAs are often presented as multi-part components, with
each bank of pins being a separate schematic part. Moving pins from one part to another would result in these
symbols becoming logically incorrect, as the bank symbol would include pins that did not belong in that bank. In this
situation performing pin swaps by changing net labels is the correct approach.
Repeat as Often as Required
This process can actually be run as many times as required, and at any time during the design process.