US 20090168493A1
(19) United States
(12) Patent Application Publication (10) Pub. No.: US 2009/0168493 A1
Kim et al.
(54)
(43) Pub. Date:
SEMICONDUCTOR MEMORY DEVICE WITH
STACKED MEMORY CELL AND METHOD
Publication Classi?cation
(51)
algl?g?gFéEcLTLURlNG THE STACKED
(75) Inventors:
Int Cl
G11C 11/00
(2006.01)
Sung-min Kim, lncheon
H01L 21/00
H011‘ 47/00
(2006.01)
(200601)
Yun,
HWaseong-si
Metropolitan
Seoul (KR);Jong-soo
Du-eung
Eun-jung
s60’
Kim,
U.S.
............... ..
Yongin-si (KR); Beak-hyung Cho,
(57)
HWaseong-si (KR); Byung-seo
In a semiconductor memory device and method, resistive
Kim, SuWon-si (KR)
of control transistors formed on different layers and variable
resistance devices comprising a resistive-change memory.
Each resistive-change memory cell includes a plurality of
MILLS & ONELLO LLP
ELEVEN BEACON STREET, SUITE 605
BOSTON, MA 02108 (US)
SAMSUNG ELECTRONICS
CO., LTD, SuWon-si (KR)
(21) Appl. No.:
12/273,225
(22) Filed:
Nov. 18, 2008
ABSTRACT
change memory cells are provided, each including a plurality
Correspondence Address:
(73) Assignee:
Jul. 2, 2009
control transistors formed on different layers, and a variable
resistance device formed of a resistive-change memory. In
one example, the number of the control transistors is tWo. The
semiconductor memory device includes a global bit line; a
plurality of local bit lines connected to or disconnected from
the global bit line via local bit line selection circuits Which
correspond to the local bit lines, respectively; and a plurality
of resistive-change memory cell groups storing data While
being connected to the local bit lines, respectively. Each of the
resistive-change memory cells of each of the resistive-change
memory cell groups comprises a plurality of control transis
Related US. Application Data
(63) Continuation-in-part of application No. 11/238,381,
tors formed on different layers, and a variable resistance
?led on Sep. 29, 2005, noW Pat. No. 7,453,716.
device formed of a resistive-change memory. In addition, the
(30)
semiconductor memory device has a hierarchical bit line
structure that uses a global bit line and local bit lines. Accord
Foreign Application Priority Data
ingly, it is possible to increase both the integration density of
Oct. 26, 2004
(KR) ...................... .. 10-2004-0085804
the semiconductor memory device and the amount of current
Apr. 26, 2005
(KR) ...................... .. 10-2005-0034552
?owing through each of the resistive-change memory cells.
700
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Patent Application Publication
Jul. 2, 2009
Sheet 1 0f 18
US 2009/0168493 A1
FIG. 1 (PRIOR ART)
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Patent Application Publication
Jul. 2, 2009
Sheet 2 0f 18
FIG. 2 (PRIOR ART)
BL
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US 2009/0168493 A1
Patent Application Publication
Jul. 2, 2009
Sheet 3 0f 18
US 2009/0168493 A1
FIG. 3A
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Patent Application Publication
Jul. 2, 2009
Sheet 4 0f 18
US 2009/0168493 A1
FIG. 4A
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FIG. 5
Jul. 2, 2009
Sheet 5 0f 18
US 2009/0168493 A1
GBL
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Patent Application Publication
Jul. 2, 2009
Sheet 6 0f 18
US 2009/0168493 A1
FIG. 6A
CF11
FIG. 6B
Patent Application Publication
Jul. 2, 2009
Sheet 7 0f 18
US 2009/0168493 A1
FIG. 6C
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Sheet 8 0f 18
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Jul. 2, 2009
Sheet 9 0f 18
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FIG. "7C
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Patent Application Publication
Jul. 2, 2009
Sheet 11 0f 18
US 2009/0168493 A1
FIG. 9A
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Jul. 2, 2009
Sheet 12 0f 18
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FIG. 9C
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Sheet 13 0f 18
US 2009/0168493 A1
FIG. 10
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Patent Application Publication
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Sheet 14 0f 18
US 2009/0168493 A1
FIG. 13
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Patent Application Publication
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Sheet 15 0f 18
US 2009/0168493 A1
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Jul. 2, 2009
Sheet 16 0f 18
US 2009/0168493 A1
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Sheet 17 0f 18
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Jul. 2, 2009
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US 2009/0168493 A1
Jul. 2, 2009
US 2009/0168493 A1
SEMICONDUCTOR MEMORY DEVICE WITH
STACKED MEMORY CELL AND METHOD
OF MANUFACTURING THE STACKED
MEMORY CELL
[0010] FIG. 2 is a circuit diagram of a phase-change
memory array 100 comprising a plurality of phase-change
memory cells 10 equivalent to the phase-change memory 10
of FIG. 1. The plurality of phase-change memory cells 10 are
connected to a bit line BL Which is connected to a sense
RELATED APPLICATIONS
[0001] This application is a continuation-in-part applica
tion ofU.S. Ser. No. 11/238,381, ?led Sep. 29, 2005, Which
claims the priority of Korean Patent Application Nos.
10-2004-0085804, ?led on Oct. 26, 2004 and 10-2005
0034552, ?led on Apr. 26, 2005 in the Korean Intellectual
Property O?ice. The disclosures of all the above applications
are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
ampli?er (not shoWn).
[0011] The PRAM has lately attracted considerable atten
tion as a next-generation memory. HoWever, integrity of the
PRAM needs to be improved in order for the PRAM to be
competitive With other types of memory, such as Dynamic
Random Access Memory (DRAM), Static Random Access
Memory (SRAM), and ?ash memory.
[0012] As described above, data is Written to the PRAM by
heating the PRAM using Joule heat. HoWever, there is a
restriction to reducing a siZe of a control transistor of a con
memory device, and more particularly, to a semiconductor
memory device With a stacked memory cell.
ventional memory cell, Which supplies current required to
generate the Joule heat, thereby preventing an increase in the
integration density of the PRAM.
[0013] Accordingly, there is a groWing requirement for a
cell structure that can increase the integration density of the
[0004]
PRAM and an improvement of the con?guration of a semi
[0002]
[0003]
1. Field of the Invention
The present invention relates to a semiconductor
2. Description of the Related Art
[0005] A Phase-change random Access Memory (PRAM)
conductor memory device using the improved cell structure.
is formed of a phase-change material such as a chalcogenide
alloy that changes into a ?rst of tWo phases When it is heated
and cooled, and changes into a second phase When it is heated
and cooled again. Here, the tWo phases are crystalline and
amorphous phases. The PRAM is disclosed in US. Pat. Nos.
6,487,113 and 6,480,438. The PRAM has a loW resistance
value When it becomes crystalline, and a high resistance value
When it is amorphous. A logic value can be determined as 0 or
1 according to the resistance value of the PRAM. The crys
talline phase of the PRAM corresponds to a set state or has a
logic value of 0, and the amorphous phase thereof corre
sponds to a reset state or has a logic value of 1.
[0006] To change the phase of the PRAM into the amor
phous phase, the PRAM is heated to a temperature greater
than a melting temperature of the PRAM and rapidly cooled
doWn. To change the phase of the PRAM into the crystalline
phase, the PRAM is heated to a temperature loWer than the
melting temperature for a predetermined time.
[0007] A key point to the PRAM is that it is formed of a
phase-change material such as chalcogenide. In general, the
phase-change material is a GST alloy composed of germa
nium (Ge), antimony (Sb), and tellurium (Te). When the GST
alloy is heated or cooled, its state rapidly changes betWeen the
amorphous state (reset state) and the crystalline state (set
SUMMARY OF THE INVENTION
[0014] The present invention provides a phase-change
memory cell With improved integration density.
[0015]
The present invention also provides a semiconduc
tor memory device With such a random change access
memory (PRAM) cell.
[0016] According to an aspect of the present invention,
there is provided a phase-change memory cell comprising a
plurality of control transistors formed on different layers, and
a variable resistance device formed of a phase-change mate
rial.
[0017]
In one embodiment, the number of control transis
tors is tWo.
[0018]
In another embodiment, the control transistors
include a ?rst control transistor Which is a bulk transistor, and
a second control transistor Which is formed on the ?rst control
transistor and is a thin layer transistor.
[0019]
In another embodiment, the control transistors fur
ther include a third control transistor formed on the second
control transistor. The control transistors may be MOS tran
sistors, and form a diode. The control transistors may option
state), that is, its logic value is sWitched betWeen 1 and 0.
ally comprise bipolar transistors. The second control transis
Therefore, the GST alloy is useful as a material for a PRAM
memory device.
[0008] To Write data to a memory cell of the PRAM, the
chalcogenide is heated to a temperature equal to or greater
tor may be formed on the ?rst control transistor. The variable
than its melting temperature and rapidly cooled doWn to place
the chalcogenide in an amorphous state. Otherwise, chalco
tion, there is provided a semiconductor memory device com
genide is heated at a temperature less than the melting tem
perature, maintained at the temperature, and cooled to change
the chalcogenide into a crystalline state.
[0009] FIG. 1 is a circuit diagram of a conventional phase
change memory cell 10 disclosed in US. Pat. No. 5,883,827.
The memory cell 10 includes a phase-change variable resis
tance device R1, a ?rst terminal of Which is connected to a bit
line BL and a second terminal of Which is connected to a drain
of a selection transistor N1, and the selection transistor N1
Whose gate is connected to a Word line WL and Whose source
is connected to a reference voltage VSS.
resistance device may comprise germanium (Ge), antimony
(Sb), and tellurium (Te).
[0020]
According to another aspect of the present inven
prising a global bit line; a plurality of local bit lines connected
to or disconnected from the global bit line through local bit
line selection circuits Which correspond to the local bit lines,
respectively; and a plurality of phase-change memory cell
groups storing data When connected to the local bit lines,
respectively. Each of the phase-change memory cells of each
of the phase-change memory cell groups comprises a plural
ity of control transistors formed on different layers, and a
variable resistance device formed of a phase-change material.
[0021] In one embodiment, the local bit line selection cir
cuits are transistors Which connect the local bit lines to the
global bit line or disconnect the local bit lines from the global