EE671
I.M. Filanovsky
Lecture No 2
Characteristics and Design of Passive IC components
I. Resistors
1. Properties of resistive layers
Design of resistors requires knowledge of properties of the resistive layers allowed in a
given technology. The following table (which has a lot of gaps and does not pretend to be
complete) is prepared using different sources available in literature.
Table 2-1. Properties of resistive layers and resistors
Technology
Layer
Resistivity, Resitor
tolerance
Ω/square
(±3σ)
General CMOS
BiCMOS 0.8µm
BiCMOS 0.8µm
BiCMOS 0.8µm
CMOS 0.35µm
CMOS 0.35µm
General CMOS
Resistor
temperature
coefficient
ppm/oC
1000
Resistor
matching
(dog-bone
design)
Gate PolySi
Gate PolySi
PolySi
Base
diffusion
PolySi
n+ diffusion
n-well
1-20
32
750
100
±30%
±21%
±27%
-351
1340
0.81%
0.82%
95
75
1000-10000
±30%
±30%
50-80%
722
1473
3000-5000
±5%
±5%
metal (Al)
interconnect
0.05
3900
2. Design of passive resistors
Two basic shapes are used in RF circuit design (Fig. 2-1): dog-bone design (a) and
meandering design (b). For both design the minimal size of contact is determined by the
design rules established by manufacturer (say, for 0.35µm technology, the contact size is
0.4X0.4µm2), the overlap size depends on the chosen layer and is also established by
manufacturer (say, 0.25µm). The resistor minimal width is also established by the design
rules. Increase of resistor width improves the resistor precision and, especially, matching,
yet, simultaneously increases the resistor capacitance and reduces the resistor frequency
range. The resistor values higher than 30-40 kΩ should be avoided even in bias circuits.
W
The resistor value is determined by the ratio n =
which is called the number of
L
squares (not necessary an integer). For the dog-bone design
R = ρ n + 2 Kρ
(2-1)
where ρ is the layer resistivity, and K is the contact resistance coefficient. For the
meandering design one has to take into consideration the corner squares (they are shown
in Fig. 2-1, b in gray color), and to calculate resistor value as
R = ρ n + K 1 n1 ρ + 2 Kρ
(2-2)
1
Here n1 is the number of corner squares, C is the corner square resistance coefficient. In
many cases one can consider that K = 0.5 and K 1 = 0.56 .
Example. Assume that resistors shown in Fig. 2-1 are fabricated in BiCMOS 0.8µm
technology. Find the resistor values. Assume polysilicon resistors.
a) The resistor includes 16 resistive squares and two contacts. The resistance of one
square is 750Ω. Hence, the resistor value is
R=16*750+2*0.5*750=12750 Ω (12.75 kΩ)
b) The resistor includes 34 resistive squares, 12 corner squares and two contacts. The
resistance of one square is 750Ω. Hence, the resistor value is
R=34*750+16*0.56*750+2*0.5*750=32970 Ω (32.97 kΩ)
2. MOS transistors used as resistors
Using of a MOS transistor as a resistor is a standard tool of design in low frequency
circuits (voltage-controlled transconductance amplifiers for application in continuous and
switched-capacitor filters). Their application in RF circuits is more questionable (see
capacitors and capacitance calculations).
MOS transistor, in this case, is used in triode operation. The resistance is determined by
the formula
W
rds = {µ C ox ( )[(VGS − VT ) − VDS ]}−1
(2-3)
L
Here VGS and VDS are static gate-source and drain-source voltages, VT is the threshold
voltage, and rds is the dynamic (ac) impedance. This result does not take into
consideration the body effect (which depends on the VDS voltage). More exact result
(Tsividis, 1987) is
W
rds = {µ C ox ( )[(VGS − VT ) − α VDS ]}−1
(2-4)
L
where α = 1.7 (this coefficient, in general, depends on technology and transistor length).
The mobility µ n ≈ 500cm2/V*s, µ p ≈ 200cm2/V*s, the capacitance per unit area, C ox ,
see below.
It is considered (Lee, 1998) that MOS resistor can be used as a resistor of a very loose
tolerance (the tolerance of mobility, µ , is usually unknown, the tolerance of 10-15% for
the threshold voltage, as was established by the author, is considered normal by many
manufacturers) and strongly temperature dependent (the temperature dependence of
mobility is given by the formula
1
µ∝ a
(2-5)
T
where α = 1.5-2.5, the temperature dependence of threshold voltage is given by
VT = VT 0 + α T (T − T0 )
(2.6)
where α T = -1.4 to -2 mV/oC).
Yet, one remark should be given. As follows from the mentioned figures, the mobility
and threshold voltage, in general case, decrease with temperature. It means that in certain
technologies one can have mutual compensation of influence of these parameters on the
resistor values, and obtain temperature independent resistors. The fact of possible
compensation was well known in JFET transistors (and used for temperature stable
2
operational amplifiers, see, for example, Dostal, 1997), yet, it was practically overlooked
by CMOS circuit designers (it was mentioned only by Manku, 1995). The author used
this mutual compensation in transconductance characteristics of CMOS 0.35µm
technology for design of a voltage reference, the experimental verification is yet to be
established.
II. Capacitors
1.Standard capacitors
Many technologies allow inclusion of capacitors in the fabrication process. Usually this
capacitor is located on the field oxide, and the dielectric used is close in properties and
thickness to the gate oxide. The bottom and top plates are of polysilicon. The
approximate value of this capacitor is equal to
C = C oWL
(2-7)
where C o is the capacitance per unit area (for example, for BiCMOS technology
C o = 1.9fF/µm2, for CMOS 0.35µm technology C o = 4.6fF/µm2 , notice that the inverse
proportionality is approximately correct, the reduction of the smallest device feature
involves the approximate proportional oxide thickness).
To take into consideration the fringe effect one uses the formula
C = C oWL + 2C fr (W + L)
(2.8)
where C fr is the fringe capacitance (in fF/µm, notice change of the unit). If C fr is not
given, one can use the approximation C fr ( fF/µm) ≈ 0.1 C o (fF/µm2).
Finally, if the oxide thickness is only given one can use the common sense formula
WL
C ≈ε
(2-9)
t
where ε = ε o K ox ≈ 0.35pF/cm, with the silicon oxide relative dielectric constant
K ox = 3.9 and ε o = 8.86*10-14F/cm. The fringe effect may be approximately taken into
consideration by the formula
(W + 2t )( L + 2t )
(2-10)
C ≈ε
t
(more detailed calculation of the fringe effect see below).
Finally, one can mention the following parameters of the standard capacitors. The
temperature coefficient of the capacitance is about 30-50ppm/oC (low), voltage
coefficient is about 100ppm/oV (low), and the bottom plate parasitic capacitance about
5% (small).
2. Lateral flux capacitors
Lateral flux capacitors are used in technologies that do not have a special capacitance
layer. The lateral flux capacitor (Fig. 2-3) is using a lateral flux between two adjacent
pieces of silicon or metal which do not touch each other. The capacitance is calculated
using the formula
C = C olat L gap
(2-11)
where C olat is the unit capacitance (for gate polysilicon layer of BiCMOS technology
this value is about 0.2fF/µm) and L gap is total length of the gap. Lateral flux capacitors
3
appear in the cheapest (one metal layer) MOS technologies. Using the so-called fractal
patterns (i.e. self-repeatable scaled patterns) one can design relatively large (up to 5 pF)
capacitors.
3. MOS gate capacitors
MOS gate capacitors usually have the same capacitance per unit as the standard
capacitance (i.e. C ox =1-5 fF/µm2) and the same temperature coefficient (about 3050ppm/oC). Yet, they are closer to substrate (in fact, they are on the substrate), and their
electric circuit (Fig. 2-4) include losses. To reduce the losses it is desirable that the
transistor operates in the region of strong inversion (i.e. the gate voltage should be high)
and triode operation, and the device should be designed as a small channel length device.
These requirements maximize the capacitor quality factor, Q, which is
1
4
Q=
≈
(2-12)
ωRoe C ω rds C
The MOS gate capacitor may be used as bypass capacitor between analog and digital
areas of the chip.
4.Junction capacitance
The most frequently used junction capacitor in CMOS technology is the junction
capacitor created using the p+ layer and n-well (Fig. 2-5, a). The capacitance of this
capacitor can be calculated as
C j0
Cj =
(2-13)
n
 VF 
1 −

φ 

Here C j 0 is the capacitance per unit area, n=1/2 for abruptly diffused junctions and n=1/3
for graded junctions, V f is the bias voltage across the capacitor, φ is the built-in
potential(for example, for BiCMOS 0.8µm technology C o =0. 4 fF/µm2, n=1/2,
φ =0.9V). The capacitor is used for tuning purposes (for example, in VCO oscillators),
and one of the most important parameters of this capacitor is its temperature coefficient,
1 dC
, which changes from 200ppm/oC for large negative bias to 1000ppm/oC for small
C dT
positive bias. This figure can be obtained the following way. It is known that
C j0
for abrupt junctions, and
 ε qN 

= 
 2 |φ |
1/ 2
(2-14)
1/ 3
 ε 2 qa 

C j 0 = 
(2-15)
 12 | φ | 
for graded junctions. In (2-14) and (2-15) ε = ε Si and φ are temperature dependent
1 dε Si
1 d |φ |
parameters (the temperature coefficients are
≈ 250 ppm/oC and
=
ε Si dT
|φ | T
(-1000 to –3000 ppm/oC). Other parameters: the electron charge q, the average
4
NAND
, and the slope of dopant concentration a may be considered
NA + ND
as temperature independent (the result (2-15) assumes that in the vicinity of the p-n
junction the dopant concentration may be approximated as N A = − a ( y − yi ) | y ≤ yi and
concentration N =
N D = a( y − y i ) | y ≥ yi ). Then, denoting n=1/r one can write that
C j0 = B
(ε
r −1 n
)
φn
=B
ε 1− n
φn
(2-17)
and
C j (VF ) = B
ε 1− n
(φ − VF ) n
(2-18)
Differentiating (2-18) one finds
dε
dφ 

(1 − n)ε − n (φ − VF ) n
− n(φ − VF ) n −1 ε 1− n
1 dC j (φ − VF ) n 
dT
dT 
=
B

1− n
2n
C j dT
(φ − VF )
Bε

 (2-20)


1 dε
1
1
dφ
= (1 − n)
−n
= (1 − n)TC Si − n
TCφ
ε dT
(φ − VF ) dT
(1 − V F / φ )
This voltage dependence of the capacitor temperature coefficient should be considered in
VCO design.
5. Interconnect capacitance
Parasitic capacitors of interconnects become important at RF. The formula for calculation
of parallel plates capacitor is not satisfactory. Three particular cases are most important.
a) Single conductor over ground plane (Fig. 2-6). The results of calculation and
approximation of calculated results by different formulas are compiled in Table 2-2
Table 2-2 Capacitor of single wire over single conducting plane
Authors
Capacitance per unit of length
Examples,
dimensions in µm
W=1.36 W=2.38
H=1.65
H=0.87
T=0.8
T=0.3
0.115
0.190
MeijsFokkema
W
 W  0.25  T  0.25  
C MF ≈ ε  + 0.77 + 1.06   +    
 H   
 H
 H 
SakuraiTamaru
0.222
W

W
T 
C ST ≈ ε  + 0.15 + 2.8 

H
H
 H

0.115
0.185
YuanTrick
W
T 
2π
CYT ≈ ε  +
−

 H ln 1 + (2 H / T )(1 + 1 + T / H ) 2 H 
W
C ≈ε
H
0.114
0.172
0.028
0.094
Parallel
plates
[
]
5
Permittivity of SiO2 ε ox ≈ 3.5*10 -13 F/cm
Capacitance in fF/µm
One can notice that the parallel plates component is only a small fraction of total
capacitance when W and H are comparable (from one quarter to one half). To evaluate
the maximal frequency of interconnection one has to evaluate the RC product per unity of
length. When fringing is significant, it is possible to obtain substantial reduction in RC
product by increasing width, since fringe capacitance grows only slowly with width while
R decreases in direct proportion.
b) Wire sandwiched between two conducting planes (Fig. 2-7).
The capacitance of a wire between two conducting planes is calculated on the basis of
Table 2-2. The considered capacitance can be approximately calculated as a sum of two
parallel capacitances. Yet, when the distances H 1 and H 2 change (and their sum is
constant) then the fringe field and its contribution in the total capacitance changes as
well. The following approaches are used. Using the Table 2.2 and choosing one of the
formulas one finds the components that are called "area components" (using the term that
is proportional to W/H) and the components that are called "fringe components" (using
the term(s) including the ratio T/H). After that the "area components" are added and only
one, the maximum, fringe components is added. This procedure usually gives the result
that is within ±10% of the capacitance obtained by using a two-dimensional field
simulator.
Sometimes a better result can be obtained if the fringe components are summed with
certain weights. Usually one uses the simplest sum ( ε is not included)
 T T
,
f 
 H1 H 2
  f n (T / H 1 ) + f n (T / H 2 ) 
 = 

2
 

1/ n
(2-21)
Multiplying the result by ε one obtains the required fringe term. The exponent n may be
different for different configurations and formulas. For example, if n=4 is chosen, and the
capacitance is calculated on the basis of the Meijs-Fokkema (MF) result, then the
capacitance of a wire between two planes is
0.25
0.25


 T  2  T  2  




1
1
W
W

 + 0.77 + 0.891
 + 
 + 
   (2-22)
C ≈ ε W 
+
+
  H 1 H 2 
H
H
H
H
 1   2   
2 
 1


(notice also change of the numerical coefficient before non-parallel-plates terms). To
finish this part we give a small table comparing the results of capacitance calculations
using different formulas with the result produced by two-dimensional field solver
(Maxwell). The result is given for W=2.38µm, H1=0.87µm, H2=0.48µm, and T=0.3µm.
Table 2-3 Capacitance of single wire between two conducting planes
Method
Capacitance, fF/mm
Sacurai sum of capacitances
0.468
Yuan sum of capacitances
0.434
Yuan with maximum fringe
0.343
6
MF with maximum fringe
MF with weighted fringe
Two-dimension field solver
0.375
0.370
0.361
c) Three adjacent wires over a single plane
A satisfactory result (i.e. close to the numerical result obtained by solution of twodimensional field problem) for the total capacitance of central wire symmetrically located
between two adjacent wires (Fig. 2-8) is obtained only on the basis of Sacurai result. The
Sacurai formula expresses the total capacitance as the sum of two components, namely
C total = C sin gle + 2C mutual
(2-23)
The first term is simply the ordinary wire-over-ground plane term of case a), i.e.
0.222
1.15W

T 
C sin gle = ε 
+ 2.8 
(2-24)

H
H




and
0.222
 W
 S  −1.34
T
T 
(2-25)
C mutual ≈ ε 0.3 + 0.83 − 0.07 
 
H
H
 H
 H 
It is worth to mention that the notations used by Sacurai are misleading. The total sum
gives the correct result, yet each term does not have the correct physical sense (as it is
defined for the self and mutual capacitance.
III.Inductors
1. Spiral inductors
a) Inductance calculation
The only widely used on-chip inductor is the planar spiral. The square version of this
spiral is shown in Fig. 2-9. Also a circular spiral is known to provide somewhat higher Qfactor, non-Manhattan geometries are not supported by many layout tools and not
permitted in many technologies.
The bulk of the spiral is implemented in the topmost available metal (sometimes two or
more levels are connected in parallel to reduce resistance), and the connection to the
center of the spiral is made with a cross-under of some lower level of metal.
The inductance of such a spiral is a complicated function of geometry, and accurate
computations require the use of field solvers. However, a very approximate estimate,
suitable for quick hand calculations, is
L ≈ 4πµ 0 n 2 r ≈ 1.2 * 10 −6 n 2 r
(2.26)
Here L will be in Henries, when r is in meters; n is the number of turns. The formula (226) gives the result which is 30% or better on the high side in comparison with field
simulator results. For octagonal spirals the result should be multiplied by 0.91, and for
circular spirals spirals by π / 2 = 0.89 (for an arbitrary shape multiply by the square
root of the area ratio).
Using this simple approach one can realize the coils in the range of L=5-20 nH (they have
the sizes of 2r up to 500µm) and with Q-factor of 5-10.
More useful for the approximate design of a square spiral inductor is the following
equation
7
1/ 3
1/ 3
 PL 
 PL 
n≈  ≈
(2.27)
−6
1.2 * 10 
 µ0 
where P is the winding pitch in turns/meter. In (2-27) the permeability of free space is
assumed.
The flat spiral is a very area inefficient structure. Let us try to design a coil of L=120 nH
and evaluate its parameters. Let us choose the pitch of one turn every five micrometers
(say, assuming w=3µm metal width and s=2 µm the distance between turns), i.e. with the
pitch of 2*105. Using (2-27) one finds that the number n of turns needed is about 27
corresponding to a required radius, r, of 5*27= 135 µm. The area of this coil will be
about 2*135*2*135=72900 µm2. The size pad is usually 80*80=6400 µm2 (typical
unprotected pad for many technologies). Hence, the area occupied by this coil will be
about the area of 11 typical bond pads; it is huge.
In addition, such coil would have quite large capacitance as well. Assume that this coil is
fabricated using the top metal layer in a three metal layer technology. The distance of this
coil from substrate is 2 µm. The medium turn of this coil will be a square with the length
of the side about 135 µm, and its area is 4*135*3=1620 µm2. This gives the total area of
the coil A=27*1620=43740 µm2. Assuming the permittivity of SiO2 equal to 3.5*10-13
F/cm, and using the flat capacitor formula one can find that the capacitance of this coil is
C = (ε A) / H = 0.765 pF (in reality, the capacitance due to the fringe effect will be even
higher).Then, the self-resonant frequency of this coil will be rather low
f 0 = 1 /(2π 120 * 10 −9 * 0.765 *10 −12 ) = 0.526 GHz (we remind that we need the passive
elements which are useful at the frequencies of 2-3 GHz at least).
Finally, let us evaluate the Q-factor of this coil. Assume that the top metal chosen for
design has the resistivity of 25mΩ/square. The length of the coil is about
4*135*27=14580 µm. Hence, the resistance of the coil will be R=25*(14580/3)=121500
mΩ ≈ 122Ω. At the resonant frequency
Q = 2πf 0 L / R =(2*3.14*120*10-9*0.526*109)/122=3.25
These calculations show very well the design difficulties of RF circuits with integrated
coils: the coils are bulky, have low Q-factor, and low resonant frequency.
To increase the Q-factor one has to increase the width of the metal. This would increase
the coil capacitance and further reduce the resonant frequency. All these consideration
result in the conclusion that the optimal value of inductance should be about 5-10 nH, the
Q-factor achieved at the frequency 1-2 GHz will be about 5-10. These coils will consist
of 5-10 turns, and they should be designed using minimal space between turns. The
maximal width of the metal (usually it is about 15-30 µm) is usually established using an
optimization for resonance frequency or Q-factor. One such optimization program is
prepared at the University of Berkley and available for public use.
b) "Hole inductor"
A slightly more complicated formula that yields significantly better accuracy is
45µ 0 n 2 a 2
(2-28)
L≈
22r − 14a
where a is the square spiral mean radius, defined as the distance from the center of the
inductance to the middle of the windings. Checks with the field solver indicate that this
8
formula usually has an error under 5%. This formula accommodates also "hollow" spiral
inductors (Fig. 2-9, b) in which one or more innermost turns have been removed to
improve Q-factor. In fact, this last design should be recommended for practical
applications.
c) Inductor equivalent circuit
The inductor equivalent circuit is shown in Fig. 2-11. Besides the inductance L it includes
some additional elements. The resistance RS represents resistive losses. The DC resistive
losses (as they were calculated before) are exacerbated by the skin effect which causes a
nonuniform current distribution in a conductor at RF. This results in a reduction of the
effective cross-section, increasing the series resistance. The series resistance in this case
may be calculated as
1
l
(2-29)
Rs =
≈
−t / δ
wσδ (1 − e )
 1  t 
wtσ 1 −  
 2  δ 
Here l is the total spiral length, w is width of the metal strip, t is thickness, σ is
conductivity, and δ is skin-effect depth. Notice that if skin-effect depth is large, the result
becomes familiar Rs = l /( wtσ ) , which is the DC resistance. The skin effect depth can be
evaluated as
2
1
δ =
=
(2-30)
ωµ 0σ
πfµ 0σ
The conductivity of aluminum σ Al =4*107S/m, and the permeability of free space
µ 0 =4π*10-7H/m. With this numbers, the skin depth is approximately 2.5 µm at 1 GHz (a
useful figure to remember). If the thickness t is about 1 µm the skin effect will increase
the coil resistance by additional 25%.
The capacitance with respect to the substrate is represented by two capacitors C ox / 2
ε
where C ox = wl ox (here t ox means the thickness of oxide between the coil metal and the
t ox
closest conductive layer under the coil, see below). The capacitance C P represent a small
total capacitance of all cross-unders. It can be calculated as
ε
C p = nw 2 ox
(2-31)
t ox
The proximity of the substrate also degrades Q-factor because of the energy coupled into
the lossy substrate. Considering the coil as a long line over conducting surface one can
evaluate the substrate loss representing it by the resistor
2
R1 ≈
(2-32)
wlG sub
Here G sub is a fitting parameter with a typical value of 10-7S/µm2. The substrate
conductance decreases with temperature, as a result the Q-factor has a tendency to
increase with temperature. A typical temperature coefficient of the Q-factor is about 100
ppm/oC. Finally, the capacitor
9
wlC sub
(2-33)
2
reflects a substrate capacitance. The parameter C sub is a fitting parameter as well; its
typical value is 0.01-0.01 Ff/µm2.
The equations (2-28) to (2-33) are usually used for optimization. The optimization
usually confirms that the inner terms may be removed, yet even the optimized coils have
Q-factor below 10. A minor refinement allowing increase of Q is a patterned ground
shield (Fig. 2-11). This patterned shield may be constructed using one of the bottom
metal layers or the heavily doped polysilicon. At a reasonable distance from the coil, the
slices are usually connected by a ring. This ring is connected to the substrate. In addition
one may also place alternating wedges of n-well and substrate underneath the inductor to
push image currents deeper into substrate. Another advantage of these measures is that
shielding reduces coupling of noise from the substrate to the inductor.
When used together, the hollow coil design, patterned ground shield, and patterned nwells under the shield can sometimes increase Q by 50% or more. These three measures
do not require any additional processing steps and should be included in the coil design.
The penalty paid is a reduction in self-resonant frequency caused by increased
capacitance. If the inductor is constructed out of metal layers sufficiently removed from
the shield layer, this penalty can be tolerated in most cases.
When two ore more coils are used on the same chip the distance between coil centers
should be two times or more larger than the coil diameter for each couple of coils.
Two technological measures increasing Q should be mentioned. The first measure is
using copper (Cu) alloys instead of aluminum (Al) alloys (this measure increases Q in
two or three times). The second measure is removal of the substrate under the coil (by
etching or micromachining). It increases Q in addition by two or three times. The
micromachined Cu inductors may have Q's as high as 50. and allow realization of bandpass filters with the insertion loss which is better than –5dB at the frequency about 6GHz,
the low-noise band-pass amplifiers with the gain of 20 dB and noise figure about 2.5 dB
(also at 6 GHz), and voltage controlled oscillators of low phase noise (for the oscillator
with the oscillation frequency 5 GHz the power was below –160 dBm at the frequency
offset of 50 MHz). These figures show that three basic blocks of an analog front end can
be realized with high quality parameters.
2. Bond wires
a) Bond wire inductors
In addition to planar spirals, bond wires are also frequently used to make inductors,
especially in power amplifiers. The bond wires are also a source of problems, especially
instability.
Because bond wires are located in air, i.e. far from the substrate they have much less
resistive loss, and therefore higher Q values. Also, they are placed well above any
conductive plane and their capacitance is quite low. Hence, the bond wires have high
self-resonant frequency. If one neglects the influence of nearby conductors, the DC
inductance (i.e. the inductance which includes external and internal components) of a
bond wire is given by

  2l 

 µ l    2l 
(2-34)
L ≈  0  ln  − 0.75 ≈ 2 *10 − 7 l ln  − 0.75
 2π    r 

 r 

C1 ≈
10
For a 1mm long standard bond wire, this formula yields approximately 0.865 nH, leading
to a handy rule of thumb that the inductance is approximately 1nH/mm.
In simulations it is necessary to include 2-3 nH in each terminal, especially in terminals
which carry heavy currents (for example, ground terminal). It is very good to remember
that the impedance of 1nH at the frequency of 1 GHz is 6.28 Ω. For the AC current of
100 mA (and this current is easily developed in output stages of power amplifiers) the
voltage drop at this impedance will be about 0.63 V, i.e. quite high. Hence, these stages
should have many drain and ground contacts with the bond wires connected in parallel
between the contact points and output pads.
The Q of a bond wire is easy to estimate. As it was mentioned before, the skin depth in
aluminum is about 2.5 µm, i.e. it is small compared with 25 µm diameter. Hence, the
effective resistance per length can be found as
fµ 0
R
1
1
≈
=
(2-35)
σ
l 2πrδσ 2 π
One can find that this value is about 125 mΩ/mm at 1 GHz. This, together with inductive
impedance of 6.28 Ω, gives the Q-values of 50 at this frequency.
Finally, the temperature coefficient of a bond wire inductor is due to combination of two
effects. One is simly the linear expansion of the wire with increasing temperature; this
component has a TC of approximately 25 ppm/oC. The other is the change in the
contribution of the internal flux to the total inductance. As follows from (2-35) the
resistance goes up with temperature (σ decreases), causing the skin depth to increase,
increasing the amount of internal flux (and, hence the inductance. The contribution of the
internal flux can be determined from the following equation for the internal inductance
per unit length of a piece of wire at DC
µ
Lint = 0
(2-36)
8π
One can find that this value is 0.05 nH/mm, so internal inductance is only about 5% of
the total inductance, and using (2-34) at high frequencies does not introduce an essential
error. At 1 GHz the skin depth is only one tenth of the bond wire diameter, and the
internal inductance is practically absent. The change of temperature increases the skin
depth and forces the internal inductance to reappear. This change in internal inductance
results in additional increase of the total inductance with temperature (20-50 ppm/oC) so
one may expect the total inductance of a bond wire to possess a TC of approximately 5070 ppm/oC.
b) Coupled bond wires
There can be substantial magnetic coupling between adjacent bond wires. A measure of
this coupling is the mutual inductance between them. For two parallel bond wires of
equal length, this mutual inductance is given as
µ l   2l 
D
M ≈ 0 ln  − 1 + 
(2-37)
2π   D 
l
where l is the length of bond wires and D is the distance between them.
One model for the coupled inductors is an inductive T-network in cascade with ideal
transformer (Fig. 2-13). In this model, L1 and L2 are the values each inductor has with
no current flowing in the other. One can check that the coupling coefficient
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k = M / L1 L2 for two wires located at a distance of 1 mm is about 0.4. This is quite
high figure that should be taken into account in critical designs.
IV. Monolithic transformers
Monolithic transformers represent the extension of coil design. The basic designs are
shown in Fig.2-14. Fig. 2.14, a shows the transformer with a relatively high coupling
coefficient (k =0.7-0.8). Both coils are using the same top metal, the different colors used
for primary and secondary was chosen to make the perception easier. Fig. 2-14, b shows a
transformer design for lower coupling coefficient. Here the primary and secondary are
using different layers of two top metals.
The equivalent circuits of both transformers are similar (Fig. 2-15) and reduction of
substrate coupling requires the same design measures that were used for the coil design: a
patterned ground shield, and patterning n-wells in the substrate.
The calculation of transformer parameters may be done following the same routine as it
was used for the coils. When the inductances of the primary and secondary are found, the
mutual inductance can be calculated as the ratio of common area to the area of one coil.
12
Problem set for the lecture No 2
Problem 1
Extend to circular capacitors the simple fringe correction method outlined for square
capacitors. Compute the ratio of your corrected capacitance to the uncorrected value for
the following ratios of plate spacing to diameter: 0.005, 0.01, 0.025, 0.05, 0.1. Compare
your result to the actual correction factors shown in the Table 2P-1.
Table 2P-1 Correction factors for fringing in circular capacitors
s/D
Ccorr/Cuncorr
0.005
1.023
0.01
1.042
0.025
1.094
0.05
1.167
0.1
1.286
Problem 2
(a) Design a 10 nH square spiral inductor in which the total length of the interconnect is
350 µm, the spacing between turns is 2 µm, the metal and oxide ate both 1 µm thick, and
the metal conductivity is 4*107 S/m. The oxide has a relative dielectric constant of 3.9.
(b) Compute the values of for the model elements of your design at 1.5 GHz if on
terminal is grounded. Initially assume that the substrate is a superconductor.
(c) If this inductor is used as part of a tank in which the external capacitance and and
resistance are 500 fF and 10 kΩ, respectively, what is the impedance of the combination
at resonance? Do not bother recomputing the model parameters values for the new
resonant frequency.
(d) Change your model to use the default values for G sub and C sub . Use SPICE to
determine the new impedance magnitude at resonance. Again, do not bother recomputing
the other model parameter value. Compare with your previous result.
Problem 3
A parallel resonant tank circuit is constructed from a 4-turn, 80-µmx80-µm square spiral
inductor, and a 5-µmx5-µm capacitor constructed from two metal layer separated by an
atypically thin 0.2 µm oxide dielectric ( ε = 3.9ε 0 ).
(a) Initially neglecting fringing and all other parasitics, what is the nominal resonant
frequency of this network?
(b) Now assume that the substrate is a superconductor, and that the bulk of the inductor is
built of a layer that is 3 µm above the substrate. Ignoring the shunt capacitance of the
inductor's crossunder, but not the capacitance to the substrate, what now is the
approximate parallel resonant frequency of the network if the substrate is connected to
one terminal of the tank? The inductor windings are 8 µm wide and 1 µm thick. You
may assume a symmetrical inductor model.
13
(c) What is the value of the inductor's effective series resistance at this new resonant
frequency if the interconnect has a conductivity of 5*107 S/m? It may help to know that
the permeability is about 1.26*10-6 H/m.
(d) One measure of how little loss a reactive network has is Q, the quality factor. What is
the Q of this resonator if it is defined here as Q = ωL / R and is measured at the resonant
frequency?
Problem 4
A common problem, especially in digital systems, is how best to size the interconnect. A
wider line has more capacitance, but lower resistance, so how wide is wide enough? To
put this question on a somewhat quantitative basis, use a Sacurai formula for a single
conductor over a ground plane and derive an equation for the RC product of such a line,
where R and C are the total resistance and capacitance, respectively. We will use a
simplified approach here, and ignore the effect of interconnect loading on whatever has to
drive it. Instead , we focus entirely on the interconnect itself.
(a) If the propagation delay of signals is proportional to RC, how does the delay increase
if the length doubles?
(b) Your formula should show that the RC product asymptotically approaches a minimum
value as the width goes to infinity. What width produces a delay just 25% above the
minimum value? Express your answer in terms of the thickness T and the height H above
the substrate.
Problem 5
Junction capacitors are normally used in reverse bias as varactors. To explore why they
are almost never used in (strong) forward bias, assume that the diode behaves as follows
in the forward direction:
i D ≈ I S exp(v j / VT )
(P2-1)
Assume that the thermal voltage VT is 25 mV at the operating temperature, and that the
diode is built in such a fashion that the forward current is 1mA at a junction voltage of
0.5 V.
(a) Calculate the increment resistor at 1 mA.
(b) If the zero-bias capacitance C j 0 is 2 pF, what is the capacitance at the forward bias of
0.5 V? Assume an abruptly doped (step) junction and a φ of 0.8 V.
(c) Compute the reactance of the capacitance found in part (b) at 1 GHz. Does thevaractor
appear mainly resistive or capacitive at this frequency.
Problem 6
Design a 7.3 nH inductor. You have at your disposal a total of 6 mm of bond wire and
900 µm2 of die area. Assume that the bond wire can be controlled no better than 10%.
Maximize the Q of the resulting inductor, subject to the constraint that the final inductor
value be within 5% of the target value. For the simplicity's sake, you may assume that the
following planar spiral inductance formula is exact
(P2-2)
L ≈ µ0n2r
Problem 7
Derive an expression for the resistance of interconnect as a function of temperature for
two cases as follows.
(a) The skin depth is very small compared with the conductor dimensions.
(b) The skin depth is very large compared with the conductor dimensions.
14
You may assume that the resistivity of the interconnect is itself PTAT.
(c) Using your result to part (a), how much variation in Q would you expect for a square
spiral inductor between -–55oC and 125oC?
Problem 8
(a) Derive a circuit model for two coupled bond wires, each of which is 7 mm in length,
and which are separated by 4 mm. You may ignore resistive and capacitor parasitics.
(b) Assume that one bondwire is driven by a voltage source through the resistance of 50
Ω. Also assume that the other bondwire is shunted by a 200 Ω load resistance. if the
voltage source provides a 1 V unit step, use SPICE to plot the voltage across the load
resistor.
(c) Now double the separation to 8 mm and repeat. What do you conclude about the
effectiveness of separation as a means to reduce parasitic coupling?
Problem 9
A 10 k Ω polysilicon resistor is to be made out of material with a sheet resistivity of 100
Ω per square.
(a) Determine the minimum dimensions of this resistor if the width can not be controlled
to an uncertainty better than 0.2 µm, and the variation in resistance due to width variation
must be kept below 5%. For simplicity, assume a straightforward linear layout.
(b) Determine the parasitic capacitance to the substrate if the oxide dielectric layer
(relative dielectric constant is 3.9) is 1 µm thick. Using a single RC-model for this
structure, what is the approximate maximum frequency above which this resistor ceases
to appear predominantly resistive.
Problem 10 Another constraint on conductor dimensions is imposed by electromigration
effects. At high enough current densities, momentum transfer between electrons and
metal atoms can cause physical motion of parts of interconnect. A narrowing of
interconnect causes an increase in the current density, which accelerates the narrowing,
and so on until either the resistance increases to unacceptable level or the interconnect
actually open-circuits.
Electromigration rules for most commonly used interconnect metals usually dictate an
upper bound within a factor of 2 of about 109 A/m2 DC current (much larger densities are
permitted for high frequency sinusoidal currents because little net migration can occur in
such a case).
(a) Assuming a maximum allowable current density of 2*109 A/m2 determine the
minimum acceptable width capable of supporting a current of 100 mA if the conductor is
0.5 µm thick.
(b) Compute the resistance per millimeter of your design if the conductivity is 4*107 S/m.
(c) Estimate the parasitic capacitance per millimeter if the oxide is 1 µm thick.
15