Vol. 35, No. 3
Journal of Semiconductors
March 2014
An L-shaped low on-resistance current path SOI LDMOS with dielectric field
enhancement
Fan Ye(范叶), Luo Xiaorong(罗小蓉)Ž , Zhou Kun(周坤), Fan Yuanhang(范远航),
Jiang Yongheng(蒋永恒), Wang Qi(王琦), Wang Pei(王沛), Luo Yinchun(罗尹春),
and Zhang Bo(张波)
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of
China, Chengdu 610054, China
Abstract: A low specific on-resistance (Ron; sp / SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with
an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI
layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.
First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation
layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases
the Ron; sp . Second, in the y-direction, the BOX’s electric field (E-field) strength is increased to 154 V/m from
48 V/m of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide
trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens
the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and
thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage
(BV), but also reduces the cell pitch and Ron; sp . Compared with the TG LDMOS, the NBL TLDMOS improves the
BV by 105% at the same cell pitch of 6 m, and decreases the Ron; sp by 80% at the same BV.
Key words: MOSFET; silicon-on-insulator; breakdown voltage; specific on-resistance
DOI: 10.1088/1674-4926/35/3/034011
EEACC: 2570
2. Structure and mechanism
1. Introduction
The lateral double-diffused MOSFET (LDMOS) is widely
used in power ICs due to its ease of integration and high frequency advantagesŒ1 3 . For the conventional LDMOS, high
lateral BV (BVlat / needs a long drift region, which inevitably
leads to a high specific on-resistance (Ron; sp /Œ4 . To address this
inherent tradeoff, an oxide trench is incorporated in the drift region to reduce the cell pitch and Ron; sp without sacrificing the
BVŒ5 7 . The trench gate is applied in the LDMOS to increase
the current density and reduce Ron; sp Œ8 . The SOI technology
has excellent integration and strong latch up immunityŒ9 11 .
However, the vertical BV (BVver / for the conventional SOI
LDMOS is limited because the substrate does not share the BV.
One effective method for improving the BVver is to enhance
the E-field strength in the BOXŒ12 15 , such as implanting the
buried N layer technologyŒ16 .
In this paper, a novel trench gate SOI LDMOS with an
N buried layer (NBL) and an oxide trench is proposed. The
NBL and the electron accumulation layer beside the trench gate
form a low-resistance conduction path, significantly reducing
the Ron; sp . The oxide trench and the NBL enhance the BVlat
and BVver . Moreover, the oxide trench reduces the cell pitch
and increases the doping concentration of drift region, and thus,
further decreases the Ron; sp .
Figure 1(a) shows the schematic cross section of the SOI
NBL TLDMOS. This structure is characterized by a thin NBL
located on the top interface of BOX, an oxide trench inserted
into the drift region, and an extended trench gate. The NBL
reduces the Ron; sp and increases the BVver . The oxide trench
not only supports the blocking voltage, but also decreases the
cell pitch and Ron; sp . DT and WT are the depth and width of
the dielectric trench, respectively. ND and NNBL are doping
concentrations of N drift region and the NBL, respectively.
The NNBL is one order of magnitude higher than the ND . tI ,
ts , and tNBL are the thicknesses of BOX, SOI layer and NBL,
respectively. The x-direction and the y-direction are given in
Fig. 1(a).
In the on-state, an electron accumulation layer is formed
beside the extended trench gate. The NBL and the accumulation layer constitute an L-shaped low-resistance current path.
Most of the current flows through the “L-shaped” path (as
shown by the bold line). Furthermore, the drift doping is increased due to the multiple-directional depletion and enhanced
RESURF effect caused by the oxide trench. Both reduce the
on-state resistance (Ron /. The oxide trench also folds the drift
region in the y-direction, which reduces the device cell pitch,
and thus, the specific on-resistance (Ron; sp D Ron cell pitch)
is decreased drastically.
* Project supported by the National Natural Science Foundation of China (No. 61176069), the Program for New Century Excellent Talents
in University of Ministry of Education of China (No. NCET-11-0062), and the China Postdoctoral Science Foundation (No. 2012T50771).
† Corresponding author. Email: xrluo@uestc.edu.cn
Received 1 August 2013, revised manuscript received 12 September 2013
© 2014 Chinese Institute of Electronics
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J. Semicond. 2014, 35(3)
Fan Ye et al.
Fig. 1. Schematic cross sections of (a) the proposed SOI NBL TLDMOS, (b) the charges distribution and the E-field profiles along the CC0 line,
(c) SOI TLDMOS, and (d) SOI TG LDMOS.
In the off-state, the oxide trench and the NBL significantly
enhance the BVlat and BVver of the SOI NBL TLDMOS. In the
x-direction, based on the Gauss theorem on the Si/trench-oxide
interface:
"S ES D "ox ETOX ;
(1)
the oxide trench improves the E-field (ETOX / owing to the
lower permittivity ("ox D 3.9) of the oxide than that of Si
("S D 11.9), resulting in an increased BVlat . Furthermore, the
multiple-directional depletion effect caused by the oxide trench
enhances the bulk E-field in the Si region.
The high concentration ionized donors in the NBL enhance
the E-field strength in the BOX (EBOX /. Figure 1(b) shows the
vertical E-field profiles along the CC’ line for the NBL TLDMOS (solid line) and TLDMOS (dotted line; without the NBL
and shown in Fig. 1(c)). Based on the 1D Poisson’s equation,
the vertical E-field Es in silicon can be determined as:
8
qND
ˆ
ˆ
; 0 6 y 6 ts tNBL ;
ˆ
ˆ
"s
ˆ
ˆ
ˆ
ˆ
SOI NBL TLDMOS;
ˆ
ˆ
ˆ
ˆ
< qN
dEs .y/
NBL
; ts tNBL 6 y 6 ts ;
(2)
D
ˆ
"
dy
s
ˆ
ˆ
ˆ
ˆ
SOI NBL TLDMOS;
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ qND
:̂
; 0 6 y 6 ts ; SOI TLDMOS;
"s
where ND is the optimal drift doping of the TLDMOS, and
NNBL > ND > ND . The E-field strength at y D ts for the NBL
TLDMOS and TLDMOS are defined as Em and Em , respectively. The steep slope of Ey in the NBL for the NBL TLDMOS
is much larger than that of the TLDMOS because of NNBL >
ND from Eq. (2), as shown in Fig. 1(b). In the SOI/BOX interface, EBOX 3Es from Eq. (1), we therefore can obtain the
relationship of the BOX’s E-fields for these two devices:
Em Em ;
EBOX EBOX
:
(3)
The shaded area in Fig. 1(b) shows the increase in the volt
age sustained by the BOX (EBOX EBOX
/tI . Since the NBL is
thin enough, the high E-field region is localized within the very
narrow NBL region, and it contributes little to the ionization integralŒ17 and is not prone to premature breakdown in the NBL.
3. Results and discussion
Figure 2 shows the vertical E-field distributions for the
SOI NBL TLDMOS, TLDMOS and TG LDMOS [structure
showed in Fig. 1(d)]. According to Eq. (2), the different doping concentrations ND , NNBL and ND generate the different Efield gradients in SOI layer for the above three structures, especially in the dashed rectangle of Fig. 2. The interface E-field
strengths of Em and EBOX are therefore different. For the NBL
TLDMOS, the Em reaches 51 V/m due to the high NNBL and
EBOX is 154 V/m, while Em is just 32 V/m and 16 V/m
for the TLDMOS and the TG LDMOS, respectively. In Fig. 2,
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Fan Ye et al.
Fig. 2. E-field distribution in the y-direction under the drain (ts D 4
m, tI D 0.5 m, DT D 3 m, WT D 3 m, tNBL D 0.5 m, and a
cell pitch of 6 m); ND and NNBL are optimized for each device.
EBOX1 of 58 V/m is caused by the NBL, and EBOX2 of
48 V/m is attributed to the oxide trench, which strengthens the
multiple-directional depletion and RESURF effect. The combination of NBL and oxide trench improves the EBOX by 220%
and BV by over 100% for the NBL TLDMOS, compared with
those of the TG LDMOS.
Figure 3(a) compares the E-field distributions for the
above three devices in the x-direction. On one hand, in the xdirection, the oxide trench enhances the lateral E-field strength
(ETOX / due to the lower permittivity of oxide than that of Si,
and the ETOX of the TLDMOS approaches 5 105 V/cm, while
the E-field strength in Si for the TG LDMOS is below 3 105
V/cm. On the other hand, the NBL modulates the E-field distribution in the bulk and avoids vertical premature breakdown in
silicon, therefore NBL TLDMOS has higher ETOX than that of
the TLDMOS. Figure 3(b) shows the field contour distribution
in the Si region around the oxide trench for the NBL TLDMOS
and TLDMOS. Compared with the TLDMOS, NBL TLDMOS
has a more uniform field contour distribution and the average
E-field strength in the bulk retains a high level (> 20 V/m).
The voltage drop in Si along the ABB0A0 line equals the voltage drop in the AA’ line (i.e., across the trench at the surface).
This indicates that the oxide trench effectively folds the drift
region and achieves a high BV with a reduced cell pitch and a
reduced Ron; sp (Ron; sp D Ron cell pitch).
Figure 4 shows the equi-potential contours for the
NBL TLDMOS, TLDMOS and TG LDMOS at breakdown.
Comparing these three structures, the oxide trench and NBL
significantly improve the lateral and vertical E-field distribution for the NBL TLDMOS. Consequently, the NBL TLDMOS achieves a higher BV [more equi-potential contours in
Fig. 4(a)] than TG LDMOS and TLDMOS.
In Fig. 5, the current flowlines of the above three devices
are displayed. In Fig. 5(a), most of the current flows through
the “L-shaped” path [dashed line rectangle in Fig. 5(a)], which
sharply decreases the Ron; sp . Compared with Fig. 5(a) and
Fig. 5(b), the Ron; sp is decreased from 2.17 to 1.64 mcm2
since most of the current flows through the NBL with NNBL D
4.5 1016 cm 3 . In addition, the optimal drift doping concentrations (ND / are 8 1015 cm 3 and 3.6 1015 cm 3 for the
NBL TLDMOS and TG LDMOS, respectively. This is the rea-
Fig. 3. E-field distributions in the (a) x-direction (y D 0 ), (b) around
the oxide trench (ts D 4 m, tI D 0.5 m, DT D 3 m, WT D 3 m,
tNBL D 0.5 m, and a cell pitch of 6 m); ND and NNBL are optimized
to obtain the maximum BV for each device.
son why the NBL TLDMOS can still keep a lower Ron;sp than
that of the TG LDMOS (see Fig. 5(c)) though the oxide trench
takes up a large conduction area.
Figure 6 shows the influences of tNBL and NNBL on the BV
and Ron;sp . In Fig. 6(a), the BV increases with an increasing
tNBL at tNBL 6 0.5 m because of the enhancement in EBOX ,
while it decreases at tNBL > 0.5 m because the E-field strength
in Si above the NBL is driven down by the reduced optimal
ND . The Ron; sp reduces as tNBL increases at tNBL 6 0.7 m,
while increasing at tNBL > 0.7 m because the reduced optimal ND increases the drift region resistance under the drain
(marked by RDD in Fig. 5(a)). In Fig. 6(b), the BVmax first increases and then decreases with the increasing NNBL . Premature breakdown happens in the bottom interface of the NBL
when the NNBL exceeds a critical value, leading to a reduced
BVmax . An increasing NNBL leads to an decreasing optimal ND ,
consequently, RDD and Ron;sp increase. From Figs. 6(a) and
6(b), the optimal ranges are 0.3 m 6 tNBL 6 0.7 m and 4 1016 cm 3 6 NNBL 6 5 1016 cm 3 at ts D 4 m and 6 m
cell pitch.
Figure 7 shows the influences of ND , DT and WT on the
BV and Ron; sp . In Figs. 7(a) and 7(b), the BVmax increases with
an increasing DT at DT 6 3 m due to the enhanced field reshaping effect, while it decreases at DT > 3m, owing to the
premature breakdown at the B0 point (see Fig. 1). In Fig. 7(c),
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J. Semicond. 2014, 35(3)
Fan Ye et al.
Fig. 4. Equi-potential contours at breakdown for (a) SOI NBL TLDMOS (166 V), (b) SOI TLDMOS (143 V), (c) SOI TG LDMOS (81 V) (10
V/contour, ts D 4 m, tI D 0.5 m).
Fig. 5. Current flowline contours for (a) SOI NBL TLDMOS, (b) SOI TLDMOS, and (c) SOI TG LDMOS (1.5 10
4 m, tI D 0.5 m).
6
Am
1 /contour, t
s
D
Fig. 6. Dependencies of BV and Ron; sp on tNBL and NNBL for SOI NBL TLDMOS. (a) tNBL (NNBL D 4.5 1016 cm 3 /. (b) NNBL (tNBL D
0.5 m). ND is optimized for each tNBL and NNBL . DT D 3 m, WT D 3 m, ts D 4 m, tI D 0.5 m, and cell pitch of 6 m for (a) and (b).
034011-4
J. Semicond. 2014, 35(3)
Fan Ye et al.
Fig. 8. Key process steps to fabricate a prototype SOI NBL TLDMOS.
(a) Form the NBL and bonding. (b) Preoxidation, etch Si to form the
oxide trench. (c) Form the p-well, pC contact and nC source/drain
regions. (d) Deposit ploy-silicon to form the trench gate and finally
form the electrodes.
Fig. 7. Dependencies of BV and Ron; sp on ND , DT and WT for SOI
NBL TLDMOS. (a) ND (WT D 3 m). (b) DT (WT D 3 m). (c) WT
(DT D 3 m). ts D 4 m, tI D 0.5 m, tNBL D 0.5 m and NNBL D
4.5 1016 cm 3 .
the BVmax augments with an increase in WT 6 3 m because
the folded drift region is lengthened. Figures 7(b) and 7(c) reflect that the Ron; sp increases along with the DT and WT , owing
to the narrowed conduction area. To improve the trade-off between BV and Ron; sp , the optimal ranges are 2.7 m 6 DT 6
3 m and 2.8 m 6 WT 6 3.3 m at ts D 4 m and 6 m cell
pitch.
The values of BV, Ron; sp , cell pitch and the figure of merit
(FOM: FOM D BV2 /Ron; sp / for the aforementioned structures are given in Table 1. The NBL TLDMOS achieves the
highest BV of 166 V and simultaneously the lowest Ron;sp of
1.64 mcm2 . Compared with the TG LDMOS, NBL TLDMOS improves the BV by 105% at the same pitch of 6 m
or reduces Ron; sp by 80% at the same BV. Compared with TG
LDMOS, the oxide trench in TLDMOS folds the drift region
and greatly reduces the Ron; sp at the same BV. Whereas, the
Ron; sp of TLDMOS is greater than that of TG LDMOS at the
same cell pitch since the oxide trench narrows the conduction
area. Although the oxide trench for the NBL TLDMOS also
narrows the conduction path, the Ron; sp can maintain a very
low value due to the L-shaped low resistance conduction path.
It can be seen from Table 1, the Ron; sp of the NBL TLDMOS
decreases by 24% compared with that of the TLDMOS.
The key process steps to fabricate SOI NBL TLDMOS in
Fig. 8 are described as follows: (a) Implant arsenic on a device
wafer to form the NBL, and thermally grow 0.5 m buried oxide layer on a substrate wafer, and then bond the two wafers;
(b) Form the oxide trench, including etch silicon, preoxidation to ensure good interface characteristic, followed by depositing and flattening SiO2 ; (c) Implant boron and arsenic to
form the p-well, the PC contact, and the nC source/drain regions; (d) Form the trench gate, including etch silicon to the
buried oxide layer and thermal oxidation by preoxidation-etch
oxide-reoxidation with oxygen–hydrogen synthesis oxidation,
and then deposit ploy-silicon. Finally, make contact holes and
deposit metal to form the source, drain and electrodes.
4. Conclusion
An SOI trench gate power lateral MOSFET with a shallow
N-type buried layer and an oxide trench in the drift region is
proposed and investigated by simulation. The NBL and oxide
trench effectively increase the E-field strengths of the BOX and
trench-oxide, enhancing the RESURF effect as well, resulting
034011-5
J. Semicond. 2014, 35(3)
Fan Ye et al.
Table 1. Optimized NNBL , ND , BV and Ron;sp for SOI NBL TLDMOS, TLDMOS and TG LDMOS.
SOI device type
Cell pitch
Optimized NNBL Optimized ND BV (V)
Ron; sp
FOM
(m)
(cm 3 /
(cm 3 /
(mcm2 /
(MW/cm2 /
NBL TLDMOS
TLDMOS
TG LDMOS
TG LDMOS
6
6
6
12
4.5 1016
N/A
N/A
N/A
8 1015
1.1 1016
3.6 1015
3.4 1015
in the increases in the BVver and BVlat with a reduced cell pitch.
The drift doping is increased due to the multiple-directional
depletion and enhanced RESURF effect caused by the oxide
trench. Moreover, the NBL combined with the trench gate provides an L-shaped low resistance conduction path. Both reduce
the Ron; sp . Compared with the conventional SOI TG LDMOS,
BV is increased by 105% at the same cell pitch of 6 m and
Ron; sp is reduced almost by 80% at the same BV.
[10]
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