High Density Packaging User Group
“Reducing the costs and risks for the
electronics industry”
Progress Report for 2013-2014
2013-2014
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Foreword
As the High Density Packaging User Group (HDP User Group) completes its 21st year, the Staff has
prepared this document to highlight the efforts and accomplishments of the past year together with a
view into what is coming next in both the organizational and technical aspects of the consortia. HDP
User Group was founded on the premise that by working together and sharing the risks and rewards of
implementing new technology, all of the Members and the industry as well would accomplish much
more at a much lower cost than going it alone. 21 years of successful operation, as well as continued
growth in both Membership and projects has proven that premise to be true.
In creating this document, we have endeavored to increase your understanding of the organization
and our projects so that you may maximize the benefit to your company of participation in HDP User
Group. Although few companies will be interested in all of the projects we have underway, the
leverage of HDP User Group is so great that just one project can justify the cost of membership many
times over. Add to this value the interaction with the other companies, visibility into the industry
direction acquired through participation in the Member Meetings and project discussions, and it is no
wonder that HDP User Group continues to grow and expand.
The HDP User Group model of a small staff support group for member driven projects and activities
continues to bear fruit as witnessed by the detail project activities and accomplishments included in
this report. These project areas reflect the interests of the industry, and any company involved in
Electronics Manufacturing should find plenty of interest in the project portfolio. The fact that all work
was done by the member companies in their own laboratories by their own people adds further
credence to the project results.
This is the second year in which we have published this progress report. The first edition was very well
received, and we collected several suggestions from readers on how we could improve the document
and make it more worthwhile to the reader. We have tried to incorporate those suggestions in this
version and we continue to solicit suggestions on how we can improve. Like HDP User Group, this
document will continue to grow, evolve, and change to meet the needs of our Members and the
industry we serve.
Marshall Andrews, Executive Director of HDP User Group International Inc.
© 2014 HDP User Group International, Inc. All rights reserved
Page 1
TABLE OF CONTENTS
1
HDP User Group Highlights _______________________________________________________4
1.1
2
3
Executive Summary................................................................................................................................... 4
Health of the Organization _______________________________________________________5
2.1
Membership.............................................................................................................................................. 5
2.2
Leverage .................................................................................................................................................... 6
2.3
Published Papers and Conferences ........................................................................................................... 7
2.4
Intangible Benefits of Membership .......................................................................................................... 8
Project Impact Summary _________________________________________________________9
3.1
Completed Projects................................................................................................................................... 9
3.1.1
PWB Environmental Life Cycle Analysis: (Lead: TTM-Meadville) ......................................................... 9
3.1.2
High Frequency Laminate Measurements: (Lead: Oracle) ................................................................. 10
3.1.3
Optoelectronics: (Co-Leads: Cisco, TTM-Meadville) .......................................................................... 12
3.1.4
Pad Cratering: (Lead: Celestica) ......................................................................................................... 14
3.1.5
Process Sensitive Components: (Lead: IBM) ..................................................................................... 15
3.2
Current Implementation Projects ........................................................................................................... 16
3.2.1
Alternative Alloy Study for Hole Fill and Copper Dissolution: (Lead: Nihon Superior) ...................... 16
3.2.2
SAC Aging 2: (Lead: Alcatel-Lucent) ................................................................................................... 17
3.2.3
Modules-to-PWB Interconnections: (Lead: Juniper Networks) ......................................................... 18
3.2.4
Multiple Lamination: (Lead: Curtiss-Wright) ..................................................................................... 18
3.2.5
Thin Cu Stress Test: (Lead: Fujitsu) .................................................................................................... 19
3.2.6
Anti-Counterfeit 2: (Lead: IBM) ......................................................................................................... 20
3.2.7
FCBGA Package Warpage: (Lead: Plexus)........................................................................................... 21
3.2.8
Lead Free PWB Materials Reliability IV: (Lead: IBM) ......................................................................... 21
3.2.9
Low/No Ag Alloy Solderpaste Reliability Phase 1: (Lead: Flextronics) ............................................... 22
3.2.10
Optical Flexible Printed Circuit (FPC) Assembly: (Lead: Huawei) ................................................. 23
3.2.11
PWB Backdrilling Failure Analysis: (Lead: PWB Interconnect Solutions) ...................................... 24
3.3
Current Definition Projects ..................................................................................................................... 25
3.3.1
Through-Silicon Vias (TSV) Signal Integrity Project: (Lead: NIST)....................................................... 25
3.3.2
Electro-Chemical Migration (ECM): (Lead: Kyzen) ............................................................................ 26
3.3.3
Press Fit Technology: (Lead: Ericsson) .............................................................................................. 26
3.3.4
Lead Free PWB Materials Reliability Phase 4: (Lead: IBM) ............................................................... 27
© 2014 HDP User Group International, Inc. All rights reserved
Page 2
3.3.5
BFR/PVC-Free Cables II: (Lead: IBM) ................................................................................................. 28
3.3.6
Optoelectronics II: (Lead: Cisco/TTM-Meadville) ............................................................................. 29
3.3.7
Ultra-Thin HDI Multi-Purpose Test Vehicle: (Lead: TTM-Meadville) ................................................. 30
3.4
Current Idea Projects .............................................................................................................................. 31
3.4.1
Mini-Power Cycles: (Lead: Ericsson) .................................................................................................. 31
3.4.2
TSV SMTA Characterization Guidelines and Reliability Project: (Lead: NIST) ..................................... 32
3.4.3
Future HDI: (Lead: Curtiss-Wright) ................................................................................................... 33
4
Collaboration and Infrastructure Development ______________________________________34
5
Looking Ahead ________________________________________________________________35
6
List of Members _______________________________________________________________36
7
Company Information __________________________________________________________37
© 2014 HDP User Group International, Inc. All rights reserved
Page 3
1 HDP USER GROUP HIGHLIGHTS
1.1 EXECUTIVE SUMMARY
2013-2014 was another banner period for the High Density Packaging User Group (HDP User Group). Our
Membership continued to grow with the addition of 9 new Members and 2 new members to the Board of
Directors, bringing our total membership to 50. This represents a new high for the organization, and
continues the trend of increasing membership every year for the past 5 years. New members mean more
resources for our projects, more of the supply chain involved in and using the results of our activities, more
leverage and value to the membership, and reflects the confidence the industry has in our organization.
Leveraging is one of the keys to HDP User Group’s success. Our projects continue to provide extraordinary
cost savings and resource leveraging for our membership. During the past year, some of our projects have
given savings as high as 40 to 1 considering the cost of one company doing the project alone and bearing all
of the costs. Even for projects with lower ratios, the savings are significant. Companies participating in
more than one project are able to magnify their savings accordingly.
Leveraging is not just about cost savings. The more the industry is aware of what we are doing, the more
likely that material suppliers will be putting effort toward developing materials to address our issues,
manufacturing companies will adopt procedures and techniques of interest to our members, and end users
will have confidence in the products from our OEMs. We help promote these peripheral activities by
publishing papers describing our work and develop activities of mutual interest with other industry
organizations. During the past year, 9 technical papers covering the work accomplished in some of our
projects were presented at worldwide conferences and symposia, and the paper presented by Bill Birch of
PWB Interconnect Solutions at ECWC13, received a best paper award. Mutually beneficial activities were
undertaken with 11 different industry groups and organizations, the highest level of industry outreach in our
history.
While all of these activities are important, and contribute to the value of HDP User Group, our lifeblood is
our projects. Our project portfolio remained relatively steady as we completed 5 projects and began work
on 6 new topics. Following are some highlights of our project accomplishments:
PWB Life Cycle Analysis – Completed and delivered a model of greenhouse gas emissions for PWB
manufacturing which is unique to the industry because it is based on actual manufacturing data. The model
can compare emissions for different PWB design options, including high density micro-via sequential
lamination designs, and is customizable for different manufacturing facilities.
High Frequency Halogen-Free Laminate Measurements – Created and evaluated a single test board
containing coupons for each of the 12 most used test methods for Dk and Df above 2 GHz to understand the
correlation between the test methods. Correlations are better than expected and will allow the industry to
choose high frequency materials and designs with more confidence.
Optoelectronics – Designed and tested PWBs with both optical and copper interconnects, using different
PWB materials to compare the performance limits of the two technologies up to 40GHz. The project
confirmed the feasibility of a full optical system implementation using waveguide technology to solve the
problems of increasing bandwidth and speed.
Process Sensitive Components - The Project Team compiled a comprehensive guideline document
examining and illustrating the risks of exposing various sensitive components to temperatures or other
processes beyond their capability, and identifying best practices for dealing with the numerous classes of
process sensitive components that now confront the Pb-free electronics industry.
© 2014 HDP User Group International, Inc. All rights reserved
Page 4
2 HEALTH OF THE ORGANIZATION
The organization has continued to flourish and bring benefits to our membership. The consortium has never
been stronger nor more in tune with the issues of the electronic industry. Our membership continues to grow
in both number and type of companies from a wide selection of industry sectors. Since January of this year
we have had nine new companies officially join our ranks; record growth for our organization. This is a result
of the value HDP projects are providing to our membership, and the visibility our work is receiving in the
industry. New Members mean more resources for our projects and increased value for the HDP User Group
Membership. Below are a few perspectives from our members:
“A key advantage of the HDP User Group is its ability to identify critical R&D needs, assemble
teams of industry experts, and launch projects in a timely manner. HDPUG also encourages
working relationships with other organizations in the field, such as the International
Electronics Manufacturing Initiative (iNEMI), Universal A.R.E.A Consortium, as well as
universities to leverage skill sets and expertise and avoid duplication of effort.” -Richard Coyle,
Alcatel-Lucent
“Technology innovations lead to miniaturization, convergence and interconnection of the
semiconductor package with the circuit board. As technologies converge new challenges arise.
Collaborating, networking and working with technologists on projects targeted at technology
gaps help our organization develop a better understanding and knowledge of industry
challenges that relate to our core competency.” –Mike Bixenman, Kyzen
The organization has continued to control cost and keep the membership dues constant for a span of 8 years.
Although the consortium is still guided by a majority of OEM members, we are incorporating more of the
supply chain. This report shows some of the highlights from 2013-2014 on the important aspects of HDP User
Group membership, such as leveraging critical resources, tangible and intangible benefits, and impacts to the
industry direction and collaboration with external groups.
2.1 MEMBERSHIP
The HDP User Group membership continues to grow with a total of 50 members as of September 2014. Our
group has strived to recruit the best companies in areas where our members wanted to focus project activity.
Our new members include: three PCB fabricators (Compeq, Sanmina, and Wus); two device suppliers (Nvidia
and Freescale); two material suppliers (Doosan and Integral Technologies); two test/measurement equipment
companies
(Introbotix
and
Agilent). The composition of the
membership is very dynamic and
changes with the industry trends
and issues and as such we have
lost 3 members.
System
Integrators/OEMs still represent
the major sector of the
membership and Board of
Directors, with two new additions
to the board this year, Panasonic
and Sanmina. As Figure 1 shows,
the membership growth and
composition for the last 5 years is Figure 1: HDP User Group Membership Composition and Growth
dynamic and driven by the specific
project mix and issues being resolved. This is good for HDP User Group as it means we are attracting the
correct members required to complete projects in a timely and cost effective manner.
© 2014 HDP User Group International, Inc. All rights reserved
Page 5
2.2 LEVERAGE
Leverage is a major benefit to HDP User Group members. The ability to multiply the expertise of a full supply
chain to perform expensive testing and evaluations for minimal to no cost other than the organization’s
membership dues is the power of this consortium. HDP User Group is very effective at leveraging its
membership and providing extremely cost effective projects. The Leverage Ratio chart, Figure 2, gives an
example of the leverage for some completed projects based on the cost of a Class A (>50M annual revenue)
Membership Fee. It is based solely on hard dollars that would have been spent by any company doing this
project alone and does not take into account the leverage gained by the time (person hours) and expertise of
the project members. As an example, the Pad Cratering project would have cost 40 times the yearly Class A
Membership Fee for any member performing this work alone. For companies in the <$50 M category (Class
B Membership) your leverage ratio would be even greater than that shown. The average cost per project to a
single company to complete just these five projects has been calculated at $345,000 as shown in the Leverage
Ratio Chart. It should be noted that some projects, although extremely valuable to our membership, do not
have hard cost associated with them; for example the Process Sensitive Component and PWB LCA projects.
Some projects require new test methods and methodologies that are not commercially available and
therefore are hard to cost, an example is the Opto-electronic Interconnect I project.
Leverage Ratio Equation: Cost of a project DOE-TV-Analysis / Cost of a Class A Membership Fee
Figure 2: Leverage Ratios for Completed Projects (Estimated Cost of Project)
© 2014 HDP User Group International, Inc. All rights reserved
Page 6
2.3 PUBLISHED PAPERS AND CONFERENCES
Influencing the electronic industry for the benefit of our membership is one of HDP’s goals. One method
HDP utilizes to accomplish this task is to help disseminate technical data and highlight projects by our
members at international conferences. The following technical papers have been published and presented
at international technical conferences throughout the 2013 – 2014 year.
2013
Board Level Reliability And Assembly Process of Advanced Fine Pitch QFN Packages - Jeffrey Chang
Bing Lee – IST Interconnect Service Technology, Li Li – Cisco Systems, Brian Smith- HDP User Group, Joe
Smetana – Alcatel-Lucent, David Geiger – Flextronics , Chris Katzko – TTM Meadville, Richard Coyle –
Alcatel-Lucent, Alex Chan – Alcatel-Lucent – Presented at ICEP, Osaka, Japan
The Green Material Effect on the Board Level Reliability Qualification of QFN Packages – J.C Lee- IST
Integrated Service Technology, Li Li – Cisco Systems, Brian Smith-HDP User Group. – Presented at ICEPT
2013, Dalian, China
Lead-Free Laminate DMA and TMA Data to Develop Stress Versus Temperature Relationship for
Predicting Plated Hole Reliability – Stephanie Moran-Oracle, Joe Smetana – Alcatel-Lucent, Michael
Freda – Oracle. – Presented at SMTAi, Fort Worth, TX, USA
Materials Testing of PWB Substrates to Determine Survivability Through Lead-Free Assembly - Bill
Birch - PWB Interconnect Solutions Inc., Jason Furlong - PWB Interconnect Solutions - Presented at
SMTAi, Fort Worth, TX, USA
Conductive Anodic Filament (CAF) Performance of PWB Materials Before and After Pb-free Reflow
Joe Smetana - Alcatel-Lucent, Kim Morton – Viasystems, Thilo Sack – Celestica - Presented at SMTAi,
Fort Worth, TX, USA
Impact Of Lead Free Assembly On Laminate Electrical Performance For High Layer Count And High
Reliability PCB - Deassy Novita, Gary Brist, and Gary Long - Intel Corporation - Presented at SMTAi, Fort
Worth, TX, USA
Reliability Testing of PWB Plated Through Holes using Interconnect Stress Testing Thermal Cycling
Before and After Pb-free Reflow Preconditioning - Bill Birch, PWB Interconnect Solutions - Presented at
SMTAi, Fort Worth, TX, USA
2014
Establishing Effective Acceleration Testing Conditions and Criteria for Confirming Reliability for High
Density Interconnect Circuits – Bill Birch, PWB Interconnect Solutions – Presented at ECWC13,
Nuremberg, Germany NOTE: Awarded the Best paper at the Conference
Dielectric Material Characterization for PCB Pad Cratering Resistance - Jeffrey Chang-Bing Lee and
Cheng-Chih Chen IST-Integrated Service Technology, Thilo Sack – Celestica, Gary Long – Intel, Chris
Katzko – TTM Meadville, Jack Fisher – HDP User Group – Presented at ECWC13, Nuremberg, Germany
© 2014 HDP User Group International, Inc. All rights reserved
Page 7
2.4 INTANGIBLE BENEFITS OF MEMBERSHIP
HDP User Group projects deliver well documented DOE evaluations, guideline and analysis. There are also
many intangible benefits delivered with an HDP User Group membership. This section highlights some of these
benefits as seen by the project members.
Exclusive HDP User Group member-only access to detailed project methodology, current and past results
and recommendations enabling members to apply project deliverables to their specific area of interest.
Immediate access to results and associated failure analysis as it becomes available allows members to
leverage the benefits identified in projects at the earliest opportunity. The results, verified by several
OEMs participating in the projects, can be used in place of undertaking similar costly in-house evaluations.
Activities are peer reviewed through periodic member meeting status updates lending credibility and
relevance to each program of work.
A collaborative approach, leveraging the knowledge and expertise of members representing a broad
spectrum of the electronics manufacturing supply chain guarantees efficiently executed projects
delivering high returns on the effort invested by our participants. Members have the opportunity to
benefit from gaining direct access to these experts for guidance on deployment within their own
companies.
Quarterly members meetings enable development of strong personal contacts between members which
facilitate discussion on all levels of personal and business opportunities. It gives members the ability to
access and understand all levels of the supply chain. The informal nature of HDP member meetings
encourages more free exchange of non-sensitive information than other conferences.
HDP User Group projects often give members a window into new developments worldwide, such as OptoElectronics and 3D technologies which are quickly moving into implementation.
Our projects regularly achieve a reputation within the industry for developing unwritten standards/test
methodologies of material testing for high reliability applications. Members of HDP User Group can utilize
project data knowing that it has a high degree of recognition and credibility across the industry supply
chain.
A large portion of the supply chain for electronics is now in Asia and HDP User Group, as a global
organization, has many Asian members in every tier. As such, the organization is working to provide its’
members more access to Asian expertise and knowledge by initiating Asian centric projects that run in
time zones more convenient for Asian participation.
HDP User Group projects engage companies within the industry to gain early access to new manufacturing
materials, test methodology and products with a chance to be an early evaluator. An example is our access
to the latest RF TSV test method developed by NIST and the electrically testable back drill methodology.
By doing the project work in-house with their own personnel; our Members avoid many technology
transfer problems. Having worked with the project team, their personnel understand the technology and
results when the project is finished, and no further training is necessary.
© 2014 HDP User Group International, Inc. All rights reserved
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3 PROJECT IMPACT SUMMARY
This section of the report highlights some of the benefits and impact of the projects. Although the benefits of
a project can vary with each company and project, it is important to note that every project affects the
business activities and knowledge base of HDP User Group members. Some projects are designed to improve
the time to market of a technology, improve reliability of a product, reduce development time or develop
guidelines and influence the industry to accept new technologies. This is where the consortium excels and
paves the way for new, lower cost and more reliable products and technologies.
3.1 COMPLETED PROJECTS
HDP User Group will bring 5 projects to completion this year. The following section describes some of the
accomplishments and benefits of these completed projects.
3.1.1 PWB Environmental Life Cycle Analysis: (Lead: TTM-Meadville)
This project was due to complete in 2013 but was extended by the team to enable additional analysis and
benchmarking activity to be undertaken. The electronics industry is becoming increasingly focused on the
environmental impact of their products. European legislation is already in place requiring engineers to
design products that are energy efficient in operation. However, product manufacturing is now coming
under the microscope, driven by market demand and corporate sustainability policies. While there are
industry collaborative programs looking at
many parts of the supply chain, the team
associated with this project identified a clear
gap in the availability of trust worthy data for
evaluating CO2/greenhouse gas (GHG)
emissions and water consumption associated
with PWB fabrication
As customers begin to exert greater demands
on suppliers to measure the global warming
potential (GWP) associated with their
operations, the need by fabricators for a
mechanism to calculate such GWP data on a
PWB design by design basis will intensify. This Figure 3: CO2 Calculator - Summary Page
project developed a calculator to serve this
purpose. The project was designed to generate a model (Figure 3) using real time volume PWB production
energy and water consumption data to determine overall GWP impact and water usage totals as a function
of PWB design. The information gathered represents real consumption data, taking into account process
idling times and plant overheads as well as actual production time, offering a more accurate alternative to
many theoretical derived models currently being marketed. The calculator is available with data already
populated based on measurements from a leading fabricator. This can be used as reference data or the user
can add data from their own facility/supplier.
Project Accomplishments:
The project completed early in 2014 delivering the planned calculator which enables HDP User Group
members to estimate greenhouse gas emissions associated with different PWB designs. The calculator is
unique in that it is based on energy and water consumption readings taken from fabrication plants owned
by one of our member’s high volume fabrication plants. Another feature, not readily available from other
commercially available environmental LCA applications, is the capability to determine results for high
density interconnect (HDI) designs that use sequential lamination processing techniques.
© 2014 HDP User Group International, Inc. All rights reserved
Page 9
While the calculator has been designed around data available from specific production plants, with minor
adjustments, it can be customized to any fabrication facility. Phase 2 of the project will focus of developing
the flexibility of the model to facilitate this and enable non-conventional designs and emerging technologies
to be incorporated.
Significant findings derived from the project:
Design choice has a significant impact on the
GHG emissions associated with PWB
fabrication. Board size, number of layers and
processes used all affect the overall emission
levels. While HDI technology delivers space
efficient solutions, energy consumption is far
more intensive giving higher emission scores
per PWB square area.
Analysis of the individual processes within the
fabrication cycle indicated that a few
operations accounted for the majority of the
fabrication emissions associated with each
Figure 4: Example of CO2 emissions associated with individual
product (Figure 4). Targeting these processes
PWB fabrication processes for a high volume consumer product
for improved energy efficiency will result in
major emission reductions. It was also noted that the overall efficiency levels at which the plant is
operated greatly affects the calculations.
The geographical region in which a PWB is manufactured has a major influence (up to 2x) on the
emissions attributed to it. This is due to the different methods of power generation (e.g. coal fired
generators, nuclear power etc.)
Benchmarking results from the HDP calculator against other commercial LCA applications indicated that
the HDP scores were significantly lower. The exact reasons for this are still being researched but the use
of actual production plant data as opposed to theoretical equipment rating estimates is a likely factor.
Benefits of Project:
The MS Excel based calculator developed by this project allows designers and environmental mangers to
determine the approximate GWP impact of PWB designs produced/procured by their company and
enable environmentally conscious design decisions to be made to reduce the overall impact.
The MS Excel Calculator provides producers and fabricators with a valuable reference tool to make
calculations of environmental impact straight forward and time efficient. Alternative software databases
are available on the market but these are expensive and do not necessarily reflect day to day
manufacturing operations.
3.1.2 High Frequency Laminate Measurements: (Lead: Oracle)
Currently, there are no industry common platforms to evaluate high frequency materials for dielectric loss
(Df) and dielectric constant (Dk). This project is designed to characterize all of the nine different test
processes regularly used by laminators, fabricators or OEM’s and provide the HDP user group membership
with a tool for understanding the individualities of each of these processes.
The project characterization utilized 17 different in-production materials ranging in Dk from 3.3 to 4.7 and
Df from 0.003 to 0.018 with each of the 9 different test processes at several different test locations at
various frequencies (2 Ghz, 10 Ghz, and up to 30 Ghz if possible). Where possible more than one tester
location tested the same material with the same process.
© 2014 HDP User Group International, Inc. All rights reserved
Page 10
All test board coupons have the same resin content,
construction stack-up and copper foil surface
roughness. Both as-received and baked-dry
preconditioning tests were done to check for the
impact of moisture content. Figure 5 shows the test
vehicle layout
Project Accomplishments:
This project addressed a major problem in the
industry - understanding the great diversity of
high frequency Dk and Df test methods with little
known overlap or correlation between them.
This project developed a single test board design
Figure 5: High Frequency Test Vehicle Layout showing
able to contain all the test coupons for the 12
the different test coupons on a single panel
most commonly used methods for testing Dk and
Df above 2 GHz.
The results to date are much better than expected; several of the high frequency test methods show
very good correlations with each other. As an example, Figure 6 shows the correlation between the Triplate resonator method and the Bereskin method.
A final report is being prepared for the membership of HDP, and an industry presentation is planned for
the 2015 IPC APEX/EXPO Technical Conference.
Benefits of Project:
The project report will describe the
different test processes, the coupon
design and test results. All HDP User
Group members will benefit from
information not readily available in the
industry
The entire industry will benefit from this
project as the understanding of the types
of testing and the frequency limits of each
type of test are explained along with an
illustration of the coupon characteristics
required for each test.
The results of this project will not
Figure 6: Correlation between the Tri-plate resonator
eliminate any of the current tests, but will
method and the Bereskin method.
allow a thoughtful discussion between
material suppliers and OEM’s and provide a vehicle of understanding that does not exist today.
© 2014 HDP User Group International, Inc. All rights reserved
Page 11
3.1.3 Optoelectronics: (Co-Leads: Cisco, TTM-Meadville)
To meet the increasing bandwidth demands in high-speed telecom and data communication systems, higher
data rate, higher channel density and longer interconnect links are required. For copper interconnects,
scaling is limited due to fundamental obstacles (such as loss, crosstalk, reflection and parasitic) that may
block copper from meeting the increasing bandwidth
demands of 25Gbps, 40Gbps or even higher. In addition there
is a significant increase in cost/power consumption for copper
to achieve 20Gbps operation and beyond. With the recent
development and market introductions of embedded boardmounted optical transceivers (Avago, Finisar, Ultracomm,
Samtec, FCI to mention a few) and various optical connectors,
the cost of optical interconnect has decreased. With this
trend, optical interconnect can become a viable alternative
for short-range interconnects within backplane, inter-board,
and inter-chip, in the coming years.
The optoelectronics project evaluated the performance of
optical polymer waveguides embedded on a 14 layer PCB
construction. The project selected three dielectric materials
for copper to optoelectronic performance comparison. Figure
7 shows the two test vehicles designed for the evaluations – a
small mixed signal PCB (Waveguide/Copper) and a large PCB
backplane (Copper only). In addition, the project evaluated
connectorized waveguide samples and a 1.4m-longwaveguide loops for their performance (Figure 8 shows the
optical waveguide). Optical testing of the waveguides and
Figure 7. a) 8” and b) 18” copper test
terminated waveguide links were conducted using externally
vehicles tested for SI characteristics (up to
launched test source and fiber-optic ribbons (passive optical
40 GHz)
test board). The project conducted extensive round robin
testing for one waveguide sample to compare different methods of optical measurements.
Figure 8 a) TV1_1 with optical layer on 14L construction, b) L/S 50/75µm polymer
waveguide array c) green light illustrating test pattern with cascading bends.
Project Accomplishments:
Two test vehicles were designed and fabricated with three laminate materials – Isola FR408HR, Hitachi
HE-679G, Rogers RO 6202/2929. These test vehicles provided a method to analyze both copper and
optical waveguides geometries and allowed the team to extract the best practices that will enable next
generation systems with high bandwidth and high speed using waveguide technology and mitigate the
© 2014 HDP User Group International, Inc. All rights reserved
Page 12
risks of copper interfaces. The TV designs are available to the HDP membership for their individual
company use.
Characterization/Measurements include:
o TDR, TDT, VNA, S-parameters (up to 40GHz), crosstalk, IL, RL. Dynamic measurements incl. eye
diagram, jitter budget. Figure 9 shows and example of an eye diagram at 12.5 and 25 Gbps
o Link level assessment (end-to-end
link) using paddle cards with high
speed connectors (Amphenol XCede)
Optical analysis and results obtained for the
critical optical tracing building blocks include:
o Straight, bends and overcrossings.
Multiple design variants incl.
waveguide variables: length, spacing,
geometry (straight, bend, cross).
Channel lengths: 4”, 7”, 35” (spiral).
Two groups with different spacing to
test cross-talk: 5 and 10 mils (125µm
and 250µm)
o Optical measurement including
transmission @ 850nm, @ 1000nm,
Figure 9: Eye Diagram Results for 12.5 & 25 Gbps
bend loss (low mode fill, high mode
fill), crossing loss, eye diagrams @
8Gbps, @10Gbps and BERT
This project confirmed the feasibility of a full optical system implementation using waveguide
technology, in regards to solving the increase in bandwidth and speed. This had not been demonstrated
previously in an open forum.
The project defined several different techniques of terminating the waveguides which will be carried
into the Phase 2 project. AN example is the development of a new edge mounted MT connectors. Figure
10 shows this new edge mounted MT connector.
The test vehicles designed and built allowed an analysis of both
copper and optical waveguides geometries and allowed the team to
extract the best practices that will enable next generation systems
with high bandwidth and high speed using waveguide technology
and mitigate the risks of copper interfaces. The TV designs are
available to the HDP membership for their individual company use.
Benefits of Project:
The final report contains the largest collection of test results
comparing different test methods for measuring optical waveguide
loss ever reported in the industry. The report also includes a round
robin of a waveguide sample tested sequentially by six testing sites
with various methods specified in the report
This project provided the members an in-depth knowledge of the
Figure10: New edge mounted MT
performance and maturity of optical waveguides and also
connector.
demonstrated how optoelectronic PCBs are designed, fabricated,
connectorized and characterized. This information has never been published prior to this project.
HDP product designers and decision makers will gain insight for placement of optical waveguides into
their product roadmaps.
© 2014 HDP User Group International, Inc. All rights reserved
Page 13
3.1.4 Pad Cratering: (Lead: Celestica)
The conversion to lead free Ball Grid Array (BGA) packages has
raised several new assembly and reliability issues. One reliability
concern becoming more prevalent is the increased propensity for
pad cratering on PWBs. Lead-free solder joints are stiffer than tinlead solder joints, and lead-free compatible (Phenolic-cured) PWB
dielectric materials are more brittle than the FR4 (dicy-cured)
PWB materials typically used for eutectic assembly processes.
These two factors, coupled with the higher peak reflow
temperatures used for lead-free assemblies, can transfer more
strain to the PWB dielectric structure causing a cohesive failure
underneath the BGA pads. Figure 11 shows the cratered laminate
under a copper pad due to pad cratering.
Figure 11: Cu pad removed showing cratered
laminate
This project evaluated 34 different
combinations of both filled and unfilled
laminate materials with a (6 layers/93
mils) test vehicle using a single large
BGA. The project evaluated a set of
tests to verify if these various test
methods would produce a similar rank
ordering of a material’s propensity for
pad cratering. These tests included:
single bend to break using resistance
Figure 12: Spherical bend (left) vs. Cold Ball Pull (right) Test Methods
measurements, repeated bend to
break, Cold Ball Pull (CBP Testing), Charpy Impact and Surface Impact testing, and full strain analysis using
spherical bend with strain gauges and dye & pry techniques. Figure 12 shows the Spherical Bend and Cold Ball
Pull test methods.
Project Accomplishments:
All of the individual testing has been
completed with final data analysis in progress.
The project will produce a written report that
will rank order the materials based on
electrical failure due to several mechanical
stresses.
Fig 13 shows an example of the results
comparing the full strain gauge analysis vs.
the single bend to break using resistance
monitoring methods.
Figure 13: Comparison of Full Strain Gauge vs. Single Bend
to Break Resistance Fails
Benefits of Project:
As a major membership benefit, only HDP User Group members will have the full rank order listing of the
34 different laminates based on pad cratering propensity.
Understanding the impact of mechanical stress on the issue of pad cratering will lead to significantly
improved products in the marketplace. This will allow laminate suppliers to improve their material
properties and OEM & design houses to choose laminates with better mechanical properties aligned to
their specific use conditions.
© 2014 HDP User Group International, Inc. All rights reserved
Page 14
3.1.5 Process Sensitive Components: (Lead: IBM)
Industry diligence in managing temperature sensitive components is perceived to be lax, and the
consequences may be significant for complex board
assemblies in high reliability or mission critical
applications. These process sensitive components may
fail when exposed to process temperatures or
chemicals exceeding their qualified parameters to
current industry specifications. See Figure 14 for an
example of a failed component. Some failures may
occur at time zero or there may be a reduction in the
long term reliability of the components. Depending on
the lifetime reliability requirements of the system level
product, these failures may impact the OEMs risk level
Figure 14: Electrolytic capacitor after Pb-free
for quality and reliability.
reflow. Wickham, 2003. This component failed
Final Test after Assembly.
High Reliability and Mission Critical components may be
adversely impacted by exposure to temperatures or chemicals outside of qualified parameters. The
specifications may cover conditions components experience in normal processing, especially lead-free
assembly (Figure 15). Although there may be no obvious damage, problems may manifest themselves in the
form of reduced long-term reliability. This project brings industry attention to manufacturers sensitivity data
verses related industry specifications.
Project Accomplishments:
This Project has compiled a comprehensive guideline document examining and illustrating the risks of
exposing various sensitive components to temperatures or other processes beyond their capability, and
identifying best practices for dealing with the numerous classes of process sensitive components that now
confront the Pb-free electronics industry.
In the process of creating the Guideline, the Team identified
and catalogued specific failure modes for different types of
components, such as capacitors, light emitting diodes, fuses,
inductors and electrochemical double layer or super
capacitors.
The document content includes: the origin of component
process sensitivity, the temperature demands of Pb-free
soldering, the industry specification infrastructure now in
place to manage process sensitive components, and other
Figure 15: Electrolytic capacitor burn from
Pb-free hand soldering. IBM 2007
processes that can have adverse impacts on components,
such as baking or cleaning.
Benefits of Project:
An Industry Guideline Document will be published on the HDP User Group website for temperature
sensitive components and components susceptible to other process sensitivities such as chemicals and
washes. The entire industry will benefit from this guideline document as it will define proper
interpretation and usage of J-STD-020 and J-STD-075.
© 2014 HDP User Group International, Inc. All rights reserved
Page 15
3.2 CURRENT IMPLEMENTATION PROJECTS
During the Implementation stage, project participation and results are limited to HDP User Group members.
All members can participate and contribute to implementation projects by attending regular project calls or
visiting the project page on the HDP website.
3.2.1 Alternative Alloy Study for Hole Fill and Copper Dissolution: (Lead: Nihon Superior)
Copper Erosion is not a new topic in the PWB industry. The uniqueness of this project is that it will identify
the effect of process parameters and board design for
hole-fill with alternative alloys for thick boards (0.130
mil / 12 layers), measure the hole-fill and the amount of
Cu erosion in the wave solder process and determine the
hole-fill vs. Cu erosion rate for various alloys. Figure 16
shows the copper erosion at the knee of a PTH.
This project is a DOE of three different solder alloys,
multiple types of solder waves, and various solder
temperatures / contact times. The components
selected are thermally challenging, DC/DC power
supplies, DIMM’s and large electrolytic capacitors. Via
size and several thermal relief designs are being
evaluated by the project.
Figure 16: Copper dissolution at knee of PTH
Progress to Date:
The wave soldering DoE has been completed with three alloys, two solder temperatures, and two dwell
times with one leg without nitrogen.
Review and analysis of the hole-fill data has
been completed. The effect of component
type, connection type, and hole diameter has
been plotted and analyzed for the three
alloys for the DoE conditions. Also, the effect
of nitrogen was identified. Figure 17 shows
the effect of dwell time on hole fill.
The cross-sectioning of various components
for measurements of the resulting copper
thicknesses is currently in process.
A final report to the HDP membership will be
published by Q4 2014.
Figure 17: Effects of dwell time on hole fill
Benefits of Project:
The primary HDP User Group benefactors of this project will be our solder suppliers, assemblers, and
OEM/ODMs, who will receive a unique industry report that will allow them to understand the tradeoffs
between copper erosion and hole fill for thick communications industry type boards. The report will
characterize erosion, hole fill, solder wave types, contact temperature, and solder alloys allowing a better
understanding of the hole fill/copper erosion tradeoff. It will contain variations in solder temperature, pre
heat and contact time which will give the HDP User Group membership a better understanding of the
solder process.
© 2014 HDP User Group International, Inc. All rights reserved
Page 16
3.2.2 SAC Aging 2: (Lead: Alcatel-Lucent)
ATC testing from previous projects showed that the magnitude of the aging effects on SAC alloys is strongly
dependent on the component type, CTE mismatch, nominal
strain level, and ATC test parameters. Previous work
showed that the effects due to in-situ aging during thermal
cycling can control the failure process of both SAC & Sn-Pb.
This project will determine to what extent thermal cycling
does or does not control the failure process and the effects
of component type, CTE mismatch, strain level and ATC test
parameter have on the aging effects. Further, a comparison
to data collected in previous versions of this project will be
done using the same TV as previous projects completed at
INEMI, UIC and HDPUG (Figure 18).
Progress to Date:
Figure 18: Common SAC Test Vehicle
Currently the testing of the 192CABGA group has been completed and removed from the chambers.
There seems to be anomalous ATC results in the 10 day age case. This is likely influenced by severe
temperature induced board warpage. This board warpage mechanism is under investigation.
The 10 min dwell parts of the 84 CTBGA group are completed. These parts seem to have consistent
results. The 60 min dwell parts of the 84CTBGA group are at ~N50 and seem to have consistent results.
A paper on the results of the F/A of the
84CTBGA group, has been written and
will be presented at SMTAI 2014.
The 3rd samples (18 mo.) of the
Isothermal Aging cells were removed in
July 2014. It had been noticed that a
majority of the 0.5 mm pitch solder balls
have solidified with an interlaced twin
Sn grain structure often mixed with
larger cyclic twin grains. In such mixed
Sn grain morphology joints, the
interlaced twin regions were typically
associated with the printed circuit board
copper pad (Figure 19). Further
Figure 19: Darkfield images using crossed-polarizers of the outer
investigation to follow.
row of 84 I/O CTBGA with 0.5 mm pitch solder joints.
Benefits of Project:
The designer will have a reliable design guide to better select component packages for type, CTE
mismatch, and strain level, along with the PCB manufacturer’s better understanding of the CTE
mismatch in their materials selection.
The material suppliers can formulate or tune their materials to align with the project findings.
The industry will have a quantum leap forward in the knowledge of SAC solder aging and the
relationship of component type, CTE mismatch, the strain level and the ATC test parameter themselves.
© 2014 HDP User Group International, Inc. All rights reserved
Page 17
3.2.3 Modules-to-PWB Interconnections: (Lead: Juniper Networks)
Power bricks are one of few “hold-out” components still demanding wave solder. The conversion to SMT
bricks would allow the elimination of wave processing for many printed circuit assemblies. Currently 1/16th
and 1/8th brick types have wide adoption in SMT with a variety pin/leg styles, this is not the case for the 1/4
brick and above sizes.
This project focuses on the impact of DC/DC module (bricks)
features on soldered PTH hole-fill and the module-PWB
attachment reliability of SMT bricks. The project will
measure the impact of various brick pin and footprint
feature variants such as, gas vents, hole size, and thermal
plane connections on the hole-fill of a pin through hole
soldered joint. Besides the PTH configuration, SMT attach
variants to be studied are “Pure Post”, “PIP/SMT hybrid”,
and “Pedestal and ball”. Figure 20 shows a Pedestal and Ball
configuration. Different brick styles will be studied in a 1/4
brick package to assess comparative thermal cycling and
vibration reliability with the bricks carrying full current.
Figure 20: SMT – Pedestal and Ball
Progress to Date:
A mini project to evaluate vibration testing requirements and methods is complete.
The project test plan is complete.
The test vehicle is in design and fabrication is expected to start soon. High current testing and Vibration
testing have been resourced but the team still has need of an ATC test resource.
Benefits of Project:
This project will benefit the OEM’s/ODMs using DC/DC modules, the module supply industry and other
assembly organizations with the data collected on SMT assembly of large bricks, especially since there is
very little SMT data available for 1/4 and larger bricks.
All HDP User Group Member DC/DC designers will benefit from the reliability data showing vibration at
full current (60A/90A) as this data is not found at industry conferences or in reports.
3.2.4 Multiple Lamination: (Lead: Curtiss-Wright)
As BGA pitch decreases and I/O count increases, stacked microvia designs become more prevalent However,
there is little data in the public domain on the reliability of these stacked designs and what does exist is
disquieting. Previous studies done by PWB
Interconnect Solutions and EIT showed that there
can be a significant reliability degradation of stacked
microvias in certain constructions.
This project is designed to evaluate 2, 3, and 4 stack
microvias both “stand alone” and stacked on buried
via (Figure 21 shows the microvia construction) and
compare the data to a plated through holes (PTH)
using Interconnect Stress Testing (IST) and
TMA/DMA/TGA testing. The test vehicle will consist
of three different thicknesses (.062, .093, and .125)
with various laminate materials (high, medium and
low z-axis CTE) and will simulate 0.8/0.4mm and
1.0/0.5mm BGA pitches.
Figure 21: TV microvia construction
© 2014 HDP User Group International, Inc. All rights reserved
Page 18
Progress to Date:
The test vehicle is being fabricated at two different fabricator locations. One fabricator has completed
both the 12 layer (0.062“) boards and the 18 layer (0.093”) thick boards. The second fabricator has the 12
and 18 layer boards in progress. Both fabricators will also build the 24 layer (0.125”) boards.
IST testing of the 12 layer has started at PWB Interconnect. Some preliminary data analysis has been
shared with the HDP members on the project.
Benefits of Project:
The HDP User Group membership will receive six new IST coupon designs useable on any additional
consortium projects along with a detailed report containing the full variables data. The report will include
an evaluation of thickness vs. reliability and CTE vs. reliability of the various microvia configurations.
The HDP User Group OEM’s, PWB designers and ODMs will learn what design configurations, material
types/characteristics provide the highest and lowest design reliability.
3.2.5 Thin Cu Stress Test: (Lead: Fujitsu)
Thickness of plated copper in a small plated through hole (PTH) or in a through hole with a high aspect ratio
is critical to securing adequate reliability for temperature cycling. Accelerated Temperature Cycle (ATC)
testing is widely used to confirm PTH reliability, but it requires long test times. HDP User Group previously
carried out mechanical fatigue test projects that studied
the life time prediction of solder joints using mechanical
fatigue test and has shown the relationship between
ATC and the mechanical fatigue test. Mechanical
fatigue testing has the possibility of shortening the
solder joint lifetime prediction time and may be
applicable to PTH reliability predictions. Figure 22 show
a typical Weibull plot of the number of cycles to failure.
This project applies the mechanical fatigue test
methodology to PTH reliability. It will develop a
measurement method to obtain stress-strain and creep
properties of thin plated Cu for FEM simulation and
define the similarities and differences between ATC and
mechanical fatigue testing. This project is utilizing Figure 22: Weibull plot of the number of cycles to
collaboration between consortium members from failure.
across the supply chain and experts from Shibaura
Institute of Technology to define and execute the project.
Progress to Date:
The difference of material property between suppliers is not
significant, but the mechanical property of thin Cu plating is
quite different from bulk Cu.
It is possible to evaluate the PTH by applying low cycle
fatigue test using an hourglass shaped plastic sample with Figure 23: Hourglass shaped plastic
sample with thin plated Cu.
thin plated Cu. (Figure 23)
Figure 24 shows the thin Cu fatigue fracture mechanism
found by Backscattered electron image and crystal orientation mapping. Copper crystals show different
orientations on both sides of a microcrack, therefore, the fatigue microcrack may have initiated and
propagated at grain boundary.
The life time of a PTH was obtained by ATC. The project will next complete a FEM simulation to calculate
the inelastic strain range.
© 2014 HDP User Group International, Inc. All rights reserved
Page 19
Figure 24: Shows Thin Cu fatigue fracture mechanism was found by (a) Backscattered electron image and (b)
crystal orientation mapping.
Benefits of Project:
OEM/ODMs, PWB Fabricators and Test Labs will benefit greatly from updated knowledge about
developing a mechanical fatigue reliability prediction test method for printed circuit board/PTH that could
greatly reduce the testing time now required for ATC.
3.2.6 Anti-Counterfeit 2: (Lead: IBM)
Counterfeit products are ubiquitous in today’s society and
have been identified in all segments of the supply chain,
including Defense and Medical. Figure 25 shows the
increasing sophistication of the counterfeiters. Can you tell
which battery is the fake? To address this phenomenon, the
HDP User Group consortium, in conjunction with industry
leaders, created a three-phased project. In Phase 1, the team
identified a protocol listing the information that must travel
Figure 25: A real and counterfeit battery
up and down the supply chain to provide traceability. In
Phase 2, this project will illuminate new and emerging
technologies capable of carrying the information identified in Phase 1.
The team will investigate new and emerging technologies capable of moving information up and down the
supply chain, along with strengths and weaknesses of each, resulting in selection of an optimal technology
for the protocol identified in Phase 1. Figure 26 shows an example of a holographic label and un-clonable
marking technology being investigated.
Progress to Date:
Team members with specific expertise have been
assigned specific technologies to evaluate and sections
to write.
Collecting sections for the Anti-counterfeiting of
Electronics Phase 2 White Paper contrasting the varied
technologies available for Track and Trace. The findings
of this White Paper will identify the optimum technology
for use in an industry trial (Phase 3).
Figure 26: An example of a Holographic label
Benefits of Project:
This project will provide the electronics industry with a side-by-side comparison of technologies capable
of moving a protocol up and down the supply chain.
© 2014 HDP User Group International, Inc. All rights reserved
Page 20
3.2.7 FCBGA Package Warpage: (Lead: Plexus)
Most of the electronic industry is experiencing assembly problems with the decreasing thickness of IC
packages. With denser packages (QFN's, Area Array's and Stacked Packages), the flatness of the packages and
PWB becomes critical. Warpage is an assembly
manufacturing problem resulting in open, weak
joints, Head on Pillow (HOP) and None Wet Opens
(NWO) defects. Figure 27 shows the HOP and NWO
defects often associated with warpage. With the IC's
becoming increasingly thinner, the silicon has less
ability to resist deformation of the component
package. This deformation combined with short IC
leads and a very flexible substrate often exceeds the
termination-to-solder paste gap. Figure 28 shows Z- Figure 27: Head on Pillow (left) & None Wet Open
(right)
axis movement stabilization
Progress to Date:
Several test methods are under evaluation.
One of the proposed methods was found to
be ineffective and dropped, while a second
method required modification by altering
the equipment’s part mounting.
The team developed a new test vehicle
when the original test vehicle proved to be
unstable.
Benefits of Project:
Figure 28: Chart showing the stabilization of the Z-Axis
movement on the final pic and place machine.
This will improve the yields on the EMS
production lines and reduce the restarts/rework in the assembly process.
HDP User Group EMS providers will receive yield improvements from implementing the most promising
mitigation path(s) that will reduce up to 15% of the HOP and NWO defects on assembled products.
HDP User Group OEMs will see a reduction in field failures as a result of improved quality of solder joints.
3.2.8 Lead Free PWB Materials Reliability IV: (Lead: IBM)
This project is the 4th phase of a Lead-Free materials reliability
program that was originally launched in 2008. This phase
focusses on high speed PWB material laminates recently
released for use by the manufacturer or about to be released.
As with previous phases an extensive series of tests are planned
to evaluate mechanical reliability and electrical performance,
and to assess the impact of exposing the materials to typical
SMT soldering conditions associated with the assembly of
highly complex high layer count PWB designs with densely
Figure 29: Typical material damage induced by
packed high thermal mass components. Figure 29 is a typical elevated SMT reflow conditions
example of thermally induced damage.
Progress to Date:
Test vehicles for each of the materials tested are currently in manufacture completing early Q3 2014.
Testing is scheduled for Q3 through early Q1, 2015 with the project completing by Q2, 2015. Figure 30
shows the MRT-5 test vehicle used in the project
© 2014 HDP User Group International, Inc. All rights reserved
Page 21
Benefits of Project:
Test data generated from this project will enable product designers to accurately compare the relative
performance of each of the materials tested, along
with materials tested in previous phases, using
common test houses and procedures for all materials.
This unique opportunity will help the designer to
select, with confidence, the best material for their
application.
SMT reflow conditioning at elevated temperatures
appropriate to complex PWB designs is typically not
conducted in supplier testing. This program therefore
addresses the uncertainty that designers have about
the risk of internal damage and drift of electrical
characteristics potentially induced by these conditions.
Suppliers supporting the project receive independent
test data on the performance of their laminates and Figure 30: MRT-5 Test Vehicle
their competitor’s products allowing them to identify
strengths and opportunities to improve.
3.2.9 Low/No Ag Alloy Solderpaste Reliability Phase 1: (Lead: Flextronics)
The price of metals and particularly silver (Ag) has been increasing in recent years. This has created an
increased interest in the use of low/no silver alloy in the
manufacturing process. Low silver alloy BGA solder balls
(such as SAC105) are being used in products, but there is
very little information about the alternative (low/no) silver
alloy solder pastes, it’s process feasibility and reliability.
Within the past couple of years, many alternative low/no
silver alloy solder pastes have been developed and are
available in the market.
This project will study and document the process
feasibility/characterization and reliability of low/no silver
alloy solder pastes compared to the standard SAC 305
paste for integration into a development assembly line.
Both the microstructure at time zero and intermetallic
layer will be analyzed along with printability, wetting,
bridging, voiding behavior and other common defects.
Three surface finishes, OSP, I-Ag, ENIG and 8 components
will be evaluated in both air and N2.
Figure 31: The Low Ag alloy candidates.
Progress to Date:
The 17 candidate alloys have been chosen. Low Ag/High Temp has 9 candidates, Low Ag/Low Temp has
8 candidates under evaluation. Figure 31 shows the Low Ag alloy candidates.
The eight components have been procured and the test vehicle fabricated.
The Characterization Reflow Profiles have been developed and both the High Temp and Low Temp Alloys
have been processed. The process assembly and metallurgical evaluations are underway.
© 2014 HDP User Group International, Inc. All rights reserved
Page 22
Benefits of Project:
HDP User Group OEMs and EMS members will benefit by their increased understanding of the potential
to introduce a reduced cost low/no silver alloy paste into products with a suitable use condition.
Low Ag / Low Temperature Alloys can extend the temperature headroom for assembly. We are running
out of temperature headroom with Pb Free, especially for large components. This information will benefit
the CMS/EMS and component suppliers.
Low Ag / Low Temperature Alloys can improve reliability of the final OEM product by lowering thermal
stress and potential warpage on the components/PBCA.
3.2.10 Optical Flexible Printed Circuit (FPC) Assembly: (Lead: Huawei)
The uptake of use of optical transceiver components in data products has increased significantly in recent
years. The trend is set to continue but, driven by space
constraints, optical package designs and the available space
to interconnect them will continuously shrink in size. Due to
temperature sensitivity, these devices cannot be attached
directly to PWBs and are therefore typically connected via
flexible printed circuit (FPC) boards which are attached at
the PWB interface using local heating techniques such as hot
bar thermodes (Figure 32). With attachment pad arrays
decreasing in pitch and size, and designers increasingly
adopting multiple row and irregular layouts, the demand on
assemblers to achieve reliable high yielding connections has
intensified, challenging traditional soldering techniques.
Figure 32: Hot Bar Thermode for FPC to PWB
soldering
This project explores a range of assembly techniques for
attaching fine pitch FPCs, including hot bar soldering, anisotropic conductive films (ACF), laser and microwave soldering with an aim to evaluate and optimize each technique to achieve maximum yields. Using
custom designed test vehicles the team will characterize and determine the best process parameters for
each method before running extensive reliability testing to assess the mechanical and thermal integrity of
the resulting joints. The project will be run in a series of phases with phase 1 focusing on hot bar and ACF
attachment processes.
Progress to Date:
The test boards and FPCs have been designed and
fabricated and the first round of assembly trials have
been completed and evaluated (Figure 33). The second
round of assembly trials followed by final build of test
boards will take place in Q3 2014. The project is
progressing on schedule with a phase 1 finish date
forecast for Q1 2015.
Benefits of Project:
Figure 33: Example of FPC attachment using the ACF
process
Findings from the project will provide printed circuit assemblers with valuable process
recommendations about the yield capabilities and associated reliability data for fine pitch FPC assembly
for each attachment technique evaluated. This will assist in selecting the most suitable approach,
minimize process set up and shorten new product introduction cycles.
For package designers, the project findings will offer important design for manufacture feedback
ensuring that optical transceiver and associated FPC designs are compatible with industry leading edge
assembly capabilities.
© 2014 HDP User Group International, Inc. All rights reserved
Page 23
3.2.11 PWB Backdrilling Failure Analysis: (Lead: PWB Interconnect Solutions)
Back drilling, or controlled depth drilling of plated through holes (PTH), is increasingly being used in high speed
designs (Figure 34). While back drilling of PWBs helps to remove
signal distortion by removing via related stubs, reliability issues
attributed to this practice appear to be on the rise. Both the
number of back drilled vias and the variation of depths (any & all
layers) are increasing. Design rules are driven by electrical
requirements, not necessarily based on PWB reliability data or
fabrication capabilities.
This project will explore the reason for back drilling related PWB
failures and identify potential solutions and design/process
guidelines to prevent future problems associated with this
process.
A phased approach will define existing design
tolerances, test the reliability of these tolerances/designs and
develop a recommended design guide based on reliability results.
A series of new electrically testable backdrill coupons have been
designed and will be evaluated in the project.
Figure 34: Backdrilled Vias
Progress to Date:
Thirteen electrically testable coupons have been designed, 3 modified IST coupons for evaluating the
backdrill reliability at three different depths, 3 new construction coupons to electrically determine the
exact depth of each layer of interest in the stack (Figure 35) and 1 stub length measurement coupon
using TDR signal reflection.
The DoE has been ratified to evaluate 3 conditions; as
received, pre-conditioned (6X @ 260 C) through a reflow
oven and simulated reflow conditioning as per IPC TM 650
IPC 2.6.27 on the PWB IST system.
The test vehicle is in fabrication at 3 sites.
Benefits of Project:
This methodology will save the OEM/PWB fabricator money
in post build inspection by providing a coupon design and
test methodology to electrically test backdrill holes for
reliability and conformance to specification during
fabrication.
These design guidelines will help reduce development cost
for redesigns and improve time to market by delivering a set
of design parameters for HDP members that will guide OEM,
ODM, and system designers in designing a more reliable back
drill product.
© 2014 HDP User Group International, Inc. All rights reserved
Figure 35: Construction Coupon
Page 24
3.3 CURRENT DEFINITION PROJECTS
Projects at the definition stage remain open to all interested parties. The consortium wants to gather as much
information as possible from both the membership and industry and develops the project plan during this
phase. A good project plan is essential to get the necessary resources and deliverables aligned.
3.3.1 Through-Silicon Vias (TSV) Signal Integrity Project: (Lead: NIST)
One way to increase bandwidth in high-end network and computer systems is to take advantage of the third
dimension, Z. The two primary proposals for this method are 3D Packaging (stacking active silicon devices)
and 2.5D Packaging (horizontal MCM where a silicon substrate has TSVs, Figure 36 shows an example of a
2.5D device). Examples of these in early
production are Micron's Hybrid Memory Cube
(3D) and Xilinx' Virtex 2000T (2.5D). Very little
data exists in the public domain that actually
verifies the bandwidth advantages of 2.5D
Figure 36: A cross-sectional view of the Device Under Test (DUT)
Packaging. This project is designed to close that circuit for the 2.5D portion of the test
gap.
Traditional package-on-PCB will be tested alongside with devices mounted on 2.5D interposers. Figure 37
shows the proposed test vehicle layout. The following S-Parameter data will be generated. The TV will contain
6 interconnects in 3 differential pairs for each of the conventional and 2.5D packaging. The middle pair is the
victim, and the two side pairs act as aggressors. Using a VNA the project will measure 12 port S-Parameters
to create an .s12p touchstone file deck.
Differential insertion loss (SDD21)
Differential reflections (SDD11)
Differential cross talk (FEXT and NEXT)
Common and Differential mode impedance
Delay
Differential to common mode conversion
number
Progress to Date:
Figure 37: Proposed test vehicle layout
Project has been defined
Open for project membership and resource commitment
Benefits of Project:
The project will produce a written report that will provide the S-Parameter data and bandwidth capability
of not just the entire circuit, but also the individual components of that circuit, such as TSVs. This will be
done by de-embedding using a variation on the circuit shown above. As a major membership benefit, only
HDP User Group members will get early access to S-Parameter data, including TSVs themselves. Packaging
strategy decisions can be made based on data.
© 2014 HDP User Group International, Inc. All rights reserved
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3.3.2 Electro-Chemical Migration (ECM): (Lead: Kyzen)
The current industry standard test protocols were originally developed to identify highly ionic contaminant
levels (halides) after a cleaning process. Various forms of corrosion and ECM failures resulting in field failures
on products that passed the current cleanliness and
corrosion resistance test protocols have demonstrated
that these test procedures are not effective. Figure 38
shows an example of an ECM open circuit defect. The
current testing does not take into consideration various
acceleration factors associated with no clean flux and
product design features.
This project is designed to create and evaluate the
failure mechanisms, correlate failures in test method
gaps and identify modifications to the test methods
required to predict where a failure will occur (Figure
39). The project will collect and evaluate test data and
Figure 38: ECM open circuit defect
draft proposed changes to existing test methods, test
protocols and the IPC and JEDEC specs.
Progress to Date:
The fabrication of all the DoE test vehicles
are completed and are being uniquely
identified using an ID system.
Process flow charts have been developed
for each cell on each test vehicle with a
unique spreadsheet for each IPC test
protocol.
Identified the location and quantity of
the Witness boards and test observation
boards. These are being kitted for
shipment.
Benefits of Project:
Figure 39: Test Methods to be used in the project
HDP User Group OEMs and EMS
suppliers will greatly benefit by redefining their processes to eliminate these corrosive defects. As a
result the OEMs could reduce these types of field failures by almost 100%, reduce the failure analysis
and engineering time, and improve customer satisfaction.
HDP User Group OEMs and EMS suppliers will benefit as the ECM defect reduction will reduce potentially
expensive line purges/restarts and product recalls both of which can damage EMS/OEM relationships.
3.3.3 Press Fit Technology: (Lead: Ericsson)
More and more products use electronic devices to communicate, and in 2020 it is expected that there will
be more than 50 billion connected devices in the world.
This means that many electronic products, especially
mobile base stations and core network nodes, need to
handle enormous amount of data per second. One
important link in this communication chain is high speed
press fit connectors (Figure 40) that are often used to
connect mother boards and back planes in core network
nodes. These new high speed press fit connectors have
several hundreds of thin, short and frail pins that easily
Figure 40: Typical high speed press fit connector
could be damaged if not produced and handled
© 2014 HDP User Group International, Inc. All rights reserved
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correctly. These new connectors are very expensive and small variations in via hole dimensions and hole
plating thickness will affect the connections for these sensitive
press fit pins. If the holes are too small, the pins will bend. If the
holes are too big, they will not form a gas tight connection. These
connectors are at high risk for board assembly failures, therefore
it is important to have a robust rework process.
The project goal is to understand and document how rework
affects press fit connection strength and hole wall deformation
(Figure 41) for new high-speed press fit connectors.
In this project the damages that rework could cause (e.g. holeFigure 41: Example of hole wall
wall deformation and cracks in the plating) will be evaluated. The
deformation
strength of the press fit connection will also be investigated by
examining how the insertion and retention forces are affected by
several rework cycles. The project will also evaluate the gas tight connection after each rework. Figure 42
shows a “good” gas tight connection.
Progress to Date:
Team has been selected and the DOE defined based upon specific resource commitments.
The test vehicle is in design.
Specialized resources for the gas tight connections
are being identified.
Benefits of Project:
There is very little public information on rework of
these new high speed press fit connectors. The
entire supply chain will benefit from this project. The
results of this project will be published to the HDP
User Group membership in a comprehensive final
report.
Figure 42: Picture of a “good” gas tight
connection
3.3.4 Lead Free PWB Materials Reliability Phase 4: (Lead: IBM)
This project was created based on findings from
the recently completed Pb-Free PWB materials
reliability project. Delamination testing in that
project revealed that over 60% of the materials
evaluated, using 20 layer test boards, exhibited
signs of material damage and delamination after 6
x solder reflow pre-conditioning (Figure 43).
Furthermore, most of the damage was detected
around test coupons with via arrays on a 0.8mm
pitch. Other independent work carried out by
project members pointed to damage being more
prevalent on certain types of constructions and
specifically where power distribution planes are
located in the middle layers of a PWB. This project
will study the influence of printed circuit design on
the propensity for material damage to occur in
SMT reflow soldering. Three different test vehicle
designs with 12, 16 and 20 layer constructions will
be used. A range of test coupons with different
Figure 43: PWB Materials delamination testing results
© 2014 HDP User Group International, Inc. All rights reserved
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pitch via arrays are to be incorporated into the design. Figure 44 shows the proposed Test Vehicle. Different
materials, selected for their tendency to partially delaminate during previous materials reliability testing, will
be evaluated. The project will run in parallel with the Phase 4 of the Pb-Free PWB materials reliability
project.
Progress to Date:
The project is currently in definition stage and
scheduled to start the implementation phase late
in Q3 2014.
All resources have been identified and preliminary
design work has been completed.
Fabrication of test vehicles will commence in
September when capacity becomes available from
our committed fabricator.
Benefits of Project:
Product designers/engineers will gain a greater
understanding of how design choices can
influence the chances of potential reliability issues Figure 44: Modified MRT-5 test vehicle with multiple pitch via
associated to laminate and pre-preg performance.
Using these project results in conjunction with the findings from the Pb-Free PWB materials reliability
program will help to de-risk material selection for specific designs and greatly enhance the chances of a
positive qualification testing outcome.
3.3.5 BFR/PVC-Free Cables II: (Lead: IBM)
The first HDP PVC Free project completed in 2012 identified several potential candidates to replace
Brominated Flame Retardants (BFR) and Poly Vinyl Chloride (PVC) in cables (Figure 45 shows an example of a
cable). Several obstacles remained before complete
implementation of an alternative could be realized. Processing
and cost issues remained, as well as requirement and
specification issues.
There are no cable industry trade organizations that create and
distribute specifications for the industry. Current specifications,
such as those written by Underwriter Laboratories (UL), were
written around BFR/PVC, and because no material exists with
exactly the same properties as BFR/PVC, no replacement
material will meet those specifications.
Progress to Date:
Figure 45: Example of an electronic cable
Team selection has been completed
The cable selection and DOE has been completed and the project is ready to go to the build step.
The team is looking for a cable source.
Benefits of Project:
This project will provide the basis of unifying the current global standards into one comprehensive
document that will serve as the definition for BFR/PVC free cables. The outcome will be environmentally
friendly cables that will be universally accepted and specified by OEMs for use in their associated
products.
© 2014 HDP User Group International, Inc. All rights reserved
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This project will bring together the entire supply chain required for success. Resin manufacturers, cable
manufacturers, OEM’s and the U.S. standards organization to develop materials build cables and test
them to U.S. and International specifications.
3.3.6 Optoelectronics II: (Lead: Cisco/TTM-Meadville)
Phase 2 of the HDP optoelectronic activity is a critical phase in helping HDP members understand the
differences between optical waveguide and copper channels using different type of dielectrics. Phase 2 will
leverage the knowledge developed in Phase 1 in addition to validating different components needed for a
system level integration.
Phase 2 will bring a different perspective to the optoelectronic task group by building a “pseudo” system
level demonstration vehicle (Figure 46) that will serve as a baseline for future optical system deployments.
This pseudo system will have physical
attributes found in today’s systems
such as: routers, switches, and storage
systems. Its’ design will rely on
photonic components to solve many
limitations of electrical interfaces. The
channels will be a mix of polymer
waveguides and fibers to enable high
bandwidth per link at speeds
exceeding 50 Gb/s per channel. The
pseudo system will be composed of
many linecards that will be inserted
into a chassis type of architecture to
mimic today’s systems. These
linecards will be interconnected using
Figure 46: Diagram of pseudo optical test system
optical links and transmit and receive
high bandwidth and high speed
signals. Features that may be introduced in this design include:
Several optical channels to reflect the flexibility and density needed for high density system-like
architecture.
New high speed transceivers (transmitters and receivers) will be used from different suppliers.
Optical connectors will be used to demonstrate the termination of waveguides and fibers, interconnect
between linecards and backplane, and interconnect between the transceivers and the related linecards.
The linecards will be a pluggable type that can be inserted to a chassis containing an optical/hybrid
backplane.
The pseudo system will be active in generating, detecting and processing signals/data.
Progress to Date:
The project team has been formed
The primary architecture has been defined and ratified
The design concepts have been started by Seagate at their Great Britain location.
Engent will provide assembly support
Benefits of Project:
The system will be used to demonstrate the power of optical integrated channels and the set of
challenges that need to be solved to put such systems on the market. The data that will be generated
will serve as first in the industry to put such fully integrated system with all advanced components.
© 2014 HDP User Group International, Inc. All rights reserved
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3.3.7 Ultra-Thin HDI Multi-Purpose Test Vehicle: (Lead: TTM-Meadville)
As the electronics market moves to smartphones and tablets, miniaturization and modularization with high
flex content is becoming the norm. Extensive use of SoC designs with SiP, PoP, low profile CSP, WCSP and
Micro QFN devices with ultra-thin 10 – 14 layer HDI PCBs are now the rule. As a result of this transition, the
older test vehicles have become obsolete and are no
longer applicable, forcing the PWB fabricators and
EMS to make a different test vehicle for each product.
This engineering effort drives delays in production
and manifests itself as an increased cost for both
OEM and suppliers. The current test vehicles do not
capture the newer interconnect density or thinness,
and often miss potential failure mechanisms (e.g., ion
migration).
This project will design, build, test and standardize an
open-source rigid High Density Interconnect test
vehicle for qualification of components, PWBs’ &
Printed Circuit Board Assemblies (PCBAs’). The TV
(Figure 47) will be scaled to smartphone form factors
and modularized for various mixes of bare board &
assembly testing.
Figure 47: HDI PCB test vehicle
Progress to Date:
The design of the PCB TV is now complete and ready to prototype.
The first version design of the PCBA TV is now in final review.
The components have been defined and selected.
Benefits of Project:
Cycle time to approve new material could decrease by five to six times.
Introduction time for a new product design will be reduced two fold.
Manufacturing cycle time for new products will be cut in half.
© 2014 HDP User Group International, Inc. All rights reserved
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3.4 CURRENT IDEA PROJECTS
Idea phase projects are in the beginning stages of project formation and are often newly proposed projects.
Participation in the idea phase of projects offers the greatest opportunity for members to influence the
project’s direction. The projects go through a predefined gating process before moving to the definition phase,
which assures maximum return to our members.
3.4.1 Mini-Power Cycles: (Lead: Ericsson)
Energy efficient operation is becoming a must have in all electronic products. The ability to power down and
then power up quickly is a new constraint being placed on all new equipment for improved energy efficiency.
The advent of Pb-free alloys is expected to increase susceptibility to power cycling-induced damage. This is
exacerbated in outside plant equipment where the new rapid mini-power cycling is coupled with the stress
from diurnal cycling and typical thermal operating conditions.
This project proposes to investigate new energy saving power up and down operating modes and their
potential impact on reliability of Pb-free alloys. The objective is to provide realistic assessment of the
interaction between emerging, higher-stress operating conditions and the Pb-free alloy formulations.
Project Focus Areas:
Prior work on this topic was researched by the team to develop ideas on potential test vehicles. Some
failures have been seen on large solder joints
(Figure 48). One potential idea proposed is to
develop a test vehicle to look at various solder
alloy performance under mini-power cycling.
Another area of interest is large processor
devices in which various sections of the large
array packaged devices cycle and cause localized
stress. The team has been investigating potential
test vehicles and potential test methods.
Benefits of Project:
The main benefit of this project will be to assess
reliability impact of mini-power cycling and Figure 48: Large capacitor - solder joint failure caused by
potential methods for mitigation of any failures power cycling
found.
© 2014 HDP User Group International, Inc. All rights reserved
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3.4.2 TSV SMTA Characterization Guidelines and Reliability Project: (Lead: NIST)
We learned in the late 90s about the effect on the new Flip Chip PBGA packages by board-level SMTA
processing and strains imposed by stiff PCBs in the network and server regime. Standard package-level
reliability tests were inadequate to predict the behavior of these devices after mounting on boards. Also,
much effort had to be spent on SMTA process development and characterization to achieve high quality solder
attach to PCB.
These issues will likely be much worse with the new TSV packages. The TSV structures themselves are delicate
and very little is known about their behavior under bending stress. On top of that, it is very likely that these
silicon devices will come from the most advanced CMOS process nodes, which come along with very delicate
low-K dielectrics. Figure 49 shows an
example of an advanced 2.5D package.
All packages and PCBs are slightly
warped, there is a concern about what
happens to the silicon devices when
they are soldered flat to a PCB.
This project is intended to get an early
look at these board-level issues with
2.5D packaging.
Figure 49: Example of an advanced 2.5D package
Project Focus Areas:
2.5D Package Assembly Process Development
Package-level Reliability Report. NIST RF-based fault detection much more sensitive than Event
Detectors or DC resistance to detect incipient failures
Detailed SMT Assembly Characterization Report
SMT Assembly of 2.5D Packages Guideline Document
Board-level Reliability Report
Board-level Mechanical Stress Models of 2.5D Package
Thermal Resistance Report, empirical + modeled
Benefits of Project:
This project will benefit package producers and silicon providers who typically do not provide data on
SMTA guidelines or expectations for board-level reliability. They can start providing this data to
customers in order to help them with the learning curve on New Product Introduction.
OEMs and users of 2.5D packaging will be able to make good package strategy decisions based on data.
© 2014 HDP User Group International, Inc. All rights reserved
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3.4.3 Future HDI: (Lead: Curtiss-Wright)
BGA pitch is moving steadily downward and high I/O BGAs are common at 1mm and 0.8mm pitch and
starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large
I/O BGA’s at 0.5 and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every
Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less).
There is interest in determining the maximum PCB thickness that can be supported with “Any Layer”
designs. Figure 50 shows a proposed stack-up design for the TV.
High density packages require 3 + stacks of
microvias for routing (depending on how many I/O
and design specifics) just to escape route these
packages. It is inevitable that high I/O BGAs for high
complexity products (Telecom, Server, etc.) will also
trend downward in pitch, following the consumer
trend.
The uniqueness of this project is using a new
construction concept merging aspects of today’s
high end telecom/computer designs with aspects of
consumer PCB’s. There is no other similar project
known to have been proposed or completed.
Project Focus Areas:
ATC test evaluation of the technology
Define the current carrying capacity
IST thermal cycle analysis
CAF analysis
Figure 50: Proposed TV stack up/design
Benefits of Project:
This project will design, build, test and publish to the membership of HDP a report on the current
carrying capacity of the technology, an IST thermal cycle analysis of the technology, a CAF analysis and
possibly some electrical analysis. Finally the membership will receive a complete ATC test evaluation of
the technology
© 2014 HDP User Group International, Inc. All rights reserved
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4 COLLABORATION AND INFRASTRUCTURE DEVELOPMENT
External collaboration with Universities, Government and Industry organizations and other Consortia is an
important part of the organization’s success and value. It is often through these collaborative efforts that HDP
User Group can influence industry specifications, direction and infrastructure development. The membership
gains insight into larger industry issues and often an early look at new equipment, materials and technologies
through these collaborations. The following section highlights some of collaboration and infrastructure
development efforts and benefits.
AREA Consortium: PWB Materials Reliability Project and Future HDI project
CAMEST: HDP facilitators are working with CAMEST to develop their publication on Gap Analysis of 2.5D
and 3D packaging
IEC (International Electrotechnical Committee): The HDP User Group Optoelectronics project waveguide
test protocol is the basis for an IEC specification on measuring optical waveguide performance.
iNEMI (International Electronic Manufacturing Initiative): HDP User Group and iNEMI exchanged raw data
information on SAC Aging II test vehicle. This was a common test vehicle used by both consortium in their
SAC Alloy analysis projects.
IPC (Association Connecting Electronics Industries): HDP User Group acts as a technical source for the
“IPC International Roadmap for Electronic Interconnections”. HDP User Group provides technology
updates and reviews selected chapters. The Electro Chemical Migration Project will propose changes to
existing test methods and test protocols for modification/updates to IPC’s Coatings and Cleaning
subcommittee specifications. The IPC Ambassador Council and HDP User Group are jointly working on a
project to evaluate PCB Counterfeit materials.
JEDEC (Joint Electron Devices Engineering Council): The Electro Chemical Migration Project, based on the
results of their activities, will propose changes to existing test methods and test protocols for
modification/updates to JEDEC specifications.
MIT (Massachusetts Institute of Technology): The PWB Environmental LCA project team has established
a collaborative relationship with members of the MIT Materials Systems Lab. MIT is providing statistical
and uncertainty analysis of data produced by the project as part of a broader life cycle analysis initiative.
NIST (National Institute of Standards and Technology): NIST is one of our Infrastructure development
partners. Their collaboration and input is helping the consortium develop industry infrastructure needed
for rapid deployment of new technologies. Yaw Obeng from NIST is chairing our two projects on TSV’s
and is also active in the Anti-counterfeiting Electronics Project.
PhoxTroT: The HDP User Group Optoelectronics project has been in contact with the PhoxTroT research
group out of Europe. They are discussing mutual activities that will benefit both organizations and move
optoelectronics technology forward. PhoxTroT is a large-scale research effort focusing on highperformance, low-energy and cost and small-size optical interconnects.
PINFA (Phosphorus Inorganic and Nitrogen Flame Retardants Association): HDP User Group is a member
of the PINFA committee.
Shibaura Institute of Technology: The Thin CU fatigue testing project is working with Shibaura Institute of
Technology in Japan to define the testing methodology, conduct modeling, project definition and
performing some of the testing.
© 2014 HDP User Group International, Inc. All rights reserved
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5 LOOKING AHEAD
Every year industry experts and pundits forecast the demise of More’s Law, the insightful observation that
the number of transistors in semiconductor devices doubles every 2 years. This observation has both
characterized and driven the industry for the last 50 years, and many innovations in lithography and
processing have kept us on the line; however, as semiconductor feature sizes scale below 20 nanometers
and the cost of a new IC fab exceeds $1 billion, the dire predictions of falling off the curve are appearing
more realistic.
Many innovations in materials and processing, particularly lithography, are being pursued to keep the
industry on the curve, and the area of packaging and interconnect technology is receiving increased
emphasis as the traditional methods begin to run out of steam. Although second level packaging and
interconnect cannot double the number of transistors on a semiconductor device, it can offer many
solutions that increase the system level performance and reduce cost similar to the effect of increasing
transistor density. As semiconductor feature sizes approach sub20 nanometers, packaging and interconnect
technology is going to become a critical component of keeping the industry on the More’s law curve of
performance.
HDP User Group, as a Member driven organization is responding to this with projects in the areas of
Through Silicon Via (TSV) signal integrity, Optoelectronics 2, Optical Flexible Printed Circuit Assembly, and is
growing projects in the idea stage in TSV SMTA Characterization Guidelines and Reliability and Future HDI.
With feedback from the industry experts on our Technology Committee, and guidance from the HDP User
Group membership and Board of Directors, we expect to see more projects in advanced packaging and
interconnect in the coming year.
Advanced technology is important, but our membership prospers through the products they make using
today’s technology and manufacturing processes, and those technologies and processes are far from
perfect. In addition to efforts at constant improvement, new materials are being introduced at an increasing
rate and pressure from environmental conscious manufacturing issues requite that we constantly evaluate
and tweak our manufacturing to insure the highest quality at lowest cost. This is where HDP User Group
really shines. These types of issues face every company in the supply chain and in today’s world of
distributed manufacturing, the lowest cost solutions are those supported by the supply chain rather than
just one company. By working together, sharing the costs, risks and results, our Members find mutually
supported solutions faster and cheaper than if each company shouldered the entire burden alone.
As a result, HDP User Group’s project portfolio will continue to be focused on relatively short term
technology and manufacturing issues. Through the direction of our Members, we will continue to put major
effort into Environmental Manufacturing and Compliance with projects like our PWB Environmental
Lifecycle Analysis 2, SAC Aging 2, Lead Free PWB Materials 4, and Manufacturing technology with projects
like Board Mounted Power Supply Modules, Multiple Lamination, and Backdrilling Failure Analysis and
Reliability.
More’s Law has been a strict taskmaster but by working together and sharing resources and risk, the
industry will continue to march along that curve delivering continuously increasing performance at
continuously reduced cost like no other industry in the world; and HDP User Group will be there as one of
the tools the industry uses to achieve that remarkable goal.
Marshall Andrews
Executive Director of HDP User Group
© 2014 HDP User Group International, Inc. All rights reserved
Page 35
6 LIST OF MEMBERS
Executive Level
Celestica
Cisco Systems
Huawei
IBM
Juniper®Networks
Oracle
Panasonic
Sanmina
FCI
Flextronics
Freescale
Fujitsu
Hitachi Chemical
Indium
Integral Technology
Introbotix
Isola
IST
ITEQ
Kyzen
Nabaltec
Nihon
NIST
NVIDIA
Park Electrochemical
Phillips Medical
Plexus
Polar Instruments
PWB Interconnect
Rogers
Shengyi Tech (Sytech)
Senju Metal
TTM
Viasystems
WUS PC Inc.
Corporate Level
Agilent
Akrometrix
Alcatel-Lucent
Arlon
Boeing
Ciena
Clariant
Compeq
Conpart AS
Curtiss Wright
Dell
Doosan
Elite
Engent
Ericsson
© 2014 HDP User Group International, Inc. All rights reserved
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7 COMPANY INFORMATION
HDP User Group International, Inc.
5722 E. Sugarloaf Trail
Cave Creek, AZ 85331
Phone: 480-951-1963
www.hdpug.org
For general or management questions,
Contact Marshall Andrews, Executive Director: Marsh57@HDPug.org
For information or help in becoming a member of HDP User Group,
Contact Larry Marcanti, Marketing Director: Larrym@hdpug.org
For administrative information,
Contact Kim Andrews, Administrator: kima77@hdpug.org
For Purchasing and Billing questions,
Contact Darryl Reiner, General Manager at Headquarters in USA: DarrylR@HDPug.org
© 2014 HDP User Group International, Inc. All rights reserved
Page 37
USA Office: Cave Creek, Arizona USA
European Office: Alvsjo, Sweden
Far East Office: Tokyo, Japan
www.hdpug.org
© 2014 HDP User Group International, Inc. All rights reserved
Page 38
