Experiments in Analog Electronics

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Ministry of Higher Education and
Scientific Research
University of Technology
Department of Electrical Engineering
Analog Electronics Laboratory
Experiments in Analog
Electronics
By
Firas Mohammed Ali
2013
Ministry of Higher Education and Scientific Research
University of Technology
Department of Electrical Engineering
Analog Electronics Laboratory
Experiments in Analog
Electronics
By
Firas Mohammed Ali
Reviewed by
Nidhal H. Fathalla
&
Dr. Ahmed S. Ezzulddin
2013
Preface
Experiments in Analog Electronics is a manual designed specifically to enhance the practical
side of a contemporary course in analog electronic circuits for the second-year electrical
engineering students. Each experiment contains the necessary theoretical analysis of the
relevant topic beside the application circuits. A well-organized systematic procedure is also
included in each experiment to facilitate the practical work. In addition to that, discussion
questions and problems are added for the sake of extending student understanding of the
topic, and to increase his/her intuitive sense and thinking.
The practical circuits are to be implemented on breadboards using the off-the-shelf
components available in the laboratory, and then would be tested using suitable equipments
and instruments to see the operating characteristics of the circuit. Students can then compare
their measured quantities with the calculated values and write their reports. Students should
learn the construction of the practical circuits as well as the diagnosis of connection faults.
Their experience can be accumulated from one experiment to another.
In summary, this work is the outcome of two years teaching and training students the art of
practical electronic circuit implementation and testing. I hope that this effort be helpful and
adequate for the curriculum of second year electrical engineering.
Firas M. Ali
Baghdad, 2013
i
Acknowledgements
I would like to express my deep gratitude to the senior lecturer, Mrs. Nidhal H. Fathalla,
for reviewing the manuscript of this manual. Her valuable notes and suggestions were very
useful in writing the theoretical sections of the experiments. Actually, she has a long
experience in this field.
The continuous advice and technical support of Dr. Ahmed Saadoon Ezzulddin is highly
appreciated. His discussion and scientific notations about the topics, material, and procedures
of the experiments were very helpful in preparing them. He also provided me with a valuable
textbook about the subject.
Finally, I am also indebted to Assistant Prof. Dr. Hadi Tarish, the head of electronic
engineering division, for his encouragement and support.
ii
Table of Contents
Subject
Page
Experiment 1: Diode Characteristics ………………………………………………....
1
Experiment 2: Rectifier Circuits ……………………………………………………...
7
Experiment 3: Clipping and Clamping Circuits ………………………………………
17
Experiment 4: The Zener Diode ………………………………………………………
25
Experiment 5: Light Emitting Diodes ………………………………………………...
35
Experiment 6: Characteristics of Bipolar Junction Transistors ……………………….
41
Experiment 7: Transistor DC Biasing Circuits ……………………………………….
53
Experiment 8: Logic Gate Circuits …………………………………………………...
61
Experiment 9: The Common Emitter Amplifier ……………………………………...
73
Experiment 10: The Common Base Amplifier ……………………………………….
83
Experiment 11: The Emitter Follower ………………………………………………..
89
Experiment 12: Amplifier Frequency Response ……………………………………..
95
Experiment 13: JFET Characteristics ………………………………………………...
101
Experiment 14: The Common Source Amplifier ……………………………………..
107
Appendix-A: Resistor Color Code Chart ……………………………………………..
113
Appendix-B: Data Sheets for Active Components …………………………………...
115
iii
Diode Characteristics
Experiment 1
Experiment 1
Diode Characteristics
Objectives
The purpose of this experiment is to measure and plot the forward and reverse IV
characteristics of a silicon diode, and to measure the DC and AC (dynamic) resistances of the
diode.
Required Parts and Equipments
123456-
DC Power Supply
Digital Multimeters
Electronic Test Board
Small Signal Silicon Diode 1N4148
Resistors, 470 Ω, 1 MΩ
Leads and wires
1. Theory
When a P-type and N-type semiconductor materials are effectively made on the same crystal
base, a diode is formed. The P-type side of the diode is called the anode, and the N-type side
is called the cathode. When the diode’s anode is at a higher potential than the cathode, the
diode is forward-biased, and current will flow through the diode from anode to cathode. On
the other hand, if the anode is at a lower potential than the cathode, the diode is said to be
reverse-biased, and only a very small reverse current flows from cathode to anode until breakdown occurs at a very high reverse voltage VBR, and a successive current may flow in the
reverse direction. The breakdown voltage VBR is above 50V for typical diodes.
Unlike a resistor, in which the current is directly (linearly) proportional to the voltage across
it, the diode is a nonlinear device. When the diode is forward-biased, a small voltage drop
occurs across it. This voltage drop is called the barrier potential with an approximate value of
0.3V for germanium diodes, and 0.7V for silicon diodes.
Fig.1 presents the IV characteristics curve for a typical semiconductor diode. This
characteristic curve can be approximately estimated in the forward-bias region from the
equation:
I D = I S (eVD / VT − 1)
(1)
Where:
ID: is the diode current
VD: is the diode voltage
IS: is the diode reverse saturation current
VT: is the thermal voltage, which is approximately 26 mV at room temperature
-1-
Diode Characteristics
Experiment 1
Figure 1: Diode IV Characteristics
The diode forward static (or DC) resistance at a particular DC operating point (Q) is given by:
RDC = RD =
VDQ
(2)
I DQ
Where VDQ is the diode bias voltage, and IDQ is the diode operating current.
The diode dynamic (or AC) resistance can be found from the characteristic curve at the QPoint as:
rac = rd =
∆VD
∆I D
(3)
Where ∆VD is a small increment in diode voltage around VDQ, and ∆ID is a small increment in
diode current around IDQ as depicted in Fig.2..
The dynamic resistance depends on the operating point, and can be calculated approximately
from the equation:
rd =
VT
I DQ
(4)
Where VT is the thermal voltage, and IDQ is the diode operating current.
Fig.2 shows the determination of the dynamic resistance graphically.
-2-
Diode Characteristics
Experiment 1
Figure 2: Graphical Determination of the Diode Dynamic Resistance
2. Procedure
1- Connect the diode circuit shown in Fig.3.
Figure 3: Diode Forward-Biased Circuit
2- Set the DC supply voltage Vin at 0V, and increase it gradually. Record diode voltage VD and
current ID in each step according to Table 1 below.
Table 1: Recorded Data for the Forward-Biased Diode Circuit
ID (mA)
0
0.5
1
2
4
6
8
10
12
16
18
20
22
VD (V)
-3-
Diode Characteristics
Experiment 1
3- Connect the reverse-biased diode circuit shown in Fig.4. Set the DC power supply voltage
Vin at 0V, and increase it gradually in several steps and record diode reverse voltage VR and
reverse current IR as indicated in Table 2.
Figure 4: Diode Reverse-Biased Circuit
Table 2: Recorded Data for the Reverse-Biased Circuit
VR(V)
0
5
10
15
20
25
IR(µA)
3. Calculations and Discussion
1- Plot the diode forward characteristics from the results obtained, and determine the
cutin voltage Vγ from the sketch.
2- From the sketched characteristic curve determine the static resistance of the diode RDC
at IDQ = 10mA. Determine also the diode dynamic resistance at IDQ = 10mA, and
compare it with the theoretical value obtained from equation 4.
3- Plot the diode reverse characteristic, and estimate an approximate value for the reverse
saturation current IS.
4- From the results obtained in this experiment, compute the maximum power dissipated
in the diode.
5- Explain how you could use an ohmmeter to identify the cathode of an unmarked
diode.
6- Explain why a series resistor is necessary when a diode is forward-biased.
-4-
Diode Characteristics
Experiment 1
7- In a certain silicon diode, it was found that the diode current is 15mA when the diode
voltage is 0.64V at room temperature. Determine the diode current when the voltage
across it becomes 0.68V. Use the approximate diode characteristic equation.
8- From the approximate diode characteristic equation, derive an expression for the
dynamic resistance rd.
-5-
Diode Characteristics
Experiment 1
This page is left intentionally blank
-6-
Experiment 2
Rectifier Circuits
Experiment 2
Rectifier Circuits
Objectives
The purpose of this experiment is to demonstrate the operation of three different diode
rectifier circuits which are the half-wave rectifier, center-tapped full-wave rectifier, and the
bridge full-wave rectifier. In addition to that, the operation of a capacitor filter connected to
the output of the rectifier will also be demonstrated.
Required Parts and Equipments
12345678-
Digital Multimeters
Electronic Test Board
Step-down center-tapped transformer (220V/12Vr.m.s)
Dual-Channel Oscilloscope
General Purpose Silicon Diodes 1N4007
Resistor 100kΩ
Capacitors 2.2µF, 10µF
Leads and BNC Adaptors
1. Theory
The rectifier is circuit that converts the AC input voltage into a pulsed waveform having an
average (or DC) value. This waveform can then be filtered to remove the unwanted variations.
Rectifiers are widely used in power supplies which provide the DC voltage necessary for
electronic circuits. The three basic rectifier circuits are the half-wave, the center-tapped fullwave, and the full-wave bridge rectifier circuits. The most important parameters for choosing
diodes for these circuits are the maximum forward current, and the peak inverse voltage rating
(PIV) of the diode. The peak inverse voltage is the maximum voltage the diode can withstand
when it is reverse-biased. The amount of reverse voltage that appears across a diode depends
on the type of circuit in which it is connected. Some characteristics of the three rectifier
circuits will be investigated in this experiment.
1.1 Half-Wave Rectifier
Figure 1 shows a schematic diagram of a transformer coupled half-wave rectifier circuit. The
transformer is useful in electrically isolating the diode rectifier circuit from the 220V AC
source, and also is used to step-down the input line voltage into a suitable value according to
the turns ratio.
The transformer’s turns ratio is defined by:
n=
V pr ( r .m.s )
(1)
Vs ( r .m.s )
Where Vpr(r.m.s) is the r.m.s value of the transformer primary winding voltage, and Vs(r.m.s) is the
r.m.s value of the transformer secondary winding voltage.
In the circuit of Fig.1, Vpr(r.m.s) = 220V.
-7-
Experiment 2
Rectifier Circuits
Figure 1: Half-Wave Rectifier with Transformer-Coupled Input Voltage
The peak value of the secondary winding voltage Vsp is related to the r.m.s value by the
relation:
Vsp = 2 .Vs ( r .m.s )
(2)
When the sinusoidal voltage across the secondary winding of the transformer goes positive,
the diode is forward-biased and conducts current through the load resistor RL. Thus, the output
voltage across RL has the same shape as the positive half-cycle of the input voltage.
When the secondary winding voltage goes negative during the second half of its cycle, the
diode is reverse-biased. There is no current in this case, so the voltage across the load resistor
is 0V. The net result is that only the positive half-cycles of the AC input voltage on the
secondary winding appear across the load as shown in Fig.2. Since the output does not change
polarity, it is a pulsating DC voltage with frequency equals to that of the input AC voltage.
Figure 2: Waveforms of the Half-Wave Rectifier Circuit
When taking the voltage drop across the diode into account, the peak value of the output
voltage is given by:
Vop = Vsp − 0.7
(3)
In equation (3), it was assumed that the voltage drop across the silicon diode is 0.7V when it
conducts.
-8-
Experiment 2
Rectifier Circuits
It can be verified that the average (or DC) value of the output voltage is given by:
Vdc =
Vop
π
=
Vsp − 0.7
(4)
π
The peak inverse voltage (PIV) of the diode for this circuit equals the peak value of the
secondary winding voltage:
PIV = Vsp = Vop + 0.7
(5)
1.2 Center-Tapped Full-Wave Rectifier
The full-wave center-tapped rectifier uses two diodes connected to the secondary of a centertapped transformer as shown in Fig.3.
Figure 3: The Center-Tapped Full-Wave Rectifier Circuit
The Input voltage is coupled through the transformer to the center-tapped secondary. For the
positive half cycle of the input signal, the polarities of the secondary winding voltages are
shown in Fig.3. This makes the upper diode D1 conducting and the lower diode D2 to be
reverse-biased. The current path is through D1 and the load resistor RL. For the negative half
cycle of the input voltage, the voltage polarities on the secondary winding of the transformer
will be reversed causing D2 to conduct, while reverse-biasing D1.The current path is through
D2 and RL. Because the output current during both the positive and negative portions of the
input cycle is in the same direction through the load, the output voltage developed across the
load resistor is a full-wave rectified DC voltage as shown in Fig.4.
Figure 4: Waveforms of the Full-Wave Rectifier
-9-
Experiment 2
Rectifier Circuits
The DC output voltage of the full-wave rectifier is given by:
Vdc =
2Vop
π
=
2(Vsp − 0.7)
(6)
π
The peak inverse voltage (PIV) of each diode in this circuit is obtained as:
PIV = 2Vsp − 0.7 = 2Vop + 0.7
(7)
The frequency of the output voltage equals twice the line frequency as shown from the
waveform of the output voltage.
1.3 Full-Wave Bridge Rectifier
The full-wave bridge rectifier uses four diodes as shown in Fig.5. When the input cycle is
positive, diodes D1 and D2 are forward biased and conduct current. A voltage is developed
across RL which looks like the positive half of the input cycle. During this time, diodes D3 and
D4 are reverse-biased.
When the input cycle is negative, diodes D3 and D4 become forward-biased and conduct
current in the same direction through RL as during the positive half-cycle. During the negative
half-cycle, D1 and D2 are reverse biased. A full-wave rectified output voltage appears across
RL as a result of this action.
Figure 5: The Full-Wave Bridge Rectifier Circuit
In this circuit, two diodes are always in series with the load resistor during both the positive
and negative half-cycles. If these diode drops are taken into account, the output peak voltage
is:
Vop = Vsp − 1.4
(8)
The DC output voltage is given by:
Vdc =
2Vop
π
=
2(Vsp − 1.4)
(9)
π
The peak inverse voltage of each diode in the circuit is given by:
PIV = Vsp − 0.7 = Vop + 0.7
(10)
- 10 -
Experiment 2
Rectifier Circuits
1.4 Capacitor Filter
As stated previously, the filter is used to reduce the ripples in the pulsating waveform of the
rectifier. A half-wave rectifier with a capacitor filter is shown in Fig.6.
Figure 6: Half-Wave Rectifier with a Capacitor Filter
During the positive first quarter-cycle of the input signal, the diode is forward-biased,
allowing the capacitor to charge to within 0.7V of the peak value of the secondary winding
voltage. When the input begins to decrease below its peak, the capacitor retains its charge and
the diode becomes reverse-biased because the cathode is more positive than the anode. During
the remaining part of the cycle, the capacitor can discharge only through the load resistance at
a rate determined by the RLC time constant, which is normally long compared to the period of
the input signal. Figure 7 shows the output voltage of the filter circuit.
Figure 7: Output Waveform of the Capacitor Filter
Connected with the Half-Wave Rectifier
The variation in the capacitor voltage due to the charging and discharging is called the ripple
voltage as illustrated in Fig.7. Generally, ripple is undesirable. Thus, the smaller the ripple,
the better the filtering action.
For a half-wave rectified capacitor filter, the approximate value of the peak-to-peak ripple
voltage is given by:
⎛ 1 ⎞
⎟⎟Vop
Vr ( pp ) ≅ ⎜⎜
fR
C
⎝ L ⎠
(11)
Where f is the frequency of the input signal, and Vop is the measured peak value of the output
waveform.
- 11 -
Experiment 2
Rectifier Circuits
The DC voltage of the output waveform can be approximated by:
Vdc = Vop −
Vr ( pp )
(12)
2
Or,
⎛
1 ⎞
⎟⎟Vop
Vdc ≅ ⎜⎜1 −
⎝ 2 fRLC ⎠
(13)
For the full-wave rectifier, the output frequency is twice that of the half-wave rectifier. This
makes a full-wave rectifier easier to filter because of the shorter time between peaks. The
peak-to-peak ripple voltage for the full-wave rectified capacitor filter is given by:
⎛ 1 ⎞
⎟⎟Vop
Vr ( pp ) ≅ ⎜⎜
fR
C
2
L
⎠
⎝
(14)
The DC voltage of the output waveform for the full-wave rectified capacitor filter can be
approximated by:
⎛
1 ⎞
⎟⎟Vop
Vdc ≅ ⎜⎜1 −
⎝ 4 fRLC ⎠
(15)
The ripple factor is an indication of the effectiveness of the filter and is defined as:
r=
Vr ( pp )
(16)
Vdc
The lower the ripple factor, the better the filter. The ripple factor can be lowered by
increasing the value of the filter capacitor or increasing the load resistance.
2. Procedure
1. Connect the half-wave rectifier circuit shown in Fig.8. Measure the DC output
voltage, peak value of the secondary winding voltage, and the peak value of the output
voltage as tabulated in Table 1. Sketch the output waveform.
Figure 8: The Practical Half-Wave Rectifier Circuit
- 12 -
Experiment 2
Rectifier Circuits
Table 1: Recorded Data for the Half-wave Rectifier Circuit
Quantity
Vsp
Vop
Vdc
Measured Value
Calculated Value
2. Connect a capacitor filter at the output of the half-wave rectifier as shown in Fig.9,
and measure the DC output voltage and peak-to-peak ripple voltage in the output.
Figure 9: Practical Capacitor Filter Connected to the Half-Wave Rectifier
Table 2: Recorded Data for the Half-wave Rectifier and Filter Circuit
Quantity
Vdc
Vr(pp)
Measured Value
Calculated Value
3. Repeat step 2 after replacing the filter capacitor with another one of value 10µF.
4. Connect the full-wave center-tapped transformer rectifier circuit shown in Fig.10.
Measure the DC output voltage, peak value of the secondary winding voltage, and the
peak value of the output voltage as tabulated in Table 3. Sketch the output waveform
in this case.
Figure 10: Practical Circuit for the Center-Tapped Full-Wave Rectifier
- 13 -
Experiment 2
Rectifier Circuits
Table 3: Recorded Data for the Center-Tapped Rectifier Circuit
Quantity
Vsp
Vop
Vdc
Measured Value
Calculated Value
5. Connect a capacitor filter at the output of the full-wave rectifier as shown in Fig.11,
and measure the DC output voltage and peak-to-peak ripple voltage at the output.
Figure 11: Practical Circuit for the Center-Tapped Full-Wave
Rectifier with the Capacitor Filter
Table 4: Recorded Data for the Full-wave Center-Tapped Rectifier and Filter Circuit
Quantity
Vdc
Vr(pp)
Measured Value
Calculated Value
6. Replace the filter capacitor with another one of value 10µF and repeat step 5.
7. Connect the full-wave bridge rectifier circuit shown in Fig.12. Measure the DC output
voltage, and the peak value of the output voltage as tabulated in Table 5. Sketch the
output waveform in this case. It should be noted that the secondary winding waveform
in this case is similar to that of the center-tapped full-wave rectifier.
Figure 12: The Practical Full-Wave Bridge Rectifier Circuit
- 14 -
Experiment 2
Rectifier Circuits
Table 5: Recorded Data for the Full-Wave Bridge Rectifier Circuit
Quantity
Vop
Vdc
Measured Value
Calculated Value
8. Connect a capacitor filter at the output of the full-wave bridge rectifier as shown in
Fig.13, and measure the DC output voltage and peak-to-peak ripple voltage at the
output.
Figure 13: Practical Circuit for the Full-Wave Bridge
Rectifier with the Capacitor Filter
Table 6: Recorded Data for the Full-wave Bridge Rectifier and Filter Circuit
Quantity
Vdc
Vr(pp)
Measured Value
Calculated Value
9. Replace the filter capacitor with another one of value 10µF and repeat step 8.
3. Calculations and Discussion
1. Calculate the theoretical output DC voltage of the half-wave rectifier circuit and
compare it with measured value. For the capacitive filter, obtain the theoretical values
of the DC output voltage and the ripple voltage and compare these values with the
measured quantities. Determine also the practical and theoretical values of the ripple
factor.
2. Calculate the theoretical output DC voltage of the center-tapped full-wave rectifier
circuit and compare it with measured value. For the capacitive filter, obtain the
theoretical values of the DC output voltage and the ripple voltage and compare these
values with the measured quantities. Determine also the practical and theoretical
values of the ripple factor.
3. Repeat the calculations for the full-wave bridge rectifier and filter circuit.
4. Determine the peak inverse voltage (PIV) on each diode in the three rectifier circuits.
- 15 -
Experiment 2
Rectifier Circuits
5. If diode D4 in the bridge rectifier circuit of Figure 5 was removed or burned, explain
the operation of the circuit in this case and sketch the predicted waveform of the
output.
6. Explain the effect of increasing the filter capacitance on the output voltage in the halfwave rectifier and filter circuit.
7. Compare the DC output voltages of the three rectifier circuits. Which circuit has the
highest output? On the other hand, which circuit has the lowest peak inverse voltage
on each diode?
8. What value of filter capacitor is required to produce 1% ripple factor for a full-wave
rectifier having a load resistance of 1.5kΩ? Assume that the peak value of the output
voltage is 18V.
- 16 -
Experiment 3
Clipping and Clamping Circuits
Experiment 3
Clipping and Clamping Circuits
Objectives
The purpose of this experiment is to demonstrate the operation of diode clipping and
clamping circuits.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
7.
Function Generator
Dual-Channel Oscilloscope
DC Power Supply
Electronic Test Board
Resistors 1KΩ, 68KΩ
Silicon Diode 1N4007
Leads and Adaptors
1. Theory
In addition to the use of diodes as rectifiers, there are a number of other interesting
applications. For example, diodes are frequently used in applications such as wave-shaping,
detectors, voltage multipliers, switching circuits, protection circuits, and mixers.
In this experiment, we will investigate two widely used applications of diode circuits, namely
diode clipping circuits and diode clamping circuits.
1.1 Clipping Circuits
Diode clipping circuits are wave-shaping circuits that are used to prevent signal voltages
from going above or below certain levels. The clipping level may be either equal to the
diode’s barrier potential or made variable with a DC voltage source (or bias voltage). Because
of this limiting capability, the clipper is also called a limiter.
There are, in general, two types of clipping circuits: parallel clippers and series clippers. In
parallel clippers, the diode is connected in a branch parallel to the load, while in series
clippers, the diode is connected in series with the load.
Fig.1 presents a simple diode clipping circuit. This circuit is known as the unbiased parallel
diode clipper, and is used to clip or limit the positive part of the input voltage. As the input
voltage goes positive, the diode becomes forward-biased. The anode of the diode in this case
is at a potential of 0.7V with respect to the cathode. So, the output voltage will be limited to
0.7V when the input voltage exceeds this value. When the input voltage goes back below
0.7V, the diode is reverse-biased and appears as an open circuit. The output voltage will look
like the negative part of the input voltage.
- 17 -
Experiment 3
Clipping and Clamping Circuits
Figure 1: Simple Unbiased Parallel Diode Clipping Circuit
The level to which an AC voltage is limited can be adjusted by adding a bias voltage VB in
series with the diode as shown in Fig.2.
Figure 2: Biased Parallel Diode Clipping Circuit
In this circuit, the input voltage must equal VB + 0.7V before the diode will become forwardbiased and conduct. Once the diode begins to conduct, the output voltage is limited to VB +
0.7V so that all input voltage above this level is clipped off.
In Fig.3, a simple series diode clipping circuit is presented. Its action is actually similar to
that of the half-wave rectifier.
Figure 3: Simple Unbiased Series Diode Clipping Circuit
When the input signal goes positive and exceeds 0.7V, the diode becomes forward-biased and
the output voltage is Vin – 0.7V. When the input voltage becomes less than 0.7V, the diode
becomes reverse-biased and no current flows in the circuit, resulting in zero output voltage.
- 18 -
Experiment 3
Clipping and Clamping Circuits
Fig.4 shows a biased series clipping circuit.
Figure 4: Biased Series Diode Clipping Circuit
When the input voltage is less than VB + 0.7V, the diode does not conduct and no current
flows through the load, and hence the output voltage will be 0V. If the input signal becomes
larger than VB + 0.7V, the diode will conduct and the output voltage becomes Vin – (VB +
0.7). The output voltage waveform will be as shown in Fig.4.
1.2 Clamping Circuits
Diode clamping circuits are used to shift the DC level of a waveform. If a signal has passed
through a capacitor, the DC component is blocked. A clamping circuit can restore the DC
level. For this reason these circuits are sometimes called DC restorers. There are two kinds of
clamping circuits, positive clampers and negative clampers.
Fig.5 shows a positive diode clamper that inserts a positive DC level in the output waveform.
Figure 5: Unbiased Positive Clamping Circuit
During the negative half cycle, the diode conducts and the capacitor charges to Vp volts
(assuming ideal diode). In the positive half cycle, the capacitor which was charged initially,
discharges through the resistor by a time constant RLC. This happens only if RLC time
constant is much less than half the time period of the waveform. Hence if RLC is larger than
half the time period, it will not discharge through RL. Now C acts as a DC battery of Vp volt.
- 19 -
Experiment 3
Clipping and Clamping Circuits
Hence during the positive half cycle, the diode is reverse biased by (Vin + Vp) volts, which
appears across it. The magnitude of RL and C must be chosen such that the time constant τ =
RLC is large enough to ensure the voltage across the capacitor does not discharge significantly
during the interval of the diode when it is non-conducting ( τ >> T ) . So, for an acceptable
approximation we have:
RL .C ≅ 10T
(1)
Where T is the time period of the input signal.
Biased clamping circuits produce an output waveform which is clamped by a variable level
defined by a bias voltage source connected in series with the diode. If a battery of value VB is
added to forward bias the diode of Fig.5 then the clamping level of the output waveform is
raised from Vp to Vp + VB volts. Consider Fig.6, where a biased positive clamper circuit is
presented. The capacitor gets charged to Vp + VB volts assuming an ideal diode. In the
positive half cycle the same C acts as a battery of Vp + VB volts, and hence the output is ( Vin
+ Vp + VB ) volts.
Figure 6: Biased Positive Clamping Circuit
2. Procedure
1. Connect the clipping circuit shown in Fig.7, and apply a 20Vpp sinusoidal input waveform
with frequency of 1 kHz at the input. Display and sketch both input and output signals.
Figure 7: Practical Unbiased Parallel Clipping Circuit
- 20 -
Experiment 3
Clipping and Clamping Circuits
2. Connect the biased parallel clipping circuit shown in Fig.8, and apply a 20Vpp sinusoidal
input waveform with frequency of 1 kHz at the input. Display and sketch the input and
the output waveforms.
Figure 8: Practical Biased Parallel Clipping Circuit
3. Connect the series clipping circuit shown in Fig.9, and apply a 20Vpp sinusoidal input
waveform with frequency of 1 kHz at the input. Display and sketch the input and the
output waveforms.
Figure 9: Practical Unbiased Series Clipping Circuit
4. Connect the biased series clipping circuit shown in Fig.10, and apply a 20Vpp sinusoidal
input waveform with frequency of 1 kHz at the input. Display and sketch the input and
the output waveforms.
Figure 10: Practical Biased Series Clipping Circuit
- 21 -
Experiment 3
Clipping and Clamping Circuits
5. Connect the clamping circuit shown in Fig.11, and apply a 10Vpp sinusoidal input
waveform with frequency of 1 kHz at the input. Display and sketch the input and the
output waveforms.
Figure 11: Practical Unbiased Positive Clamping Circuit
6. Repeat step 5 after applying a square wave of 10Vpp amplitude and 1 kHz frequency.
7. Connect the biased positive clamping circuit shown in Fig.12, and apply a 10Vpp sinusoidal
input waveform with frequency of 1 kHz at the input. Display and sketch the input and the
output waveforms.
Figure 12: Practical Biased Positive Clamping Circuit
8. Repeat step 7 after applying a square wave of 10Vpp amplitude and 1 kHz frequency.
3. Discussion
1. What is the effect of the diode voltage drop on the output of the clipping circuit in Fig.4?
Compare the waveforms with those obtained when assuming ideal diodes.
2. If the diode in the circuit of Fig.2 was reversed, then sketch the output waveform in this
case and explain briefly the operation of the circuit.
- 22 -
Experiment 3
Clipping and Clamping Circuits
3. Design a clipping circuit that will limit the output voltage to 5V when applying an input
sinusoidal waveform with a peak value of 10V. Assume available diodes with voltage drop
of 0.5V. Sketch the output waveform of the circuit.
4. Sketch the output waveform for the clipping circuit of Fig.1 if a load resistance RL of value
1 kΩ is connected at the output terminals in parallel with the diode.
5. Discuss how diode limiters and diode clampers differ in terms of their function.
6. Design a clamper circuit that shifts the DC level of an input sinusoidal waveform by +6V if
the peak value of the input signal is 3V, and its frequency is 500 Hz. Assume diode voltage
drop is 0.6V.
7. What is the effect of reducing the load resistor on the output of the clamper circuit shown in
Fig.5 if the input signal is a square wave?
8. What is the difference between a positive clamper and a negative clamper? Explain with
the aid of circuit diagrams and output waveforms.
- 23 -
Experiment 3
Clipping and Clamping Circuits
This page is left intentionally blank
- 24 -
Experiment 4
The Zener Diode
Experiment 4
The Zener Diode
Objectives
The purposes of this experiment are to demonstrate the characteristics of a zener diode and
its use as a simple voltage regulator.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
Variable DC Power Supply.
Digital Multimeters.
Zener Diode, BZX55C5V1 (5.1V, 0.5W).
Carbon Resistors 330Ω (2W), 1kΩ (2W).
Variable Box Resistor.
Leads and Wires.
1. Theory
The zener diode is a silicon PN junction device that differs from rectifier diodes because it is
designed to operate in the reverse-breakdown region. The breakdown voltage of the zener
diode is set by carefully controlling the doping level during the manufacturing process. Fig.1
shows the zener diode’s symbol and current-voltage characteristic.
Figure 1: Zener Diode Symbol and IV Characteristic
- 25 -
Experiment 4
The Zener Diode
As shown from Fig.1b, as the reverse voltage VR is increased, the reverse current IR remains
extremely small up to the knee of the curve. At this point, the breakdown effect begins and the
zener breakdown voltage VZ remains approximately constant as the zener current IZ increases.
The reverse current in this region is actually called the zener current.
A zener diode operating in breakdown acts as a voltage regulator because it maintains a
nearly constant voltage across its terminals over a specified range of reverse current values.
The minimum value of reverse current required to maintain the zener diode in breakdown for
voltage regulation is known as the knee current IZK as illustrated in Fig.1b. When the reverse
current is reduced below IZK, the voltage decreases drastically and regulation is lost. On the
other hand, the maximum current that the diode can withstand is abbreviated as IZM, and is
defined as the zener current above which the diode may be damaged due to excessive power
dissipation. This current can be determined from:
I ZM =
PZM
VZ
(1)
Where PZM represents the maximum DC power dissipation of the zener diode, which is
usually specified in the datasheet.
So, the practical operating range of the zener diode current should be maintained between IZK
and IZM for proper voltage regulation.
Fig.2 shows the ideal and practical models of the zener diode in the reverse breakdown
region.
Figure 2: Zener Diode Equivalent Circuit Models
The ideal model of the zener diode shown in Fig.2a has a constant voltage drop equal to the
nominal zener voltage. This constant voltage drop is represented by a DC voltage source
which indicates that the effect of reverse breakdown is simply a constant voltage across the
zener terminals.
Fig.2b represents the practical model of the zener diode, in which the internal zener
resistance rz is included. Since the actual voltage curve is not ideally vertical, a change in
zener current ∆IZ produces a small change in zener voltage ∆VZ as illustrated in Fig.3. By
Ohm’s law, the ratio of ∆VZ to ∆IZ is the zener diode internal resistance as expressed in the
following equation:
- 26 -
Experiment 4
rz =
The Zener Diode
∆V Z
∆I Z
(2)
In most cases, we can assume that rz is constant over the full linear range of the zener diode
current values.
Figure 3: Reverse Characteristic of a Zener Diode Showing the
Determination of the Internal Resistance rz
1.1 The Zener Diode as a Voltage Regulator
The zener diode is often used as a voltage regulator in DC power supplies. Fig.4 presents a
simple voltage regulator circuit. In this circuit, the zener diode should maintain a constant
output voltage against variations in input voltage Vin, or load resistance RL. Resistor RS is used
as a series current limiting resistor.
Figure 4: Simple Zener Diode Voltage Regulator
- 27 -
Experiment 4
The Zener Diode
The analysis of the circuit depends on the state of the zener diode if it enters the zener
breakdown region or not. To determine the state of the zener diode, we can remove it from the
circuit temporarily and calculate the voltage across the open circuit. The load voltage in this
case can be obtained from the voltage divider rule:
VL =
RL .Vin
RS + R L
(3)
If VL ≥ VZ, then the zener diode is ON, and the appropriate equivalent model can be
substituted. On the other hand, if VL < VZ, the zener diode is OFF, and it is substituted with an
open circuit.
When the zener diode operates in its zener breakdown region, it can be substituted simply
with a constant voltage source VZ. In this case:
V L = VZ
(4)
The source current IS can be found from the equation:
IS =
Vin − VZ
RS
(5)
The load current is calculated as the ratio of load voltage to load resistance:
IL =
VL
RL
(6)
The zener current is obtained by applying Kirchhoff’s current law:
IZ = IS − IL
(7)
The power dissipated by the zener diode is determined from:
PZ = VZ .I Z
(8)
This value of PZ must be less than the maximum power rating of the diode PZM in order to
avoid damaging the zener diode.
1.2 Zener Voltage Regulator with a Variable Load Resistance
Fig.5 shows a zener voltage regulator with a variable load resistor across the output
terminals. The zener diode maintains a nearly constant voltage across RL as long as the zener
current is greater than IZK and less than IZM. This is called load regulation.
When the output terminals of the zener regulator are open (RL = ∞), the load current is zero
and the entire source current IS passes through the zener diode. When a load resistor RL is
connected, part of the source current passes through the zener diode, and part through RL. As
- 28 -
Experiment 4
The Zener Diode
RL is decreased, the load current IL increases and IZ decreases. The source current passing
through RS remains essentially constant.
Figure 5: Zener Regulator with Variable Load Resistance and Fixed Input Voltage
To determine the minimum load resistance that will turn on the zener diode, we simply
calculate the value of RL that will result in a load voltage VL = VZ. Assuming IZK =0, we have
from voltage divider rule:
V L = VZ =
Vin .RL
R L + RS
Solving for RL yields:
RL (min) =
RS .VZ
Vin − VZ
(9)
1.3 Zener Voltage Regulator with a Variable Input Voltage
Fig.6 illustrates how a zener diode can be used to regulate a varying input DC voltage. This is
called input or line regulation.
Figure 6: Zener Regulator with Variable Input Voltage and Fixed Load Resistance
- 29 -
Experiment 4
The Zener Diode
For fixed values of RL, the input voltage must be sufficiently large to turn on the zener diode.
Neglecting IZK, the minimum turn-on voltage is determined by:
V L = VZ =
Vin .RL
R L + RS
Solving for Vin, we have:
Vin (min) =
( RL + RS ).VZ
RL
(10)
The maximum value of Vin is limited by the maximum zener current IZM. We have:
I S (max) = I ZM + I L
(11)
IL is given by:
IL =
V L VZ
=
RL RL
(12)
Therefore, the maximum input voltage is given by:
Vin (max) = I S (max) .RS + VZ
Or,
Vin (max) = ( I ZM +
VZ
).RS + VZ
RL
(13)
2. Procedure
1. Connect the zener diode test circuit shown in Fig.7. Increase the input voltage
gradually in several steps from 0 to 15V, and record VZ and IZ according to Table 1.
Figure 7: Practical Circuit Used to Obtain the Characteristics of the Zener Diode
- 30 -
Experiment 4
The Zener Diode
Table 1: Recorded Data for the Circuit of Figure 7
Vin(V)
0
1
2
3
4
4.5
5
5.5
6
7
8
10
12
14
15
VZ(V)
IZ(mA)
2. Connect the voltage regulator circuit shown in Fig.8, and vary the load resistor RL in
several steps as shown in Table 2. Record VL, IS, IZ, and IL where IL = IS -IZ.
Figure 8: Practical Circuit for Zener Diode Voltage Regulator with Variable Load Resistor
3. Connect the voltage regulator circuit shown in Fig.9, and vary the input voltage in several
steps from 0 to 15V as shown in Table 3. Record VL, IS, IZ, and IL where IL = IS -IZ.
- 31 -
Experiment 4
The Zener Diode
Table 2: Recorded Data for the Voltage Regulator Circuit of Figure 8
RL(Ω) VL(V) IS(mA) IZ(mA) IL(mA)
50
100
150
200
300
500
800
1.0k
1.5k
2.0k
2.5k
5.0k
∞
Figure 9: Practical Circuit for Zener Diode Voltage Regulator with Variable Input Voltage
Table 3: Recorded Data for the Voltage Regulator Circuit of Figure 9
Vin(V) VL(V) IS(mA) IZ(mA) IL(mA)
0
1
2
4
5
6
6.5
7
8
10
12
14
15
- 32 -
Experiment 4
The Zener Diode
4. Calculations and Discussion
1. Plot the characteristic curve of the zener diode in the reverse-breakdown region from
the results obtained in step 1 of the procedure.
2. Determine the internal resistance rz of the zener diode from your data. Do this
calculation only on the straight-line breakdown region of the characteristic curve
plotted in step 1 above.
3. Determine the power dissipation in the zener diode for the maximum zener current
flowing through it from the obtained data of step1 in the procedure, and compare it
with PZM.
4. For the zener diode voltage regulator circuit of Fig.8, sketch the relation between VL
and IL (VL versus IL). Plot the relation between IS and RL. Sketch also the relation
between IZ and IL. Comment on the resulting curves.
5. Calculate the theoretical minimum value of RL required for putting the zener diode in
the zener breakdown region for the regulator circuit of Fig.8. What value of load
resistance results in the maximum zener current? Determine the maximum zener
current IZ(max) in this case and compare it with IZM.
6. Plot the relation between VL and Vin for the voltage regulator circuit in Fig.9, and
comment on the resulting sketch. From this sketch, determine the minimum value of
input voltage required to turn-on the zener diode.
7. Calculate the theoretical minimum value of Vin required to turn-on the zener diode in
the voltage regulator circuit of Fig.9. Determine also the maximum permissible value
of Vin knowing that the maximum DC power dissipation of the BZX55C5V1 zener
diode is 0.5W.
8. Explain the difference between line regulation and load regulation.
- 33 -
Experiment 4
The Zener Diode
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- 34 -
Experiment 5
Light Emitting Diodes
Experiment 5
Light Emitting Diodes
Objectives
The purpose of this experiment is to determine and plot the characteristics of the light
emitting diode in the forward-bias region, and to compare between different colored diodes.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
Variable DC Power Supply.
Digital Multimeters.
Electronic Test Board.
Light Emitting Diodes (LEDs) with different colors (Red, Yellow, and Green).
Resistor (470Ω, 1W).
Leads and Wires.
1. Theory
The Light-Emitting Diode (LED) is a semiconductor PN junction diode that emits visible
light or near-infrared radiation when forward biased. LEDs switch off and on rapidly, are
very rugged and efficient, have a very long lifetime, don’t heat up, and are easy to use. They
are used as indicators, displays, and as light transmitters.
Various impurities are added during the doping process to vary the color output. The LED is
basically just a specialized type of PN junction diode, made from a very thin layer of fairly
heavily doped semiconductor material. Fig.1 depicts the construction of the light emitting
diode.
Figure 1: LED Construction
- 35 -
Experiment 5
Light Emitting Diodes
When the diode is forward biased, electrons from the semiconductors conduction band
recombine with holes from the valence band releasing sufficient energy to produce photons
which emit a monochromatic (single color) of light. Because of this thin layer a reasonable
number of these photons can leave the junction and radiate away producing a colored light
output. Then we can say that when operated in a forward biased direction Light Emitting
Diodes are semiconductor devices that convert electrical energy into light energy. Fig.2 shows
the LED external package and its electronic symbol.
Figure 2: The LED Package and Symbol
As shown from Fig.1, the cathode is the short lead and there may be a slight flat on the body
of round LEDs. Light emitting diodes are available in a wide range of colors with the most
common being RED, ORANGE, YELLOW and GREEN, and are thus widely used as visual
indicators and as moving light displays. Visible LEDs emit relatively narrow bands of green,
yellow, orange, or red light. Infrared LEDs emit in one of several bands just beyond red light.
Light Emitting Diodes are made from special semiconductor compounds such as Gallium
Arsenide (GaAs), Gallium Phosphide (GaP), Gallium Arsenide Phosphide (GaAsP), Silicon
Carbide (SiC) or Gallium Indium Nitride (GaInN) all mixed together at different ratios to
produce a distinct wavelength of color. Silicon and germanium are not used because they are
heat producing materials and are very poor in producing light. Thus, the actual color of a light
emitting diode is determined by the wavelength of the light emitted, which in turn is
determined by the actual semiconductor compound used in forming the PN junction during
the manufacturing process. Therefore, the color of an LED is determined by the
semiconductor material, not by the coloring of the 'package' (the plastic body). Table 1 below
shows typical technical data for some LEDs with diffused packages.
Table 1: Some Important Characteristics of Typical LEDs
Type
Color
Standard
Red
ID
VD VD
Wavelength
max. typ. max.
30mA 1.7V 2.1V
660nm
Standard
Bright red 30mA 2.0V 2.5V
625nm
Standard
Yellow 30mA 2.1V 2.5V
590nm
Standard
Green
25mA 2.2V 2.5V
565nm
High intensity
Blue
30mA 4.5V 5.5V
430nm
- 36 -
Experiment 5
Light Emitting Diodes
When an LED is forward biased to the threshold of conduction, its current increases rapidly
and must be controlled to prevent destruction of the device. The light output is quite linearly
proportional to the forward LED current as shown in Fig.3.
Figure 3: LED Bias Circuit and Power Output Characteristic
A series resistor (Rs) should be used to limit the current through the LED to a safe value. The
LED diode voltage drop ranges from about 1.3V to about 3.6V. This resistor is calculated
from:
RS =
VS − VD
I D (max)
(1)
Where VS is the source bias voltage, VD is the LED voltage drop, and ID(max) is the maximum
current of the LED.
Fig.4 shows the IV characteristics in the forward bias region for some typical diodes with
different colored packages.
Figure 4: LED I-V Characteristics Curves Showing the Different Colors Available
- 37 -
Experiment 5
Light Emitting Diodes
2. Procedure
1. Connect the circuit shown in Fig.5, and increase the input DC voltage from 0V to 15V in
several steps. Use red LED and record VD and ID according to Table 2.
Figure 5: The LED Test Circuit
Table 2: Recorded Data of the LED Test Circuit
Vin(V) VD(V) ID(mA)
0
1
2
3
4
5
6
8
10
12
14
15
2. Repeat step 1 after replacing the red LED with a yellow colored one.
3. Repeat step 1 after replacing the LED with a green colored one.
3. Discussion
1. Plot the forward characteristics of each LED on the same graph.
2. From the sketched curves, determine the threshold voltage for each LED. Determine also
the forward static resistance at 10mA for each diode.
3. Which factor determines the color of the emitted light of the LED?
- 38 -
Experiment 5
Light Emitting Diodes
4. A certain LED has a typical forward voltage of 2.2V, and a maximum current of 30mA. If
this diode is to be connected to a voltage source of 15V, determine the suitable value of the
current limiting resistor. Find the current flowing in the LED when the input voltage is
reduced to 8V. Assume the voltage drop across the diode remains constant.
5. Determine the minimum input voltage required to turn on the zener diode in the following
circuit.
6. What are the features of LEDs over conventional bulbs? Name some applications for
LEDs.
7. A yellow colored LED with a forward voltage drop of 2.1V is to be connected to a 5.0V
stabilized DC power supply. Calculate the value of the series resistor required to limit the
forward current to less than 10mA. Also calculate the current flowing through the diode if a
100Ω series resistor is used instead of the calculated first.
8. How can you connect two LED diodes with different colors in parallel to the same DC
power supply? Sketch the circuit diagram and justify the method of wiring.
- 39 -
Experiment 5
Light Emitting Diodes
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- 40 -
Experiment 6
Characteristics of Bipolar Junction Transistors
Experiment 6
Characteristics of Bipolar Junction
Transistors
Objectives
The purpose of this experiment is to determine and graph the input and output characteristics
of a bipolar junction transistor (BJT) in the common emitter configuration, and to measure its
h-parameters at a given DC bias point.
Required Parts and Equipments
1. Dual DC Power Supply.
2. Digital Multimeters.
3. Electronic Test Board.
4. NPN Silicon Transistor 2N3904.
5. Resistors 56 KΩ, 120Ω.
6. Leads and Wires.
1. Theory
A bipolar junction transistor (BJT) is a three-terminal device capable of amplifying a small
AC signal. The three terminals are called the base, emitter, the collector. BJTs consist of a
very thin base material sandwiched between two of the opposite type materials. Bipolar
transistors are available in two forms, either NPN or PNP. The middle letter indicates the type
of material used for the base, while the outer letters indicate the emitter and collector
terminals. The emitter is heavily doped, the base is lightly doped, and the collector is
intermediately doped. Fig.1 shows BJT transistor construction and symbols.
Figure 1: Types of BJT Transistors
- 41 -
Experiment 6
Characteristics of Bipolar Junction Transistors
As shown in Fig.1, two P-N junctions are formed when a transistor is made, the junction
between the base and emitter, and the junction between the base and collector. These two
junctions form two diodes, the emitter-base diode and the collector-base diode.
There are three configurations in connecting the BJT depending on which of the three
terminals is used as the common terminal. These configurations are the common emitter (CE),
the common base (CB), and the common collector (CC). Common emitter configuration is
most effective because of its high current gain, high voltage gain and power gain. In common
emitter configuration, emitter terminal is made common to both input and output circuits as
shown in Fig.2. Input junction (Emitter-Base Junction) is forward biased and output junction
(Collector-Base Junction) is reverse biased so that the input junction is having low resistance
(since it is forward biased) and the output junction is having high resistance (since it is reverse
biased).
Figure 2: Common Emitter Transistor Configuration
Bipolar transistors are primarily current amplifiers. In the CE configuration, a small base
current is amplified to a larger current in the collector circuit. The ratio of the DC collector
current IC to the DC base current IB is called the DC beta (βdc) of the transistor. Thus:
β dc =
IC
IB
(1)
Typical values of βdc range from 20 to 250 or higher. βdc is usually designated as hFE in
transistor datasheets. Hence:
hFE = β dc
(2)
Another useful parameter in bipolar transistors is the DC alpha (αdc). It is defined as the ratio
of the DC collector current IC to the DC emitter current IE. Thus:
α dc =
IC
IE
(3)
Typically, values of αdc range from 0.95 to 0.99, but αdc is always less than 1.
1.1 Common Emitter Input and Output Characteristics
Two sets of characteristics are necessary to describe fully the behavior of the common
emitter configuration: the input (or base) characteristics, and the output (or collector)
- 42 -
Experiment 6
Characteristics of Bipolar Junction Transistors
characteristics. Input characteristics of a transistor are curves showing the variation of input
(base) current IB as a function of input (base-emitter) voltage VBE, when the output (collectoremitter) voltage VCE is kept constant. Fig.3 depicts the input characteristics for a typical
transistor.
Figure 3: Typical Input Characteristics of a Silicon NPN Transistor in the
Common Emitter Configuration
As shown from Fig.3, the input characteristics are similar to that of a forward-biased diode
since the emitter-base junction is forward-biased. Note also the slight shift in the curves when
increasing VCE.
Output characteristics of a transistor are curves showing the variation of the output current IC
as a function of output voltage VCE, when the input current IB is kept constant. Fig.4 depicts
the output characteristics for a typical transistor.
Figure 4: Typical Output Characteristics of a Silicon NPN Transistor in the
Common Emitter Configuration
- 43 -
Experiment 6
Characteristics of Bipolar Junction Transistors
As shown from Fig.4, for very small values of VCE the collector-base junction is forward
biased and the transistor is in the saturation region. In this portion of the curves, IC is
increased linearly with VCE. As VCE increases, the collector-base junction becomes reversebiased and the transistor goes into the active region. In this portion of the curves, IC remains
essentially constant (for a given value of IB) as VCE continues to increase. Actually, IC
increases very slightly as VCE increases due to widening of the collector-base depletion region.
For this portion of the characteristic curves, the value of IC is only determined by the
expression IC = βdc IB.
Fig.5 shows a common emitter circuit that can be used to generate the input and output
characteristic curves. The purpose of RB in this circuit is to limit the base current to a safe
level.
Figure 5: Test Circuit used to generate the Common Emitter
Input and Output Characteristics
1.2 Transistor h-parameters
In order to analyze transistor amplifier operation, an AC small signal model for the BJT is
required. The most widely used equivalent circuit model to describe the transistor behavior at
low and mid-band frequencies is the h-parameter model. For the common emitter
configuration, when the transistor is considered as a linear two port network, the input small
signal AC voltage (vbe) and the output small signal AC current (ic) can be expressed in terms
of the input current (ib) and output voltage (vce) by the following equations:
vbe = hie .ib + hre .vce
(4.a)
(4.b)
ic = h fe .ib + hoe .vce
The common emitter hybrid parameters in equation 4 are defined as:
hie = input resistance =
vbe
ib
(5)
v ce = 0
hre = reverse transfer voltage ratio =
vbe
vce
(6)
ib = 0
- 44 -
Experiment 6
Characteristics of Bipolar Junction Transistors
hfe = forward transfer current ratio =
hoe = output conductance =
ic
vce
ic
ib
(7)
v ce = 0
(8)
ib = 0
The unit of hie is the Ohm, and that of hoe is the Siemens, while hfe and hre are unit-less. This
versatility in the units is the reason behind the name of the hybrid parameters.
Fig.6 shows the small-signal AC equivalent circuit of the transistor in the common emitter
configuration.
Figure 6: Common Emitter Transistor Hybrid Equivalent Circuit Model
The h-parameters of the transistor can be determined graphically from its input and output
characteristics. The parameters hie and hre are determined from the input (or base)
characteristics, while the parameters hfe and hoe are obtained from the output (or collector)
characteristics.
Fig.7 presents the method of finding the input resistance hie graphically at the specified Qpoint of the transistor. It should be noted that h-parameters depend on the specific operating
point (Q-Point) of the transistor. As observed from the figure, hie is determined from the
equation:
hie =
∆VBE
∆I B
(9)
VCE = const .
The small increments ∆IB and ∆VBE should be taken around the Q-point as depicted in Fig.7.
The parameter hre can also be obtained from the input characteristics as shown in Fig.8. In this
case:
hre =
∆VBE
∆VCE
(10)
I B = const .
The base current IB should be taken as the Q-point operating value IBQ. The parameter hre is
very low and can be ignored in most practical cases.
- 45 -
Experiment 6
Characteristics of Bipolar Junction Transistors
Figure 7: Graphical Determination of hie from the Input Characteristics
Figure 8: Graphical Determination of hre from the Input Characteristics
The small signal current gain hfe can be determined from the output characteristics of the
transistor as shown in Fig.9. As shown from this figure, hfe can be found from:
- 46 -
Experiment 6
h fe =
∆I C
∆I B
Characteristics of Bipolar Junction Transistors
(11)
VCE = const .
Actually, hfe represents the AC beta of the transistor:
h fe = β ac
(12)
Figure 9: Graphical Determination of hfe from the Output Characteristics
If IC is plotted against IB for a given VCE, then an approximate linear relation can be obtained
in the active region of the transistor as shown in Fig.10.
Figure 10: IC versus IB for a Typical Transistor in the Active Region
The output conductance hoe can also be gotten from the output characteristics of the transistor
at a specific Q-point as shown in Fig.11. In this case:
- 47 -
Experiment 6
hoe =
∆I C
∆VCE
Characteristics of Bipolar Junction Transistors
(13)
I B = const .
Figure 11: Graphical Determination of hoe from the Output Characteristics
2. Procedure
1. Connect the common emitter test circuit shown in Fig.12. Try to identify the leads of the
2N3904 transistor correctly. It is built in a TO-92 package as depicted in Fig.12.
Figure 12: Transistor Test Circuit Used to obtain the Input Characteristics
- 48 -
Experiment 6
Characteristics of Bipolar Junction Transistors
2. Set VCE = 0V, and increase the base current IB in several steps from 0 to 100µA by
varying the DC supply voltage VBB, and record VBE in each step as shown in Table-1.
3. Reduce VBB to 0V and set VCE = 5V by adjusting the DC power supply VCC. Increase IB
from 0 to 100µA (by slowly increasing VBB) in several steps and record VBE. VCE should
be kept constant at 5V in each step by adjusting VCC.
Table-1: Recorded Data for the Transistor Input Characteristics
VCE = 0V
VCE = 5V
IB(µA) VBE(V) IB(µA) VBE(V)
0
0
10
10
20
20
30
30
40
40
50
50
60
60
70
70
80
80
90
90
100
100
4. Connect the circuit shown in Fig.13 to obtain the output characteristics of the transistor.
Figure 13: Transistor Test Circuit Used to obtain the Output Characteristics
5. Start with both power supplies set to 0V. Slowly increase VBB until IB = 20µA. Now
slowly increase VCC in several steps and record VCE and IC in each step as shown in
Table-2.
- 49 -
Experiment 6
Characteristics of Bipolar Junction Transistors
6. Repeat step 5 for base current values of 40µA, and 60µA respectively. Record data as
illustrated in Table-2.
Table-2: Recorded Data for the Transistor Output Characteristics
IB = 20µA
IB = 40µA
IB = 60µA
VCE(V) IC(mA) VCE(V) IC(mA) VCE(V) IC(mA)
0
0
0
0.1
0.1
0.1
0.2
0.2
0.2
0.4
0.4
0.4
0.6
0.6
0.6
0.8
0.8
0.8
1
1
1
3
3
3
5
5
5
7
7
7
8
8
8
10
10
10
3. Calculations and Discussion
1. From the obtained data in Table-1, plot the input characteristic curves of the transistor.
2. Sketch the three output characteristic curves of the transistor from the results obtained
in Table-2.
3. Find the h-parameters of the transistor at IB = 40µA and VCE = 5V from the plotted
input and output characteristics.
4. Use the plotted characteristic curves to determine the DC current gain βdc for the
transistor at VCE = 3.0V and base current of 20µA, 40µA, and 60µA respectively.
Repeat for VCE = 5.0V. Tabulate your results as illustrated in Table-3 below.
Table-3
DC Current Gain βdc
VCE IB = 20µA IB = 40µA IB = 60µA
3.0V
5.0V
5. Does the experimental data indicate that βdc is constant at all points? Does this have
any effect on the linearity of the transistor? What effect would a higher βdc have on the
characteristic curves you measured?
- 50 -
Experiment 6
Characteristics of Bipolar Junction Transistors
6. What is the maximum power dissipated in the transistor for the data taken in the
experiment?
7. Show that the DC alpha of the transistor is given by:
α dc =
β dc
β dc + 1
Compute αdc for your transistor at VCE = 5.0V and IB = 40µA.
8. What value of VCE would you expect if the base terminal of the transistor is opened?
Explain your answer.
- 51 -
Experiment 6
Characteristics of Bipolar Junction Transistors
This page is left intentionally blank
- 52 -
Experiment 7
Transistor DC Biasing Circuits
Experiment 7
Transistor DC Biasing Circuits
Objectives
The purpose of this experiment is to determine the DC operating point (Q-Point) for the
transistor fixed-bias circuit, and the voltage divider bias circuit, and also to compare between
their bias stabilities against changes in the transistor beta.
Required Parts and Equipments
1. Electronic Test Board.
2. DC Power Supply.
3. Digital Multi-meters.
4. NPN Transistors (BC107, 2N2222).
5. Resistors (470 KΩ, 10 KΩ, 5.6 KΩ, 1 KΩ).
6. Leads and Wires.
1. Theory
The analysis or design of a transistor amplifier requires knowledge of both the DC and the
AC response. The analysis or design of any amplifier therefore has two components: the DC
portion and the AC portion. In fact, the improved output AC power level is the result of a
transfer of energy from the applied DC supplies.
The term biasing refers to the application of DC voltages to establish a fixed level of current
and voltage. For transistor amplifier, the resulting DC current and voltage establish an
operating point on the characteristics that define the region that will be employed for the
amplification of the applied signal. Because the operating point is a fixed point on the
characteristics, it is also called the quiescent point (Q-point). The biasing circuit should be
designed to set the device operation at a Q-point within the active region. For the BJT to be
biased in the active region, the following must be verified:
1- The base-emitter junction must be forward-biased, with a resulting forward-bias voltage of
about 0.6 to 0.7V.
2- The base-collector junction must be reverse-biased, with the reverse-bias voltage being any
value within the maximum limits of the device.
-53-
Experiment 7
Transistor DC Biasing Circuits
1.1 The Fixed-Bias Circuit
The Fixed-Bias circuit of Fig.1 is the simplest DC bias configuration.
In the base-emitter loop, applying KVL yields:
VCC = I B .RB + VBE
Solving for IB, we have:
I BQ =
VCC − VBE
RB
(1)
Figure 1: The Fixed -Bias Transistor Circuit
The collector current is related to base current by:
I CQ = β .I BQ
(2)
Therefore,
(VCC − VBE )
RB
In the collector-emitter loop, we have:
I CQ = β .
(3)
VCC = VCEQ + I CQ .RC
Solving for VCE yields:
VCEQ = VCC − I CQ .RC
(4)
-54-
Experiment 7
Transistor DC Biasing Circuits
The transistor operating point is ICQ, VCEQ.
To sketch the DC load line, the saturation and cut-off limits should be obtained.
I C ( sat ) =
VCC − VCE ( sat )
RC
(5)
VCE ( off ) = VCC
(6)
Although the fixed-bias circuit is very simple in construction, it has poor stability, and the Qpoint may change or shift considerably if the transistor parameters (β and VBE) change with
temperature. This will result in change in the characteristics of the amplifier circuit.
The value of VBE can be taken as 0.7V theoretically for silicon transistors. However, the
measured practical value may be slightly different from the theoretical value.
1.2 The Voltage-Divider Bias Circuit
In the fixed bias circuit, the bias current ICQ and voltage VCEQ are functions of the current
gain β of the transistor. However, because β is temperature sensitive, especially for silicon
transistors, this may result in change in bias current and voltage. Therefore, it would be
desirable to develop a bias circuit that is independent of the transistor beta. The voltage
divider circuit shown in Fig.2 is such a circuit. Voltage-Divider bias circuit is often used
because the base current is made small compared to the currents through the two base
(voltage-divider) resisters. Consequently, the base voltage and therefore the collector current
are stabilized against changes in the transistor beta.
Figure 2: The Voltage-Divider Bias Circuit
-55-
Experiment 7
Transistor DC Biasing Circuits
The approximate analysis of the voltage divider bias circuit can be established by neglecting
the base current IB when compared to the current flowing in resistor R2.This is justified by
assuming that the input resistance seen from the base is much greater than R2
( Ri = β ⋅ RE >> R2 ) . Thus, the necessary condition for the approximate analysis of the circuit
is:
β .RE ≥ 10 R2
(7)
In this case, the base voltage is given by:
VB =
VCC .R2
R1 + R2
(8)
The DC emitter voltage is given by:
VE = VB − VBE
(9)
Quiescent DC collector current can be found from:
I CQ ≅ I EQ =
VE
RE
(10)
Collector voltage is found as:
VC = VCC − I CQ .RC
(11)
The quiescent DC collector-to-emitter voltage is calculated from:
VCEQ = VCC − I CQ ( RC + RE )
(12)
The collector saturation current in this case is given by:
I C ( sat ) =
VCC − VCE ( sat )
(13)
RC + RE
VCE(sat) is approximately equal to 0.2V for silicon transistors. The collector-emitter voltage at
cut-off is:
VCE ( off ) = VCC
(14)
-56-
Experiment 7
Transistor DC Biasing Circuits
2. Procedure
1- Connect the circuit shown in Fig.3. Use the NPN transistor BC107.
Figure 3: Practical Fixed Bias Transistor Circuit
2- Measure the DC voltages VC and VB using digital multi-meters. Determine the quiescent
base current, collector current, and collector- emitter voltage, where:
I BQ =
VCC − VB
RB
(15)
I CQ =
VCC − VC
RC
(16)
VCEQ = VC
(17)
VBEQ = VB
(18)
3- Measure the transistor current gain as follows:
β dc =
I CQ
I BQ
(19)
4- Calculate the expected values of IBQ, ICQ, and VCEQ. Use the value of β determined in step 3
above. Assume that VBE = 0.7 theoretically. Tabulate you results as shown in Table 1.
Table 1: Measured and Calculated Transistor Parameters for the Fixed Bias Circuit
Transistor 1 (BC107)
Quantity
Measured
Calculated
VB
VC
VBEQ
IBQ
ICQ
VCEQ
βdc
-57-
Experiment 7
Transistor DC Biasing Circuits
5. Replace the BC107 transistor with a 2N2222 NPN transistor and repeat steps 1 to 4.
Tabulate the results as in Table 2.
Table 2: 2N2222 Transistor Parameters in the Fixed Bias Circuit
Transistor 2 (2N2222)
Quantity
Measured
Calculated
VB
VC
VBEQ
IBQ
ICQ
VCEQ
βdc
6- Determine the drift in the measured Q- point:
∆I CQ = I CQ 2 − I CQ1
(20)
∆VCEQ = VCEQ 2 − VCEQ1
(21)
7- Connect the voltage-divider bias circuit shown in Fig.4.
Figure 4: Practical Voltage-Divider Transistor Bias Circuit
8- Measure the DC voltages VB, VE, and VC using digital multi-meters. Determine the
quiescent point of the transistor as follows:
-58-
Experiment 7
Transistor DC Biasing Circuits
VE
RE
(22)
VCEQ = VC − VE
(23)
VBEQ = VB − VE
(24)
I CQ ≅ I EQ =
9- Calculate the expected Q-point of the transistor. Tabulate your results as shown in Table 3.
Table 3: Measured and Calculated Transistor Parameters for the
Voltage Divider Bias Circuit
Transistor 1 (BC107)
Quantity
Measured
Calculated
VB
VC
VE
VBEQ
ICQ
VCEQ
10- Replace the BC 107 transistor with a 2N2222 NPN transistor and repeat steps 7 to 9.
Table 4: Measured and Calculated Transistor Parameters of the
Voltage Divider Bias Circuit for the 2N2222 transistor
Transistor 2 (2N2222)
Quantity
Measured
Calculated
VB
VC
VE
VBEQ
ICQ
VCEQ
11- Find the drift in the measured Q-Point resulting from replacing the transistor. Use
equations 20 and 21.
3. Calculations and Discussion
1. Perform the theoretical calculations to determine the Q-point for both circuits and for
each transistor, and compare them with the measured values.
2. Determine the drift in the Q-point for the two biasing circuits and therefore compare
their bias stabilities.
-59-
Experiment 7
Transistor DC Biasing Circuits
3. Sketch the DC load line for the fixed bias circuit for each transistor case and place the
Q-point on it.
4. Sketch the DC load line for the voltage divider bias circuit for each transistor case and
place the Q-point on it. Is there a difference between the load lines in this case?
5. What is the effect of increasing resistor R2 in the voltage-divider bias circuit on ICQ?
How should we select its practical value for better stability considerations?
6. What is the effect of decreasing resistor RB on ICQ for the fixed – bias circuit? What is
its minimum value to ensure that the transistor is working in the active region?
7. For the fixed bias circuit of Fig.3, if the minimum β of the transistor is specified in the
datasheet as 50, and the maximum value is 250, then determine the range of the Qpoint of the transistor.
8. Sketch the circuit diagram of the collector-feedback bias circuit and compare its
stability with that of the voltage-divider bias circuit.
-60-
Experiment 8
Logic Gate Circuits
Experiment 8
Logic Gate Circuits
Objectives
The purpose of this experiment is to implement the basic logic gate circuits and verify their
operation practically.
Required Parts and Equipments
1. Experimental Test Board.
2. 5V DC Power Supply.
3. Digital Voltmeter.
4. Two BC107 NPN Silicon Transistors.
5. Resistors (10KΩ and 1KΩ).
6. Two 1N4007 Silicon Diodes.
1. Theory
A logic gate is a switching circuit with two or more inputs and whose output will be either a
high voltage or a low voltage, depending on the voltages on the various inputs. Logic gates
are widely used in computers and in all types of digital circuits and systems.
Digital circuits are characterized by the fact that they contain voltages that exist at either of
two levels, for example 0V and 5V. In other words, at any instant of time each circuit input
and output voltage will either be at some LOW voltage (VL) or some HIGH voltage (VH). In
practice, the LOW level is actually a range of voltages, as is the HIGH level. For example,
between 0V and 0.8V might be the low level, and between 2V and 5V might be the HIGH
level. The range of voltages between 0.8V and 2V is not allowed except during transitions
between VH and VL. This concept is illustrated in Fig.1.
Figure1: Typical Voltage Levels in a Digital System
- 61 -
Experiment 8
Logic Gate Circuits
There are several types of logic gates, and many different ways to construct each type using
discrete components. The basic logic gates are the OR gate, AND Gate, NOT gate, NOR gate,
and NAND gate.
1.1 Diode OR Gate
An OR gate is a circuit that has two or more inputs and whose output is equal to the OR sum
(Logical Addition) of the inputs. Fig.2 shows the logic symbol and truth table of a two input
OR gate.
A B Y=A+B
0
0
0
0
1
1
1
0
1
1
1
1
Figure 2: The Logic Symbol and Truth Table of the OR Gate
The OR gate operates such that its output is HIGH (Logic 1) if either input A or B or both are
at a logic -1 level. The OR gate output will be LOW (logic 0) only if all its inputs are at logic0. Fig.3 presents a discrete circuit for the OR gate using two diodes and a resistor. Each input
can be at either 0V or 5V, so there are four possible input combinations.
V1
V2
Vo
0V 0V
0V
0V 5V 4.3V
5V 0V 4.3V
5V 5V 4.3V
Figure 3: Two-input OR Gate Circuit
Examination of the truth table shows that the output will be at a HIHG level when either V1 or
V2 or both are at a HIHG level. The value of Vo is LOW only when both inputs are at a LOW
level.
- 62 -
Experiment 8
Logic Gate Circuits
Consider first the case where V1 = V2 = 0V. In this case neither diode will conduct; thus, no
current flows in the circuit, and the output voltage is zero. When V1 = 0V and V2 = 5V then
diode D2 will be forward biased because its anode is made positive relative to its cathode.
Thus, current will flow through D2 and R. If the diodes are assumed to be silicon, the forward
voltage drop across D2 will be 0.7V, so V0 must equal 5V - 0.7V = 4.3V. Diode D1 is reversebiased because its cathode is at +4.3 V relative to ground, and its anode is at 0V. The third
case, where V1 = 5V and V2 = 0V ,will obviously be the same as the second case except that
D1 will be ON, and D2 will be OFF. In the final case, where both V1 and V2 are 5V, both
diodes are ON, so each will have a 0.7V drop. Again, the output will be 4.3V.
1.2 Diode AND Gate
The second logic gate is the AND gate. Its symbol and truth table are presented in Fig.4. The
output is equal to the AND product of the logic inputs (Logical Multiplication). The AND
gate operates such that its output is HIGH only when all its inputs are HIGH. For all other
cases the AND gate output is LOW.
A B Y=A.B
0
0
0
0
1
0
1
0
0
1
1
1
Figure 4: The Logic Symbol and Truth Table of the AND Gate
The electronic circuit for the AND gate is shown in Fig.5. Consider the first case when V1 =
V2 = 0V. In this case both diodes will be forward-biased and conduct current.
V1
V2
Vo
0V 0V 0.7V
0V 5V 0.7V
5V 0V 0.7V
5V 5V
5V
Figure 5: Two-input AND Gate Circuit
- 63 -
Experiment 8
Logic Gate Circuits
The output voltage in this case will equal the voltage drop across the diodes, which is 0.7V.
When V1 = 0V and V2 = 5V, diode D1 will have its cathode at 0V, and thus will be forward biased. So, current will flow from the 5V supply through R and D1. Diode D2 is OFF, since its
cathode is at +5V. The output voltage V0 will be 0.7V, which is the voltage drop across D1.
In the third case when V1 = 5V and V2 = 0V, diode D1 will be OFF and D2 will be ON and V0
will equal the voltage drop across D2 which is 0.7V.
Finally, when V1 = V2 = 5V, both diodes will be OFF and thus no current will flow through
resistor R resulting in a zero voltage across R and 5V across the output (V0 = VCC -VR = 5V - 0
= 5V).
3. The NOT Gate Circuit
The NOT gate has a single input and output. The output equals the inverse of the input or the
complement of the input. Fig.6 shows the symbol for the NOT gate, which is also called an
inverter.
A Y=A
0
1
1
0
Figure 6: The Logic Symbol and Truth Table for the NOT Gate
The most widely used inverter circuit uses a bipolar transistor in the common-emitter
configuration as shown in Fig.7. The input signal is applied to the base and the output is taken
from the collector.
Figure 7: Transistor Inverter Circuit
- 64 -
Vi
Vo
0V
5V
5V
0V
Experiment 8
Logic Gate Circuits
The circuit operates so that when Vi = 0V, the transistor is OFF. Therefore, IC is zero and no
current flows through RC. This means that the voltage drop across RC is zero and the collector
is at +5V above ground, producing V0 = 5V.
When Vi = 5V, the transistor becomes ON and enters the saturation region when IB is large
enough. So, the collector voltage will be VCE(sat) , and this produces V0 = VCE(sat) ≈ 0V.
1.4 The NOR Gate Circuit
Figure 8 shows the logic symbol for a two-input NOR gate. The operation of the NOR gate is
equivalent to the OR gate followed by an inverter.
A B Y = A+ B
0
0
1
0
1
0
1
0
0
1
1
0
Figure 8: The Logic Symbol and Truth Table for the NOR Gate
Figure 9 shows a practical electronic circuit for implementing the NOR gate. It consists of
two transistors connected in parallel.
V1
V2
Vo
0V
0V
5V
0V
5V
0V
5V
0V
0V
5V
5V
0V
Figure 9: The NOR Gate Circuit
When V1 = V2 = 0V, both transistors are in the cut-off region (OFF), and hence no current
flows in resistor RC. Therefore, the output voltage V0 equals VCC and is +5V.When V1=0 and
V2=5V, transistor Q1 will be OFF and transistor Q2 will now be ON and enters the saturation
- 65 -
Experiment 8
Logic Gate Circuits
region. In this case, the current will flow in RC through transistor Q2. The output voltage will
equal the saturation voltage of Q2 and is approximately 0V (Vo =VCE2(sat) ≈ 0V).
When V1 = 5V and V2 = 0V, the situation will be opposite to the previous case and Vo =
VCE2(sat) ≈ 0V.
Finally, when V1 = V2= 5V, both transistors will conduct, and the output voltage will equal
the saturation voltage of the transistors and hence is approximately 0V (Vo= VCE (sat) ≈ 0V).
5. The NAND Gate Circuit
Figure 10 shows the logic symbol and the truth table of a two-input NAND gate. The
operation of the NAND gate can be understood as being constituted from an AND gate
followed by an inverter.
A B Y = A⋅ B
0
0
1
0
1
1
1
0
1
1
1
0
Figure 10: The Logic Symbol and Truth Table for the NAND Gate
In Figure 11, an electronic circuit representing a NAND gate is depicted. This circuit is
constituted from two transistors connected in series with two different inputs.
V1
V2
Vo
0V
0V
5V
0V
5V
5V
5V
0V
5V
5V
5V
0V
Figure 11: The NAND Gate Circuit
- 66 -
Experiment 8
Logic Gate Circuits
When V1 = V2 = 0V, both transistors are OFF and no-current flows through RC and therefore
Vo = VCC = 5V. When V1=0, and V2=5V transistor Q2 will be ON, but Q1 is OFF, and
therefore no-current will flow through resistor RC and V0 is HIGH and equals 5V. In the third
case, when V1 = 5V, and V2= 0V, transistor Q1 becomes ON and Q2 will be OFF and no
current flows through RC, and hence V0 = VCC = 5V.
Finally, when V1 = V2 = 5V, both transistors will be ON and enter the saturation region. So,
V0 = 2Vsat ≈ 0V and will be LOW.
2. Procedure
1- Connect the OR gate circuit shown in Fig.12 and verify its operation.
V1
V2 Vo
0V 0V
0V 5V
5V 0V
5V 5V
Figure 12: Practical OR Gate circuit
2- Connect the AND gate circuit shown in Fig.13 and verify its truth table.
V1
V2 Vo
0V 0V
0V 5V
5V 0V
5V 5V
Figure 13: Practical AND Gate Circuit
- 67 -
Experiment 8
Logic Gate Circuits
3- Connect the inverter circuit shown in Fig.14 and verify its operation. When Vi = 5V
(HIGH), try to measure VBE and VCE of the transistor at saturation.
Vi
Vo
0V
5V
Figure 14: Practical Inverter Circuit
4- Connect the NOR gate circuit shown in Fig.15 and verify its truth table.
V1
V2
0V
0V
0V
5V
5V
0V
5V
5V
Figure 15: Practical NOR Gate Circuit
5- Connect the NAND gate circuit shown in Fig.16 and verify its truth table.
- 68 -
Vo
Experiment 8
Logic Gate Circuits
V1
V2 Vo
0V 0V
0V 5V
5V 0V
5V 5V
Figure 16: Practical NAND Gate Circuit
3. Discussion
1- Determine the current flowing in each diode in the practical OR logic circuit of Fig.12
when both inputs are HIGH (5V).
2- What is the maximum current rating that each diode should have in the logic circuit shown
below? Assume that the voltage drop across the silicon diode is 0.7V when it conducts.
3- For the inverter circuit of Fig.14, prove that the transistor is working deeply in saturation
when Vi = 5V. Assume that β = 150 for the BC107 NPN transistor.
- 69 -
Experiment 8
Logic Gate Circuits
4- In the logic circuit shown below, what is the minimum RL that the inverter can drive
without causing the output to drop below 4V when Vi = 0V?
5- What is the function of the digital circuit shown below? Describe its operation briefly and
find its truth table.
6- Design a NAND Gate digital circuit using an AND gate and an inverter. Describe the
operation of the circuit.
7- Design a NOR gate circuit using an OR gate circuit and an inverter. Describe briefly the
operation of the circuit.
- 70 -
Experiment 8
Logic Gate Circuits
8- Determine the truth table of the digital circuit shown in the figure below and explain its
operation.
- 71 -
Experiment 8
Logic Gate Circuits
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- 72 -
Experiment 9
The Common Emitter Amplifier
Experiment 9
The Common Emitter Amplifier
Objectives
The purpose of this experiment is to demonstrate the operation of the small signal commonemitter amplifier and investigate the factors influencing the voltage gain as well as to
determine the input and output impedances.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
7.
8.
Experimental Test Board
Function Generator
DC Power Supply
Two-channel Oscilloscope
DC Multimeter
BC107 NPN Silicon Transistor
Resistors 10 KΩ, 3.3 KΩ, 2.7 KΩ, 1 KΩ, 120 Ω.
Capacitors 2.2 µF and 10 µF.
1. Theory
The common-emitter amplifier is characterized by the application of the input signal to the
base lead of the transistor while taking the output from the collector, which always gives 180o
phase shift between the input and output signals. Figure 1 presents a schematic diagram for a
typical common-emitter amplifier using the voltage-divider bias configuration.
Figure 1: Schematic Diagram for a Typical Common Emitter Amplifier Circuit
- 73 -
Experiment 9
The Common Emitter Amplifier
The DC coupling capacitors Cin and Cout are used to block the DC current and thus to prevent
the source internal resistance and the load resistance RL from changing the DC bias voltages at
the base and collector. Capacitor CE is a bypass capacitor for the emitter resistor RE2. Resistor
RE2 is used for bias stability, while RE1 is used to minimize the change in the emitter internal
AC resistance re due to temperature effects, and thereby to obtain a stable voltage gain.
The base DC voltage can be calculated approximately from the following equation assuming
that β.(RE1+RE2) >> R2:
R2 .VCC
R1 + R2
The emitter DC voltage is therefore:
VB ≅
(1)
VE = VB − VBE
The emitter DC bias current can be obtained as:
(2)
VE
≅ I CQ
RE1 + RE 2
Transistor AC emitter resistance is obtained from:
I EQ =
VT
I EQ
Where VT = 26 mV at room temperature.
re =
(3)
(4)
The quiescent DC collector-emitter voltage is calculated from:
VCEQ = VCC − I CQ ( RC + RE1 + RE 2 )
(5)
1.1 Voltage Gain Analysis
Figure 2 presents the AC small-signal equivalent circuit for the common emitter amplifier.
From this circuit, the amplifier voltage gain can be found as:
vout
R || RL
=− C
vin
RE1 + re
If the load resistor RL is removed then the voltage gain will become:
Av =
Av = −
RC
RE1 + re
(6)
(7)
On the other hand if the bypass capacitor CE is removed, then the voltage gain will be
modified as:
Av = −
RC || RL
RE1 + RE 2 + re
(8)
- 74 -
Experiment 9
The Common Emitter Amplifier
Figure 2: The Small-Signal AC Equivalent Circuit for the Common Emitter Amplifier
1.2 AC Load Line and Maximum Symmetrical Swing
The AC load line of the amplifier circuit can be sketched to predict the swing of the output
voltage and collector current. Figure 2 shows the AC and DC load lines of the circuit.
Figure 3: DC and AC Load Lines and Collector Current and Voltage Swing
As shown in Fig.2, both load lines intersect at the Q-point of the transistor. The slope of the
AC load line is equal to -1/Rac, where Rac is the AC equivalent resistance seen between the
collector and emitter terminals. Rac can be obtained from the amplifier’s small signal
equivalent circuit of Fig.2. The total collector current and voltage can be expressed as the sum
of the quiescent values and the AC signal quantities as shown below:
- 75 -
Experiment 9
The Common Emitter Amplifier
iC = I CQ + ic
(9)
vCE = VCEQ + vce
(10)
It can be shown that iC(max) and vCE(max) in Fig.3 are given by:
VCEQ
Rac
= VCEQ + I CQ .Rac
iC (max) = I CQ +
(11)
vCE (max)
(12)
Where:
Rac = RE1 + RC || RL
(13)
Maximum symmetrical swing in the output signal can be obtained if the Q-point bisects the
AC load line. The AC load line concept can be used to predict the maximum amplitude in the
output signal before clipping.
1.3 Input and Output Impedances
The input and output impedances of the amplifier can be found theoretically as the Thevenin
equivalent impedances at the input and output terminals respectively. For the equivalent
circuit of Fig.2, the input impedance (Zin) of the amplifier seen by the source is:
Z in = R1 || R2 || β (re + RE1 )
(14)
Similarly, the output impedance (Zout) seen from the output terminals is:
Z out = RC
(15)
The amplifier circuit can be represented as a two-port network as illustrated in Fig.4. In this
figure, Avo represents the no-load voltage gain of the amplifier, Zin is the amplifier’s input
impedance, and Zout is the amplifier’s output impedance. Resistor RS is the internal resistance
of the signal source, while RL is the load resistance.
Figure 4: The Amplifier as a Two-Port Network
- 76 -
Experiment 9
The Common Emitter Amplifier
The overall voltage gain of the amplifier taking the effects of RS and RL into account can be
expressed as:
Av =
vin vout
.
vs vin
Av =
Z in
A .R
. vo L
Z in + RS RL + Z out
(16)
For the input port, when RS = Zin, we have:
vin =
Z in
1
vS = vS
2
Z in + RS
Assuming that the amplifier is connected with no-load, we have:
Av =
vin vout 1
.
= Avo
vS vin 2
Thus, the input impedance can be estimated practically by inserting a variable source resistor
RS in series with the source and varying it until the voltage gain of the amplifier equals half
the no-load gain Avo. This value of RS represents the input impedance Zin.
For the output port, when RL = Zout, and assuming that RS = 0, then we have:
Av =
vout
A .R
1
= vo L = Avo
vin RL + Z out 2
So that the output impedance can be estimated practically by connecting a variable load
resistor RL and varying it until the voltage gain becomes equal to half the value of the no-load
gain with RS = 0. This value of RL represents the output impedance Zout.
2. Procedure
1. Connect the circuit shown in Fig.5 and measure the DC voltages VB, VE, and VC. Try to
measure the DC current gain of the BC107 transistor hFE using a multi-meter. Tabulate
your results as illustrated in Table-1.
Table-1: Measured Quantities for the DC Bias Circuit
Parameter β
VB
VE
VC
Value
- 77 -
ICQ
VCEQ VBEQ re
Experiment 9
The Common Emitter Amplifier
Figure 5: The DC Bias Circuit of the Common Emitter Amplifier
2. Connect the amplifier circuit shown in Fig.6, and apply a sinusoidal source signal with
peak amplitude of 0.1V and frequency of 10 KHz. Display both the input (source) and
output (load) signals on the oscilloscope. Try to measure the voltage gain Av, where Av =
Vout/Vs.
Figure 6: The Practical Common Emitter Amplifier Circuit
3. Remove load resistor RL and re-measure the voltage gain.
- 78 -
Experiment 9
The Common Emitter Amplifier
4. Remove the bypass capacitor CE and measure the voltage gain with the load resistor RL
connected at the output. Tabulate your results as shown in Table-2.
Table-2: Voltage Gain for Different Cases
Case
Voltage Gain
Normal (RL=10KΩ)
No-Load (RL = ∞)
No Bypass Capacitor
5. Increase the amplitude of the source input signal gradually until clipping occurs in the
output signal. Find the maximum peak amplitude for vout and vs at the edge of clipping for
the three cases illustrated in Table-3.
Table-3: Peak Input and Output Voltages before Clipping
Case
Vs(max) Vout(max)
Normal
No-Load
No Bypass Capacitor
6. Connect the circuit shown in Fig.7, where Rtest is a variable resistor box. This circuit is used
to measure the input impedance of the amplifier.
Figure 7: Test Circuit to Measure the Input Impedance of the Amplifier
- 79 -
Experiment 9
The Common Emitter Amplifier
7. Set Rtest = 0 Ω initially, and measure the no-load voltage gain Avo.
8. Increase Rtest in steps until the voltage gain becomes equal to half the no-load gain. Record
this value of Rtest as Zin.
9. Connect the circuit shown in Fig.8 to measure the output impedance of the amplifier.
Resistor Rtest is inserted at the output terminals instead of RL.
Figure 8: Test Circuit for Measuring the Output Impedance of the Amplifier
10. Vary Rtest in steps until the voltage gain becomes equal to half the no-load gain. Record
this value of Rtest as Zout.
3. Calculations and Discussion
1. Calculate the theoretical DC voltages and currents for the transistor bias circuit and
compare them with the practically measured values.
2. Calculate the theoretical values of the voltage gain for the three cases and compare them
with the measured quantities.
3. Sketch the AC load line for the amplifier circuit and find the theoretical maximum
symmetrical swing in collector voltage vce before clipping when RL = 10 KΩ. Determine
Vout(max) before clipping and compare it with the measured value.
4. Determine the theoretical value of the input impedance and compare it with the measured
value.
5. Calculate the theoretical value of the output impedance and compare it with the measured
value.
- 80 -
Experiment 9
The Common Emitter Amplifier
6. What is the role of resistor RE1 in the amplifier circuit? Derive two expressions for the
voltage gain with and without the existence of RE1 and compare between them in terms of
gain value and gain stability?
7. If resistor R2 is opened (or removed) in the circuit of Fig.5, what is its effect on the
transistor circuit? Determine the collector current IC and voltage VCE in this case.
8. Calculate the current gain Ai of the amplifier circuit of Fig.6.
- 81 -
Experiment 9
The Common Emitter Amplifier
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- 82 -
Experiment 10
The Common Base Amplifier
Experiment 10
The Common Base Amplifier
Objectives
The purpose of this experiment is to test the common base amplifier circuit and evaluate its
characteristics.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
7.
8.
Experimental Test Board.
DC Power Supply.
Function Generator.
Two-Channel Oscilloscope.
Digital Multimeter.
NPN Silicon Transistor, 2N2222.
Resistors 10 kΩ, 3.3 kΩ, 1.5 kΩ, 1 kΩ.
Capacitors 2.2 µF, and 10 µF.
1. Theory
The common base amplifier is shown in the schematic diagram of Fig.1.
Figure 1: The Common Base Amplifier Topology
The DC biasing circuit uses one power supply and is identical to that of the common emitter
amplifier with voltage-divider biasing. Thus, the same technique used for β-independent
operating point biasing in the common emitter amplifier will work for this application. As
shown from this circuit, the input signal is coupled to the emitter of the transistor through the
DC blocking capacitor Cin, and the output signal is taken from the collector via the coupling
capacitor Cout. The base capacitor CB is used to bypass the base resistors R1 and R2, thereby
putting the base at AC ground.
- 83 -
Experiment 10
The Common Base Amplifier
The Q-point point (VCBQ, ICQ) of the transistor can be obtained by evaluating the base voltage,
VB, assuming that IB is negligible when compared with the current flowing in resistor R2. This
condition can be justified if β.RE ≥ 10 R2. On this basis, the DC voltage at the base is
approximated by:
R2 .VCC
R1 + R2
VB =
(1)
The emitter voltage, VE, is given by:
VE = VB − VBE
(2)
The emitter quiescent current, IEQ, can be calculated from:
VE
RE
(3)
I CQ ≅ I EQ
(4)
I EQ =
The collector voltage, VC, is determined from:
VC = VCC − I CQ .RC
(5)
On the other hand, the collector-base quiescent voltage, VCBQ, is determined from:
VCBQ = VC − VB
(6)
The emitter small signal AC resistance is found from:
re =
VT
I EQ
(7)
Where VT is the thermal voltage and equals to 26 mV at room temperature.
The small signal AC equivalent circuit of the amplifier is presented in Fig.2.
Figure 2: The Small Signal Equivalent Circuit of the Common Base Amplifier
- 84 -
Experiment 10
The Common Base Amplifier
The theoretical value of the voltage gain can be estimated from the small signal equivalent
circuit to be:
RC || RL
(8)
re
As indicated from the voltage gain equation, the output signal is in-phase with the input
signal.
Av ≅
The input impedance seen from the signal source is determined as:
Z in = RE || re
(9)
The output impedance seen from the load terminals is given by:
Z out = RC
(10)
It is important to remember that the common base amplifier provides no current gain. On the
other hand, the input impedance is very low which may load the signal source resulting in a
reduction of the net input voltage delivered to the amplifier especially when the source
resistance is significantly high. In this case, the overall voltage gain of the amplifier, taking
the effect of source resistance Rs into account, will be:
Avs =
vout vout vin RC || RL
Z in
=
. =
.
vs
vin vs
re
Z in + Rs
(11)
2. Procedure
1. Connect the DC bias circuit shown in Fig.3.
Figure 3: The Practical Common Base Bias Circuit
- 85 -
Experiment 10
The Common Base Amplifier
2. Measure the DC voltages VB, VE, and VC using a digital voltmeter. Try to measure the
transistor current gain β with the aid of a multi-meter. Tabulate your results as shown in
Table-1.
Table-1: Measured Bias Circuit Parameters
Parameter β
VB
VE
VC
ICQ
VCBQ VBEQ re
Value
3. Connect the amplifier circuit shown in Fig.4.
Figure 4: The Practical Common Base Amplifier Circuit
4. Apply a sinusoidal source signal with 0.1Vp-p amplitude, and frequency of 10 KHz (In this
case Vs(p-p) = 0.1V). Display the input signal at channel 1 of the oscilloscope, and the output
signal at channel 2. Measure the amplitudes of both signals and determine the practical
voltage gains Av and Avs as indicated in Table-2.
Table-2: Voltage Gain Measurement
Quantity
Vin(p-p)
Vout(p-p)
Av = Vout(p-p) /Vin(p-p)
Avs = Vout(p-p) /Vs(p-p)
- 86 -
Value
Experiment 10
The Common Base Amplifier
3. Calculations and Discussion
1. Determine the theoretical bias point of the transistor and compare it with the measured
value.
2. Calculate the theoretical voltage gain Av of the amplifier, and compare it with the
measured value.
3. Justify the difference between the measured value of Av and that of Avs.
4. Determine the input impedance Zin and the output impedance Zout for the amplifier.
5. Estimate the value of the internal source resistance Rs from Av and Avs.
6. Assume that the DC coupling capacitor Cout in Fig.4 is shorted. What DC voltage will
appear at the collector of the transistor in this case?
7. If capacitor CB in the circuit of Fig.4 is opened, what is its effect on the voltage gain
and the input impedance of the amplifier?
8. What is the main disadvantage of the common base amplifier when compared to the
common emitter amplifier?
- 87 -
Experiment 10
The Common Base Amplifier
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- 88 -
Experiment 11
The Emitter Follower
Experiment 11
The Emitter Follower
Objectives
The purpose of this experiment is to examine the operation of the emitter follower and
evaluate its characteristics.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
7.
8.
Experimental Test Board.
DC Power Supply.
Function Generator.
Two-Channel Oscilloscope.
Digital Multimeter.
PNP Silicon Transistor, BC178.
Resistors 10 kΩ, 2.2 kΩ.
Capacitors 10 µF.
1. Theory
In the common collector amplifier, the output signal is taken from the emitter while the input
signal is applied to the base of the BJT. This amplifier is usually referred to as an emitter
follower. In this amplifier, the output voltage (emitter voltage) is always slightly less than the
input voltage (base voltage) in magnitude, and is in-phase with it. The voltage gain is
therefore approximately equal to unity. So, the emitter voltage always follows the base voltage
and hence the circuit is well-known as the emitter follower. Figure 1 shows a schematic
diagram for a typical emitter follower using a PNP transistor.
Figure 1: Schematic Diagram for a Typical Emitter Follower Circuit
- 89 -
Experiment 11
The Emitter Follower
The base bias voltage VB can be approximately calculated from:
VEE .R2
R1 + R2
VB ≅
(1)
The emitter DC voltage is thus given by:
VE = VB + VEB
(2)
Where VEB = -VBE ≈ 0.7V for Silicon. In this case VE > VB.
The emitter quiescent current IEQ is given by:
I EQ =
VEE − VE
RE
(3)
The collector current IC is approximately equal to emitter current IE.
The emitter-collector voltage VEC is equal to the emitter voltage as the collector is grounded in
this circuit. Thus:
VEC = VE
(4)
Where VC = 0. Note that in PNP transistor biasing VE > VB > VC.
The emitter small-signal resistance can be obtained from:
re =
VT
I EQ
(5)
Where VT is the thermal voltage and equals to 26 mV at room temperature.
Figure 2 presents the small-signal equivalent circuit of the amplifier.
Figure 2: The Small Signal Equivalent Circuit of the Emitter Follower
- 90 -
Experiment 11
The Emitter Follower
The output signal vo is related with the input signal vi according to the relation:
vo = vi + vbe
(6)
Since vbe is a very small signal, therefore vo follows vi in magnitude and phase. The voltage
gain of the amplifier can be derived to be:
Av =
vo
RL || RE
=
vi RL || RE + re
(7)
In this case the signal generator internal resistance is neglected.
The input impedance seen from the input terminal can be proved to be:
Z i = R1 || R2 || (β (re + RE || RL ) )
(8)
On the other hand, the output impedance seen from the load resistance after neglecting the
internal resistance of the source generator is:
Z o = RE || re
(9)
As indicated in the above equations, the emitter follower has large input impedance and very
low output impedance and can therefore be used as a buffer stage between a high output
impedance amplifier and a low resistance load.
2. Procedure
1. Connect the DC bias circuit shown in Figure 3.
Figure 3: The Practical Emitter Follower Bias Circuit
- 91 -
Experiment 11
The Emitter Follower
2. Measure the DC voltages VB and VE using a digital voltmeter. Try to measure the
transistor current gain β with the aid of a multi-meter. Tabulate your results as shown
in Table-1.
Table-1: Measured Bias Circuit Parameters
Parameter β
Value
VB
VE
VEBQ VECQ IEQ
re
3. Connect the amplifier circuit shown in Figure 4.
Figure 4: The Practical Emitter Follower Circuit
4. Apply a sinusoidal signal with amplitude of 2Vp-p and frequency of 10 KHz. Display
the input signal on channel 1, and the output signal on channel 2. Try to measure the
amplitude of the output signal before and after removing RL.
5. Tabulate your results as shown in Table-2.
Table-2: Measured Voltage Gain
Vo(p-p)
RL = 10KΩ
RL = ∞
- 92 -
Av = Vo(p-p) /Vs(p-p)
Experiment 11
The Emitter Follower
3. Calculations and Discussion
1. Calculate the Q-Point parameters of the circuit and compare them with the measured
values.
2. Sketch the DC load line of the transistor (IE versus VEC) indicating the position of the
Q-Point.
3. Evaluate the theoretical values of the voltage gain for both cases before and after
removing the load resistor, and compare them with the measured quantities.
4. Determine the input and output impedances of the amplifier.
5. What is the effect of adding a collector resistor RC = 1KΩ on the Q-Point and the
voltage gain of the amplifier?
6. Derive an equation for the emitter quiescent current IEQ if resistor R1 in Figure 1 is
removed.
7. Modify the circuit of Figure 1 if an NPN transistor is to be used instead of the PNP
transistor.
8. Derive an equation for the current gain of the amplifier circuit shown in Figure 1.
- 93 -
Experiment 11
The Emitter Follower
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- 94 -
Experiment 12
Amplifier Frequency Response
Experiment 12
Amplifier Frequency Response
Objectives
The purpose of this experiment is to evaluate the frequency response of a common emitter
amplifier.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
7.
Experimental Test Board
Signal Generator
Two-Channel Oscilloscope
Digital Multimeter
NPN Silicon Transistor BC107
Resistors 10 KΩ, 3.3 KΩ, 2.7 KΩ, 1 KΩ, 120 Ω.
Capacitors 2.2 µF and 10 µF.
1. Theory
All amplifiers have a finite bandwidth. The low cutoff frequency can in some cases extend
down to DC and is a parameter under direct control of the designer. The ultimate high
frequency limit is determined by the physical characteristics of the components and the
construction of the circuit.
A typical BJT common emitter amplifier is shown in Fig.1. The input signal source and load
resistor are capacitively coupled to the amplifier via capacitors Cc1 and Cc2 respectively. The
coupling capacitors Cc1 and Cc2, emitter bypass capacitor CE, and internal transistor
capacitances shape the frequency response of the amplifier.
Figure 1: Typical Common Emitter Amplifier
- 95 -
Experiment 12
Amplifier Frequency Response
A typical amplifier frequency response curve is shown in Fig.2. This curve presents the
magnitude of the voltage gain versus frequency.
Figure 2: Typical Amplifier Frequency Response
The voltage gain in decibels is calculated as:
Av (dB ) = 20 log( Av )
(1)
In Fig.2, Avm represents the mid-band (or mid range) gain of the amplifier. For the circuit of
Fig.1, it is given by:
( RC || RL )
(2)
re + RE1
At the lower cut-off frequency fL and upper cut-off frequency fH, the voltage gain of the
amplifier drops to 0.707 of its mid-band value (or -3dB below the maximum value). The
frequency fL is dependent on the coupling and bypass capacitors, while the frequency fH is
determined by the transistor internal capacitances (mainly Cbc and Cbe). The bandwidth of the
amplifier is the difference between fH and fL:
Avm = −
BW = f H − f L
(3)
As the signal frequency drops below mid-band, the impedances of the coupling and bypass
capacitors will increase, resulting in a reduction of the voltage gain. In other words, the low
frequency response of the amplifier is determined by the capacitors Cc1, Cc1, and CE. Each one
of the three capacitors makes a contribution to the overall frequency response of the amplifier.
Each capacitor behaves like a capacitor in a high pass filter. Therefore, each one will
contribute with a cut-off frequency of its own.
The cut-off frequency due to the input coupling capacitor Cc1 is fL1, and is calculated from the
following equation when ignoring the source resistance Rs:
1
2π .Z in .Cc1
Where Zin is the input impedance of the amplifier and is given by:
f L1 =
- 96 -
(4)
Experiment 12
Amplifier Frequency Response
Z in = R1 || R2 || ( β (re + RE1 ))
(5)
The cut-off frequency due to the output coupling capacitor Cc2 is fL2, and is given by:
fL2 =
1
2π ( RC + RL ).Cc 2
(6)
Finally, the cut-off frequency due to the emitter bypass capacitor CE is fL3, and is given by:
f L3 =
1
2π .Z e .CE
(7)
Where Ze is the effective emitter impedance seen from the terminals of capacitor CE, and is
given by:
Z e = ( RE1 + re ) || RE 2
(8)
In equation (8), the source resistance Rs is so small to be ignored.
Among the three corner frequencies, fL3 will usually have the largest value.
The low cut-off frequency of the amplifier can be approximated as the largest value of the
three individual lower corner frequencies:
f L = max( f L1 , f L 2 , f L 3 )
(9)
The high frequency response of the amplifier is determined by the internal parasitic
capacitances of the transistor. These capacitances, Cbe and Cbc, are proportional to the
physical area of the junctions and inversely proportional to the width of the depletion region.
This means that the capacitance is a function of bias conditions. A forward biased junction
has relatively high capacitance (tens to over one hundred pico-farads) because the width of
the depletion region is narrow. A reverse biased junction has relatively low capacitance
(typically less than ten pico-farads) because the width of the depletion region is wide.
Two corner frequencies are existed due to the total transistor parasitic capacitances at input
(base) and output (collector). The first corner frequency fH1 is inversely proportional to
Cbe+CM, where CM is known as the Miller capacitance and is given by:
CM = Cbc .(1 + Avm )
(10)
The second corner frequency fH2, on the other hand, is inversely proportional to Cbc. The
corner frequencies fH1 and fH2 can be determined from the high-frequency equivalent circuit of
the amplifier.
The high cut-off frequency of the amplifier can be approximated as the lowest value of the
two individual upper corner frequencies:
- 97 -
Experiment 12
Amplifier Frequency Response
f H = min( f H 1 , f H 2 )
(11)
The frequency at which the amplifier’s gain drops to 1 (or 0 dB) is called the unity-gain
frequency and is denoted by fT. The significance of fT is that it always equals the product of
the mid-band gain times the bandwidth of the amplifier.
fT = Avm .BW
(12)
2. Procedure
1. Connect the circuit shown in Fig.3 and measure the DC voltages VB, VE, and VC. Try
to measure the DC current gain of the BC107 transistor hFE using a multi-meter.
Tabulate your results as illustrated in Table-1.
Table-1: Measured Quantities for the DC Bias Circuit
Parameter β
VB
VE
VC
ICQ
VCEQ VBEQ re
Value
Figure 3: The DC Bias Circuit of the Amplifier
2. Connect the amplifier circuit shown in Fig.4. Apply a sinusoidal source signal with peakto-peak amplitude of 0.2V and vary the frequency from 50 Hz to 10 MHz in several steps.
Display both the input (source) and output (load) signals on the oscilloscope. Try to
measure the amplitude of the output signal, and the amplifier gain as unit-less value, and in
dB as well. Tabulate your results as illustrated in Table-2.
- 98 -
Experiment 12
Amplifier Frequency Response
Figure 4: The Practical Amplifier Circuit
Table-2: Measured Voltage Gain versus Frequency
Frequency (Hz) Vout(p-p) Av=Vout/Vs Av(dB)=20log(Av)
50
100
150
200
400
800
1K
2K
4K
8K
10K
20K
- 99 -
Experiment 12
Amplifier Frequency Response
Table-2: Continued
Frequency (Hz) Vout(p-p) Av=Vout/Vs Av(dB)=20log(Av)
50K
100K
200K
500K
600K
800K
1M
2M
4M
6M
8M
10M
3. Calculations and Discussion
1. Sketch the frequency response of the amplifier on a semi-log paper.
2. From the frequency-response plot, determine the -3 dB cut-off frequencies fL and fH of
the amplifier, and find the bandwidth.
3. Calculate the lower break frequencies fL1, fL2, and fL3 due to the coupling and bypass
capacitors. Find the dominant corner frequency and compare it with the measured
value of fL.
4. From your plot, determine the unity-gain frequency fT.
5. Calculate the theoretical value of the mid-band gain, and compare it with the
practically measured value.
6. State how you can reduce the overall bandwidth of the amplifier practically.
7. What is meant by Miller input capacitance, and what are the factors on which it
depends?
8. What is meant by one decade, and one octave?
- 100 -
Experiment 13
JFET Characteristics
Experiment 13
JFET Characteristics
Objectives
The purpose of this experiment is to determine and sketch the characteristics of the JFET and
to find its parameters.
Required Parts and Equipments
1.
2.
3.
4.
5.
Experimental Test Board.
Dual Polarity Variable DC Power Supply
Digital Multimeters.
N-Channel JFET 2N3819.
Resistors 1 MΩ, 100 Ω.
1. Theory
The Junction Field Effect Transistor (JFET) is a three-terminal device with one terminal
(called the gate) capable of controlling the current between the other two terminals (drain and
source). The primary difference between FET and BJT transistors is the fact that the BJT
transistor is a current-controlled device, while the JFET transistor is a voltage-controlled
device. The FET transistor is a unipolar device depending on either electron conduction (Nchannel JFET) or hole conduction (P-channel JFET). In contrast, the BJT transistor is a
bipolar device, meaning that the conduction depends on two charge carriers (electrons and
holes) in the same time.
Another difference between two devices is the high input impedance of the JFET when
compared with the BJT. The input impedance is usually larger than 1 MΩ. However, typical
AC voltage gains for BJT amplifiers are greater than those for FET amplifiers. Furthermore,
FETs are more temperature stable than BJTs and are usually smaller in size, making them
particularly useful in integrated circuit chips.
The basic construction of an N-channel JFET is shown in Fig.1 together with its symbol.
Figure 1: N-Channel JFET Structure and Symbol
- 101 -
Experiment 13
JFET Characteristics
The drain current (ID) of the JFET is controlled by the application of reverse-biased voltage
between gate and source terminals (VGS). The relationship between ID and VGS is defined by
the well-known Shockley’s equation:
⎛ V
I D = I DSS ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
2
(1)
Where VP is called the pinch-off voltage and IDSS is known as the drain saturation current.
When VGS = VP then ID = 0, and the FET is in the cut-off region. Equation (1) indicates that
the FET is a square-law device.
The relation between ID and VGS is also referred as the transfer characteristic of the JFET and
is presented in Fig.2. This curve is obtained by varying the negative voltage VGS between VP
and 0 and measuring ID for a given value of the drain to source voltage (VDS). Equation (1)
can approximate this curve to an acceptable level.
Figure 2: The Transfer Characteristics of the JFET
On most specification sheets, the pinch-off voltage is specified as VGS(off) rather than VP as
shown in Fig.2. In this case, VGS(off) represents the cut-off voltage.
The circuit used to obtain the JFET characteristics is shown in Fig.3. To obtain the transfer
characteristic, the drain supply voltage VDD should be maintained at a certain value, and the
gate supply voltage is adjusted to several negative values while recording ID in each step.
Figure 3: A Test Circuit for Getting JFET Characteristics
- 102 -
Experiment 13
JFET Characteristics
On the other hand, to sketch the drain characteristic, the gate-source voltage VGS must be kept
at a certain level while varying VDS in several steps and recording ID in each step. Figure 4
shows the drain (or output) characteristics of the JFET.
Figure 4: Typical JFET Drain Characteristics
As shown from Fig.4, for small values of VDS (VDS < |VP|) the drain current increases linearly
with VDS. This region is called the linear or Ohmic region in which the JFET behaves as a
voltage-controlled resistor. For larger values of VDS (VDS > |VP|), the drain current (ID) is
approximately constant and enters the saturation region.
The transconductance of the JFET (gm) is defined as the change in drain current (∆ID) for a
given change in gate-to-source voltage (∆VGS) with the drain-to-source voltage (VDS) kept
constant. It has the unit of siemens (S).
gm =
∆I D
∆VGS
(2)
V DS = const .
Because the transfer characteristic curve for a JFET is nonlinear, gm varies in value depending
on the location on the curve as depicted in Fig.5. A datasheet normally gives the value of gm
measured at VGS = 0, which is referred as gmo.
Theoretically, gm can be calculated at any point on the transfer characteristic curve from the
following equation:
⎛ V
g m = g mo ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
(3)
Where gmo is found from:
- 103 -
Experiment 13
g mo =
JFET Characteristics
2 I DSS
| VP |
(4)
Figure 5: Graphical Determination of the JFET Transconductance
2. Procedure
1. Connect the circuit shown in Fig.6.
Figure 6: The Test Circuit for Getting JFET Characteristics
2. Adjust VDD so that VDS = 5V, and vary VGG to change VGS from 0V to -3V in different
steps recording ID for each step. Repeat with VDS = 10V. Tabulate your results as shown in
Table-1.
- 104 -
Experiment 13
JFET Characteristics
Table 1: Recorded Data for the JFET Transfer Characteristics
VDS = 5V
VDS = 10V
VGS(V) ID(mA) VGS(V) ID(mA)
0
0
-0.25
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1
-1.25
-1.25
-1.5
-1.5
-1.75
-1.75
-2
-2
-2.5
-2.5
-3
-3
3. Set VGG to 0V so that VGS = 0V and vary VDD so that VDS changes in several steps
recording ID in each step. Repeat with VGS = -1V. Tabulate your results as illustrated in
Table 2.
- 105 -
Experiment 13
JFET Characteristics
Table 2: Recorded Data for the JFET Drain Characteristics
VGS = 0V
VGS = -1V
VDS(V) ID(mA) VDS(V) ID(mA)
0
0
0.5
0.5
1
1
1.5
1.5
2
2
2.5
2.5
3
3
4
4
5
5
6
6
8
8
10
10
3. Calculations and Discussion
1. From the obtained data, sketch the transfer characteristics of the JFET.
2. Determine the values of VP and IDSS from the plot.
3. From the sketched curves, find the value of the JFET transconductance at VGS = -1V
and VGS = -2V for VDS = 10V and compare between the two values.
4. Calculate theoretically the value of gm at VGS = -1V and VGS = -2V when VDS = 10V
and compare them with the measured quantities.
5. Sketch the drain characteristics of the JFET from the obtained data.
6. From the linear region of the drain characteristic, determine the value of the drain to
source resistance rds when VGS = 0V.
7. Determine the value of rds in the saturation region of the JFET drain characteristic
when VGS = 0. Compare this value with that obtained in step 6.
8. Compare between the JFET and the BJT.
- 106 -
Experiment 14
The Common Source Amplifier
Experiment 14
The Common Source Amplifier
Objectives
The purpose of this experiment is to test the performance of the common source amplifier
using the self-bias circuit.
Required Parts and Equipments
1.
2.
3.
4.
5.
6.
7.
8.
Experimental Test Board.
Dual Polarity Variable DC Power Supply
Digital Multimeters.
Dual-Channel Oscilloscope.
Function Generator.
N-Channel JFET 2N3819.
Resistors 1 MΩ, 1 kΩ, 3.3 kΩ.
Capacitors 2.2 µF, 10 µF.
1. Theory
The common source amplifier configuration is widely used amongst other JFET
configurations and can provide both high voltage gain and large input impedance. In this
configuration, the input signal is applied to the gate and the output signal is taken from the
drain, while the source terminal being the reference or common. In order to work as an
amplifier, the JFET should be properly biased by setting the gate-source voltage which results
in the required drain current.
The N-channel JFET requires that the gate-source voltage always be less negative than the
pinch-off voltage, but less than zero. Since virtually no gate current flows due to the JFET’s
high input impedance, the gate voltage is essentially at ground level. Consequently, using
only a drain-supply voltage, the required negative quiescent gate-source voltage is developed
by the voltage drop across the source resistor of the self-bias circuit shown in Fig.1. This
circuit is one of the simplest and practical bias circuits for JFET amplifiers in which a single
power supply is used.
In this circuit, the gate voltage is zero.
VG = 0
(1)
Thus, the gate-source voltage is given by:
VGS = − I D .RS
(2)
Where the drain current is given by:
-107-
Experiment 14
The Common Source Amplifier
Figure 1: The Self-Bias JFET Circuit
⎛ V
I D = I DSS ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
2
(3)
Solving equations (2) and (3) simultaneously will give both IDQ and VGSQ.
The drain-source voltage is given by:
VDS = VDD − I D .( RD + RS )
(4)
A typical common-source amplifier circuit is shown in Fig.2. In this circuit, capacitors Cc1
and Cc2 are DC blocking capacitors, while CS is a bypass capacitor for the source resistor RS.
Figure 2: A Typical Common Source Amplifier
-108-
Experiment 14
The Common Source Amplifier
The small-signal approximate equivalent circuit for the amplifier of Fig.2 is presented in
Fig.3.
Figure 3: The Simplified Small-Signal Equivalent Circuit of the Amplifier
The transconductance of the JFET at the Q-point is derived as:
dI D
dVGS
gm =
Q − po int
⎛ V
= g mo ⎜⎜1 − GS
VP
⎝
⎞
⎟⎟
⎠
(5)
Where gmo is given by:
g mo =
2 I DSS
VP
(6)
The voltage gain of the amplifier can be derived from the equivalent circuit of Fig.4:
Av =
Vout
= − g m .( RD || RL )
VS
(7)
It can be shown that when the source bypass capacitor CS is removed, the voltage gain will
become:
Av =
− g m .( RD || RL )
1 + g m .RS
(8)
The input impedance of the amplifier seen from the gate terminal is:
Z in = RG
(9)
And the output impedance seen from the output terminals is:
Z out = RD
(10)
-109-
Experiment 14
The Common Source Amplifier
2. Procedure
1. Connect the test circuit shown in Fig.4 to measure IDSS. Increase the supply voltage until ID
no longer increases. This level of drain current is recorded as IDSS.
Figure 4: Test Circuit for Measuring IDSS
2. Connect the test circuit shown in Fig.5 to measure VP. The gate supply voltage VGG is
adjusted from 0 to larger negative values until the drain current ID just reaches 0. The
voltage VGS to just cause the drain current to reach 0 is the measured value of VP. Tabulate
your results as shown in Table-1.
Figure 5: Test Circuit for Measuring VP
Table-1: Measured JFET Parameters
Device Parameter Value
IDSS
VP
-110-
Experiment 14
The Common Source Amplifier
3. Connect the JFET self-bias circuit shown in Fig.6 and measure the DC voltages VG, VS, and
VD with the aid of a digital multi-meter. Determine VGSQ, IDQ, VDSQ, and gm at the Q-point.
Tabulate your results as illustrated in Table-2.
Figure 6: The Practical Bias Circuit of the Amplifier
Table-2: Measured Bias Circuit Parameters
Quantity Value
VG
VS
VD
VGS
ID
VDS
gm
4. Connect the amplifier circuit shown in Fig.7. Sketch the input and output signals and
determine the voltage gain of the circuit in three cases as illustrated in Table-3.
Table-3: Measured Voltage Gain Conditions
Case
Voltage Gain (vout/vs)
Normal Case
No-Load Condition
No-Source Bypass Capacitor Condition
-111-
Experiment 14
The Common Source Amplifier
Figure 7: The Practical Common-Source Amplifier Circuit
3. Calculations and Discussion
1. Using the measured device parameters IDSS and VP, calculate the theoretical Q-point values
of IDQ and VGSQ and compare them with the measured quantities.
2. Calculate the amplifier voltage gain theoretically for the three conditions and compare them
with the measured values.
3. Derive an expression for the voltage gain when the source capacitor CS is removed. Sketch
the small signal equivalent circuit of the amplifier in this case.
4. Indicate graphically the effect of increasing the source resistor RS on the Q-point of the
JFET.
5. Determine the input and output impedance of the amplifier in both cases of holding and
removing the source bypass capacitor CS.
6. Determine the DC power dissipation in the JFET connected in the amplifier circuit of Fig.7.
7. What is the effect of increasing the source resistance RS on the voltage gain of the amplifier
circuit?
8. Suggest another bias circuit for the JFET and evaluate its performance.
-112-
Appendix-A
Resistor Color Code Chart
- 113 -
This page is left intentionally blank
- 114 -
Appendix-B
Data Sheets for Active Components
-
The small signal silicon diode 1N4148
The general purpose rectifier diode 1N4007
The Zener diode BZX55C5V1
The NPN general purpose transistor 2N3904
The NPN general purpose transistor BC107
The NPN switching transistor 2N2222
The PNP general purpose transistor BC178
The N-Channel JFET transistor 2N3819
- 115 -
This page is left intentionally blank
- 116 -
1N4148 / 1N4150 / 1N4448 / 1N914B
Diodes
Switching diode
1N4148 / 1N4150 / 1N4448 / 1N914B
∗This product is available only outside of Japan.
!External dimensions (Units : mm)
!Applications
High-speed switching
!Features
1) Glass sealed envelope. (GSD)
2) High speed.
3) High reliability.
CATHODE BAND (BLACK)
Type No.
φ 0.5±0.1
C
A
29±1
!Construction
Silicon epitaxial planar
3.8±0.2
φ 1.8±0.2
29±1
ROHM : GSD
EIAJ : −
JEDEC : DO-35
!Absolute maximum ratings (Ta = 25°C)
Type
VRM
(V)
VR
(V)
IFM
(mA)
IO
(mA)
IFSM
1µs
(A)
IF
(mA)
P
(mW)
Tj
(°C)
Topr
(°C)
Tstg
(°C)
1N4148
100
75
450
150
200
2
500
200
−65~+200
−65~+200
1N4150
50
50
600
200
250
4
500
200
−65~+200
−65~+200
1N4448
(1N914B)
100
75
450
150
200
2
500
200
−65~+200
−65~+200
!Electrical characteristics (Ta = 25°C)
VF (V)
Type
@
@
0.1mA 0.25mA
BV (V) Min.
@
@
@
@
@
@
@
1mA
2mA
5mA
10mA
20mA
30mA
50mA
@
@
100mA 200mA 250mA
1N4148
1.0
0.66
0.54
0.76
0.82
0.87
1N4150
0.74
0.62
1N4448
(IN914B)
0.86
0.92
0.62
0.72
@
1.0
The upper figure is the minimum VF and the lower figure is the maximum VF value.
1.0
@
5µA
@
100µA
75
100
−
50
−
100
IR (µA) Max.
@25°C
VR (V)
0.025
20
5.0
75
0.1
50
0.025
20
5.0
75
Cr (pF)
trr (ns)
VR=6V
VR=0
IF=10mA
VR (V) f=1MHz RL=100Ω
@150°C
50.0
20
4
4
100.0
50
2.5
4
50.0
20
4
4
1N4148 / 1N4150 / 1N4448 / 1N914B
Diodes
!Electrical characteristic curves (Ta = 25°C)
REVERSE CURRENT : IR (nA)
20
10
5
2
0.2
0
25°C
Ta=75°C
Ta=25°C
Ta=−25
°C
1
0.5
100°C
3000
Ta=1
FORWARD CURRENT : IF (mA)
50
1000
70°C
300
50°C
100
30
Ta=25°C
10
3
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
20
FORWARD VOLTAGE : VF (V)
40
60
80
100 120
Fig. 2 Reverse characteristics
3
100
SURGE CURRENT : Isurge (A)
VR=6V
Irr=1/10IR
2
1
PULSE
Single pulse
50
20
10
5
2
0
0
10
20
1
0.1
30
FORWARD CURRENT : IF (mA)
10
5Ω
50Ω
SAMPLING
OSCILLOSCOPE
INPUT
100ns
OUTPUT
trr
0.1IR
0
IR
1000
10000
Fig. 5 Surge current characteristics
D.U.T.
PULSE GENERATOR
OUTPUT 50Ω
100
PULSE WIDTH : Tw (ms)
Fig. 4 Reverse recovery time
characteristics
0.01µF
1
Fig. 6 Reverse recovery time (trr) measurement circuit
3.0
f=1MHz
2.5
2.0
1.5
1.0
0.5
0
0
5
10
15
20
25
30
REVERSE VOLTAGE : VR (V)
REVERSE VOLTAGE : VR (V)
Fig. 1 Forward characteristics
REVERSE RECOVERY TIME : trr (ns)
CAPACITANCE BETWEEN TERMINALS : CT (pF)
100
Fig. 3 Capacitance between
terminals characteristics
1N4001-1N4007
1N4001 - 1N4007
Features
•
Low forward voltage drop.
•
High surge current capability.
DO-41
COLOR BAND DENOTES CATHODE
General Purpose Rectifiers (Glass Passivated)
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
4001
4002
4003
4004
4005
4006 4007
50
100
200
400
600
800
VRRM
Peak Repetitive Reverse Voltage
IF(AV)
Average Rectified Forward Current,
.375 " lead length @ TA = 75°C
Non-repetitive Peak Forward Surge
Current
8.3 ms Single Half-Sine-Wave
Storage Temperature Range
-55 to +175
°C
Operating Junction Temperature
-55 to +175
°C
IFSM
Tstg
TJ
1000
V
1.0
A
30
A
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
Thermal Characteristics
Symbol
Parameter
Value
Units
PD
Power Dissipation
3.0
W
RθJA
Thermal Resistance, Junction to Ambient
50
°C/W
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Device
4001
4002
4003
4004
Units
4005
4006 4007
VF
Forward Voltage @ 1.0 A
1.1
V
Irr
Maximum Full Load Reverse Current, Full
Cycle
TA = 75°C
Reverse Current @ rated VR TA = 25°C
TA = 100°C
Total Capacitance
VR = 4.0 V, f = 1.0 MHz
30
µA
5.0
500
µA
µA
pF
IR
CT
2001 Fairchild Semiconductor Corporation
15
1N4001-1N4007, Rev. C
(continued)
1.6
20
1.4
10
1.2
4
Forward Current, IF [A]
Average Rectified Forward Current, IF [A]
Typical Characteristics
1
SINGLE PHASE
HALF WAVE
60HZ
RESISTIVE OR
INDUCTIVE LOAD
.375" 9.0 mm LEAD
LENGTHS
0.8
0.6
0.4
0.2
0
1
0.4
0.2
0.1
0.04
20
40
60
80 100 120 140
Ambient Temperature [ºC]
160
0.01
0.6
180
24
100
Reverse Current, IR [mA]
1000
18
12
6
1
2
4 6 8 10
20
40 60
Number of Cycles at 60Hz
100
Figure 3. Non-Repetitive Surge Current
2001 Fairchild Semiconductor Corporation
0.8
1
1.2
Forward Voltage, VF [V]
1.4
Figure 2. Forward Voltage Characteristics
30
0
T J = 25ºC
µS
Pulse Width = 300µ
2% Duty Cycle
0.02
0
Figure 1. Forward Current Derating Curve
Peak Forward Surge Current, IFSM [A]
2
TJ = 150ºC
10
TJ = 100ºC
1
0.1
0.01
T J = 25ºC
0
20
40
60
80
100 120
140
Percent of Rated Peak Reverse Voltage [%]
Figure 4. Reverse Current vs Reverse Voltage
1N4001-1N4007, Rev. C
1N4001-1N4007
General Purpose Rectifiers (Glass Passivated)
BZX55C 3V3 - BZX55C 33 Series
Discrete POWER & Signal
Technologies
N
BZX55C 3V3 - 33 Series Half Watt Zeners
Absolute Maximum Ratings*
Tolerance: C = 5%
TA = 25°C unless otherwise noted
Parameter
Value
Units
-65 to +200
°C
Maximum Junction Operating Temperature
+ 200
°C
Lead Temperature (1/16” from case for 10 seconds)
+ 230
°C
500
4.0
30
mW
mW/°C
W
Storage Temperature Range
Total Device Dissipation
Derate above 25°C
Surge Power**
*These ratings are limiting values above which the serviceability of the diode may be impaired.
** Non-recurrent square wave PW= 8.3 ms, TA= 50 degrees C.
DO-35
NOTES:
1) These ratings are based on a maximum junction temperature of 200 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed
or low duty cycle operations.
Electrical Characteristics
VZ
Device
BZX55C 3V3
BZX55C 3V6
BZX55C 3V9
BZX55C 4V3
BZX55C 4V7
BZX55C 5V1
BZX55C 5V6
BZX55C 6V2
BZX55C 6V8
BZX55C 7V5
BZX55C 8V2
BZX55C 9V1
BZX55C 10
BZX55C 11
BZX55C 12
BZX55C 13
BZX55C 15
BZX55C 16
BZX55C 18
BZX55C 20
BZX55C 22
BZX55C 24
BZX55C 27
BZX55C 30
BZX55C 33
VF
ZZ
(V)
MIN
MAX
3.1
3.4
3.7
4.0
4.4
4.8
5.2
5.8
6.4
7.0
7.7
8.5
9.4
10.4
11.4
12.4
13.8
15.3
16.8
18.8
20.8
22.8
25.1
28.0
31.0
3.5
3.8
4.1
4.6
5.0
5.4
6.0
6.6
7.2
7.9
8.7
9.6
10.6
11.6
12.7
14.1
15.6
17.1
19.1
21.1
23.3
25.6
28.9
32.0
35.0
Ω)
(Ω
85
85
85
75
60
35
25
10
8.0
7.0
7.0
10
15
20
20
26
30
40
50
55
55
80
80
80
80
@
TA = 25°C unless otherwise noted
IZT
ZZK
(mA)
Ω)
(Ω
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
600
600
600
600
600
550
450
200
150
50
50
50
70
70
90
110
110
170
170
220
220
220
220
220
220
@
IZT
VR
(mA)
(V)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
3.0
5.0
6.2
6.8
7.5
8.2
9.1
10
11
12
13
15
16
18
20
22
24
Foward Voltage = 1.0 V Maximum @ IF = 100 mA for all BZX 55 series
@
IR
µ A)
(µ
2.0
2.0
2.0
1.0
0.5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
@
IR
µ A)
(µ
TA= 150°°C
40
40
40
20
10
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
TC
IZM
(%/°° C)
(mA)
- 0.060
- 0.055
- 0.050
- 0.040
- 0.020
+0.010
+0.025
+0.032
+0.040
+0.045
+0.048
+0.050
+0.055
+0.060
+0.065
0.070
0.070
0.075
0.075
0.080
0.080
0.080
0.085
0.085
0.085
115
105
95
90
85
80
70
64
58
53
47
43
40
36
32
29
27
24
21
20
18
16
14
13
12
This page is left intentionally blank
2N3904 / MMBT3904 / PZT3904
NPN General Purpose Amplifier
Features
• This device is designed as a general purpose amplifier and switch.
• The useful dynamic range extends to 100 mA as a switch and to 100 MHz as an amplifier.
2N3904
PZT3904
MMBT3904
C
C
E
E
TO-92
SOT-23
Absolute Maximum Ratings*
Symbol
Value
Units
40
V
Collector-Base Voltage
60
V
Emitter-Base Voltage
6.0
V
200
mA
-55 to +150
°C
Collector-Emitter Voltage
VCBO
VEBO
IC
B
Ta = 25°C unless otherwise noted
Parameter
VCEO
TJ, Tstg
SOT-223
B
Mark:1A
EBC
C
Collector Current - Continuous
Operating and Storage Junction Temperature Range
* These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle
operations.
Thermal Characteristics
Symbol
PD
Ta = 25°C unless otherwise noted
Max.
Parameter
2N3904
625
5.0
Total Device Dissipation
Derate above 25°C
RθJC
Thermal Resistance, Junction to Case
83.3
RθJA
Thermal Resistance, Junction to Ambient
200
*MMBT3904
350
2.8
**PZT3904
1,000
8.0
357
125
Units
mW
mW/°C
°C/W
°C/W
* Device mounted on FR-4 PCB 1.6" X 1.6" X 0.06".
** Device mounted on FR-4 PCB 36 mm X 18 mm X 1.5 mm; mounting pad for the collector lead min. 6 cm2.
© 2011 Fairchild Semiconductor Corporation
2N3904 / MMBT3904 / PZT3904 Rev. B0
www.fairchildsemi.com
1
2N3904 / MMBT3904 / PZT3904 — NPN General Purpose Amplifier
October 2011
Symbol
Ta = 25°C unless otherwise noted
Parameter
Test Condition
Min.
Max.
Units
OFF CHARACTERISTICS
V(BR)CEO
Collector-Emitter Breakdown Voltage
V(BR)CBO
Collector-Base Breakdown Voltage
V(BR)EBO
Emitter-Base Breakdown Voltage
IBL
ICEX
IC = 1.0mA, IB = 0
40
V
IC = 10μA, IE = 0
60
V
IE = 10μA, IC = 0
6.0
V
Base Cutoff Current
VCE = 30V, VEB = 3V
50
nA
Collector Cutoff Current
VCE = 30V, VEB = 3V
50
nA
ON CHARACTERISTICS*
hFE
DC Current Gain
IC = 0.1mA, VCE = 1.0V
IC = 1.0mA, VCE = 1.0V
IC = 10mA, VCE = 1.0V
IC = 50mA, VCE = 1.0V
IC = 100mA, VCE = 1.0V
40
70
100
60
30
300
VCE(sat)
Collector-Emitter Saturation Voltage
IC = 10mA, IB = 1.0mA
IC = 50mA, IB = 5.0mA
0.2
0.3
V
V
VBE(sat)
Base-Emitter Saturation Voltage
IC = 10mA, IB = 1.0mA
IC = 50mA, IB = 5.0mA
0.65
0.85
0.95
V
V
Current Gain - Bandwidth Product
IC = 10mA, VCE = 20V,
f = 100MHz
300
Cobo
Output Capacitance
VCB = 5.0V, IE = 0,
f = 1.0MHz
4.0
pF
Cibo
Input Capacitance
VEB = 0.5V, IC = 0,
f = 1.0MHz
8.0
pF
NF
Noise Figure
IC = 100μA, VCE = 5.0V,
RS = 1.0kΩ,
f = 10Hz to 15.7kHz
5.0
dB
VCC = 3.0V, VBE = 0.5V
IC = 10mA, IB1 = 1.0mA
35
ns
SMALL SIGNAL CHARACTERISTICS
fT
MHz
SWITCHING CHARACTERISTICS
td
Delay Time
tr
Rise Time
ts
Storage Time
tf
Fall Time
VCC = 3.0V, IC = 10mA,
IB1 = IB2 = 1.0mA
35
ns
200
ns
50
ns
* Pulse Test: Pulse Width ≤ 300μs, Duty Cycle ≤ 2.0%
Ordering Information
Part Number
Marking
Package
Packing Method
Pack Qty
2N3904BU
2N3904
TO-92
BULK
10000
2N3904TA
2N3904
TO-92
AMMO
2000
2N3904TAR
2N3904
TO-92
AMMO
2000
2N3904TF
2N3904
TO-92
TAPE REEL
2000
2N3904TFR
2N3904
TO-92
TAPE REEL
2000
MMBT3904
1A
SOT-23
TAPE REEL
3000
MMBT3904_D87Z
1A
SOT-23
TAPE REEL
10000
PZT3904
3904
SOT-223
TAPE REEL
2500
© 2011 Fairchild Semiconductor Corporation
2N3904 / MMBT3904 / PZT3904 Rev. B0
www.fairchildsemi.com
2
2N3904 / MMBT3904 / PZT3904 — NPN General Purpose Amplifier
Electrical Characteristics
VCESAT- COLLECTOR-EMITTER VOLTAGE (V)
500
V CE = 5V
400
125 °C
300
25 °C
200
- 40 °C
100
0
0.1
1
10
I C - COLLECTOR CURRENT (mA)
100
Base-Emitter Saturation
Voltage vs Collector Current
1
0.8
VBE(ON)- BASE-EMITTER ON VOLTAGE (V)
VBESAT- BASE-EMITTER VOLTAGE (V)
h FE - TYP ICAL PULSED CURRE NT GAIN
Typical Pulsed Current Gain
vs Collector Current
ββ = 10
- 40 °C
25 °C
0.6
125 °C
0.4
0.1
IC
1
10
- COLLECTOR CURRENT (mA)
100
Collector-Emitter Saturation
Voltage vs Collector Current
0.15
125 °C
0.1
25 °C
0.05
- 40 °C
0.1
1
VCE = 5V
0.8
- 40 °C
25 °C
0.6
125 °C
0.4
0.2
0.1
1
10
I C - COLLECTOR CURRENT (mA)
100
10
f = 1.0 MHz
VCB = 30V
CAPACITANCE (pF)
ICBO- COLLECTOR CURRENT (nA)
100
Capacitance vs
Reverse Bias Voltage
500
10
1
0.1
25
1
10
I C - COLLECTOR CURRENT (mA)
Base-Emitter ON Voltage vs
Collector Current
Collector-Cutoff Current
vs Ambient Temperature
100
ββ = 10
50
75
100
125
TA - AMBIENT TEMPERATURE ( °C)
4
3
C ibo
2
C obo
1
0.1
150
© 2011 Fairchild Semiconductor Corporation
2N3904 / MMBT3904 / PZT3904 Rev. B0
5
1
10
REVERSE BIAS VOLTAGE (V)
100
www.fairchildsemi.com
3
2N3904 / MMBT3904 / PZT3904 — NPN General Purpose Amplifier
Typical Performance Characteristics
Noise Figure vs Source Resistance
Noise Figure vs Frequency
12
I C = 1.0 mA
R S = 200ΩΩ
10
V CE = 5.0V
I C = 1.0 mA
NF - NOISE FIGURE (dB)
NF - NOISE FIGURE (dB)
12
μA
I C = 50 μA
R S = 1.0 kΩ
kΩ
8
I C = 0.5 mA
R S = 200ΩΩ
6
4
2
μA, R S = 500 Ω
I C = 100 μA
Ω
0
0.1
1
10
f - FREQUENCY (kHz)
10
I C = 5.0 mA
6
μA
I C = 100 μA
4
2
0
0.1
100
V CE = 40V
I C = 10 mA
PD - POWER DISSIPATION (W)
- CURRENT GAIN (dB)
fe
h
θθ
10
100
f - FREQUENCY (MHz)
1000
SOT-223
0.75
TO-92
0.5
SOT-23
0.25
0
0
Turn-On Time vs Collector Current
500
I B1 = I B2 =
VCC = 40V
10
t r - RISE TIME (ns)
TIME (nS)
15V
2.0V
10
10
I C - COLLECTOR CURRENT (mA)
100
150
I B1 = I B2 =
Ic
10
T J = 25°C
T J = 125°C
5
100
© 2011 Fairchild Semiconductor Corporation
2N3904 / MMBT3904 / PZT3904 Rev. B0
125
10
t d @ VCB = 0V
1
50
75
100
TEMPERATURE (o C)
Rise Time vs Collector Current
t r @ V CC = 3.0V
5
25
500
Ic
40V
100
100
1
θθ - DEGREES
0
20
40
60
80
100
120
140
160
180
h fe
1
1
10
kΩ) )
R S - SOURCE RESISTANCE ((kΩ
Power Dissipation vs
Ambient Temperature
Current Gain and Phase Angle
vs Frequency
50
45
40
35
30
25
20
15
10
5
0
μA
I C = 50 μA
8
1
10
I C - COLLECTOR CURRENT (mA)
100
www.fairchildsemi.com
4
2N3904 / MMBT3904 / PZT3904 — NPN General Purpose Amplifier
Typical Performance Characteristics (continued)
Storage Time vs Collector Current
I B1 = I B2 =
T J = 25°C
Fall Time vs Collector Current
500
Ic
I B1 = I B2 =
10
t f - FALL TIME (ns)
t S - STORAGE TIME (ns)
500
100
T J = 125°C
10
5
T J = 125°C
100
T J = 25°C
1
10
I C - COLLECTOR CURRENT (mA)
5
100
1
10
I C - COLLECTOR CURRENT (mA)
Current Gain
V CE = 10 V
f = 1.0 kHz
T A = 25oC
100
10
0.1
1
I C - COLLECTOR CURRENT (mA)
1
1
I C - COLLECTOR CURRENT (mA)
10
© 2011 Fairchild Semiconductor Corporation
2N3904 / MMBT3904 / PZT3904 Rev. B0
V CE = 10 V
f = 1.0 kHz
T A = 25oC
10
1
0.1
1
I C - COLLECTOR CURRENT (mA)
10
Voltage Feedback Ratio
)
_4
h re - VOLTAGE FEEDBACK RATIO (x10
V CE = 10 V
f = 1.0 kHz
T A = 25oC
10
0.1
0.1
100
10
Input Impedance
100
100
Output Admittance
μmhos)
h oe - OUTPUT ADMITTANCE ( μnhos
h fe - CURRENT GAIN
VCC = 40V
10
500
(kΩ)
Ω)
h ie - INPUT IMPEDANCE (k
Ic
10
10
7
V CE = 10 V
f = 1.0 kHz
T A = 25oC
5
4
3
2
1
0.1
1
I C - COLLECTOR CURRENT (mA)
10
www.fairchildsemi.com
5
2N3904 / MMBT3904 / PZT3904 — NPN General Purpose Amplifier
Typical Performance Characteristics (continued)
2N3904 / MMBT3904 / PZT3904 — NPN General Purpose Amplifier
Test Circuits
3.0 V
275 ΩΩ
300ns
300
ns
10.6 V
Duty Cycle == 2%
kΩ
Ω
10 KΩ
0
C1 << 4.0pF
4.0 pF
- 0.5 V
1.0 ns
<< 1.0ns
FIGURE 1: Delay and Rise Time Equivalent Test Circuit
3.0 V
10
500500
μs μs
10 <<t1 t<1 <
t1
Ω
275 Ω
10.9 V
Duty Cycle == 2%
kΩ
Ω
10 KΩ
0
< 4.0pF
C1 <
4.0 pF
1N916
- 9.1 V
<< 1.0ns
1.0 ns
FIGURE 2: Storage and Fall Time Equivalent Test Circuit
© 2011 Fairchild Semiconductor Corporation
2N3904 / MMBT3904 / PZT3904 Rev. B0
www.fairchildsemi.com
6
BC107
BC108
BC109
MECHANICAL DATA
Dimensions in mm (inches)
GENERAL PURPOSE
SMALL SIGNAL
NPN BIPOLAR TRANSISTOR
5.84 (0.230)
5.31 (0.209)
12.7 (0.500)
min.
5.33 (0.210)
4.32 (0.170)
4.95 (0.195)
4.52 (0.178)
0.48 (0.019)
0.41 (0.016)
dia.
FEATURES
• SILICON NPN
• HERMETICALLY SEALED TO18
2.54 (0.100)
Nom.
• SCREENING OPTIONS AVAILABLE
3
1
2
TO–18 METAL PACKAGE
Underside View
PIN 1 – Emitter
PIN 2 – Base
PIN 3 – Collector
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise stated)
VCBO
VCEO
Collector – Base Continuous Voltage
BC017
50V
BC108, BC109
30V
Collector – Emitter Continuous Voltage With Zero Base Current BC107
45V
BC108, BC109
VCES
VEBO
20V
Collector – Emitter Continuous Voltage With Base Shortcircuited to Emitter
Emitter – Base Continuous Voltage Reverse Voltage
BC107
50V
BC108, BC109
30V
BC107
6V
BC108, BC109
5V
IC
Continuous Collector Current
100mA
ICM
Peak Collector Current
200mA
Ptot
Power Dissipation @ Tamb = 25°C
300mW
Tamb
Ambient Operating Temperature Range
-65 to +175°C
Tstg
Storage Temperature Range
-65 to +175°C
Semelab plc.
Telephone +44(0)1455 556565. Fax +44(0)1455 552612. e-mail [email protected]
Website http://www.semelab.co.uk
3/99
BC107
BC108
BC109
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated)
Parameter
Typ.
Max. Unit
BC107
15
VCB = 25V
BC108, BC109
15
Collector-Emitter Leakage Current
VCB = 45V
BC107
4
@Tamb =125°C
VCB = 25V
BC108, BC109
4
Emitter Cut-off Current
VEB = 4V
IC = 0
1
VCE = 5V
IC = 2mA
Group A
BC107, BC108
110
220
Group B
All Types
180
460
Group C
BC108, BC109
380
800
BC107
110
460
BC108
110
800
BC109
180
800
Collector-Base Leakage Current
ICBO(1)
h21E
Min.
VCB = 45V
ICBO(1)
IEBO
Test Conditions
Static Forward Current Transfer Ratio
nA
µA
µA
VBE
Base – Emitter Breakdown
VCE = 5V
IC = 2mA
0.7
V
VBE(sat)(1)
Base – Emitter Saturation Voltage
IB = 0.5mA
IC = 10mA
0.83
V
VCE(sat)(1)
Collector – Emitter Saturation Voltage
IB = 0.5mA
IC = 10mA
0.25
V
fT
Transition Frequency
VCE = 5V
IC = 10mA
f = 100MHz
VCE = 5V
F
Noise Factor
MHz
150
IC = 0.2mA
R = 2kΩ f =1kHz ∆F=200Hz
BC109
4
BC107, BC108
10
dB
VCE = 5V IC = 2mA f =100kHz
BC107, BC108
125
260
Small Signal Forward Current Transfer Group B
All Types
240
500
Ratio
BC108, BC109
450
900
BC107
125
500
BC108
125
900
BC109
240
900
Group A
h21e
Group C
VCE = 5V IC = 2mA f = 1kHz
h11e
Common Emitter Input Impedance
Group A
BC107, BC108
1.6
4.5
Group B
All Types
3.2
8.5
Group C
BC108, BC109
6.0
15
kΩ
VCE = 5V IC = 2mA f = 1kHz
h22e
Common Emitter Output Admittance
C22b
Common Base Output Capacitance
Rth(j-amb)
Thermal Resistance: Junction to
Group A
BC107, BC108
30
Group B
All Types
60
Group C
BC108, BC109
110
VCB = 10V
f = 1MHz
Ambient
Semelab plc.
Telephone +44(0)1455 556565. Fax +44(0)1455 552612. e-mail [email protected]
Website http://www.semelab.co.uk
µS
6
pF
500
°C/W
3/99
DISCRETE SEMICONDUCTORS
DATA SHEET
M3D125
2N2222; 2N2222A
NPN switching transistors
Product specification
Supersedes data of September 1994
File under Discrete Semiconductors, SC04
1997 May 29
Philips Semiconductors
Product specification
NPN switching transistors
2N2222; 2N2222A
FEATURES
PINNING
• High current (max. 800 mA)
PIN
• Low voltage (max. 40 V).
APPLICATIONS
DESCRIPTION
1
emitter
2
base
3
collector, connected to case
• Linear amplification and switching.
DESCRIPTION
3
handbook, halfpage
1
2
NPN switching transistor in a TO-18 metal package.
PNP complement: 2N2907A.
2
3
MAM264
1
Fig.1 Simplified outline (TO-18) and symbol.
QUICK REFERENCE DATA
SYMBOL
VCBO
PARAMETER
collector-base voltage
CONDITIONS
60
V
−
75
V
2N2222
−
30
V
2N2222A
−
40
V
−
800
mA
Tamb ≤ 25 °C
−
500
mW
75
−
250
−
MHz
300
−
MHz
−
250
ns
collector-emitter voltage
open base
IC
collector current (DC)
Ptot
total power dissipation
hFE
DC current gain
IC = 10 mA; VCE = 10 V
fT
transition frequency
IC = 20 mA; VCE = 20 V; f = 100 MHz
2N2222
2N2222A
turn-off time
1997 May 29
UNIT
−
2N2222A
toff
MAX.
open emitter
2N2222
VCEO
MIN.
ICon = 150 mA; IBon = 15 mA; IBoff = −15 mA
2
Philips Semiconductors
Product specification
NPN switching transistors
2N2222; 2N2222A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCBO
VCEO
VEBO
PARAMETER
collector-base voltage
CONDITIONS
MIN.
MAX.
UNIT
open emitter
2N2222
−
60
V
2N2222A
−
75
V
2N2222
−
30
V
2N2222A
−
40
V
2N2222
−
5
V
2N2222A
−
6
V
collector-emitter voltage
emitter-base voltage
open base
open collector
IC
collector current (DC)
−
800
mA
ICM
peak collector current
−
800
mA
IBM
peak base current
−
200
mA
Ptot
total power dissipation
Tamb ≤ 25 °C
−
500
mW
Tcase ≤ 25 °C
−
1.2
W
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
200
°C
Tamb
operating ambient temperature
−65
+150
°C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth j-a
thermal resistance from junction to ambient
Rth j-c
thermal resistance from junction to case
1997 May 29
CONDITIONS
in free air
3
VALUE
UNIT
350
K/W
146
K/W
Philips Semiconductors
Product specification
NPN switching transistors
2N2222; 2N2222A
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
ICBO
PARAMETER
IEBO
emitter cut-off current
hFE
DC current gain
VCEsat
−
10
nA
IE = 0; VCB = 50 V; Tamb = 150 °C
−
10
µA
IE = 0; VCB = 60 V
−
10
nA
IE = 0; VCB = 60 V; Tamb = 150 °C
−
10
µA
IC = 0; VEB = 3 V
−
10
nA
IC = 0.1 mA; VCE = 10 V
35
−
IC = 1 mA; VCE = 10 V
50
−
IC = 10 mA; VCE = 10 V
75
−
IC = 150 mA; VCE = 1 V; note 1
50
−
IC = 150 mA; VCE = 10 V; note 1
100
300
35
−
2N2222
30
−
2N2222A
40
−
IC = 150 mA; IB = 15 mA; note 1
−
400
mV
IC = 500 mA; IB = 50 mA; note 1
−
1.6
V
IC = 150 mA; IB = 15 mA; note 1
−
300
mV
IC = 500 mA; IB = 50 mA; note 1
−
1
V
IC = 150 mA; IB = 15 mA; note 1
−
1.3
V
IC = 500 mA; IB = 50 mA; note 1
−
2.6
V
IC = 150 mA; IB = 15 mA; note 1
0.6
1.2
V
IC = 500 mA; IB = 50 mA; note 1
−
2
V
−
8
pF
−
25
pF
2N2222
250
−
MHz
2N2222A
300
−
MHz
−
4
dB
DC current gain
DC current gain
IC = 10 mA; VCE = 10 V; Tamb = −55 °C
collector-emitter saturation voltage
2N2222A
VBEsat
base-emitter saturation voltage
2N2222
VBEsat
IC = 500 mA; VCE = 10 V; note 1
collector-emitter saturation voltage
2N2222
VCEsat
base-emitter saturation voltage
2N2222A
Cc
collector capacitance
IE = ie = 0; VCB = 10 V; f = 1 MHz
Ce
emitter capacitance
IC = ic = 0; VEB = 500 mV; f = 1 MHz
2N2222A
fT
F
UNIT
IE = 0; VCB = 50 V
2N2222A
hFE
MAX.
collector cut-off current
2N2222A
hFE
MIN.
collector cut-off current
2N2222
ICBO
CONDITIONS
transition frequency
noise figure
2N2222A
1997 May 29
IC = 20 mA; VCE = 20 V; f = 100 MHz
IC = 200 µA; VCE = 5 V; RS = 2 kΩ;
f = 1 kHz; B = 200 Hz
4
Philips Semiconductors
Product specification
NPN switching transistors
SYMBOL
2N2222; 2N2222A
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Switching times (between 10% and 90% levels); see Fig.2
ton
turn-on time
ICon = 150 mA; IBon = 15 mA; IBoff = −15 mA −
35
ns
td
delay time
−
10
ns
tr
rise time
−
25
ns
toff
turn-off time
−
250
ns
ts
storage time
−
200
ns
tf
fall time
−
60
ns
Note
1. Pulse test: tp ≤ 300 µs; δ ≤ 0.02.
VBB
ndbook, full pagewidth
VCC
RB
RC
Vo
(probe)
oscilloscope
450 Ω
(probe)
450 Ω
R2
Vi
DUT
R1
MLB826
Vi = 9.5 V; T = 500 µs; tp = 10 µs; tr = tf ≤ 3 ns.
R1 = 68 Ω; R2 = 325 Ω; RB = 325 Ω; RC = 160 Ω.
VBB = −3.5 V; VCC = 29.5 V.
Oscilloscope input impedance Zi = 50 Ω.
Fig.2 Test circuit for switching times.
1997 May 29
5
oscilloscope
Philips Semiconductors
Product specification
NPN switching transistors
2N2222; 2N2222A
PACKAGE OUTLINE
Metal-can cylindrical single-ended package; 3 leads
SOT18/13
α
j
seating plane
B
w M A M B M
1
b
k
D1
2
3
a
D
A
A
0
5
L
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
a
b
D
D1
j
k
L
w
α
mm
5.31
4.74
2.54
0.47
0.41
5.45
5.30
4.70
4.55
1.03
0.94
1.1
0.9
15.0
12.7
0.40
45°
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT18/13
B11/C7 type 3
TO-18
1997 May 29
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-04-18
6
BC177-BC178-B179
THERMAL DATA
R t h j- cas e
R t h j -amb
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Ma x
Ma x
°C/W
°C/W
200
500
ELECTRICAL CHARACTERISTICS (T amb = 25 °C unless otherwise specified)
Symbol
Parameter
I CE S
Collector Cutoff Current
(V BE = 0)
V CE = – 20 V
V CE = – 20 V
Collector-emitter
Breakdown Voltage
(I B = 0)
I C = – 2 mA
Collector-emitter
Breakdown Voltage
(V BE = 0)
I C = – 10 µA
V (B R)E BO
Emitter-base
Breakdown Voltage
(I C = 0)
I E = – 10 µA
V CE( sat )*
Collector-emitter
Saturation Voltage
I C = – 10 mA
I C = – 100 mA
I B = – 0.5 mA
I B = – 5 mA
Base-emitter Voltage
I C = – 2 mA
V CE = – 5 V
Base-emitter
Saturation Voltage
I C = – 10 mA
I C = – 100 mA
I B = – 0.5 mA
I B = – 5 mA
Small Signal
Current Gain
I C = – 2 mA
f = 1 kHz
V CE = – 5 V
V (BR)CE O *
V (B R)CES
VB E *
V BE (s at )
hfe
Test Conditions
2/6
Typ.
Max.
Unit
– 1
– 100
– 10
nA
µA
T amb = 150 °C
for BC177
for BC178
for BC179
– 45
– 25
– 20
V
V
V
for BC177
for BC178
for BC179
– 50
– 30
– 25
V
V
V
–5
V
for
for
for
for
for
* Pulsed : pulsed duration = 300 µs, duty cycle = 1 %.
Min.
BC177
BC177
BC178
BC178
BC179
Gr. A
Gr. B
Gr. A
Gr. B
Gr. B
– 550
– 75
– 200
– 250
mV
mV
– 640
– 750
mV
– 720
– 860
125
240
125
240
240
mV
mV
260
500
260
500
500
BC177-BC178-BC179
ELECTRICAL CHARACTERISTICS (continued)
Symbol
fT
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Transition Frequency
I C = – 10 mA
f = 100 MHz
V CE = – 5 V
200
MHz
C CBO
Collector-base
Capacitance
IE = 0
V CB = – 10 V
5.0
pF
NF
Noise Figure
I C = – 0.2 mA
R g = 2 kΩ
B = 200 Hz
V CE = – 5 V
f = 1 kHz
for BC177
for BC178
for BC179
h ie
Input Impedance
I C = – 2 mA
f = 1 kHz
Reverse Voltage Ratio
I C = – 2 mA
f = 1 kHz
Output Admittance
I C = – 2 mA
f = 1 kHz
BC177
BC177
BC178
BC178
BC179
Gr. A
Gr. B
Gr. A
Gr. B
Gr. B
2.7
5.2
2.7
5.2
5.2
kΩ
kΩ
kΩ
kΩ
kΩ
BC177
BC177
BC178
BC178
BC179
Gr. A
Gr. B
Gr. A
Gr. B
Gr. B
2.7x10– 4
4.5x10– 4
2.7x10– 4
4.5x10– 4
4.5x10– 4
V CE = – 5 V
for
for
for
for
for
DC Transconductance.
dB
dB
dB
V CE = – 5 V
for
for
for
for
for
hoe
10
10
4
V CE = – 5 V
for
for
for
for
for
hre
2
2
1.2
BC177
BC177
BC178
BC178
BC179
Gr. A
Gr. B
Gr. A
Gr. B
Gr. B
25
35
25
35
35
µS
µS
µS
µS
µS
DC Normalized Current Gain.
3/6
BC177-BC178-B179
Collector-emitter Saturation Voltage.
Normalized h Parameters.
Normalized h Parameters.
Collector-base Capacitance.
Transition Frequency.
Power Rating Chart.
4/6
2N3819
Vishay Siliconix
N-Channel JFET
PRODUCT SUMMARY
VGS(off) (V)
V(BR)GSS Min (V)
gfs Min (mS)
IDSS Min (mA)
v –8
–25
2
2
FEATURES
BENEFITS
APPLICATIONS
D Excellent High-Frequency Gain:
Gps 11 dB @ 400 MHz
D Very Low Noise: 3 dB @ 400 MHz
D Very Low Distortion
D High ac/dc Switch Off-Isolation
D High Gain: AV = 60 @ 100 mA
D
D
D
D
D
D
D
D
D
Wideband High Gain
Very High System Sensitivity
High Quality of Amplification
High-Speed Switching Capability
High Low-Level Signal Amplification
High-Frequency Amplifier/Mixer
Oscillator
Sample-and-Hold
Very Low Capacitance Switches
DESCRIPTION
The 2N3819 is a low-cost, all-purpose JFET which offers good
performance at mid-to-high frequencies. It features low noise
and leakage and guarantees high gain at 100 MHz.
Its TO-226AA (TO-92) package is compatible with various
tape-and-reel options for automated assembly (see
Packaging Information). For similar products in TO-206AF
(TO-72) and TO-236 (SOT-23) packages, see the
2N4416/2N4416A/SST4416 data sheet.
TO-226AA
(TO-92)
S
1
G
2
D
3
Top View
ABSOLUTE MAXIMUM RATINGS
Gate-Source/Gate-Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Lead Temperature (1/16” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C
Forward Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Power Dissipationa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mW
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C
Document Number: 70238
S–04028—Rev. D ,04-Jun-01
Notes
a. Derate 2.8 mW/_C above 25_C
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2N3819
Vishay Siliconix
SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)
Limits
Parameter
Symbol
Test Conditions
Min
Typa
V(BR)GSS
IG = –1 mA , VDS = 0 V
–25
–35
VGS(off)
VDS = 15 V, ID = 2 nA
Max
Unit
Static
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Saturation Drain Currentb
IDSS
Gate Reverse Current
VDS = 15 V, VGS = 0 V
IGSS
Gate Operating Currentc
Drain Cutoff Current
Drain-Source On-Resistance
Gate-Source Voltage
Gate-Source Forward Voltage
2
VGS = –15 V, VDS = 0 V
TA = 100_C
–8
10
20
mA
–0.002
–2
nA
–0.002
–2
mA
IG
VDG = 10 V, ID = 1 mA
–20
ID(off)
VDS = 10 V, VGS = –8 V
2
rDS(on)
VGS = 0 V, ID = 1 mA
VGS
VDS = 15 V, ID = 200 mA
VGS(F)
IG = 1 mA , VDS = 0 V
V
–3
pA
W
150
–0.5
–2.5
–7.5
V
0.7
Dynamic
Common-Source Forward Transconductancec
gfs
Common-Source Output Conductancec
gos
Common-Source Input Capacitance
Ciss
Common-Source Reverse Transfer Capacitance
Crss
Equivalent Input Noise Voltagec
VDS = 15 V
VGS = 0 V
f = 1 kHz
2
5.5
f = 100 MHz
1.6
5.5
f = 1 kHz
VDS = 15 V, VGS = 0 V, f = 1 MHz
en
VDS = 10 V, VGS = 0 V, f = 100 Hz
6.5
mS
25
50
2.2
8
0.7
4
mS
pF
nV⁄
√Hz
6
Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
b. Pulse test: PW v300 ms, duty cycle v2%.
c. This parameter not registered with JEDEC.
NH
TYPICAL CHARACTERISTICS (TA = 25_C UNLESS OTHERWISE NOTED)
Drain Current and Transconductance
vs. Gate-Source Cutoff Voltage
On-Resistance and Output Conductance
vs. Gate-Source Cutoff Voltage
10
8
6
gfs
12
4
8
IDSS @ VDS = 15 V, VGS = 0 V
gfs @ VDS = 15 V, VGS = 0 V
f = 1 kHz
4
2
0
0
0
–2
–4
–6
–8
VGS(off) – Gate-Source Cutoff Voltage (V)
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7-2
–10
rDS(on) – Drain-Source On-Resistance ( Ω )
16
100
rDS @ ID = 1 mA, VGS = 0 V
gos @ VDS = 10 V, VGS = 0 V
f = 1 kHz
400
80
rDS
300
60
gos
200
40
100
20
0
gos – Output Conductance (mS)
IDSS
500
gfs – Forward Transconductance (mS)
IDSS – Saturation Drain Current (mA)
20
0
0
–2
–4
–6
–8
–10
VGS(off) – Gate-Source Cutoff Voltage (V)
Document Number: 70238
S–04028—Rev. D ,04-Jun-01
2N3819
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25_C UNLESS OTHERWISE NOTED)
Common-Source Forward Transconductance
vs. Drain Current
Gate Leakage Current
100 nA
10
5 mA
VGS(off) = –3 V
gfs – Forward Transconductance (mS)
1 mA
10 nA
IG – Gate Leakage
0.1 mA
1 nA
TA = 125_C
IGSS @
125_C
100 pA
5 mA
1 mA
10 pA
0.1 mA
TA = 25_C
1 pA
IGSS @ 25_C
0.1 pA
8
TA = –55_C
6
25_C
4
125_C
2
0
0
10
20
0.1
1
VDG – Drain-Gate Voltage (V)
10
ID – Drain Current (mA)
Output Characteristics
Output Characteristics
15
10
VGS(off) = –2 V
VGS(off) = –3 V
12
8
VGS = 0 V
6
ID – Drain Current (mA)
ID – Drain Current (mA)
VDS = 10 V
f = 1 kHz
–0.2 V
–0.4 V
4
–0.6 V
–0.8 V
2
–1.0 V
–1.2 V
0
–1.4 V
VGS = 0 V
–0.3 V
9
–0.6 V
–0.9 V
6
–1.2 V
–1.5 V
3
–1.8 V
2
0
4
6
8
0
2
0
10
VDS – Drain-Source Voltage (V)
4
6
8
10
VDS – Drain-Source Voltage (V)
Transfer Characteristics
Transfer Characteristics
10
10
VGS(off) = –2 V
VDS = 10 V
VGS(off) = –3 V
VDS = 10 V
8
8
ID – Drain Current (mA)
ID – Drain Current (mA)
TA = –55_C
TA = –55_C
25_C
6
125_C
4
25_C
6
125_C
4
2
2
0
0
0
–0.4
–0.8
–1.2
–1.6
VGS – Gate-Source Voltage (V)
Document Number: 70238
S–04028—Rev. D ,04-Jun-01
–2
0
–0.6
–1.2
–1.8
–2.4
–3
VGS – Gate-Source Voltage (V)
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2N3819
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25_C UNLESS OTHERWISE NOTED)
Transconductance vs. Gate-Source Voltage
Transconductance vs. Gate-Source Voltgage
10
10
VDS = 10 V
f = 1 kHz
VGS(off) = –3 V
8
gfs – Forward Transconductance (mS)
gfs – Forward Transconductance (mS)
VGS(off) = –2 V
TA = –55_C
6
25_C
4
125_C
2
0
8
TA = –55_C
6
25_C
4
125_C
2
0
0
–0.4
–0.8
–1.2
–1.6
–2
0
On-Resistance vs. Drain Current
–2.4
–3
Circuit Voltage Gain vs. Drain Current
100
TA = –55_C
g fs R L
AV + 1 ) R g
L os
Assume VDD = 15 V, VDS = 5 V
80
240
VGS(off) = –2 V
AV – Voltage Gain
rDS(on) – Drain-Source On-Resistance ( Ω )
–1.8
VGS – Gate-Source Voltage (V)
300
180
–3 V
120
RL +
60
10 V
ID
VGS(off) = –2 V
40
60
20
0
0
–3 V
0.1
1
10
0.1
1
10
ID – Drain Current (mA)
ID – Drain Current (mA)
Common-Source Input Capacitance
vs. Gate-Source Voltage
Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage
5
3.0
Crss – Reverse Feedback Capacitance (pF)
f = 1 MHz
4
Ciss – Input Capacitance (pF)
–1.2
–0.6
VGS – Gate-Source Voltage (V)
VDS = 0 V
3
2
VDS = 10 V
1
0
f = 1 MHz
2.4
1.8
VDS = 0 V
1.2
VDS = 10 V
0.6
0
0
–4
–8
–12
–16
VGS – Gate-Source Voltage (V)
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7-4
VDS = 10 V
f = 1 kHz
–20
0
–4
–8
–12
–16
–20
VGS – Gate-Source Voltage (V)
Document Number: 70238
S–04028—Rev. D ,04-Jun-01
2N3819
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25_C UNLESS OTHERWISE NOTED)
Input Admittance
Forward Admittance
100
100
TA = 25_C
VDS = 15 V
VGS = 0 V
Common Source
TA = 25_C
VDS = 15 V
VGS = 0 V
Common Source
bis
10
10
gfs
(mS)
(mS)
gis
1
–bis
1
0.1
100
200
500
0.1
100
1000
f – Frequency (MHz)
1000
Output Admittance
10
TA = 25_C
VDS = 15 V
VGS = 0 V
Common Source
500
f – Frequency (MHz)
Reverse Admittance
10
200
–brs
TA = 25_C
VDS = 15 V
VGS = 0 V
Common Source
bos
1
gos
(mS)
(mS)
1
–grs
0.1
0.1
0.01
100
200
500
0.01
100
1000
f – Frequency (MHz)
Equivalent Input Noise Voltage vs. Frequency
1000
Output Conductance vs. Drain Current
20
VDS = 10 V
VGS(off) = –3 V
gos – Output Conductance (mS)
VGS(off) = –3 V
Hz
500
f – Frequency (MHz)
20
en – Noise Voltage nV /
200
16
12
8
ID = 5 mA
4
VDS = 10 V
f = 1 kHz
16
TA = –55_C
12
25_C
8
125_C
4
ID = IDSS
0
10
100
1k
f – Frequency (Hz)
Document Number: 70238
S–04028—Rev. D ,04-Jun-01
10 k
100 k
0
0.1
1
10
ID – Drain Current (mA)
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7-5
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