Towards picosecond time measurement
using fast analog memories
D.Breton & J.Maalmi (LAL Orsay), E.Delagnes (CEA/IRFU)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Summary
1.
Using fast analog memories for precise
time measurement [D. Breton].
2.
The WaveCatcher module : description and
performances. Comparison with high-end
standard electronics for MCPPMT
characterization (NIM paper) [J. Maalmi].
3.
New SCA circuits and ongoing
developments by IRFU/LAL team [D. Breton
for E. Delagnes].
4.
Developments towards large scale
implementation of analog memories for
precise time measurement [D. Breton].
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Using fast analog memories for precise
time measurement.
Dominique Breton
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Introduction
• We have been developing electronics for high energy physics for more
than 25 years ( at least for me … ), and working on analog memories for
18 years.
• But we also use high-end ADCs in our developments, wherever really
necessary
• In the spirit of this workshop, our goal is to find solutions to perform as
precise as possible time measurements at the lowest cost and power
consumption, in order to be able to build large scale systems
• We will try to describe the problematics in a general way, and to
introduce why analog memories seem to us to be good candidates for
designing solutions
• We will tell you where we are and where we want to go …
• We feel like presenting as many interesting results as possible
=> this is helpful for the characterization of our circuits and boards
=> it pulls our capacity to make progress
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
About TDCs …
•
Existing electronics for time measurement is mostly
based on Time to Digital Converters (TDC).
A TDC converts the arrival time of a binary signal into
digital value.
It is characterized by :
–
–
–
–
•
Its time step and its main clock frequency
Its effective resolution (which can be very different from time step)
Its dead-time and its mean maximum hit rate
Its number of channels
Very few products on the market, mostly dedicated to LHC
–
–
–
•
HPTDC from CERN => 25ps & 40MHz
TDC-GPX from ACAM => 8 channels, 80ps & 40MHz
There is an important demand for time of flight measurement in the medical
community
As announced in Clermont, we are currently developping a 16-channel
generic circuit (SCATS) with high counting rate capability and very simple
way of use:
–
160MHz clock (130-200), 200ps step, resolution of 70ps, data-push (triggerless),
up to 5 MHz counting rate for all channels,
input dead time < 50ns
–
Low power, very cheap (CMOS 0.35µm)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
State of the art: TDC
•
TDC with voltage ramp:
=> best solution for precision
– Time resolution: ~ 10 ps
– Usually used with a Wilkinson ADC for power and
simplicity reasons
=> limited by dead time which can be a problem for
high rate experiments
•
TDC with digital counters and Delay Line Loops
(DLL):
=> advantage: produces directly the encoded
digital value but limited by delay line step
- Time resolution of today’s most advanced ASICs: ~
25 ps
BUT a TDC needs a binary input signal
 analog input signal has to be translated to digital with a discriminator
 overall timing resolution is given by the quadratic sum of the discrimator and TDC
timing resolutions
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
State of the art: CFD (1)
• To feed the TDC, one needs to transform analog pulse into digital without jitter
=> this is commonly done with a Constant Fraction Discriminator (CFD)
• Indeed, a simple threshold method introduces Time Walk which depends on the signal
amplitude
• Time can be corrected but this implies implementing the measurement of the amplitude in
addition to that of the time
A1
V
V
A2
k x A1
Fixed threshold
relative threshold :
constant fraction
of the peak!
A3
k x A2
k x A3
t
t
Δt : time walk
Δt ~ 0
 in order to remove the time walk, threshold has to be set as a constant fraction of the
amplitude
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
State of the art: CFD (2)
• The drawing below describes how to produce a digital edge at a constant fraction
of an analog pulse
=> the implementation with analog electronics looks easy at first order
A Δ
V
S(t)
S(t- Δ)
S(t- Δ) > k .S(t)
Δ S(t- Δ) +
k
Δ
k x S(t)
comp
t
• Difficulty:
• Delay has to be adjusted to pulse rise-time
• Ratio has to be adjusted to maximum slope
 both Δ and k have to be programmable
And …
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
-
S(t)
kxA
State of the art: CFD (3)
• Moreover, in order to avoid triggering on the noise, the system has to be armed
by a first threshold
=> the easiest implementation with analog electronics: zero crossing method
A
V
S(t)
Δ
S(t- Δ)
S(t- Δ) – k.S(t) > 0
S(t- Δ) – k x S(t)
k x S(t)
t
Arming threshold
k
-
kxA
Δ S(t- Δ) +
k x S(t) Σ
+
comp
-
S(t)
Arming threshold
Zero-crossing instant
• Problem : one cannot implement a pure delay line in an ASIC.
=> delay is usually made of:
• cascaded R-C cells => signal is deformed
• or specific shaping => very sensitive to pulse shape
• There is always some remaining dependence on transit time to amplitude
>> Time resolution of ASICs based on CFD/TDC solution : > 30 ps rms
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
State of the art: digitization
• Extraction of the time can be performed thanks to a digital
treatment of the digitized signal.
• Different types of algorithms can be used
• A simple and still very performing solution is a digital CFD (see
Jihane’s talk)
 Analog to Digital Converters :
• Sampling rate up to 3 GS/s
• Huge output data rate and power consumption
• Need of high-end FPGAs
• High total cost
• In order to get a good resolution :
– Unique data path or need to know which one was used
– Good SNR
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
About ADCs …
•
An ADC converts an instantaneous voltage into digital value.
It is characterized by:
BGA
–
Its signal bandwidth
292 pins
–
Its sampling frequency
24x1,8Gbits/s
–
Its number of bits (converted / effective)
–
Collateral dammages :
Their package, consumed power, output data rate !
•
The most powerful products on the market:
•
•
•
•
–
–
8bits => 3GS/s, 1,9 W => 24Gbits/s,
10 bits => 3GS/s, 3,6 W => 30Gbits/s
12 bits => 3,6GS/s, 4,1 W => 43,2Gbits/s
14 bits => 400MS/s, 2,5 W => 5,6Gbits/s
=> appearance of integrated circular buffers (limited by technology)
Big companies are experts => our only potential benefit to design ADCs
is to integrate them within more complex circuits
The simplest and least power consuming: ramp ADCs (Wilkinson) but
they are slow => not adapted to high counting rates
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
About ADC boards …
• Designing a board with an ADC producing tens of Gbits/s is a huge effort
– High-end FPGAs have to be used
– If one wants to record some time depth, banks of DDR3 RAMs have to be
used
• A few companies started the exercise
• These boards are expensive (5 to 40 k$) and house very few channels
(the most often 2 sharing the ADC and thus the GS/s)
• This is perfect for very high precision and very little scale, and for
systems where dead-time before digitization is critical
• This is more a problem for high scale and low power …
• Moreover, very fast ADC often use parallelized architecture, which is not
good for signal uniformity …
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Some ADC boards … (1)
PX1500-4: 3 GSPS 8-bit ADC and Virtex-5 Processing PCI Express 8x Module
ADC10D1500RB: a Low-Power, 10-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter Reference Board
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Some ADC boards … (2)
ADC12D1800RB: 12-Bit, Dual 1.8 GSPS or Single 3.6 GSPS A/D Converter Reference Board
XMC-1151: 3.2 GSPS 12-bit ADC and Virtex-6 Processing XMC PCI Express Module
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Some ADC boards … (3)
XMC-1151: 56 GSPS 8-bit dual ADC for 40G/100G communications systems
The ultimate !
Pb: different possible paths for data
 need for calibration
 need for knowledge of which path
was used
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Why Analog Memories ?
• Analog memories actually look like perfect candidates for high precision
time measurements at high scale:
– Like ADCs they catch the signal waveform (this can also be very useful for
debug)
– There is no need for precise discriminators
– TDC is built-in (position in the memory gives the time)
– Only the useful information is digitized (vs ADCs) => low power
– Any type of digital processing can be used
– Only a few samples/hit are necessary => this limits the dead time
– Simultaneous write/read operation is feasible, which may further reduces
the dead time if necessary
• But they have to be carefully designed to reach the necessary level of
performance …
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Short history of the Orsay/Saclay SCA Developments
• The story begins in 1992 with the design of the first prototype of the Switched
Capacitor Array (SCA) for the ATLAS LARG calorimeter. After 10 years of
development, the main final characteristics of this rad-hard circuit were:
HAMAC
• 12 pseudo-differential channels
• 40 MHz sampling
• 13.6-bit dynamic range with simultaneous write/read
• 80000 chips produced in 2002 and mounted on the detector.
• Since 2002, 3 new generations of fast samplers have been
•designed (ARS, MATACQ, SAM): total of more than 30000 chips in use.
• Our design philosophy:
1. Maximize dynamic range and minimize signal distorsion.
2. Minimize need for calibrations and off-chip data corrections.
3. Minimize costs (both for development & production):
• Use of inexpensive pure CMOS technologies (0.8µm then 0.35µm);
• Use of packaged chips (cheap QFP).
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
The Sampling Matrix Structure: main features
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Reminder of recording principle.
• Clock virtually multiplied by 16 inside the chip.
• Sampling Frequency servo-controlled inside the chip => no sensitivity to
temperature & process variation.
• Used as a circular buffer .
• Area of interest readout:
– Starting from Trigger cell (marked by trailing edge of the run signal) +
programmable offset.
• Total readout also possible.
• Read Cell index available.
• Low dead time due to readout
(<100ns / sample).
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Main Common design options (1):
• High dynamic range => 4-switch memory cells:
• Voltage-mode writing.
• Floating voltage-mode reading with read amplifier.
 Gain and pedestal spread insensitive to capacitor mismatches.
• Sequencing of S1-S2 switch opening.
 Sampling time very well defined and independent of signal amplitude.
Write Bus
v
Top Read Bus
N capacitors
V1=V
Q=Cs.V
1
2
1
Return Bus
Bottom Read
BUS
Vout=A / (1+A) * Q/Cs
=V1 * A/(1+A)
4
Cs
3
N
capacitors
• Use of analog input buffer (voltage follower):
• Keeps the real input impedance very high to avoid signal distortion
• Penalty in power consumption and bandwidth.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Main Common design options (2):
• Relatively high value of storage capacitance (200fF to 1pF):
• minimize both kt/C and readout noise.
• Use of differential channels:
• Coupling and noise rejection.
• Low signal distortion.
• Easier interface with modern commercial ADCs.
• Use of internally servo-controlled Delay Lines (DLL) to define the time steps:
• No need for timing calibration for standard applications.
• Stability with time and temperature.
• With on-chip phase detector and charge pump, fast setup time for the
servo-control is possible => sampling DLL
16
16
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Variable BW along the SCA.
Amplifier
bandwidth
Line
bandwidth + delay
Analog in
Cell own
bandwidth
• Analog Bus is a RC delay line:
 delay depends on the sampling cell position.
 the overall bandwidth also, especially if it is not limited by an
input amplifier or that of the intrinsic sampling cell.
• Short analog busses are better for BW uniformity => segmentation into
parallel lines
=> much less distorsion
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Advantages/ Drawbacks of the Sampling MATRIX structure
• Short DLL:
–
–
–
smallest jitter.
junction between DLLs.
potential coupling between Analog Signal and DLL control voltage.
• 1 servo control of Delay / Col: => high stability.
• Analog Input Buffering:
–
–
–
High input impedance:
• Linearity.
• No DC input current
• No Ringing. Flat response
Power consumption.
BW limitation
• Analog Bus split into divisions: lines
–
shortest analog bus :
• More uniform bandwidth.
• less analog delay along the bus.
– Parallel readout => faster readout.
– 1 buffer / line :
• Better analog BW/power consumption FOM.
• Spread of the buffer bandwidth.
• Offset between lines (corrected by DAC on-chip).
• Initial Philosophy: No Off-chip correction (pedestal, amplitude, time) => limit external computing.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Fix Pattern Apperture Jitter
Device Mismatches of components in the delay chain :
=> spread of delay duration.
=> dispersion of the sampling time.
=> fix for a given tap => Fixed Pattern Apperture Jitter
• Spread of single delays => time DNL.
• Cumulative effect => time INL.
• Systematic effect => easy correction if cell index is known
Drawbacks: potential computing power + non equidistant samples (FFT).
=> good calibration required (see Jihane’s talk).
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Jitter vs DLL length
2 sources of aperture jitter in the DLL:
• Random aperture jitter (RAJ).
• Fixed Pattern Aperture Jitter (FPJ).
• Inside the DLL jitters are cumulative. Assuming there is no correlation:
• For RAJ, the aperture jitter @ tap j will be
s Rj 
• For FPJ
j .s Rd if sRd is the random jitter added by a delay tap
s FPj 
s FPj 
j .s FPd
j .( N  j )
N
for a free running system
if the total delay is servo-controlled
.s FPd
if sFPd is the random jitter added by a delay tap (sDNL) and N is the DL length.
Short DL => Less Jitter (both kinds)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
The SAM (Swift Analog Memory) chip
• This chip was first designed for HESS2 experiment:
a big Athmospheric Cerenkov Telescope
located in the Namibia desert.
• 2 differential channels
• 256 cells per channel
• BW > 250 MHz
• Sampling Freq: 700MHz-2.5GHz
• High Readout Speed >16 MHz
• Smart Read pointer (integrate a 1/Fs
step TDC)
• Few external signals
• Many modes configurable by a serial
link.
• Auto-configuration @ power on
• Low cost for medium size prod=>
AMS 0.35 µm
NIM A, Volume 567, Issue 1, p. 21-26, 2006
6000 ASICs delivered in Q2 2007, yield of 95%.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Most recent results: bandwith spread in the memory
• The analog signal lines inside the chip act as delay lines with some attenuation
 this mainly affects high frequencies.
• The resulting pattern is the sum of:
– a modulo 16 pattern linked to the routing of the signal input and of the input buffer
supplies => will be improved on next chips
– a long range V-like shape linked to memory line attenuation
• This affects the timing very little, but mostly the time calibration … (see
Jihane’s talk)
1% @ 309 MHz
3% @ 309 MHz
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Summary of performances of the SAM chip.
NAME
SAM
Unit
Power Consumption
300
mW
Sampling Freq. Range
> 3.2
GS/s
Analog Bandwidth – Full Range (2.5V)
– 300 mV pp
450
530
MHz
Read Out time for whole chip (2 x 256 cells)
< 30
µs
Fixed Pattern noise
0.4
mV rms
Total noise (constant with frequency)
0.65
mV rms
Maximum signal
2 x 2.5
V
Dynamic Range
12.6
bits
Crosstalk
<3
per mil
Relative non linearity
<1
%
Equivalent sampling Jitter – without time correction
– with time correction
~ 20
~ 10
ps rms
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
The WaveCatcher module : description and
performances.
Comparison with high-end standard electronics
for MCPPMT characterization (NIM paper).
Jihane Maalmi
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
The USB Wave Catcher board V5
Reference clock:
200MHz => 3.2GS/s
Pulsers for reflectometry applications
1.5 GHz BW
amplifier.
Board has to be USB powered
=> power consumption < 2.5W
480Mbits/s USB interface
µ USB
Trigger
input
2 analog
inputs.
DC
Coupled.
Clock
input
Trigger
output
+5V
Jack
plug
Trigger
discriminators
SAM Chip
Dual 12-bit ADC
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Cyclone FPGA
Board Special Features
 Possibility to add a individual DC offset on each signal
 Individual trigger threshold on each channel
 External and internal trigger + numerous modes of triggering on
coïncidence (11 possibilities including two pulses on the same
channel => useful for afterpulse studies
 Embedded charge mode (integration starts on threshold or at a
fixed location) => high rates (~ 3.5 kEvents/s)
 Pulse generators for reflectometry applications
 External clock input for multi-board applications (see
Dominique’s talk)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
5 versions of the board since sept 2008 …
V2
V1
V6 is on its way …
V5
V3
V4
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
What are the jitter sources that affect the
time measurement precision at the
board level ?
 Board design
 Analog Memory
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Jitter sources
Jitter sources are :
1.
Noise : depends on the bandwidth of the system
 converts into jitter with the signal slope
2.
Sampling jitter : due to clock Jitter and to mismatches of elements in the
delay chain.
=> induces dispersion of delay durations
2.1 Random fluctuations : Random Aperture Jitter(RAJ)
- Clock Jitter + Delay Line
2.2 Fixed pattern fluctuations : Fixed Pattern Jitter(FPJ)
=> systematic error in the sampling time
=> can be corrected thanks to an original method based on a simple
70MHz/1.4Vp-p sinewave (10,000 events => ~ 1.5 min/ch)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Jitter induced by electronics noise
Simplified approach
Noise
Zoom
Time
slope = 2ЛAf3db
tr ~ 1/(3 f3db)
Jitter
Time
Jitter [ps] ~ Noise[mV] / Signal Slope [mV/ps] ~ tr / SNR
Ex: the slope of a 100mV - 500MHz sinewave gets a jitter of ~2ps rms from a noise of 0.6mV rms
Conclusions:
 The higher the SNR, the better for the measurement
 A higher bandwidth favours a higher precision (goes with its square root).
 But: for a given signal, it is necessary to adapt the bandwidth of the measurement
system to that of the signal in order to keep the noise-correlated jitter as low as
possible
 Designs become tricky for ultra fast signals with a bandwidth > 1GHz …
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
How to minimize the clock Jitter?
Block diagram of clock distribution on the board
Clean power supply
FPGA
OSC
(200MHz)
Fe=3.2GHz
Div
CPT1
Div/N
USB
interface
(~ 20MHz)
CPT2
Div/M
Sync_reset
SAM
Choice of buffers and duty cycles
also are important…
N = 11
M = 21
ADC
clock
(~ 10MHz)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Delay Line correlated Jitter
16
16
There are 2 types of jitter correlated to the Delay Line length :
 Random Aperture Jitter (RAJ) : we cannot correct it
 Fixed Pattern aperture Jitter (FPJ) => if we can measure it we can correct it!
Reminder: the way to reduce both of these jitters it is to have
short and servo-controlled DL
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Effects of the Fixed Pattern Jitter
• Dispersion of single delays => time DNL
• Cumulative effect => time INL. Gets worse with delay line length.
• Systematic & fixed effect => non equidistant samples (bad for FFT) =>
Time Base Distortion
We can measure it => we can correct it !
Δt[cell]
Real signal
Fake signal
After interpolation
In a Matrix
system, DNL is
mainly due to
signal splitting
into lines =>
modulo 16 pattern
if 16 lines
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
How can we calibrate the Time Based
Distortion or INL due to this Fixed
Pattern Jitter?
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Time calibration
Method: search of zero-crossing segments of a sine wave => length[position]
 Length[position] is proportional to time step duration assuming that:
• sine wave is a straight line (bias ~ 2ps rms).
Sine wave characteristics: 70MHz -1.4Vpp
 Higher frequency => may be bothered by slew rate
 Lower frequency => lower slope => more jitter because of noise
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Jitter calibration method
Histogram of Length[position]:
Mean_Length[position]: Fixed Pattern => DNL after integration => INL
i 1
IN L  i   (  M ea n _ L en g th  k   i  M ea n ) 
k 0
Ts
M ea n
Sigma_Length[position]: Random effect => Random Jitter
1.95ps rms
Clock jitter
7.5ps rms
DLL jitter
DNL
Random jitter
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Jitter calibration
DNL
Integration
Raw INL
16.9ps rms
7.5ps rms
=> correction with polynomial interpolation to recover equidistant samples
Re-Calibration
after correction
1.5ps rms
The INL correction is stable over a
long period of time (months …)
=>
INL values are constants and stored in
the on-board EEPROM!!
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
How time INL translates into jitter in distance measurement …
INL [ps]
Time error vs position in the memory
Open DL
ε2max
Servo-controlled DLL
ε1max
ε2min
Δt2
Time [ns]
Δt1
Position in the memory
ε1min
ε1 = 0
ε = error in distance measurement
• Peak-to-peak jitter for Δt1 is ε1max - ε1min
• Peak-to-peak jitter for Δt2 is ε2max – ε2min >> Δt1
•
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Effects of time non-linearity.
• Effects of time DNL and INL on time measurements might be misunderstood.
• When measuring the time difference between two close pulses with a an analog
memory, these effects really depend on the memory structure.
• For instance, if one sends a set of two pulses asynchronous (a fortiori
synchronous) with the memory clock) with a constant and short delay (zero or a
few ns), the jitter will be mainly due to the variations in the local DNL along the
few consecutive cells involved in each measurement. But the effect of the local
value of the INL will be mostly masked.
This means that jitter will depend on the distance between pulses
In order to fully characterize an analog memory to be used as a TDC, it is thus
necessary to perform the measurement with pulses randomly located in the
memory and to plot all the possible distances between them.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Setup used for characterizing the WaveCatcher
board for time measurement
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Description of the setup
For the least jitter at short distance …
Open cable
USB Wave
Catcher
USB Wave
Catcher
Two pulses on the same channel
Two pulses on different channels
=> with this setup, we can measure precisely the time difference between the pulses
independently of the timing characteristics of the generator!
For other distances :
* Two pulses generated with a programmable
distance
USB Wave
Catcher
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Pulses on the same channel : Method
• Source: asynchronous pulse summed with itself reflected at the end of an open cable.
• Time difference between the two pulses extracted by crossing of a fixed threshold
determined by polynomial interpolation of the 4 neighboring points (on 3000 events).
Δt ~ 11ns
σ=
Vth
10.9ps rms
Δt ~ 21ns
σ=
Vth
11.4ps rms
σΔt ~ 11ps rms => jitter for a single pulse 11/√2 ~ 8 ps !
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Pulses on different channels : CFD method
• Source: asynhronous pulse sent to the two channels with cables of different lengths or
via a generator with programmable distance.
• Time difference between the two pulses extracted by CFD method.
• Threshold determined by polynomial interpolation of the neighboring points.
Spline, extraction of the baseline, and normalization
Threshold interpolation
Ratio to peak
0.23
0.23
Time
σΔt ~ 10ps rms
jitter for each pulse ~ 10/√2 ~ 7 ps !
Other method used: Chi2 algorithm based on reference pulses.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
9.64ps rms
Time measurement results : Example with Δt ~ 0
WaveCatcher V4 : 2 pulses with Tr = Tf = 1.6ns and FWHM = 5ns
Distance between pulses : Δt ~ 0
Differential jitter = 4.61ps => sampling jitter ~ 3 ps
4.61ps rms
All matrix positions are hit!
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Jitter vs Time distance between two pulses
• Source: randomly distributed set of two positive pulses
• Results are the same with negative pulses or distance between
arches of a sine wave
Differential jitter between 2 pulses
with and without INL correction
40
Differential jitter [ps rms]
35
30
25
WaveCatcher V4 without INL correction
20
WaveCatcher V4 with INL corrected
15
10
5
0
0
10
20
30
40
50
Distance between pulses [ns]
60
70
Jitter distribution after INL correction is almost flat => coherent with INL shape
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Effect of CFD ratio on time precision
WaveCatcher V4 : 2 pulses withTr = Tf = 1.6ns and FWHM = 5ns
-Δt ~ 0 ns, - Δt ~ 10ns, - Δt ~ 20 ns
Differential jitter in relation with CFD ratio
20
18
Differential jitter [ps]
16
14
12
Delta t = 0
10
Delta t = 10 ns
Delta t = 20 ns
8
6
4
2
0
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
CFD ratio
Optimum value : corresponds to the maximum slope of the pulse!!
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
CVI acquisition software with GUI
This software can be downloaded on the LAL web site at the following URL:
http://electronique.lal.in2p3.fr/echanges/USBWaveCatcher/
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Window for time measurements
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Characterization of 10µm- MCPPMT with the
WaveCatcher Board
Comparison with high-end standard
electronics (NIM paper).
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Fermilab beam test
To test the adequation of 10µm MCPPMTs for time of flight measurements
Conditions: ~40pe and low gain (2-3 104)
Beam
Raw CFD
measurement
CFD with
walk correction
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
SLAC laser test
Same conditions as for Fermilab test:
40pe and low gain (2-3 104)
WaveCatcher Board
100Hz
Tektronix oscilloscope
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Two timing methods used
(a) Software CFD method:
(b) Reference pulse method :
Average pulse shape used for
the reference timing 2 algorithm
(black is average, red shows
± 2 s contour).
• The first analysis step was to perform a spline interpolation of the waveform, which
worked with either 1ps or 10ps time bins (in the end it was determined that 10ps binning
is sufficient). Then two timing methods were used:
• (a) One is a software CFD timing method, which consists of normalizing the pulses to the
same peak amplitude and using a constant-fraction threshold, usually set to 18-22% of the
peak amplitude.
• (b) The second one, a reference timing method, in which one determines first a reference
pulse shape. The pulse time is then determined by stepping through a chosen reference
pulse, and calculating a 2 using a certain number of time bins.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
57
Comparison of both methods
Fig.1: Reference pulses - fits to leading edge
(a) TOF 1
(b) TOF 2
Fig.2: Search for 2-minimum
Fig.3: CFD vs. Reference timing
Reference method:
CFD method:
• One can use, for example, a second order
polynomial to fit only the leading edge of the
average pulse profile for normalized pulses
(see Fig.1). Fig.2 shows (a) the 2 values as a
function of the time step, and (b) resulting
time distributions correspond to a 2minimum.
• Figs. 3a&b show the final timing results for
both (a) the reference timing method and (b)
the CFD method.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
58
SLAC test summary
Sampling
period!
From this we could conclude that applying a very simple algorithm, which is very simple
to integrate in a FPGA (finding a maximum & linear interpolation between two samples,
i.e., without a use of the Spline fit) already gives very good results (only 10% higher than
the best possible resolution limit).
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
SLAC test summary
Summary of all the test results
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
NIM paper has been accepted in November
Abstract: … There is a considerable
interest to develop new time-of-flight
detectors using, for example, microchannel-plate
photodetectors
(MCPPMTs). The question we pose in this
paper is if new waveform digitizer ASICs,
such as the WaveCatcher and TARGET,
operating with a sampling rate of 2-3
GSa/s can compete with 1GHz BW
CFD/TDC/ADC electronics ...
…
Conclusion: … The fact that we found
waveform digitizing electronics capable
of measuring timing resolutions similar to
that of the best commercially-available
Ortec CDF/TAC/ADC electronics is, we
believe, a very significant result. It will
help to advance the TOF technique in
future.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Conclusion
• The USB Wave Catcher has become a useful demonstrator for the use of matrix analog
memories in the field of ps time measurement.
• Lab timing measurements showed a stable single pulse resolution < 10 ps rms
• We hope to reach 5ps in the next timing-optimized chip (0.18µm)
• The board has been tested with MCPPMT’s for low-jitter light to time conversion
• Results confirm previous measurements with 40 photo electrons
• CFD and Chi2 algorithm give almost the same time resolution:
• Double pulse resolution ~ 23 ps => single pulse resolution ~ 16 ps
• Even the simplest CFD algorithm can give a good timing resolution
• Single pulse resolution < 18 ps
• It can be easily implemented inside an FPGA (our next step)
 Bandwidth, sampling frequency and SNR are the three key factors which have to be
adequately defined depending on the signals to measure (hard with very short signals)
 The memory structure has to be carefully chosen and designed to get a stable INL
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Summary of the WaveCatcher performances.
• 2 DC-coupled 256-deep channels with 50-Ohm active input impedance
• ±1.25V dynamic Range, with full range 16-bit individual tunable offsets
• 2 individual pulse generators for test and reflectometry applications.
• On-board charge integration calculation.
SiPM multiple photon
• Bandwidth > 500MHz
charge spectrum
• Signal/noise ratio: 11.8 bits rms
(noise = 650 µV RMS)
• Sampling Frequency: 400MS/s to 3.2GS/s
• Max consumption on +5V: 0.5A
5
• Absolute time precision in a channel (typical):
• without INL calibration:
<18ps rms (3.2GS/s)
• after INL calibration
<10ps rms (3.2GS/s)
• Relative time precision between channels: <5ps rms.
• Trigger source: software, external, internal, threshold on signals
• Acquisition rate (full events)
Up to ~1.5 kHz over 2 full channels
• Acquisition rate (charge mode)
Up to ~40 kHz over 2 channels
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
1
New SCA circuits and ongoing developments
by IRFU/LAL team.
Dominique Breton for Eric Delagnes
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Introduction
• SAM was a great demonstrator for precision time measurement.
• But in parallel there was a need for longer depth analog memories
– First a chip like SAM with 1024 cells and compatible with the WaveCatcher board:
SAMLONG. This chip would also include:
– a ramp TDC (“vernier”) for tagging the trigger arrival time (like in our former
MATACQ chip).
• New input buffers (slew rate, power)
• New readout amplifiers (noise)
• Output multiplexor (single ADC)
• Internal programmable posttrig
• Target: same performances as SAM but with less power (was 300mW / 2ch)
– Then the same chip embedding a 12-bit ADC for the CTA experiment: NECTAR0.
• Both chips were submitted in the same run (April 2010)
 SAMLONG was mounted on a WaveCatcher V4 and tested immediatly !
 NECTAR0 test board is now ready …
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
NECTAR0/SAMLONG block diagram
In SAMLONG Chip
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
NECTAR0/SAMLONG chip submission
• CMOS AMS 0.35µm technology, 3.3V supply.
• SAMLONG: 3x6 mm² chip size ,TQFP 100 (0.4mm pitch) package.
• NECTAR0: 3x7 mm² chip size ,TQFP 128 (0.4mm pitch) package.
• Both submitted in April 2010 in an engineering run also including other chips
from IRFU.
• Back from foundry in July 2010.
• SAMLONG: 150 chips already
packaged in TQFP 100
• NECTAR0: 100 chips available –
10 packaged in ceramic.
• Masks are available for larger
production.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
New features tested on SAMLONG.
Status
New Slow Control registers
Extension to 1024 cells
=> Fixed pattern noise:
(could be degraded by depth increase)
=> Raw Sampling Aperture Jitter:
OK
OK: for 400MSs<=Fs<=3.2GSs.
(25 MHz<=Fw<=200MHz)
OK= 0.35mV as in SAM.
=>No cell by cell calibration required
< 18 ps rms
(could be degraded by depth increase)
Postrig: (was fixed to 48 cells for SAM, now
OK below 2.5 GS/s
programmable from 32 to 1024 by step of 16)
Vernier: (on chip analog TDC measuring the
phase between Stop & Clk, allows to retime
accurately asynchronous pulses)
< 25ps rms
(not useful for CTA but useful for tests)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
New features tested on SAMLONG (cont).
Status
New LVDS drivers:
(true LVDS with
enable + programmable current)
New Read Amplifiers and
Reset (to avoid increase of noise
OK
OK => noise = 0.6 mV rms including FPN (=
SAM’s noise)
due to increase of depth)
ADC Multiplexor
OK => Same Crosstalk with or without
(<0.3%)
Integrated power pulsing.
(R/O part disconnect during writing
and vice versa)
OK => No difference of performances with or
without:
Chip power consumption = input amplifier
power + (10.Fs(GS/s)) mW.
Input Buffer => (power
consumption diminution although the
capacitance to drive has increased.
Class AB structure + autobias )
OK (see later).
No ghost pulses
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Chip Bandwidth (with sinewaves)
• No overshoot. Very stable response
• Large signal BW remains high even for large
signals.
• Contribution of board buffers also included.
• Power consumption tunable by a an external
resistor => effect on the frequency response.
• 2 bias conditions studied :
– 211mW / 450 MHz: « Nominal »
– 122mW / 374 MHz: «Low Power »
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
SAMLONG (nominal bias, 2.5 GS/s) vs 600MHz BW/10GS/s Scope)
• Single shot data taken from scope and merged with SAMLONG data using theoretical
signal gain
• No time calibration. No correction (pedestal is equalized only by the internal line DACs).
Large Signal
Small signal
zoom
Fall time (10-90)
Gene: 900ps
Scope: 1.1 ns
SAMLONG: 1.2ns
zoom
Fall time (10-90)
Gene: 900ps
Scope: 1.1 ns
SAMLONG: 1.2ns
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
« Quasi-static performances » (using previous pulses)
• Baseline set to 1.8V.
• Input pulse varied using programmable
attenuators.
• Amplitude measured using ONE sample on
the flat top (@ fixed time)
• 200 acquisitions => average.
Relative quasi-static non linearity < 0.4%
• Q = sum of N consecutive samples on the
flat top.
• Sigma ~ constant on the full range
(contribution from generator for large
amplitudes)
• Resolution scales as N1/2 as expected (no
strong correlation of noise between samples).
• Noise = 0.7 mV rms (with generator
connected)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Test with PM-like pulses
PM-like pulse « C »:
FWHM = 2.5ns
Trise(10-90) = 1.5ns
Ttrail(90-10) = 2.5ns
Waveforms with SAMLONG & Scope
~ identical.
• Low Xtalk = 0.15% in amplitude
• Even less in charge
(ch1 differential inputs connected
together during this measurement
while injecting in ch0)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Charge resolution & linearity with PM-like pulses
saturation
saturation
Dominated
by noise
Relative charge resolution better than
1% rms for amplitude > 100mV
Relative Non-linearity < 3%
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Bandwidth effects on SAMLONG
• Like in SAM, the analog signal lines inside the chip act as delay lines with
some attenuation
- SAMLONG is 4 times longer.
• The resulting pattern is the sum of:
– a modulo 16 pattern linked to the routing of the signal input and of the input
buffer supplies => worse than SAM but ~ understood
– a V-like shape linked to memory line attenuation (same slope as SAM)
• This pleads for rather short lines …
4% @ 309 MHz
6% @ 309 MHz
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Correcting time INL of SAMLONG
• Like for SAM, we tried to estimate the time INL in order to correct it to get the best
possible time precision
- But SAMLONG is 4 times longer.
• Applying directly the same method as for SAM does not work:
– Indeed, integrating the DNL over long distance produces divergences
– Moreover, the effect of bandwidth reduction along the chip becomes non
negligible
• It was shown that compensating the reduction of the segment length by using
groups of 4 columns gives the best result in term of equivalent jitter …
111.8 ps rms
Example of 2 pulses
separated by ~ 18 ns
16 group of
4 columns
1 group of
64 columns
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
11.62 ps rms
Time performances of SAMLONG
Differential jitter with SAMLONG chip
30
Mean differential jitter
without INL correction
is of only 25ps rms
which corresponds to
18ps rms of sampling
jitter despite the factor
4 in length!
But once corrected we
still have 12.5 ps rms
…
Differential jitter [ps rms]
25
20
15
10
With INL correction
5
Delayed with cables
Without INL correction
0
0
50
100
150
200
250
300
350
Distance between pulses [ns]
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Comparison of SAM and SAMLONG
Comparison of short distance differential jitter between SAM
and SAMLONG chip
20
Mean differential jitter
is of about 15ps rms
for SAMLONG where
it was ~ 11 ps for SAM
 should be the same
(?)
 we still have to
work to understand …
Differential jitter [ps rms]
18
16
14
12
10
8
6
WaveCatcher V4 with SAMLONG
4
WaveCatcher V4 with SAM
2
0
0
10
20
30
40
50
60
70
Distance between pulses [ns]
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Summary of Performances
NAME
SAM
Nectar0
(targeted)
SAMLONG
(measured)
Unit
Power Consumption
300
150-300
160-250
mW
<1to 2.5
(3.2)
1 to 3.2GS/s
0.4 to 3.2GS/s
GS/s
250-300
(450MHz)
300 MHz
>350
MHz
< 1.5
<2
<2
µs
0.35
mV rms
<0.8mV
0.65
(0.55mV if FPN
cancelled)
mV rms
2
(4)
2V
2V (ADC limited)
V
>11.6
(12.6)
>11.3
>11.6
bits
Crosstalk
<3
<3
<3
per mil
Relative non linearity
<1
<3
<3
%
Sampling Jitter
<15
<50
<35
ps rms
Sampling Freq. Range
Analog Bandwidth
Read Out time for a 16 cell event
(2 gains 1- cells)
Fixed Pattern noise
0.4
Total noise (constant with
frequency)
0.65
Maximum signal (limited by ADC
range)
Dynamic Range
(0.5mV if
FPN
cancelled)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Conclusion
• Nectar0 and SAMLONG chip received. SAMLONG was tested.
• Performances of SAMLONG >= performances of SAM with lower
power consumption (2/3 or ½).
• No bad surprise (unstability, ghost pulses, strange behaviours)
• As with SAM: no need of complicated calibration for normal use.
• Test with on chip ADC will start soon.
• SAM wasn’t actually optimized for time measurement
• SAMLONG => careful design of the layout of the analog inputs and
of the propagation delay in the signal lines
• Despite that, SAM performs better and it is logical because it is a
short circuit and the long distance non linearities are thus smaller
• For the same reason, we had to review our time calibration method
because there is a problem with long circuits due to error accumulation
=> there is still a progression margin …
• Pattern modulo 16 can really be improved at the layout level
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
R&D with smaller technology
• SAM and SAMLONG are of course limited in frequency by the 0.35µm technology
• We have been collaborating to the design of a new circuit in the IBM 130nm technology
with our colleagues of the University of Chicago and follow their progress with interest
• Their goal is to try to improve the time precision thanks to analog memories sampling
at very high frequency (target is 20GS/s).
• We would like to soon start the design a new TDC based on the following scheme, where
the usual DLL-based TDC structure is boosted by analog memories sampling at high
frequencies
• We think of using therefore a 0.18µm CMOS technology
Critical path
for time
measurement
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
External
Future work
It looks like the following elements are the key for long-term stable high time precision:
• Short and servo-controlled DLLs
• Perfectly differential coupling between all internal signals and DLL control voltage,
especially when the latter has a large bandwidth
• Avoiding any memory effect of previous samplings on the signal busses
 Other elements are helpful:
• Optimized routing of signal lines looking for isochronicity in order to reduce the DNL
 It looks like there is no need to push the bandwidth too far because noise goes with it, and
SNR is a key factor of the jitter.
• Sampling rate goes with it (a factor 10 to BW looks fine. Ex: 500MHz and 5GS/s)
 Beginning of 2011, we will submit an improved version of SAMLONG for production
Then the short 2-channel version of SAM re-optimized for time measurement
Then the same with an integrated derandomizer in order to drastically reduce the dead-time
This chip will handle simultaneous write and read.
We will integrate a discriminator in order to define the zone of interest inside the chip
We watch the arrival of the CMOS 0.18µm from AMS to still improve the performances
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Developments towards large scale
implementation of analog memories for
precise time measurement.
Dominique Breton
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Introduction
For the two-bar TOF test at SLAC, we decided to build a
synchronous sixteen channel acquisition system based on 8
two-channel WaveCatcher V5 boards:
1. The system has to work with a common synchronous
clock

There we take benefit of the external clock input of the
WaveCatcher V5
2. It is self-triggered but it also has to be synchronized with
the rest of the CRT

Rate of cosmics is low thus computer time tagging of events is
adequate (if all computers are finely synchronized)
3. Like the WaveCatcher, data acquisition is based on
480Mbits/s USB.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Experimental setup
Faraday cage
16 SMA connectors
To
amplifiers
PM-side harness
Patch panel
Trigger for
the electronics crate
(QTZ3)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
PM-side harness
All the lines between the MCP anodes
and the cable inputs are 14.7mm long
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Electronics setup
USB hub
From
QTZ3
8
16 amplifiers
Patch panel
36dB
Amp
36dB
Amp
CH0
CH0
CH0
CH0
CH0
CH0
CH0
CH0
CH1
CH1
CH1
CH1
CH1
CH1
CH1
CH1
USB
USB
USB
USB
USB
USB
USB
USB
Clk in
Clk in
Clk in
Clk in
Clk in
Clk in
Clk in
Clk in
USB
Ext trig out
Ext trig in
Trig
Trigout
in Trig
Trigout
in Trig
Trigout
in Trig
Trigout
in Trig
Trigout
in Trig
Trigout
in Trig
Trigout
in Trig
Trigout
in
Trig out Trig out Trig out Trig out Trig out Trig out Trig out Trig out
36dB
Amp
36dB
Amp
8 USB WaveCatcher V5
8
8
Clk out
Trig out
Trig in
Clock and control board
DAQ PC
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
8
87
MITEQ amplifier
Model: AM-1687-1000
Input and output connector: SMA
Frequency Minimum
1 MHz
Frequency Max
1000 MHz
Electrical Specifications
Gain Minimum
Gain Flatness
Noise Figure
36 dB
0.75 dB+/3.3 dB
Voltage 1 (Nominal)
Current 1 (Nominal)
Impedance
15 V
150 mA
50 Ohms
Price:
Per /1
Per /16
435 Euros
400 Euros
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Clock and control board (1)
From WaveCatchers
To WaveCatchers
From QTZ3
CRT mode : when the controller board detects a coincidence between an
external trigger from QTZ3 and one of the sixteen channels, it sends
through USB a specific interrupt to the PC in order to start the data
readout.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Clock and control board (2)
USB interface
=> 480Mbits/s
Zero jitter clock buffer
Clock outputs Trig outputs
µ USB
Trigger
Input (NIM)
Trigger
Output (NIM)
+5V
Jack
plug
Pulse
output
Cyclone FPGA
Trig inputs
Reference clock:
200MHz
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Tests at lab
• Technical challenge: to keep the 10ps precision at the crate level
• Logistical challenge: to have a running system mounted at SLAC the
13th of September
– The controller board was designed end of June
– Production of 10 WaveCatchers V5 was launched at the same time
– A first small system with 4 channels was mounted and succesfully tested at
CERN mid July on new high speed MRPCs
• Time measurements showed that even between different boards,
the 10ps rms time precicion was still there.
• The full crate was assembled at LAL end of August.
– We had a very little time to test it because of the shipping delay
– Difficulties appeared to be mostly linked to USB because of the high
number of slaves (7 is a key number for USB)
• We were lucky to get the amplifiers on time (they left LAL the 6th
and arrived at SLAC the 9th after visiting Sacramento!)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
4-channel prototype
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Full crate
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Back of the crate
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Comments about electronics
• Baseline uses sixteen individual 36 dB amplifiers but a solution with a
board housing 16 amplifiers with programmable gain is under study
– It could be used for the second step based on SL10
– This would anyhow be a very nice item on the shelf
• Common trigger for the WaveCatcher boards is the signal produced
by QTZ3:
– This will stop the signal recording into the analog memory
– but readout is performed only if at least one of the two-bar channels were
hit (done through a OR of the individual triggers on signal)
• Upon each event, the acquisition software adds the event time in the
data file
– => synchronization of events with the CRT µPC
– time is regularly (once per minute) synchronized with SLAC time server
(as µPC also does) via NTP time server.
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Setup at SLAC
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
The whole system
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Acquisition software
• WaveCatcher software was extended to 16 channels
– Each board can be set up independently
– All channels can be displayed simultaneously
– Run data can be split into multiple fixed size files (based on the user
defined number of events) => permits run survey
– A log file stores all messages generated during acquisition.
• Now available: real time histogramming of inter-channel pulse time
difference
• With the laptop we use at SLAC, there was no way to run all the 9
boards on the same USB port
– => we had to share the boards between the 3 ports
– Once the acquisition launched, USB looks stable (we can take very long
runs => one week)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
MultiWaveCatcher Main Panel
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
MultiWaveCatcher: Board Panel
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Setup with computer
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Running conditions
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
One cosmic event
• Recycled 6U crate
• Naked WaveCatchers
mounted on 3U carrier boards
For the experiment current results, see Leonid’s talk …
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
MCPPMT test bench at LAL
• In view of SuperB PID TOF, we decided to mount a high
speed PMT/SiPM test facility at LAL.
• Thus we started building a second crate
– Same as that of SLAC except that the WaveCatcher boards now have
an internal gain of 10 and AC coupling
– We also had boards with DC coupling and gain 1 which allowed us to
perform thorough time measurements which we had no time to perform
before leaving for SLAC
– There is almost no difference in time performance between gain 1 and
gain 10 boards because all the elements implied therein are located
behind where the gain is applied to the signal
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Characterization of multi-board system
• 2 pulses
• Tr = Tf = 1.6ns
• FWHM = 5ns
• Δt = 0 ps
• CFD ratio = 0.23
• Slope at CF ~ 400mV/ns
Differential jitter = 5.78 ps rms
Density is very homogeneous
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Effect of INL residue
Δt = 2.5 ns
which is a half DLL length =>
differential residue of DLL INL is
visible
Differential jitter = 12.04 ps rms
Δt = 5 ns
which is a full DLL length => no
differential residue of DLL INL is
visible
Differential jitter = 9.79 ps rms
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Effect of hit location in memory (Δt = 0)
Different Boards – Different Channels – random vs mastered location
7.64 ps rms
5.85 ps rms
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Effect of hit location in memory (Δt = 10 ns)
Different Boards – Different Channels – random vs mastered location
13.14 ps rms
12.37 ps rms
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Time performance of multi-board system
Differential jitter between 2 pulses
in a multi-board system
16,00
Differential jitter [ps rms]
14,00
12,00
Mean differential jitter
is of about 12ps rms
which corresponds to
8.5 ps rms of time
precision per pulse
10,00
8,00
6,00
Different channels on same board
Same channel on different boards
4,00
Different channels on different boards
2,00
WaveCatcher V4
0,00
0
10
20
30
40
50
60
70
Distance between pulses [ns]
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Main elements of the test bench
BURLE Planacon XP85012 – 25 µm - 64 ch
We grouped the pixels
in 16 groups of 4
Equalization of
the line lengths
for each group of
4 pixels
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Simple HT scheme
MCPPMT cabled in his test box
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Light injection
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Whole basic setup
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
First photons on the 16 channels
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
4 Analog Input
Trigger In/out
16-channel WaveCatcher
SAMLONG Chip
1024 pts - 3.2
GS/s 2 Channels
Dual 12 bits
ADC
SAMLONG Chip
1024 pts - 3.2
GS/s 2 Channels
Dual 12 bits
ADC
• Based on the very
encouraging results of the 16channel crate, we decided to
start the design of a 16channel WaveCatcher board
FPGA
FPGA
 VME Format
4 Analog Input
Trigger In/out
 USB 480 Mbits/s
 Optical fiber output
SAMLONG Chip
1024 pts - 3.2
GS/s 2 Channels
Dual 12 bits
ADC
SAMLONG Chip
1024 pts - 3.2
GS/s 2 Channels
Dual 12 bits
ADC
FPGA
• This board will be compatible
with both SAM and SAMLONG
– The board can be
synchronized externally =>
possibility to scale the system
up to 320 channels in a
crate
• The first prototype will be
available in March 2011
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Targetting the final design of SuperB TOF
• Final design will permit readout of ~ 600 channels.
– We need hit charge and time
– Pulse width ~ 5ns => 15 samples per hit at ~ 20 MHz => total memory
readout time of 750 ns per hit
– Mean hit rate of 470 kHz
– Analog memory will have to avoid creating dead-time => integrated
derandomizer
MCPPMT
Block diagram of one channel
Level1 trigger
Amplifier
Auto-triggered
analog memory
2-5 GS/s
ADC
CFD +
latency buffer
(PRO ASIC 3
Actel FPGA)
D. Breton, E. Delagnes, J. Maalmi – Workshop on timing detectors – Krakow – November 2010
Control
To DAQ