Dual 16-Bit, 1.0 GSPS
D/A Converter
Preliminary Technical Data
AD9779
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PRODUCT DESCRIPTION
DAC Output Sample Rate 1GSPS+
1.8/3.3 V Single Supply Operation
Low power: 980mW @ 1GSPS, 600mW @ 500MSPS
SFDR =82 dBc to fOUT = 100 MHz
Single Carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
CMOS data interface with Autotracking Input Timing
Analog Output: Adjustable 10-30mA (RL=25 Ω to 50 Ω)
2×, 4×, 8× Interpolation
On Chip Coarse Complex Modulator allows fDAC/2, fDAC/4, fDAC/8
Modulation
Auxiliary DACs allow control of external VGA, Offset Control
100-lead Exposed Paddle TQFP Package
Multiple Chip Synchronization Interface
84dB Digital Interpolation Filter Stopband Attenuation
Digital Inverse Sinc Filter
The AD9779 is a dual 16-bit high dynamic range DAC that
provides a sample rate of 1 GSPS, permitting multi carrier
generation up to its Nyquist frequency. It includes features
optimized for direct conversion transmit applications, including
complex digital modulation and gain and offset compensation. The
DAC outputs are optimized to interface seamlessly with analog
quadrature modulators such as the AD8349. A serial peripheral
interface (SPI) provides for programming /readback of many
internal parameters. The output current can be programmed over a
range of 10mA to 30mA. The AD9779 is manufactured on an
advanced 0.18µm CMOS process and operates from 1.8V and 3.3V
supplies for a total power consumption of 950mW. It is supplied in
a 100-lead TQFP package.
PRODUCT HIGHLIGHTS
Ultra-low noise and Intermodulation Distortion (IMD) enable
high quality synthesis of wideband signals from baseband to high
intermediate frequencies.
APPLICATIONS
• Wireless Infrastructure
o
Digital High or Low IF Synthesis
o
Internal Digital Upconversion Capability
o
Transmit Diversity
• Wideband Communications Systems:
o
Point-to-Point Wireless, LMDS
o
Multi Carrier WCDMA
o
Multi Carrier GSM
Single-ended CMOS interface supports a maximum input rate of
300 MSPS with 1x interpolation.
Uses a proprietary DAC output switching technique that enhances
dynamic performance.
The current outputs of the AD9779 can be easily configured for
various single-ended or differential circuit topologies.
FUNCTIONAL BLOCK DIAGRAM
SYNC_O
SYNC_I
Delay Line
DATACLK_OUT
Delay Line
Clock Generation/Distribution
Clock
Multiplier
2X/4X/8X
Data
Assembler
P1D[15:0]
IOUT1_P
Sinc-1
I Latch
2X
2X
2X
16-Bit
IDAC
2X
IOUT1_N
n * Fdac/8
n = 1, 2, 3… 7
Q Latch
2X
CLK+
CLK-
Complex
Modulator
IOUT2_P
2X
16-Bit
QDAC
P2D[15:0]
Sinc-1
IOUT2_N
Digital Controller
10
10
Serial
Peripheral
Interface
Reference
& Bias
10
Offset
Offset
VREF
RSET
AUX1_P
AUX1_N
AUX2_P
AUX2_N
CSB
SDO
SDIO
Gain
Power-On
Reset
10
SCLK
Gain
Figure 1 Functional Block Diagram
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners. TxDAC is a
registered trademark of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
AD9779
Preliminary Technical Data
TABLE OF CONTENTS
Specifications............................................................................................3
SPI Register Map ...............................................................................15
DC SPECIFICATIONS ......................................................................3
VCO Frequency Ranges ...................................................................21
DIGITAL SPECIFICATIONS............................................................4
PLL Loop Filter Bandwidth .............................................................21
AC SPECIFICATIONS.......................................................................4
Internal Reference/Full Scale Current Generation .......................22
Pin Function Descriptions .....................................................................5
Auxiliary DACs..................................................................................22
Pin Configuration....................................................................................6
Power Dissipation..............................................................................23
Interpolation Filter Coefficients............................................................7
Power Down and Sleep Modes........................................................23
INTERPOLATION Filter RESPONSE CURVES................................8
Internal PLL Clock Multiplier / Clock Distribution.....................23
CHARACTERIZATION DATA ............................................................9
Interpolation Filter Architecture .....................................................26
General Description ..............................................................................13
Using Data Delay to Meet Timing Requirements.........................28
Serial Peripheral Interface................................................................13
Manual or Automatic Input Timing Correction...........................29
General Operation of the Serial Interface......................................13
SYNC Pulse Generation (Master Devices) ....................................30
Instruction Byte.................................................................................13
Internal Synchronization in Slave Device ......................................31
Serial Interface Port Pin Descriptions............................................13
SYNC_I Timing Restrictions...........................................................32
MSB/LSB Transfers ...........................................................................14
Evaluation Board Schematics...............................................................33
Notes on Serial Port Operation.......................................................14
REVISION HISTORY
Revision PrA: Initial Version
Revision PrB: Updated Page 1 Features, added eval board schematics, SPI register map, filter coefficients and filter response curves
Revision PrC: Added characterization data, description of modulation modes, internal clock distribution architecture, timing information
Revision PrE: Added more ac characterization data, power dissipation, synchronization, updated evaluation board schematics and PCB
Revision PrF: Added eval board rev D schematics and PCB
Revision PrG: Added lead free and reel designations to ordering guide, fixed error in SPI table, added ESD information, fixed compliance range
error, added reset pin description
Rev. PrG | Page 2 of 46
Preliminary Technical Data
AD9779
SPECIFICATIONS1
DC SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter
Temp
Test Level
Min
RESOLUTION
ACCURACY
TEMPERATURE DRIFT
REFERENCE
ANALOG SUPPLY
VOLTAGES
DIGITAL SUPPLY
VOLTAGES
POWER CONSUMPTION
16
Bits
LSB
±5
Integral Nonlinearity (INL)
Unit
LSB
Offset Error
± TBD
% FSR
Gain Error (With Internal Reference)
± TBD
% FSR
Full Scale Output Current
Output Compliance Range
Output Resistance
10
-1.0
± TBD
20
% FSR
30
+1.25
TBD
mA
V
kΩ
pF
Output Capacitance
Offset
TBD
TBD
Gain
TBD
ppm/°C
Reference Voltage
TBD
Internal Reference Voltage
Output Current
VDDA33
1.2
100
3.3
ppm/°C
V
nA
V
3.13
VDDD33
VDDD18
VDDCLK
1.0 GSPS
500 MSPS
Standby Power
3.13
1.70
1.70
Table 1: DC Specifications
1
Max
± 1.5
Differential Nonlinearity (DNL)
Gain Error (Without Internal Reference)
ANALOG OUTPUTS
Typ
Specifications subject to change without notice
Rev. PrG | Page 3 of 46
3.3
1.8
1.8
980
600
TBD
ppm/°C
3.47
3.47
1.90
1.90
V
V
V
mW
mW
mW
AD9779
Preliminary Technical Data
DIGITAL SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter
DAC CLOCK INPUT
(CLK+, CLK-)
SERIAL PERIPHERAL
INTERFACE
INPUT DATA
Temp
Test Level
Differential peak-to-peak Voltage
Common Mode Voltage
Maximum Clock Rate
Maximum Clock Rate (SCLK)
Minimum Pulse width high
Minimum pulse width low
Set up Time, Input data to DATACLK (all
modes)
Hold Time, Input data to DATACLK (all
modes)
Reference Clock to DATACLK out
Min
Typ
Max
800
400
1
Unit
3.2
mV
mV
GSPS
MHz
ns
ns
ns
-1.6
ns
40
12.5
12.5
5ns
Table 2: Digital Specifications
AC SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter
SPURIOUS FREE
DYNAMIC RANGE
(SFDR)
TWO-TONE
INTERMODULATION
DISTORTION (IMD)
NOISE SPECTRAL
DENSITY (NSD)
WCDMA ADJACENT
CHANNEL LEAKAGE
RATIO (ACLR), SINGLE
CARRIER
WCDMA SECOND
ADJACENT CHANNEL
LEAKAGE RATIO
(ACLR), SINGLE
CARRIER
Temp
Test Level
Min
Typ
fDAC = 100 MSPS, fOUT = 20 MHz
fDAC = 200 MSPS, fOUT = 50 MHz
fDAC = 400 MSPS, fOUT = 70 MHz
fDAC = 800 MSPS, fOUT = 70 MHz
fDAC = 200 MSPS, fOUT = 50 MHz
fDAC = 400 MSPS, fOUT = 60 MHz
fDAC = 400 MSPS, fOUT = 80 MHz
fDAC = 800 MSPS, fOUT = 100 MHz
fDAC = 156 MSPS, fOUT = 60 MHz
fDAC = 200 MSPS, fOUT = 80 MHz
fDAC = 312 MSPS, fOUT = 100 MHz
fDAC = 400 MSPS, fOUT = 100 MHz
fDAC = 245.76 MSPS, fOUT = 20 MHz
fDAC = 491.52 MSPS, fOUT = 100 MHz
fDAC = 491.52 MSPS, fOUT = 200 MHz
82
82
84
87
91
88
81
88
-158
-157
-159
-159
80
79
74
fDAC = 245.76 MSPS, fOUT = 60 MHz
fDAC = 491.52 MSPS, fOUT = 100 MHz
fDAC = 491.52 MSPS, fOUT = 200 MHz
78
80
76
Table 3: AC Specifications
Rev. PrG | Page 4 of 46
Max
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBc
dBc
dBc
dBc
dBc
dBc
Preliminary Technical Data
AD9779
PIN FUNCTION DESCRIPTIONS
Pin
No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDC18
VDDC18
VSSC
VSSC
CLK+
CLKVSSC
VSSC
VDDC18
VDDC18
VSSC
VSSA
SYNC_I+
SYNC_IVSSD
VDDD18
P1D<15>
P1D<14>
P1D<13>
P1D<12>
P1D<11>
VSSD
VDDD18
P1D<10>
P1D<9>
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P1D<8>
P1D<7>
P1D<6>
P1D<5>
P1D<4>
P1D<3>
VSSD
VDDD18
P1D<2>
P1D<1>
P1D<0>
DATACLK_OUT
VDDD33
TXENABLE
P2D<15>
P2D<14>
P2D<13>
VDDD18
VSSD
P2D<12>
P2D<11>
P2D<10>
P2D<9>
P2D<8>
P2D<7>
Description
Pin
No.
Name
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
Clock Common
Differential Clock Input
Differential Clock Input
Clock Common
Clock Common
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
Analog Common
Differential Synchronization Input
Differential Synchronization Input
Digital Common
1.8 V Digital Supply
Port 1 Data Input D15 (MSB)
Port 1 Data Input D14
Port 1 Data Input D13
Port 1 Data Input D12
Port 1 Data Input D11
Digital Common
1.8 V Digital Supply
Port 1 Data Input D10
Port 1 Data Input D9
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
P2D<6>
P2D<5>
VDDD18
VSSD
P1D<4>
P1D<3>
P1D<2>
P1D<1>
P1D<0>
VDDD18
VDDD33
SYNC_OSYNC_O+
VSSD
PLL_LOCK
SPI_SDO
SPI_SDIO
SPI_CLK
SPI_CSB
RESET
IRQ
VSSA
IPTAT
VREF
I120
Port 1 Data Input D8
Port 1 Data Input D7
Port 1 Data Input D6
Port 1 Data Input D5
Port 1 Data Input D4
Port 1 Data Input D3
Digital Common
1.8 V Digital Supply
Port 1 Data Input D2
Port 1 Data Input D1
Port 1 Data Input D0 (LSB)
Data Clock Output
3.3 V Digital Supply
Transmit Enable
Port 2 Data Input D15 (MSB)
Port 2 Data Input D14
Port 2 Data Input D13
1.8 V Digital Supply
Digital Common
Port 2 Data Input D12
Port 2 Data Input D11
Port 2 Data Input D10
Port 2 Data Input D9
Port 2 Data Input D8
Port 2 Data Input D7
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDDA33
VSSA
VDDA33
VSSA
VDDA33
VSSA
VSSA
IOUT2_P
IOUT2_N
VSSA
AUX2_P
AUX2_N
VSSA
AUX1_N
AUX1_P
VSSA
IOUT1_N
IOUT1_P
VSSA
VSSA
VDDA33
VSSA
VDDA33
VSSA
VDDA33
Table 4: Pin Function Descriptions
Rev. PrG | Page 5 of 46
Description
Port 2 Data Input D6
Port 2 Data Input D5
1.8 V Digital Supply
Digital Common
Port 2 Data Input D4
Port 2 Data Input D3
Port 2 Data Input D2
Port 2 Data Input D1
Port 2 Data Input D0 (LSB)
1.8 V Digital Supply
3.3 V Digital Supply
Differential Synchronization Output
Differential Synchronization Output
Digital Common
PLL Lock Indicator
SPI Port Data Output
SPI Port Data Input/Output
SPI Port Clock
SPI Port Chip Select Bar
Reset, active high
Interrupt Request
Analog Common
Reference Current
Voltage Reference Output
120 µA Reference Current
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
Analog Common
Differential DAC Current Output, Channel 2
Differential DAC Current Output, Channel 2
Analog Common
Auxiliary DAC Voltage Output, Channel 2
Auxiliary DAC Voltage Output, Channel 2
Analog Common
Auxiliary DAC Voltage Output, Channel 1
Auxiliary DAC Voltage Output, Channel 1
Analog Common
Differential DAC Current Output, Channel 1
Differential DAC Current Output, Channel 1
Analog Common
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
AD9779
Preliminary Technical Data
VDDA33
VSSA
VDDA33
VSSA
VDDA33
VSSA
VSSA
IOUT1_P
IOUT1_N
VSSA
AUX1_P
AUX1_N
VSSA
AUX2_N
AUX2_P
VSSA
IOUT2_N
IOUT2_P
VSSA
VSSA
VDDA33
VSSA
VDDA33
VSSA
VDDA33
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN CONFIGURATION
VDDC1 8
1
75
I120
VDDC1 8
2
74
VREF
VSSC
3
73
IPTAT
VSSC
4
72
VSSA
CLK+
5
71
IRQ
CLK-
6
70
RESET
VSSC
7
69
SPI_CSB
VSSC
8
68
SPI_CLK
VDDC1 8
9
67
SPI_SDI
VDDC1 8
10
66
SPI_SDO
VSSC
11
65
PLL_LOCK
VSSA
12
64
VSSD
SYNC_ I+
13
SYNC_ I-
Analog Domain
Digital Domain
AD9779
50
P2D<7>
P2D<6>
49
51
P2D<8>
25
48
P1D<9>
P2D<9>
P2D<5>
47
52
P2D<10>
24
46
P1D<10>
P2D<11>
VDDD1 8
45
53
P2D<12>
23
44
VDDD1 8
VSSD
VSSD
43
54
VDDD18
22
42
VSSD
P2D<13>
P2D<4>
41
55
P2D<14>
21
40
P1D<11>
P2D<15>
P2D<3>
39
56
TXEnable
20
38
P1D<12>
VDDD33
P2D<2>
37
57
DATACLK
19
36
P1D<13>
P1D<0>
P2D<1>
35
58
P1D<1>
18
34
P1D<14>
P1D<2>
P2D<0>
33
59
VDDD18
17
32
P1D<15>
VSSD
VDDD1 8
31
60
P1D<3>
16
30
VDDD18
P1D<4>
VDDD3 3
29
61
P1D<5>
15
28
VSSD
P1D<6>
SYNC_ O-
27
62
P1D<7>
14
26
SYNC_ O+
P1D<8>
63
Figure 2. Pin Configuration
Rev. PrG | Page 6 of 46
Preliminary Technical Data
AD9779
INTERPOLATION FILTER COEFFICIENTS
Table 5: Halfband Filter 1
Lower
Upper
Coefficient Coefficient
H(1)
H(55)
H(2)
H(54)
H(3)
H(53)
H(4)
H(52)
H(5)
H(51)
H(6)
H(50)
H(7)
H(49)
H(8)
H(48)
H(9)
H(47)
H(10)
H(46)
H(11)
H(45)
H(12)
H(44)
H(13)
H(43)
H(14)
H(42)
H(15)
H(41)
H(16)
H(40)
H(17)
H(39)
H(18)
H(38)
H(19)
H(37)
H(20)
H(36)
H(21)
H(35)
H(22)
H(34)
H(23)
H(33)
H(24)
H(32)
H(25)
H(31)
H(26)
H(30)
H(27)
H(29)
H(28)
Integer
Value
-4
0
13
0
-34
0
72
0
-138
0
245
0
-408
0
650
0
-1003
0
1521
0
-2315
0
3671
0
-6642
0
20755
32768
Table 6: Halfband Filter 2
Lower
Upper
Coefficient Coefficient
H(1)
H(23)
H(2)
H(22)
H(3)
H(21)
H(4)
H(20)
H(5)
H(19)
H(6)
H(18)
H(7)
H(17)
H(8)
H(16)
H(9)
H(15)
H(10)
H(14)
H(11)
H(13)
H(12)
Integer
Value
-2
0
17
0
-75
0
238
0
-660
0
2530
4096
Table 7: Halfband Filter 3
Lower
Upper
Coefficient Coefficient
H(1)
H(15)
H(2)
H(14)
H(3)
H(13)
H(4)
H(12)
H(5)
H(11)
H(6)
H(10)
H(7)
H(9)
H(8)
Integer
Value
-39
0
273
0
-1102
0
4964
8192
Table 8: Inverse Sinc Filter
Lower
Upper
Coefficient Coefficient
H(1)
H(9)
H(2)
H(8)
H(3)
H(7)
H(4)
H(6)
H(5)
Integer
Value
2
-4
10
-35
401
Rev. PrG | Page 7 of 46
AD9779
Preliminary Technical Data
INTERPOLATION FILTER RESPONSE CURVES
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
4
Figure 3. AD9779 2x Interpolation, Low Pass Response to
±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
4
Figure 4. AD9779 4x Interpolation, Low Pass Response to
±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
4
Figure 5.AD9779 8x Interpolation, Low Pass Response to
±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off)
Rev. PrG | Page 8 of 46
Preliminary Technical Data
AD9779
CHARACTERIZATION DATA
6
100
5
95
4
90
3
85
SFDR - dBm
INL (LSBs)
2
1
0
-1
80
75
70
-2
65
-3
60
-4
55
F D ATA =100MSPS
F D ATA =200MSPS
F D ATA =160MSPS
50
-5
0
8192
16384
24576
32768
40960
49152
57344
65536
0
Code
20
40
60
80
100
Fout - MHz
Figure 6. AD9779 Typical INL
Figure 9. SFDR vs. FOUT, 2x Interpolation
2
100
F D ATA =125MSPS
F D ATA =100MSPS
95
1.5
90
85
SFDR - dBm
DNL (LSBs)
1
0.5
0
80
75
F D ATA =200MSPS
70
F D ATA =150MSPS
65
60
-0.5
55
50
-1
0
8192
16384
24576
32768
40960
49152
57344
65536
0
Code
40
60
80
Fout - MHz
Figure 7. AD9779 Typical DNL
Figure 10. SFDR vs. FOUT, 4x Interpolation
100
100
F D ATA =160MSPS
F D ATA =100MSPS
F D ATA =200MSPS
F D ATA =62.5MSPS
90
50MSPS
90
80
SFDR - dBm
SFDR - dBm
20
70
60
80
75MSPS
70
100MSPS
60
50
0
20
40
60
80
100
Fout - M Hz
50
0
10
20
30
Fout - M Hz
Figure 8. SFDR vs. FOUT, 1x Interpolation
Figure 11. SFDR vs. FOUT, 8x Interpolation
Rev. PrG | Page 9 of 46
40
50
AD9779
Preliminary Technical Data
100.0
F D ATA =200MSPS
100
90.0
90
IMD - dBc
IMD - dBc
100MSPS
80.0
F D ATA =160MSPS
70.0
80
112.5MSPS
75MSPS
50MSPS
70
F D ATA =62.5MSPS
60
60.0
50
0
50.0
0
20
40
60
50
100
150
200
250
300
350
400
70
80
450
Fout - MHz
80
Fout - MHz
Figure 15. Third Order IMD vs. FOUT, 8x Interpolation
Figure 12. Third Order IMD vs. FOUT, 1x Interpolation
100.0
-150
F D ATA =200MSPS
-152
NSD - dBm/Hz
IMD - dBc
80.0
F D ATA =160MSPS
70.0
F D ATA =156MSPS
F D ATA =78MSPS
-154
90.0
-156
-158
-160
-162
F D ATA =200MSPS
-164
-166
-168
60.0
-170
0
10
20
30
50.0
0
20
40
60
80
100
120
140
160
180
40
50
60
90
Fout - M Hz
200
Fout - MHz
Figure 16. Noise Spectral Density vs. FOUT, 1x Interpolation
Figure 13. Third Order IMD vs. FOUT, 2x Interpolation
100
-150
F D ATA =125MSPS
F D ATA =78MSPS
-156
F D ATA =200MSPS
80
NSD - dBm /Hz
IMD - dBc
-154
F D ATA =150MSPS
70
F D ATA =156MSPS
-152
90
F D ATA =100MSPS
60
50
-158
-160
-162
-164
-166
0
40
80
120
160
200
240
280
320
360
400
Fout - MHz
F D ATA =200MSPS
-168
-170
0
Figure 14. Third Order IMD vs. FOUT, 4x Interpolation
20
40
60
80
100
120
140
Fout - MHz
Figure 17. Noise Spectral Density vs. FOUT, 2x Interpolation
Rev. PrG | Page 10 of 46
160
180
Preliminary Technical Data
AD9779
0.7
-90
8x Interpolation
-85
F D ATA =122.88MSPS
0.6
4x Interpolation
-75
4x Interpolation,
Zero Stuffing
8x Interpolation,
Zero Stuffing
0.5
2x Interpolation,
Zero Stuffing
-70
F D ATA =61.44MSPS
-65
Power - W
ACLR - dBc
-80
-60
-55
-50
0.4
2x Interpolation
1x Interpolation,
Zero Stuffing
0.3
1x Interpolation
0
20
40
60
80
100 120 140 160 180 200 220
0.2
240 260 280 300
Fout - M Hz
0.1
Figure 18. ACLR for 1st Adjacent Band WCDMA, 4x Interpolation. On-Chip
Modulation is used to translate baseband signal to IF.
0
0
25
50
75
-85
125
150
175
200
225
250
Figure 21. Power Dissipation , I Data only, Single DAC Mode
FDATA=122.88MSPS
-80
ACLR - dBc
100
F DAT A (MSPS)
-90
1.1
-75
8x Interpolation,F DA C/4 Modulation
1
-70
FDATA=61.44MSPS
-65
8x Interpolation,F DA C/2 Modulation
0.9
8x Interpolation,F DA C/8 Modulation
4x Interpolation,F DA C/4 Modulation
8x Interpolation,Modulation off
4x Interpolation,F DA C/2 Modulation
4x Interpolation,Modulation off
0.8
-60
-50
0
20
40
60
80
100
120
140
160
180
200
220
Fout - MHz
Power - W
0.7
-55
Figure 19. ACLR for 2nd Adjacent Band WCDMA, 4x Interpolation. On-Chip
Modulation is used to translate baseband signal to IF.
0.6
2x Interpolation,
Zero Stuffing
4x Interpolation,
Zero Stuffing
8x Interpolation,
Zero Stuffing
2x Interpolation,F DA C/2 Modulation
2x Interpolation,Modulation off
0.5
1x Interpolation,
Zero Stuffing
0.4
1x Interpolation
0.3
0.2
-90
0.1
-85
0
F D ATA =122.88MSPS
0
ACLR - dBc
-80
25
50
75
100
125
150
175
200
225
250
F DATA (M SPS)
-75
Figure 22. Power Dissipation, Dual DAC Mode
-70
-65
F D ATA =61.44MSPS
0.4
-60
8x interpolation
-55
4x interpolation
0.3
-50
20
40
60
80
100 120 140 160 180 200 220 240 260 280 300
Power - W
0
Fout - M Hz
Figure 20. ACLR for 3rd Adjacent Band WCDMA, 4x Interpolation. On-Chip
Modulation is used to translate baseband signal to IF.
0.2
2x interpolation
0.1
1x interpolation
0
0
25
50
75
100
125
150
175
200
225
250
FDATA (MSPS)
Figure 23. Power Consumption, Digital 1.8V Supply, I Data only, Real Mode,
does not include zero stuffing
Rev. PrG | Page 11 of 46
AD9779
Preliminary Technical Data
0.08
0.125
8x interpolation, fDAC /8,
fDAC /4,
Power - W
0.06
Power - W
8x interpolation
4x interpolation
0.04
2x interpolation
0.02
1x interpolation
4x interpolation
fDAC /2,
no modulation
0.1
0.075
2x interpolation
0.05
0.025
1x interpolation
0
0
0
25
50
75
100
125
150
175
200
225
250
0
25
50
75
100
FDATA(MSPS)
Figure 24. Power Consumption, Clock 1.8V Supply, I Data only, Single DAC
Mode, includes modulation modes, does not include zero stuffing
150
175
200
225
250
Figure 27. Power Consumption, Clock 1.8V Supply, I Data only, Dual DAC
Mode, does not include zero stuffing
0.025
0.02
1x interpolation
0.018
All interpolation, modulation modes, excludes zero stuffing
2x interpolation
0.016
Power - W
8x interpolation
0.014
4x interpolation
0.012
Power - W
125
FDATA(MSPS)
0.01
0.0125
0.008
0.006
0.004
0
0.002
0
25
50
0
0
25
50
75
100
125
150
175
200
225
250
125
150
175
200
Figure 28. Digital 3.3V Supply, I Data only, Dual DAC Mode
Figure 25. Digital 3.3V Supply, I Data only, Single DAC Mode, includes
modulation modes and zero stuffing
0.16
0.14
8x interpolation, fDAC /8,
0.7
fDAC /4,
0.6
fDAC /2,
no modulation
0.12
0.1
Power - W
Power - W
100
FDATA (MSPS)
FDATA (MSPS)
0.8
75
4x interpolation
0.5
2x interpolation
0.4
0.08
0.06
0.04
0.3
0.02
0.2
0
1x interpolation
(no modulation)
0.1
0
25
50
75
100
125
150
175
200
225
400
600
800
1000
FDAC - M SPS
0
0
200
250
FDATA (MSPS)
Figure 26. Power Consumption, Digital 1.8V Supply, I Data only, Dual DAC
Mode, does not include zero stuffing
Rev. PrG | Page 12 of 46
Figure 29. Power Dissipation of Inverse Sinc Filter
1200
225
250
Preliminary Technical Data
AD9779
GENERAL DESCRIPTION
data will be written.
The AD9779 combines many features which make it a very
attractive DAC for wired and wireless communications systems.
The dual digital signal path and dual DAC structure allow an easy
interface with common quadrature modulators when designing
single sideband transmitters. The speed and performance of the
AD9779 allow wider bandwidths/more carriers to be synthesized
than with previously available DACs. The digital engine in the
AD9779 uses a breakthrough filter architecture that combines the
interpolation with a digital quadrature modulator. This allows the
AD9779 to do digital quadrature frequency up conversion. The
AD9779 also has features which allow simplified synchronization
with incoming data, and also allows multiple AD9779s to be
synchronized.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9779 and
the system controller. Phase 2 of the communication cycle is a
transfer of 1, 2, 3, or 4 data bytes as determined by the instruction
byte. Using one multi-byte transfer is the preferred method. Single
byte data transfers are useful to reduce CPU overhead when
register access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
Instruction Byte
The instruction byte contains the information shown in Table 9.
MSB
I7
R/W
Serial Peripheral Interface
SPI_SDO (pin 66)
SPI_SDI (pin 67)
SPI_SCLK (pin 68)
I6
N1
I5
N0
I4
A4
I3
A3
I2
A2
I1
A1
LSB
I0
A0
Table 9. SPI Instruction Byte
AD9779
SPI
PORT
R/W, Bit 7 of the instruction byte, determines whether a read or a
write data transfer will occur after the instruction byte write. Logic
high indicates read operation. Logic 0 indicates a write operation.
SPI_CSB (pin 69)
Figure 30. AD9779 SPI Port
The AD9779 serial port is a flexible, synchronous serial
communications port allowing easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O is
compatible with most synchronous transfer formats, including both
the Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9779. Single
or multiple byte transfers are supported, as well as MSB first or LSB
first transfer formats. The AD9779’s serial interface port can be
configured as a single pin I/O (SDIO) or two unidirectional pins for
in/out (SDIO/SDO).
General Operation of the Serial Interface
There are two phases to a communication cycle with the AD9779.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9779, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9779 serial
port controller with information regarding the data transfer cycle,
which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is read
or write, the number of bytes in the data transfer, and the starting
register address for the first byte of the data transfer. The first eight
SCLK rising edges of each communication cycle are used to write
the instruction byte into the AD9779.
A logic high on the CS pin, followed by a logic low, will reset the
SPI port timing to the initial state of the instruction cycle. From
this state, the next 8 rising SCLK edges represents the instruction
bits of the current IO operation This is true regardless of the
present state of the internal registers or the other signal levels
present at the inputs to the SPI port. If the SPI port is in the midst
of an instruction cycle or a data transfer cycle, none of the present
N1, N0, Bits 6 and 5 of the instruction byte, determine the number
of bytes to be transferred during the data transfer cycle. The bit
decodes are shown in Table 10.
A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte,
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers, this
address is the starting byte address. The remaining register
addresses are generated by the AD9779 based on the LSBFIRST bit
(REG00, bit 6).
N0
0
0
1
1
N1
0
1
0
1
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
Table 10. Byte Transfer Count
Serial Interface Port Pin Descriptions
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9779 and to run the internal state
machines. SCLK’s maximum frequency is 40 MHz. All data input to
the AD9779 is registered on the rising edge of SCLK. All data is
driven out of the AD9779 on the falling edge of SCLK.
CSB—Chip Select. Active low input starts and gates a
communication cycle. It allows more than one device to be used on
the same serial communications lines. The SDO and SDIO pins will
go to a high impedance state when this input is high. Chip select
should stay low during the entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the AD9779 on
Rev. PrG | Page 13 of 46
AD9779
Preliminary Technical Data
this pin. However, this pin can be used as a bidirectional data line.
The configuration of this pin is controlled by Bit 7 of register
address 00h. The default is Logic 0, which configures the SDIO pin
as unidirectional.
As described above, all serial port data is transferred to/from the
AD9779 synchronous to the SCLK pin. If synchronization is lost,
the AD9779 has the ability to asynchronously terminate an IO
operation, putting the AD9779 serial port controller into a known
state, thereby regaining synchronization.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9779 operates in a single bidirectional I/O mode,
this pin does not output data and is set to a high impedance state.
INSTRUCTION CYCLE
MSB/LSB Transfers
DATA TRANSFER CYCLE
CSB
When LSBFIRST = 1 (LSB first) the instruction and data bit must
be written from least significant bit to most significant bit. Multibyte data transfers in LSB first format start with an instruction byte
that includes the register address of the least significant data byte
followed by multiple data bytes. The serial port internal byte
address generator increments for each byte of the multi-byte
communication cycle.
The AD9779 serial port controller data address will decrement
from the data address written toward 0x00 for multi-byte I/O
operations if the MSB first mode is active. The serial port controller
address will increment from the data address written toward 0x1F
for multi-byte I/O operations if the LSB first mode is active.
R/W N0 N1
A0 A1
A2 A3
A4
SDO
D7 D6N D5N
D30 D20 D10 D00
D7 D6N D5N
D30 D20 D10 D00
03152-0-004
SDIO
Figure 31. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
A0
A1 A2
A3 A4
N1 N0 R/W D00 D10 D20
D4N D5N D6N D7N
D00 D10 D20
D4N D5N D6N D7N
SDO
03152-0-005
When LSBFIRST = 0 (MSB first) the instruction and data bit must
be written from most significant bit to least significant bit. Multibyte data transfers in MSB first format start with an instruction
byte that includes the register address of the most significant data
byte. Subsequent data bytes should follow in order from high
address to low address. In MSB first mode, the serial port internal
byte address generator decrements for each data byte of the
multibyte communication cycle.
SCLK
Figure 32. Serial Register Interface Timing LSB First
tDS
tSCLK
CSB
tPWH
tPWL
SCLK
tDS
SDIO
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
03152-PrD-006
The AD9779 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by register bit LSBFIRST (REG00, bit 6).
The default is MSB first (LSBFIRST = 0).
Figure 33. Timing Diagram for SPI Register Write
Notes on Serial Port Operation
CSB
SCLK
tDV
SDIO
SDO
The same considerations apply to setting the software reset, RESET
(REG00, bit 5). All registers are set to their default values EXCEPT
REG00 and REG04 which remain unchanged.
Use of only single byte transfers when changing serial port
configurations or initiating a software reset is recommended to
prevent unexpected device behavior.
Rev. PrG | Page 14 of 46
DATA BIT n
DATA BIT n–1
Figure 34. Timing Diagram for SPI Register Read
03152-PrD-007
The AD9779 serial port configuration is controlled by REG00, bits
6 and 7 . It is important to note that the configuration changes
immediately upon writing to the last bit of the byte. For multi-byte
transfers, writing to this register may occur during the middle of
communication cycle. Care must be taken to compensate for this
new configuration for the remaining bytes of the current
communication cycle.
Preliminary Technical Data
AD9779
SPI Register Map
Register
Name
Comm
Register
Address
00h
00
Bit 7
SDIO
Bit 6
LSB,MSB First
Bit 5
Software
Reset
Bidirectional
Digital
Control
Register
Sync
Control
Register
PLL Control
Misc.
Control
Register
Bit 4
Power
Down
Mode
01h
01
Filter Interpolation Factor <1: 0>
Filter Modulation Mode <3:0>
02h
02
Data Format
Real Mode
03h
03
Data Clock Delay Mode <1:0>
04h
04
05h
Single/Interleaved
Data Bus Mode
Data Clock
Delay
Enable
Bit 2
Auto
Power
Down
Enable
Inverse
Sinc
Enable
Bit 1
Bit 0
PLL Lock
Indicator
DATACL
K Invert
TxEnable
/ IQ
Select
Invert
Def
ault
00h
Zero
Stuffing
Enable
00h
Q First
00h
Input Data Timing Error Tolerance <3:0>
00h
Data Clock Delay <3:0>
Output Sync Pulse Divide <2:0>
Sync Out
Delay <4>
00h
05
Sync Out Delay <3:0>
Input Sync Pulse Frequency
Sync Input
Delay <4>
00h
06h
06
Sync Input Delay <3:0>
Input Sync Pulse Timing Error Tolerance <3:0>
07h
07
Sync Receiver
Enable
08h
08
PLL Band Select <5:0>
09h
09
PLL Enable
0Ah
10
PLL Control Voltage Range <2:0>
Sync Driver Enable
Extra Data Clock Divide
Ratio<1:0>
Bit 3
Sync
Triggering
Edge
Sync_I to Input Data Sampling Clock Offset <4:0>
PLL VCO AGC Gain
<1:0>
PLL VCO Divider Ratio <1:0>
PLL Loop Divide
Ratio <1:0>
PLL Bias Setting <2:0>
PLL Loop Bandwidth Adjustment <4:0>
Rev. PrG | Page 15 of 46
00h
00h
CF
h
37h
38h
AD9779
I DAC
Control
Register
Aux 1 DAC
Control
Register
Q DAC
Control
Register
Aux 2 DAC
Control
Register
Interrupt
Register
Preliminary Technical Data
0Bh
11
IDAC Gain Adjustment <7:0>
F9h
0Ch
12
IDAC
SLEEP
0Dh
13
Auxiliary DAC1 Data <7:0>
0Eh
14
Auxiliary
DAC1 Sign
0Fh
15
QDAC Gain Adjustment <7;0>
10h
16
QDAC
SLEEP
11h
17
Auxiliary DAC2 Data <7:0>
12h
18
Auxiliary
DAC2 Sign
Auxiliary DAC2
Current Direction
Auxiliary DAC2
Power Down
19h
25
Data Delay
IRQ
Sync Delay IRQ
Cross Control IRQ
IDAC
Power
Down
Auxiliary DAC1
Current Direction
IDAC Gain Adjustment <9:8>
01h
00h
Auxiliary DAC1
Power Down
Auxiliary DAC1 Data <9:8>
00h
F9h
QDAC
Power
Down
QDAC Gain Adjustment <9:8>
01h
00h
Data Delay
IRQ Enable
Table 11: SPI Register Map
Rev. PrG | Page 16 of 46
Sync
Delay
IRQ
Enable
Auxiliary DAC2 Data <9:8>
00h
Cross
Control IRQ
Enable
00h
Internal Sync
Loopback
Preliminary Technical Data
Register (hex)
Comm Register
Digital Control
Register
Sync Control
Register
00
Address
7
Name
SDIO
Bidirectional
00
6
LSB/MSB First
00
00
5
4
Software RESET
Power Down
Mode
00
3
00
1
Auto Power
Down Enable
PLL LOCK (read
only)
01
7:6
Filter
Interpolation
Factor
01
5:2
01
0
Filter Modulation
Mode
Zero Stuffing
02
7
Data Format
02
6
Dual/ Interleaved
Data Bus Mode
02
5
Real Mode
02
3
Inverse Sinc
Enable
02
2
DATACLK Invert
02
02
1
0
TxEnable Invert
Q First
03
7:6
Data Clock Delay
Mode
03
5:4
03
3:0
04
04
7:4
3:1
04
05
05
0
7:4
3:1
05
0
Extra Data Clock
Divide Ratio
Input Data
Timing Error
Tolerance
Data Clock Delay
Output Sync
Pulse Divide
Sync Out Delay
Sync Out Delay
Input Sync Pulse
Frequency
Sync Input Delay
AD9779
Function
0: Use SDIO pin as input data only
1: Use SDIO as both input and output data
0: First bit of serial data is MSB of data byte
1: First bit of serial data is LSB of data byte
Bit must be written with a 1, then 0 to soft reset SPI register map
0: All circuitry is active
1: Disable all digital and analog circuitry, only SPI port is active
Controls power down model, see page 23 for details
Default
0
0
0
0
0
0: PLL is not locked
1: PLL is locked
0
00: 1× interpolation
00
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
See Table 13 for filter modes
0000
0: Zero stuffing off
1: Zero stuffing on
0: Signed binary
1: Unsigned binary
0: Both input data ports receive data
1: Data port 1 only receives data
0: Enable Q path for signal processing
1: Disable Q path data (internal Q channel clocks disabled, I and Q
modulators disabled)
0: Inverse sinc disabled
1: Inverse sinc enabled
0: Output DATACLK same phase as internal capture clock
1: Output DATACLK opposite phase as internal capture clock
Inverts the function of TxEnable pin 39. More details on page 23.
0: First byte of data is always I data at beginning of transmit
1: First byte of data is always Q data at beginning of transmit
00: Manual, no error correction
01: Manual error correction
10: automatic, one pass check
11: automatic, continuous pass check
Data Clock Output Divider
000
Input data window delay control, see page 28 for details.
000
Sets delay of DACCLK in to DATACLK out
Sets frequency of Sync_Out pulses
0000
0000
Sync Output Delay, bit 4
Sync Output Delay, <3:0>
Input Sync Pulse Frequency Divider
0
0
Sync Input Delay, bit 4
0
Rev. PrG | Page 17 of 46
0
0
0
0
0
0
0
00
AD9779
Sync Control
Register
PLL Control
Preliminary Technical Data
06
06
7:4
3:0
07
7
07
6
07
5
07
4:0
08
7:2
08
1:0
09
7
09
6:5
Sync Input Delay
Input Sync Pulse
Timing Error
Tolerance
Sync Receiver
Enable
Sync Driver
Enable
Sync Triggering
Edge
Sync_I to input
data sampling
clock offset
PLL Band Select
VCO AGC Gain
Control
PLL Enable
PLL VCO Divide
Ratio
0
0
0
0
0
0
See Table 14. VCO Frequency Range vs. PLL Band Select Value
Lower number (low gain) is generally better for performance.
0: PLL off, DAC rate clock supplied by outside source
1: PLL on, DAC rate clock synthesized internally from data rate clock via
PLL clock multiplier
FVCO/FDAC:
110011
11
10
00 ×1
01 ×2
10 ×4
09
4:3
PLL Loop Divide
Ratio
11 ×8
FDAC/FREF:
00 ×2
01 ×4
10 ×8
11 ×16
Misc. Control
IDAC Control
Register
Aux DAC 1 Control
Register
09
0A
2:0
7:5
0A
4:0
0B
7:0
0C
7
PLL Bias Setting
PLL Control
Voltage Range
PLL Loop
Bandwidth
Adjustment
IDAC Gain
Adjustment
IDAC Sleep
0C
6
IDAC Power Down
0C
1:0
0D
7:0
0E
7
IDAC Gain
Adjustment
Aux DAC1 Gain
Adjustment
Aux DAC1 Sign
0E
6
Aux DAC1 Current
Direction
0E
5
Aux DAC1 Power
Down
0E
1:0
Aux DAC1 Gain
Adjustment
111
000 to 111, higher number means higher control voltage
See page 21 for description
(7:0) LSB slice of 10 bit gain setting word for IDAC
11111001
0: IDAC on
1: IDAC off
0: IDAC on
1: IDAC off
(9:8) MSB slice of 10 bit gain setting word for IDAC
0
01
(7:0) LSB slice of 10 bit gain setting word for Aux DAC1
00000000
0: Positive
1: Negative
0: Source
1: Sink
0: Aux DAC1 on
1: Aux DAC 1 off
(9:8) MSB slice of 10 bit gain setting word for Aux DAC1
Rev. PrG | Page 18 of 46
0
0
0
00
Preliminary Technical Data
QDAC Control
Register
Aux DAC 2 Control
Register
Interest Register
0F
7:0
QDAC Gain
Adjustment
QDAC Sleep
10
7
10
6
QDAC Power
Down
10
1:0
11
7:0
12
12
7
6
Aux DAC 2 Gain
Adjustment
Aux DAC 2 Gain
Adjustment
Aux DAC 2 Sign
Aux DAC 2
Current Direction
12
5
Aux DAC 2 Power
Down
12
1:0
19
19
19
19
7
6
5
3
19
2
19
1
19
0
Aux DAC 2 Gain
Adjustment
Data Delay IRQ
Sync Delay IRQ
Cross Control IRQ
Data Delay IRQ
Enable
Sync Delay IRQ
Enable
Cross Control IRQ
Enable
Internal Sync
Loopback
AD9779
(7:0) LSB slice of 10 bit gain setting word for QDAC
11111001
0: QDAC on
1: QDAC off
0: QDAC on
1: QDAC off
(9:8) MSB slice of 10 bit gain setting word for Aux DAC 2
0
(7:0) LSB slice of 10 bit gain setting word for Aux DAC 2
00000000
0: Positive, 1: Negative
0: Source
1: Sink
0: Aux DAC 2 on
1: Aux DAC 2 off
(9:8) MSB slice of 10 bit gain setting word for Aux DAC2
0
0
0
00
0
0
0
0
0
0
0
Table 12: SPI RegisterDescription
Rev. PrG | Page 19 of 46
AD9779
Preliminary Technical Data
Interp.
Factor
<7:6>
Filter
Mode
<5:2>
Modulation
8
00h
DC_odd
1
-0.05
0
0.05
In 8x interpolation;
8
01h
DC_even
2
0.0125
0.0625
0.1125
BW(min) =
0.0375*FDAC
8
02h
F/8_odd
3
0.075
0.125
0.175
8
03h
F/8_even
4
0.1375
0.1875
0.2375
8
04h
2F/8_odd
5
0.2
0.25
0.3
8
05h
2F/8_even
6
0.2625
0.3125
0.3625
8
06h
3F/8_odd
7
0.325
0.375
0.425
8
07h
3F/8_even
8
0.3875
0.4375
0.4875
8
08h
-4F/8_even
-8
-0.55
-0.5
-0.45
8
09h
-4F/8_odd
-7
-0.4875
-0.4375
-0.3875
8
0Ah
-3F/8_even
-6
-0.425
-0.375
-0.343
8
0Bh
-3F/8_odd
-5
-0.3625
-0.3125
-0.2625
8
0Ch
-2F/8_even
-4
-0.3
-0.25
-0.2
8
0Dh
-2F/8_odd
-3
-0.2375
-0.1875
-0.1375
8
0Eh
-F/8_even
-2
-0.175
-0.125
-0.075
8
0Fh
-F/8_odd
-1
-0.1125
-0.0625
-0.0125
4
00h
DC_odd
1
-0.1
0
0.1
In 4x interpolation;
4
01h
DC_even
2
0.025
0.125
0.225
BW(min) = 0.075*FDAC
4
02h
F/4_odd
3
0.15
0.25
0.35
BW(max) = 0.2*FDAC
4
03h
F/4_even
4
0.275
0.375
0.475
4
04h
-F/2_even
-4
-0.6
-0.5
-0.4
4
05h
-F/2_odd
-3
-0.475
-0.375
-0.275
4
06h
-F/4_even
-2
-0.35
-0.25
-0.15
4
07h
-F/4_odd
-1
-0.225
-0.125
-0.025
2
00h
DC_odd
1
-0.2
0
0.2
In 2x interpolation;
2
01h
DC_even
2
0.05
0.25
0.45
BW(min) = 0.15*FDAC
2
02h
-F/2_even
-1
-0.7
-0.5
-0.3
BW(max) = 0.4*FDAC
2
03h
-F/2_odd
-2
-0.45
-0.25
-0.05
Nyquist Zone
Passband
F_low
Center
F_High
(Freq. Normalized to FDAC)
BW(max) = 0.1*FDAC
Table 13: Interpolation Filter Modes, see Reg 01, bits 5 :2
Rev. PrG | Page 20 of 46
Preliminary Technical Data
AD9779
PLL Frequency Band
Select
PLL Band
Select Value
Frequency
Band in
MHz
111111 (63)
Auto
101111 (47)
1734-1856
011111 (31)
1422-1515
001111 (15)
1131-1208
111110 (62)
2038-2170
101110 (46)
1725-1843
011110 (30)
1397-1494
001110 (14)
1109-1189
111101 (61)
1984-2115
101101 (45)
1702-1822
011101 (29)
1384-1477
001101 (13)
1101-1176
111100 (60)
1965-2094
101100 (44)
1688-1808
011100 (28)
1357-1453
001100 (12)
1080-1155
111011 (59)
1947-2077
101011 (43)
1677-1792
011011 (27)
1344-1437
001011 (11)
1069-1142
111010 58)
1931-2059
101010 (42)
1646-1763
011010 (26)
1318-1413
001010 (10)
1050-1123
111001 (57)
1910-2038
101001 (41)
1630-1741
011001 (25)
1306-1397
001001 (9)
1040-1110
111000 (56)
1891-2018
101000 (40)
1602-1712
011000 (24)
1283-1376
001000 (8)
1021-1094
110111 (55)
1877-2005
100111 (39)
1586-1693
010111 (23)
1269-1358
000111 (7)
1010-1080
110110 (54)
1856-1982
100110 (38)
1560-1669
010110 (22)
1246-1339
000110 (6)
992-1064
110101 (53)
1837-1962
100101 (37)
1544-1646
010101 (21)
1232-1318
000101 (5)
982-1050
110100 (52)
1826-1950
100100 (36)
1518-1621
010100 (20)
1176-1261
000100 (4)
955-1021
110011 (51)
1802-1926
100011 (35)
1502-1600
010011 (19)
1197-1280
000011 (3)
928-994
110010 (50)
1781-1906
100010 (34)
1478-1578
010010 (18)
1144-1226
000010 (2)
902-966
110001 (49)
1774-1896
100001 (33)
1462-1557
010001 (17)
1165-1245
000001 (1)
878-941
110000 (48)
1750-1874
100000 (32)
1435-1534
010000 (16)
1142-1208
000000 (0)
854-915
Table 14. VCO Frequency Range vs. PLL Band Select Value
VCO Frequency Ranges
PLL Loop Filter Bandwidth
Because the PLL band covers greater than a 2x frequency range, the
user may find themselves with two options for PLL band select, one
at the lower end of the range and one at the higher end of the range.
Under these conditions, VCO phase noise will be optimal when the
user selects the band select value corresponding to the higher end
of the frequency range. Figure 35 shows how the VCO bandwidth
as well as the optimal VCO frequency varies with the band select
value.
The loop filter bandwidth of the PLL is programmed via SPI reg
0A, bits 4:0. Changing these values switches capacitors on the
internal loop filter. No external loop filter components are required.
This loop filter has a pole at zero (P1), and then a zero (Z1)-pole
(P2) combination. Z1 and P2 occur within a decade of each other.
The location of this zero-pole is determined by bit 4:0. For a setting
of 00000, the pole-zero occurs near 10MHz. By setting bits 4:0 to
11111, the Z1/P2 combination can be lowered to approximately
1MHz. The relationship between bits 4:0 and the position of the
pole-zero between 1MHz and 10MHz is linear. The internal
Rev. PrG | Page 21 of 46
AD9779
Preliminary Technical Data
components are not low tolerance, however, and can drift by as
much as ±30 %.
1.2V  27  6

× 
+
× DAC gain   × 32
R

 12  1024
62
35
58
30
54
25
IFS (ma)
50
46
20
15
42
PLL Band Select Value
10
38
5
34
0
30
0
200
26
400
600
800
1000
DAC gain code
22
Figure 37. IFS vs. DAC Gain Code
18
Auxiliary DACs
14
10
6
2
850
950
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150
VCO freq (MHz)
Figure 35. PLL Band Select vs. Frequency
Internal Reference/Full Scale Current Generation
Full scale current on the AD9779 IDAC and QDAC can be set from
10 to 30ma. Initially, the 1.2V bandgap reference is used to set up a
current in an external resistor connected to I120 (pin 75). A
simplified block diagram of the AD9779 reference circuitry is given
below in Figure 36. The recommended value for the external resistor
is 10k Ω, which sets up an I REFERENCE in the resistor of 120µa which
in turn provides a DAC output full scale current of 20mA. Because
the gain error is a linear function of this resistor, a high precision
resistor will improve gain matching to the internal matching spec
of the AD9779. Internal current mirrors provide a current gain
scaling, where IDAC or QDAC gain is a 10 bit word in the SPI port
register (registers 0A, 0B, 0E, and 0F). The default value for the
DAC gain registers gives an IFS of 20mA.
VREF
AD9779
IDAC gain
1.2V bandgap
I120
current scaling
0.1µF
IDAC
DAC full scale
reference current
QDAC
QDAC gain
10KΩ
Two auxiliary DACs are provided on the AD9779. The full scale
output current on these DACs is derived from the 1.2V bandgap
reference and external resistor. The gain scale from the reference
amplifier current I REFERENCE to the aux DAC reference current is
16.67 with the aux DAC gain set to full scale (10 bit values, SPI reg
0C, 0D, 10, 11), this gives a full scale current of 2ma for aux DAC1
and for aux DAC2. The aux DAC outputs are not differential.
Either the P or the N side of the aux DAC is turned on at one time,
with the other acting as a high impedance (>100kΩ). In addition,
the P or N outputs can act as current sources or sinks. This control
of P and N for both aux DACs via registers 0Eh and 10h, bits 7:6.
When sourcing current, the output compliance voltage is 0-1.5V,
and when sinking current the output compliance voltage is 0.81.5V.
The Aux DACs can be used for LO cancellation when the DAC
output is followed by a quadrature modulator. A typical DAC to
Quadrature Modulator interface is given in Figure 38. Often, the
input common mode voltage for the modulator is much higher
than the output compliance range of the DAC, so that ac coupling is
necessary. If the required common mode input voltage on the
quadrature modulator matches that of the DAC, then the ac
coupling capacitors can be removed. The input referred dc offset
voltage of the quadrature modulator (as well as the DAC output
offset voltage mismatch) can result in LO feedthrough on the
modulator output, degrading system performance. If the
configuration of Figure 38 is used, the Aux DACs can be used to
compensate for this dc offset, thus reducing LO feedthrough. A
lowpass or bandpass filter is recommended when spurious signals
from the DAC (distortion, DAC images) at the quadrature
modulator inputs may affect the system performance. This filter
should be placed at the quadrature modulator inputs.
Figure 36 . Reference Circuitry
where IFS is equal to;
Rev. PrG | Page 22 of 46
Preliminary Technical Data
AD9779
AUX
DAC1
IOUT1_P
AUX1_P
AUX1_N
IDAC
Quad Mod
I Inputs
IOUT1_N
Quad Mod
Q Inputs
IOUT2_P
QDAC
IOUT2_N
AUX2_P
AUX2_N
AUX
DAC2
edge of TxEnable. That is, to achieve IQ synchronization, TxEnable
should be held low until an I data word is present at the inputs to
data port one. A rising edge of TxEnable will now synchronize the I
Q data into the AD9779. TxEnable can remain high and the input
IQ data will remain synchronized. To be backwards compatible
with previous DACs from ADI, such as the AD9777 and AD9786,
the user can also toggle TxEnable once during each data input
cycle, thus continually updating the synchronization. If TxEnable is
brought low and held low for multiple DACCLK cycles, then the
AD9779 will flush the data in the interpolation filters, and will shut
down the digital engine after the filters are flushed. The amount of
DACCLK cycles it takes for the AD9779 to go into this power down
mode is then a function of the length of the equivalent 2×, 4×, or
8× interpolation filter. The timing of TxEnable, I/Q Select and filter
flush and digital power down are given in
Figure 38. Typical Use of Auxiliary DACs
interleaved input data
Power Dissipation
I
Q
I
Q
TxEnable
Figure 21 through Figure 29 show the power dissipation of the 1.8V
and 3.3V digital and clock supplies in single DAC and dual DAC
modes. In addition to this, the power dissipation/current of the
3.3V supply (mode and speed independent) in single DAC mode is
102mW/31mA. In Dual DAC mode, this is 182mW/51mA.
Power Down and Sleep Modes
The AD9779 has a variety of power down modes, so that the digital
engine, main TxDACs, or auxiliary DACs can be powered down
individually, or all at once. Via the SPI port, the main TxDACs can
be placed in sleep or power down modes. In sleep mode, the
TxDAC output is turned off, thus reducing power dissipation. The
reference remains powered on though, so that recovery from sleep
mode is very fast. With the power down mode bit set (register 00h,
bit 4), all analog and digital circuitry, including the reference, are
powered down. The SPI port remains active in this mode. This
mode offers more substantial power savings than in sleep mode,
but the time to turn on is much longer. The Auxiliary DACs also
have the capability to be programmed via the SPI port into sleep
mode.
The auto power down enable bit (register 00h, bit 3) controls the
power down function for the digital section of the AD9779. The
auto power down function works in conjunction with the TxEnable
pin (pin 39) according to the following;
TxEnable can remain high or
toggle for IQ synchronization
Figure 39. AD9779 TxEnable Function
The TxEnable function can be inverted by changing the status of
reg 02h bit 1.
Internal PLL Clock Multiplier / Clock Distribution
The internal clock structure on the AD9779 allows the user to drive
the differential clock inputs with a clock at 1x or an integer multiple
of the input data rate, or at the DAC output sample rate. A PLL
internal to the AD9779 provides input clock multiplication and
provides all of the internal clocks required for the interpolation
filters and data synchronization.
The internal clock architecture is shown in Figure 40. The
reference clock is the differential clock at pins 5 and 6. This clock
input can be run differentially, or singled ended by driving pin 5
with a clock signal, and biasing pin 6 to the mid swing point of the
signal at pin 5. There are various configurations in which this clock
architecture can be run;
1.
TxEnable (pin 39) =
0: auto power down enable =
0: Flush data path with zeroes
1: Flush data for multiple DACCLK cycles, then
automatically place digital engine in power down state,
DACs, reference, and SPI port are not affected.
1: Normal operation
The TxEnable bit is dual function. In dual port mode, it is simply
used to power down the digital section of the AD9779. In
interleaved mode, the IQ data stream is synchronized to the rising
Flushing interpolation
filters
Power down
digital section
2.
Rev. PrG | Page 23 of 46
PLL Enabled (reg 09h, bit 7=1) – The PLL enable switch
in Figure 40 is connected to the junction of the dividers
N1 (PLL VCO Divide Ratio) and N2 (PLL Loop Divide
Ratio). Divider N3 determines the interpolation rate of
the DAC, and the ratio N3/N2 determines the ratio of
Reference Clock/Input Data Rate. The VCO runs
optimally over the range 1.0GHz to 2.0GHz, so that N1 is
used to keep the speed of the VCO in this range, even
though the DAC sample rate may be lower. The loop filter
components are entirely internal and no external
compensation is necessary.
PLL Disabled (reg 09h, bit 7=0) – The PLL enable switch
in Figure 40 is connected to the Reference Clock Input.
AD9779
Preliminary Technical Data
The differential reference clock input will be the DAC
output sample rate and N3 will determine the
interpolation rate.
ADC
reg 0Ah (4:0)
Loop Filter
Bandwidth
Reference Clock
(pins 5 and 6)
PHASE
DETECTOR
reg 08h (7:2)
VCO Range
INTERNAL
LOOP
FILTER
÷N2
÷N1
reg 09h (4:3)
PLL Loop
Divide Ratio
reg 09h (6:5)
PLL VCO
Divide Ratio
reg 0Ah (7:5)
PLL Control
Voltage Range
VCO
DAC
Interpolation
Rate
÷N3
PLL Enable
(reg 09h (bit 7))
reg 01h (7:6)
DATACLK out
(pin 37)
Internal DAC Sample
Rate Clock
Figure 40. Internal Clock Architecture of AD9779
Rev. PrG | Page 24 of 46
Preliminary Technical Data
AD9779
Figure 43 shows the timing specifications for the AD9779 when the
PLL is disabled. The reference clock is at the DAC output sample
rate. In the example shown in Figure 43, if the PLL is disabled, the
interpolation is 4x.. The set up and hold time for the input data are
with respect to the rising edge of DATACLK out. Note that if reg
02h, bit2 is set, DATACLK out is inverted so the latching clock edge
will be the DATACLK out falling edge.
Timing Information
Figure 41 through Figure 43 show some of the various timing
possibilities when the PLL is enabled. The combination of the
settings of N2 and N3 means that the reference clock frequency
may be a multiple of the actual input data rate. Figure 41 through
Figure 43 show, respectively, what the timing looks like when
N2/N3 = 1, and 2.
Refe rence Clock
tD
DATA CLK out
tS
tH
Input Data
Figure 41. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 1x Input Sample Rate1
Refe rence Clock
tD
DATA CLK out
tS
tH
Input Data
Figure 42. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 2x Input Sample Rate1
Refe rence Cloc
tD
DATA CLK out
tS
tH
Input Data
tS= 3.2n s min
tH= - 1.6n s min
tD=5.0ns typ
(DATACLK DELAY disabled)
Figure 43. Timing Specifications for AD9779, PLL Disabled, 4x Interpolation1
1
For an in depth description of how TxDAC timing specifications are specified, please read Analog Devices, application note AN748, Set up and Hold Measurements in
High Speed CMOS Input DACs.
Rev. PrG | Page 25 of 46
AD9779
Preliminary Technical Data
Interpolation Filter Architecture
10
The AD9779 can provide up to 8× interpolation or disable the
interpolation filters entirely. The coefficients of the low pass filters
and the inverse sinc filter are given in Table 5, Table 6, Table 7, and
Table 8. Spectral plots for the filter responses are given in Figure 3,
Figure 4, and Figure 5.
0
-10
-20
-30
-40
With the interpolation filter and modulator combined, the
incoming signal can be placed anywhere within the Nyquist region
of the DAC output sample rate. Where the input signal is complex,
this architecture allows modulation of the input signal to positive
or negative Nyquist regions (refer to Table 13).
-50
-60
-70
-80
-90
The Nyquist regions up to 4× the input data rate can be seen in
Figure 44.
-100
-4
-3×
-2×
-1×
DC
1×
2×
-1
0
1
2
3
4
10
4×
3×
-2
Figure 46. Interpolation/Modulation Combination of -3fDAC/8
Filter in Odd Mode
-8 -7 -6 -5 -4 -3 -2 -1 1 2 3 4 5 6 7 8
-4×
-3
0
Figure 44. Nyquist Zones
-10
-20
Figure 3, Figure 4 and Figure 5 show the low pass response of the
digital filters with no modulation used. By turning on the
modulation feature, the response of the digital filters can be tuned
to any Nyquist zone within the DAC bandwidth. As an example,
Figure 45 to Figure 51 show the odd mode filter responses (refer to
Table 13 for odd/even mode filter responses).
-30
-40
-50
-60
-70
-80
10
-90
0
-100
-4
-3
-2
-1
0
1
2
3
4
-10
Figure 47. Interpolation/Modulation Combination of -2fDAC/8
Filter in Odd Mode
-20
-30
-40
10
-50
0
-60
-10
-70
-20
-80
-30
-90
-40
-100
-4
-3
-2
-1
0
1
2
3
-50
4
-60
-70
Figure 45. Interpolation/Modulation Combination of -4fDAC/8
Filter in Odd Mode
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
Figure 48. Interpolation/Modulation Combination of -1fDAC/8
Filter in Odd Mode
Rev. PrG | Page 26 of 46
4
Preliminary Technical Data
AD9779
10
Even mode filter responses allow the passband to be centered
around ±0.5, ±1.5, ±2.5 and ±3.5 FDATA. Switching from and odd
mode response to an even mode filter response does not modulate
the signal. Instead, the pass band is simply shifted. As an example,
picture the response of Figure 51, and assume the signal in band is
a complex signal over the bandwidth 3.2 to 3.3×FDATA. If the even
mode filter response is then selected, the pass band will now be
centered at 3.5×FDATA. However, the signal will still remain at the
same place in the spectrum. The even/odd mode capability allows
the filter passband to be placed anywhere in the DAC Nyquist
bandwidth.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
4
Figure 49. Interpolation/Modulation Combination of fDAC/8
Filter in Odd Mode
10
0
With reg 2, bit 6 set, the AD9779 accepts interleaved data on port
one in the sequence I, Q, I, Q……. Note that in interleaved mode,
that the channel data rate at the beginning of the I and the Q data
paths are now ½ the input data rate, due to the interleaving. The
max input data rate is still subject to the maximum specification of
the AD9779. This limits the synthesis bandwidth available at the
input to the AD9779 in interleaved mode.
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-4
The AD9779 is a dual DAC with an internal complex modulator
built into the interpolating filter response. In dual channel mode,
the AD9779 expects the real and the imaginary components of a
complex signal at digital input ports one and two (I and Q
respectively). The DAC outputs will then represent the real and
imaginary components of the input signal, modulated by the
complex carrier FDAC/2, FDAC/4 or FDAC/8.
-3
-2
-1
0
1
2
3
4
With reg 02h, bit 5 (REAL MODE) set, the Q channel and the
internal I and Q digital modulation are turned off. The output
spectrum at the IDAC then represents the signal at digital input
port one, interpolated by 1×, 2×, 4×, or 8×.
The general recommendation is that if the desired signal is within
±0.4*FDATA, that the odd filter mode should be used. Outside of
this, the even filter mode should be used. In any situation, the total
bandwidth of the signal should be less than 0.8*FDATA.
Figure 50. Interpolation/Modulation Combination of 2fDAC/8
Filter in Odd Mode
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
4
Figure 51. Interpolation/Modulation Combination of 3fDAC/8
Filter in Odd Mode
Rev. PrG | Page 27 of 46
AD9779
Preliminary Technical Data
Using Data Delay to Meet Timing Requirements
In order to meet strict timing requirements at input data rates of up
to 300MSPS, the AD9779 has a fine timing feature. Fine timing
adjustments can be made by programming values into the DATA
CLOCK DELAY register (reg 04h, 7:4). This register can be used to
add delay between the DACCLK in and the DATACLK out. Figure
52 shows the default delay present when DATACLK DELAY is
disabled. The disable function bit is found in reg 02h, bit 4. Figure
53 shows the delay present when DATACLK DELAY is enabled and
set to 0000. Figure 54 indicates the delay when DATACLK DELAY
is enabled and set to 1111. Note that the set up and hold times
specified for data to DATACLK in the datasheet are defined for
DATACLK DELAY disabled.
Figure 54. . Delay from DACCLK to DATACLK out with CLK DATA DELAY =
1111
The difference between the min delay of Figure 53 and the
maximum delay shown in Figure 54 is the range programmable via
the DATACLK DELAY register. The delay (in absolute time) when
programming DATA CLK DELAY between 0000 and 1111 is a
linear extrapolation between these two figures. (typically 175ps225ps per increment to DATA CLK DELAY).
The frequency of DATACLK out depends on several programmable
settings. Interpolation, zero stuffing and interleaved/dual port
mode all have an effect on the DACCLK frequency. The divisor
function between DACCLK and DATACLK is equal to;
Figure 52. Delay from DACCLK to DATACLK with DATACLK DELAY disabled.
Interpolation
Zero Stuffing
Input Mode
Divisor
1
disabled
dual port
1
2
disabled
dual port
2
4
disabled
dual port
4
8
disabled
dual port
8
1
disabled
interleaved
Invalid
2
disabled
interleaved
1
4
disabled
interleaved
2
8
disabled
interleaved
4
1
enabled
dual port
2
2
enabled
dual port
4
4
enabled
dual port
8
Figure 53. Delay from DACCLK to DATACLK out with CLK DATA DELAY = 0000
Rev. PrG | Page 28 of 46
Preliminary Technical Data
AD9779
8
enabled
dual port
16
1
enabled
interleaved
1
2
enabled
interleaved
2
4
enabled
interleaved
4
8
enabled
interleaved
8
The maximum divisor resulting from the combination of the above
table, and the DATACLK divide register, is 32.
Data Input Synchronization
The AD9779 also allows the user to determine how close the data
input timing is to the edge of the timing window (i.e., valid data set
up and hold times). Figure 55 represents a functional block diagram
of this circuitry. Data is effectively sampled at a time tD before and
after the clock edge. These two samples are compared. If both
values are equal, the XOR gate will indicate a logic 0 for valid
timing. Note that the Input Data Sampling Clock is the same signal
as the DATACLK out, but without the delay programmed via the
DATA CLOCK DELAY register. The time delay is programmable
via register reg 03h, bits 3:0 (INPUT DATA TIMING ERROR
TOLERANCE). The value of the XOR output is registered in reg
19h, bit 7 (DATA DELAY IRQ) when DATA DELAY IRQ ENABLE
( reg 19h, bit 3) is true.
In addition to this divisor function, DATACLK can be divided by
up to an additional factor of 4, according to the state of the DATA
CLK DIVIDE register (reg 03h, 5:4), as follows;
Reg 03h (5:4)
Divider Ratio
00
1
01
2
10
4
11
1
INPUT DATA
INPUT DATA
SAMPLING CLOCK
(DCLK_SMP)
D
PROGRAMMABLE
DELAY
PROGRAMMABLE
DELAY
FF1
Q
CLK
reg 03h, bits 3:0
IRQ, reg 19h, bit 7
IRQ enable is reg 19h, bit 3
D
FF2
Q
FF3
Q
CLK
D
REGISTERED
DATA
CLK
Figure 55 AD9779 Data Input Synchronization Logic
Manual or Automatic Input Timing Correction
Correction of input timing can be achieved manually, or the
AD9779 can be programmed to automatically correct if it senses an
error. The correction function is controlled via register 03h, bits 7:6.
The function is programmed as follows;
Reg 03h (7:6)
Function
00
Error check disabled
01
Manual correction
10
Automatic, one pass check
11
Auto, continuous pass check
With manual correction, DATA DELAY IRQ must be polled to
determine if timing is being violated. Necessary corrections can be
made by adjusting DATACLK DELAY and the DATACLK INVERT
bit (reg 2, bit 2). When doing initial timing verification, the user
should set INPUT DATA TIMING ERROR TOLERANCE (reg 03h,
3:0) to 1111. DATACLK DELAY can then be swept to find the
range over which the timing is valid. The final value for DATA
DELAY should be the value that corresponds to the middle of the
valid timing range. If a valid timing range is not found during this
sweep, the user should invert the DATACLK INVERT bit and
repeat the process. If a valid timing window is still not found, then
INPUT DATA TIMING ERROR TOLERANCE should be
decremented by one, and the procedure should be repeated.
In auto correction mode, the AD9779 will automatically sweep
DATACLK DELAY as soon as the value 11 is programmed into
Rev. PrG | Page 29 of 46
AD9779
Preliminary Technical Data
DATACLK DELAY MODE (03h, 7:6). The user should initially set
INPUT DATA TIMING ERROR TOLERANCE to 1111, then set
DATACLK DELAY to 11 to initiate the automatic timing sweep.
The AD9779 will then sweep DATACLK DELAY from 0000 to
1111. If the value for IRQ initially indicates that the timing is valid
(set up and hold times are being met) then the sweep will stop
immediately. Otherwise, the sweep will continue until IRQ
indicates that the timing is valid. If the sweep completes and a valid
timing region is not found, then the user should invert DATACLK
INVERT and repeat the operation. If this is still not successful, then
the user should decrement INPUT DATA TIMING ERROR
TOLERANCE and rewrite 11 to DATACLK DELAY MODE.
Multi-DAC Synchronization
SYNC Pulse Generation (Master Devices)
In applications where multiple AD9779s are used, and need to be
synchronized together, the AD9779 provides a flexible
synchronization engine. There are two options for multi DAC
SYNC OUT DELAY
(reg 04h bit 0; reg 05h, 7:4)
~180ps/increment
synchronization. In the first situation, one AD9779 can be used as a
master, and the rest of the AD9779 devices as slaves. The second
option is that all the AD9779 devices operate as slaves. Both
operations have the same timing restrictions, and there are no
performance tradeoffs for either mode. The following text describes
the Master mode. The differential input clock will drive the master
device, and the master will in turn generate SYNC_O+ and
SYNC_O-. These two signals use LVDS levels to generate a
differential synchronization signal, which will in turn be used to
synchronize all of the slave AD9779 devices. SYNC_O+ and
SYNC_O- must loop back to the sync inputs (SYNC_I+ and
SYNC_I-) of the master for multiple device synchronization. The
master mode is enabled by writing the Sync Driver Enable bit (reg
07h, bit 6) to a logic 1. The SYNC_O signal speed can be an integer
divisor of the DACCLK speed, according to reg 04h, 3:1. Enabling
the AD9779 in slave mode is accomplished by writing the Sync
Receiver Enable bit (reg 07 bit 7) to a logic 1. The timing of the
DAC input clock and the SYNC output signals on the master device
are shown in Figure 56.
SYNC TRIGGERING EDGE
reg 07h, bit 5
1 - rising edge
0 - falling edge
DACCLK
LV DS DA C SY NC OUT (/1)
LV DS DA C SY NC OUT (/4)
LV DS DA C SY NC OUT (/16)
SYNC OUT DIVISOR IS CONTROLLED BY
reg 04h 3:1
000 fDAC/32
001 fDAC/16
010 fDAC/8
011 fDAC/4
100 fDAC/2
101 fDAC/1
110 undefined
111 undefined
Figure 56. AD9779 DACCLK/SYNC Output Timing
Rev. PrG | Page 30 of 46
Preliminary Technical Data
AD9779
The SYNC output pulse must then be distributed from the master
to all of the slave devices. This may require that the user implement
circuitry outside of the AD9779 that splits the LVDS signal. The
splitter delivers the SYNC_O signal from the master to the multiple
slave device SYNC_I pins. A block diagram of this implementation
is shown in Figure 57. The equalization from the CLK source and
SYNC_O to the DACCLK and SYNC inputs of the multiple
AD9779 devices is critical. For the multi-chip synchronization to
operate correctly at maximum specified DAC sample rates, the
DACCLK inputs must be phase aligned to ±100ps. The SYNC_I
inputs must also be phase aligned to ±100ps. At lower DAC sample
rates, this timing alignment can be relaxed
LVDS Driver and Delay
Equalization
CLOCK
SOURCE
The following description of SYNC_IN on the AD9779 slave
devices also applies to the SYNC_I on the master device. The
timing for SYNC_I on the master must match that of the slave
devices. The SYNC IN pulses, as shown in Figure 57, are not
restricted as to their duty cycle. The only restriction is that each
SYNC pulse remain high for at least one DACCLK cycle. However,
the slave DAC receiving the SYNC pulse must know what the speed
of the input SYNC pulse is. The ratio of DACCLK to SYNC_I
speed is determined by the values in INPUT SYNC PULSE
FREQUENCY (reg 05h, 3:1) as follows;
Reg 05h, 3:1
Divider ratio
000
DACCLK/32 (default)
001
/16
010
/8
011
/4
100
/2
101
undefined
110
undefined
111
undefined
SYNC OUT
Master DAC
SYNC IN
EQUALIZATION
SYNC Pulse Receiver (Slave Devices)
DACCLK
SYNC IN
Slave DAC
DACCLK
SYNC IN
Slave DAC
Internal Synchronization in Slave Device
DACCLK
Figure 57. Implementation of SYNC Signal Distribution in Master/Slave mode
EQUALIZATION/FREQUENCY DIVISION
CLOCK
SOURCE
SYNC IN
DACCLK
Slave DAC
EQUALIZATION
SYNC IN
Slave DAC
DACCLK
SYNC IN
Slave DAC
DACCLK
Figure 58. Implementation of SYNC Signal Distribution in Slave mode
The internal timing functions in the slave AD9779 are given in
Figure 59. The duty cycle of the SYNC_I signal is not restricted to
50%. The minimum restriction on duty cycle for SYNC_I is that it
stays high for at least one full DACCLK cycle. Figure 59 shows two
possible SYNC_I signals, one with 50% duty cycle, and one with
minimum duty cycle. More detail on SYNC_I timing restriction
are given later in this section.
DACCLK samples SYNC_I and generates the internal SYNC signal
(SYNC_I_int). The period of SYNC_I_int is always DACCLK/32.
If the rate of SYNC_I is greater than DACCLK/32, then the extra
pulses are stripped off. The example Figure 59 shows SYNC_I
period = DACCLK/16, so that every other SYNC_I pulse is
stripped. DCLK_SMP is the input data sample clock, originally
defined in Figure 55. DCLK_SMP is synthesized by DACCLK, but
synchronized by SYNC_I. Note that there is also a programmable
delay (SYNC INPUT DELAY) between SYNC_I_int and
DCLK_SMP. This programmable delay adds even more flexibility
to the timing interface. The example in Figure 59 indicates that the
interpolation is set to 8× (DCLK_SMP rate is 1/8 that of
DACCLK).
Rev. PrG | Page 31 of 46
AD9779
Preliminary Technical Data
DACCLK_ext
DACCLK_int (prop delay )
SYNC_I_ext_min_duty cy cle
SYNC_I_ext_50%duty cy cle
SYNC_I_int (post SYNC DELAY)
SYNC_I_int (post SYNC DELAY)
SYNC_stripped (post edge detector)
DCLK_SMP
DCLK_OUT
SYNC INPUT DELAY
reg 06h 7:4
(~100ps/increment)
DATA CLOCK DELAY
DAC CLOCK OFFSET
reg 04h, 7:4
reg 07h, 4:0
(1 DACCLK cycle/increment)
Figure 59. Internal and External Timing for AD9779 Master or Slave
SYNC_I Timing Restrictions
In the same way that the AD9779 registers timing errors for the
data input, it can also register timing errors for the SYNC_I signals.
The block diagram for this synchronization logic is given in . This
is very similar to the data input synchronization circuit
given in Figure 59. The difference is that this circuit uses the
DACCLK to properly register SYNC_I. The delay is programmable
via reg 06h, 3:0. IRQ is registered in reg 19h, bit 6.
reg 05h, bit 0, reg 06h (7:4)
SYNC
INPUT
DELAY
D
LVDS differential
SYNC input
DACCLK
(internal
delayed)
PROGRAMMABLE
DELAY
FF1
Q
CLK
reg 06h (3:0)
PROGRAMMABLE
DELAY
Edge detector, detects on
one out of every 32 DACCLK
edges
IRQ, reg 19h, bit 6
IRQ enable is reg 19h, bit 2
D
FF2
Q
CLK
D
FF3
Q
CLK
Figure 60. AD9779 Simplified Internal Synchronization Logic
Rev. PrG | Page 32 of 46
REGISTERED
SYNC_I_int
C76
C20
Rev. PrG | Page 33 of 46
Figure 61. AD9779 Eval Board, Rev D , Power Supply Decoupling and SPI Interface
C22
22UF
16V
DPWR33_IN
TP7
RED
22UF
16V
C21
DVDD33_IN
TP6
RED
22UF
16V
AVDD33_IN
16V
22UF
DVDD18_IN
TP5
RED
C77
16V
22UF
CVDD18_IN
ACASE
ACASE
ACASE
ACASE
TP3
RED
ACASE
RED
TP21
RED
TP20
RED
TP19
.1UF
L6
LC1812
LC1812
L7
.1UF
LC1812
L13
.1UF
LC1812
L14
LC1812
L15
LC1812
EXC-CL4532U1
C48
CC0603
.1UF
EXC-CL4532U1
L5
EXC-CL4532U1
C45
CC0603
LC1812
EXC-CL4532U1
L4
EXC-CL4532U1
C28
LC1812
EXC-CL4532U1
L3
.1UF
.1UF
C42
CC0603
C49
TP9
.1UF
C26
CC0603
.1UF
C70
CC0603
.1UF
C69
CC0603
CC0603
EXC-CL4532U1
C71
CC0603
.1UF
LC1812
EXC-CL4532U1
EXC-CL4532U1
L2
C68
CC0603
CC0603
RED
TP18
RED
TP17
LC1812
TP10
BLK
DPWR33
BLK
DVDD33
TP8
BLK
AVDD33
TP4
BLK
SPI_SDO
SPI_CSB
SPI_CLK
SPI_SDI
DVDD18
TP2
BLK
CVDD18
R55
10K
TP15
DGND2
BLACK
C46
ACASE
TP14
VDDM_IN
RED
RC0805
EXC-CL4532U1
L1
RC0805
TP1
RED
R52
10K
13
SO14
12
74AC14
U6
SO14
2
74AC14
U6
1
10
SO14 11
74AC14
U5
8
9
SO14
74AC14
4
3
SO14
74AC14
U5
6
5
SO14
74AC14
U5
U5
U5
12
SO14 13
74AC14
U5
LC1812
L16
CC0402
EXC-CL4532U1
CC0402
2
1
SO14
74AC14
22UF
16V
C67
.1UF
LC1812
EXC-CL4532U1
L12
R54
R53
R51
.1UF
C66
RC0805
9K
RC0805
9K
RC0805
9K
DGND2
RED
2
TP13
VDDM
S1
1
3
2
3
2
SWSECMA
1
S3
SWSECMA
CSB
SD1
S2
RED
TP16
3
2
3
2
S4
SWSECMA
1
1
SWSECMA
SD0
SCLK
P1
FCI-68898
TJAK06RAP
CLASS=IO
1
2
3
4
5
6
U6
SO14
4
74AC14
U6
11 SO14
10
74AC14
U6
9 SO14
8
74AC14
U6
5 SO14
6
74AC14
3
Preliminary Technical Data
AD9779
EVALUATION BOARD SCHEMATICS
JP13
C78
C7
ACASE
VOLT
C15
1NF
ACASE
4.7UF
VOLT
4.7UF
1
2
R32
RC0603
DPWR33
4
5
Y
VCC
S12
1
RC0603
1
25
GND
A
NC
SN74LVC1G34
2
3
2
1
.1UF
C84
Rev. PrG | Page 34 of 46
S15
DPWR33
2
U11
JP18
3
1
2
1
2
3
J
CLK
K
PRE
74LCX112
15
CLR
R26
100
C32
.1UF
Figure 62. AD9779 Eval Board, Rev D , Circuitry Local to AD9779
Q_
Q
C4
4.7UF
JP7
6
5
4
6PINCONN
22
R58
R59
RC0805
R18
100
U10
4
5
6
CC0402
CLK_N
DVDD33
CC0402
C2
C27
C29
1NF
C12
.1UF
C5
11
J
13
CLK
12 K
PRE
CLR
74LCX112
14
DGND
Q
CC0402
C36
C30
1NF
C13
.1UF
DVDD18
CLK_P
4.7UF
P2D15
1
S16
RC0805
2
22
DPWR33
10
U10
Q_ 7
9
CC0402
CC0402
CC0402
CC0402
C35
C3
VOLT
2
4.7UF
CC0402
CC0402
C10
.1UF
VOLT
C25
1NF
CC0402
C40
DVDD18
4.7UF
ACASE
DVDD33
ACASE
2
CC0402
S11
CC0402
1
C38
.1UF
VOLT
CC0402
CC0402
D1N
ACASE
VOLT
1
2
T4A
TC1-1T
ACASE
9779TQFP
P2D6
1
P
U1
S14
S
P2D5
T4B
ADTL1-12
P2D7
6
P2D4
T3B
ADTL1-12
P2D8
3
2
1
P2D9
4
1
P2D3
3
P2D10
6.3V
C8
P2D2
6
P2D11
4
P2D1
P2D0
T3A
TC1-1T
P2D12
DGND;5
P
P2D13
R63
10K
S
P2D14
6
P2D15
4
2
1
3
2
1
R65
SW1
50
R1
1K
4
3
RC0603
RC1206
JP17
SPI_SDO
R11
50
SPI_SDI
0
SPI_CLK
RED
0
P1D0
VAL
RC0603
R10
50
P1D1
1K
10UF
SPI_CSB
TP11
TP12
RC0603
P1D2
R64
D1P
RED
D2P
P1D3
CR1
R56
10K
RC1206
JP2
P1D4
R8
P1D5
1NF
C18
CC0603
RC0603
R7
P1D6
JP3
P1D7
RC0805
JP8
IOUT2_P
IOUT2_N
D2N
CC0603
S7
AUX2_P
JP4
AUX2_N
IOUT1_P
RC0603
RC0603
AVDD33
IOUT1_N
JP16
P1D8
C1
50
R9
P1D9
CVDD18
C9
.1UF
JP15
P1D10
C14
.1UF
0
R5
AUX1_N
1NF
AUX1_P
C24
4.7UF
C37
.1UF
JP14
P1D11
C31
1NF
RC0603
P1D12
C56
1NF
0
P1D13
C57
.1UF
4
P1D14
P1D15
C58
1NF
R6
CC0402
ADTL1-12
VAL
C55
.1UF
1
2
3
CC0402
C33
1NF
CC0402
TC1-1T
T1A
CC0402
4
CC0402
6
CC0402
C59
1NF
S
VOLT
TC1-1T
T2A
P
ACASE
1
2
3
6
CR2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PAD
T1B
ACASE
VDDA33_100
VSSA_99
VDDA33_98
VSSA_97
VDDA33_96
VSSA_95
VSSA_94
IOUT1_P
IOUT1_N
VSSA_91
AUX1_N
AUX1_P
VSSA_88
AUX2_P
AUX2_N
VSSA_85
IOUT2_P
IOUT2_N
VSSA_82
VSSA_81
VDDA33_80
VSSA_79
VDDA33_78
VSSA_77
VDDA33_76
I120
VREF_74
IPTAT
VSS_72
IRQ
RESET
SPI_CSB
SPI_CLK
SPI_SDI
SPI_SDO
PLL_LOCK
VSSD_64
SYNC_OP
SYNC_ON
VDDD33_61
VDDD18_60
P2D0
P2D1
P2D2
P2D3
P2D4
VSSD_54
VDDD18_53
P2D5
P2D6
PAD
3
VDDC18_1
VDDC18_2
VSSC_3
VSSC_4
CLK_P
CLK_N
VSSC_7
VSSC_8
VDDC18_9
VDDC18_10
VSSC_11
VSS_12
SYNC_1P
SYNC_1N
VSSD_15
VDDD18
P1D15
P1D14
P1D13
P1D12
P1D11
VSSD_22
VDDD18_23
P1D10
P1D9
P1D8
P1D7
P1D6
P1D5
P1D4
P1D3
VSSD_32
VDDD18_33
P1D2
P1D1
P1D0
DCLK
VDDD33_38
TX
P2D15
P2D14
P2D13
VDD18_43
VSSD_44
P2D12
P2D11
P2D10
P2D9
P2D8
P2D7
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ADTL1-12
VOLT
1
ACASE
C62
.1UF
CC0402
6
4.7UF
CC0402
CC0402
RC0603
C61
1NF
C60
.1UF
CC0402
4
CC0402
1
CC0402
6
CC0402
T2B
RC0603
S5
S
CC0402
2
P
CC0402
3
CC0402
1
C6
AD9779
Preliminary Technical Data
4
S6
6
3
1
DPWR33
RC1206
C34
1NF
.1UF
1NF
C39
.1UF
1NF
1NF
C11
.1UF
Preliminary Technical Data
AD9779
R15
C80
C50
17.2PF
2.1PF
CC0603
CC0603
R20
CC0603
L8
40
LC0805
RC0603
C81
2.1PF
JP11
RC0603
55NH
L9
1
P
C52
.1UF
6
R12
150
C73
S
17.2PF
100PF
147.5
MODULATED OUTPUT
4
RC0603
17.2PF
T5
AUX1_P
RC0603
40
CC0603
3
C63
CC0603
C72
C47
VDDM
C41
CC0402
CC0402
ACASE
DGND2
1
2
3
4
5
6
7
8
2
J4
2
2
DGND2
2
VDDM
RC0603
10UF
10V
IBBP
QBBP
IBBN
QBBN
G1A
G4B
G1B
G4A
VPS2
LOIN
LOIP
VOUT
VPS1AD8346 G3
ENBL
G2
RC0603
20
1
DGND2100PF
16
15
14
13
12
11
10
9
R16
D1P
R22
R21
ADTL1-12
R19
RC0603
LC0805
300
RC0603
R4
300
CC0603
55NH
AUX1_N
C53
.1UF
CC0603
R17
150
RC0603
C64
17.2PF
CC0603
RC0603
20
R14
1K
U9
D1N
JP1
DGND2
2
CC0402
DGND2
C74
2
R24
100PF
CC0603
300
CC0603
RC0603
RC0603
R27
C82
R60
40
JP12
LC0805
RC0603
R3
150
R23
D2P
CC0603
C43
17.2PF
C79
17.2PF
40
RC0603
20
Figure 63. AD9779 Eval Board, Rev D , AD8349 Quadrature Modulator
Rev. PrG | Page 35 of 46
DGND2
4
2
2
JP10
C54
.1UF
RC0603
R61
CC0603
J5
2
DGND2
DGND2
2
AUX2_P
55NH
L11
5
JP9
RC0603
C65
17.2PF
4.5PF
T4
CC0603
RC0603
R25
150
R2
300
55NH
L10
3
P
C75
LC0805
C44
17.2PF
S
1
3
CC0603
AUX2_N
1
2
1
P
CC0603
T3
ADTL1-12
C83
2.1PF
S
20
ETC1-1-13
CC0402
4
RC0603
6
D2N
LOCAL OSC INPUT
100PF
CC0402
C51
.1UF
RC0603
R62
147.5
Preliminary Technical Data
C17
.1UF
CC0402
R30
1K
R31
300
CC0402
C16
DNP
RC0402
RC0402
R28
25
5
R13
VAL
4
P
T2
ETC1-1-13
CC0402
3
2
S
1
CC0402
C19
.1UF
25
RC0402
R29
RC0402
C23
.1UF
CVDD18
CLK_P
CLK_N
AD9779
J1
2
1
RC0402
Figure 64. AD9779 Eval Board, Rev D , DAC Clock Interface
Rev. PrG | Page 36 of 46
Rev. PrG | Page 37 of 46
B17
B18
B19
B20
B21
B22
B23
B24
B25
A17
A18
A19
A20
A21
A22
A23
A24
A25
PKG_TYPE=MOLEX110
VAL
B16
A16
PKG_TYPE=MOLEX110
VAL
B15
A15
B8
A8
B11
B7
A7
A11
C9
B6
A6
B9
B5
A5
B10
B4
A4
A9
B3
A3
A10
C8
B2
A2
P4
Figure 65. AD9779 Eval Board, Rev D, Digital Input Buffers
DGND
BLK
PKG_TYPE=MOLEX110
VAL
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C11
C10
C7
C6
C5
C4
C3
C2
C1
P4
B1
P4
A1
DGND1
BLK
P1D0
P1D2
P1D4
P1D6
P1D8
P1D10
P1D12
P1D14
CSB
SD1
P2D0
P2D2
P2D4
P2D6
P2D8
P2D10
P2D12
P2D14
E17
E18
E19
E20
E21
E22
E23
E24
E25
D17
D18
D19
D20
D21
D22
D23
D24
D25
PKG_TYPE=MOLEX110
VAL
E16
D16
PKG_TYPE=MOLEX110
VAL
E15
D15
E11
D11
E8
E9
E7
D8
E10
E6
D7
D10
E5
D6
D9
E4
E3
D3
D5
E2
D2
D4
P4
E1
P4
D1
P1D1
P1D3
P1D5
P1D7
P1D9
P1D11
P1D13
P1D15
SCLK
SD0
P2D1
P2D3
P2D5
P2D7
P2D9
P2D11
P2D13
P2D15
Preliminary Technical Data
AD9779
AD9779
Preliminary Technical Data
1
J2
2
U2
1
2
3
4
P2
1
2
ADP3339-1-8
1UF
1UF
CC0603
CVDD18_IN
JP19
CC0603
C85
C86
VAL
CNTERM_2P
U3
1
2
3
1UF
4
JP20
1UF
CC0603
ADP3339-1-8
CC0603
C89
DVDD18_IN
C88
U4
1
2
3
1UF
CC0603
4
DVDD33_IN
JP21
ADP3339-3-3
1UF
CC0603
C92
C91
U7
1
2
3
CC0603
AVDD33_IN
JP22
ADP3339-3-3
1UF
1UF
4
CC0603
C93
C94
U8
1
2
3
1UF
CC0603
C96
1UF
4
DPWR33_IN
JP23
ADP3339-3-3
CC0603
C97
Figure 66. AD9779 Evaluation Board, on board voltage regulators
Rev. PrG | Page 38 of 46
Preliminary Technical Data
AD9779
Figure 67 AD9779 Rev D Eval Board, Top Silk Screen
Rev. PrG | Page 39 of 46
AD9779
Preliminary Technical Data
Figure 68. AD9779 Rev D Eval Board, Top Layer
Rev. PrG | Page 40 of 46
Preliminary Technical Data
AD9779
Figure 69. AD9779 Rev D Eval Board, Layer 2
Rev. PrG | Page 41 of 46
AD9779
Preliminary Technical Data
Figure 70. AD9779 Rev D Eval Board, Layer 3
Rev. PrG | Page 42 of 46
Preliminary Technical Data
AD9779
Figure 71. AD9779 Rev D Eval Board, Bottom Layer
Rev. PrG | Page 43 of 46
AD9779
Preliminary Technical Data
Figure 72. AD9779 Rev D Eval Board, Bottom Silkscreen
Rev. PrG | Page 44 of 46
Preliminary Technical Data
AD9779
Outline Dimensions
Rev. PrG | Page 45 of 46
AD9779
Preliminary Technical Data
ESD CAUTION
Warning---Please not that this device in its current form does not meet Analog Devices’ standard requirements for ESD as measured against the
charged device model (CDM). As such, special care should be used when handling this product, especially in a manufacturing environment.
Analog Devices will provide a more ESD-hardy product in the near future at which time this warning will be removed from this datasheet.
ORDERING GUIDE
Model
AD9779BSV
AD9779BSVZ
AD9779BSVZRL
AD9779-EB
Temperature Range
-40°C to +85°C (Ambient)
25°C (Ambient)
Description
100-Lead TQFP, Exposed Paddle
100-Lead TQFP, Exposed Paddle, Lead Free
100-Lead TQFP, Exposed Paddle, Lead Free, reel
Evaluation Board
Table 15: Ordering Guide
Rev. PrG | Page 46 of 46
PR05363-0-4/05(PrG)
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.