Table 1. Table of ultra high speed analog-to-digital converter chips, the last three entries are
inexpensive comparators, essentially 1-bit ADCs.
fs (GSa/s) BW (GHz)
# bits
Manuf.
Part #
⇠cost
5
2.0
8
e2v
EV8AQ160
$300
10
20
4
Adsantec ASNT7120-KMA $800
3500
12.5
8
8
Maxtek
—
$17k
20
8
5
e2v
EV5AS210
$7k
3000
20
13
8
Agilent
—
https://www.cfa.harvard.edu/twiki5/view/SMAwideband
20
10
3+ oflow
Hittite
HMC5401LC5
$5k
30
14
6
Micram
ADC30
$10k
2500
56
15
8
Fujitsu
CHAIS
—
20
10 flexibly
1
Hittite
HMC874LC3C
$40
The SMA Wideband Astronomical ROACH2 Machine (SWARM) processes 4 GHz usable in single polarization
mode,
reconfigurable
as
full
Stokes
dual
2000
12.5
14
1
Inphi
1385DX
—
SMA
polarization. It uses open source technology from the Collaboration for Astronomy Signal Processing and
(CASPER).
A25707CP
4.6 GSa/s analog25 Electronics
18 Research
1
Inphi
—
SWARM: A Compact High Resolution CASPER Correlator and Wideband VLBI Phased Array
AD
EM
IA SINIC
A
SMITHSONI
AN
OPHYSICA
TR
L
O
AS
VATORY
ER
BS
C
A
Instantiated Multipliers
SWARM Development Team, SAO & ASIAA & SMA, Cambridge, MA and Hilo, HI
A
IA
1500
to-digital converter board uses a commercial chip from e2v on a PCB designed by ASIAA. The DSP platform is the second generation Reconfigurable Open
Architecture Computing Hardware (ROACH2). Each of two channels per ROACH2 sample a 2.3 GHz Nyquist band from a1000custom block downconverter.
due to misalignment in o↵set, gain, phase (OGP), or threshold Integral Non-Linearity (INL).
All the cores are clocked by the same external clock input. In the single-channel mode, the
D = 32
500
in-phase 1.25 GHz clock is sent to ADC core A and an inverted 1.25 GHz clock is sent to core B.
D = 64
The 90 and 270 degree phase shifted clock signals are sent to cores C and D respectively. This
D = 128
0
interleaved mode has an equivalent sampling
frequency
GSa/s.2000A CASPER
compatible
500
1000of 5 1500
2500
3000
3500
4000
of PFB channels
printed circuit board is available based on this ADC, designed Number
by Jiang
et al. [28]. Reference
[27] details how the OGP and INL corrections are derived, and figure 8 shows the improvement
3500
in Spurious Free Dynamic Range (SFDR)
Signal
Noise and
Distortion
(SINAD)
whichfor various
Fig. 3. and
Number
of to
multipliers
versus
number of
PFB channels
can be obtained using these corrections.
values of demux. The dashed line is the upper limit if multipliers are
3000
Looking ahead, we are presently
developing
PCB
based
onROACH
the 262. GSa/s Hittite
implemented
usinga DSP
slices
on the
HMCAD5831 3-bit single core ADC with an FMC (Vita 57.1) standard interface to the Xilinx
VC709 evaluation board. The VC709 2500
is based on the XC7VX690T FPGA which includes 80
GTH multi-gigabit serial transceivers, ten of which are brought out to the FMC. The GTH
transceiver is a sophisticated subsystem capable of transmitting and receiving serial data at rates
2000
M
= D have
log N D + |{z}
TD
2D for
(3)
PFB
up to 13.1 Gb/s per channel. Both transmitter
and
receiver
blocks essential
|{z}
| {z2 functional
}
reliable transmission of data across this interface—these necessary
are not
available in
optimization
FIR
FFT features
prior generations of SERDES transceiver,
1500 for example those on the Xilinx Virtex 6 family which
is used on the CASPER ROACH2. The most important thing to note from this equation is that
EV8AQ160
reening
• Temperature Range for Packaged Device
• Commercial C Grade: 0° C < Tamb < 70° C
plications
• High-speed Oscilloscopes
CASPER Packetized FX Correlator and Beamformer
(https://casper.berkeley.edu/)
Figure 1-1. Simplified Block Diagram
Block Diagram
2.5 GHz
Clock
Clock
Buffer
+
Selection
+
SDA
LVDS Buffers
1:1 or 1:2 DMUX
8-bit
1.25 Gsps
ADC core
Gain
8-bit
1.25 Gsps
ADC core
Gain
T/H
Offset
Quad
Description
Gain
8-bit
1.25 Gsps
ADC core
Gain
T/H
Phase
Offset
LVDS Buffers
1:1 or 1:2 DMUX
8-bit
1.25 Gsps
ADC core
T/H
Phase
Serial
Peripheral
Interface
LVDS Buffers
1:1 or 1:2 DMUX
Phase
Offset
Instantiated Multipliers
LVDS Buffers
1:1 or 1:2 DMUX
T/H
Phase
Offset
SWARM installation in laboratory,
fed by sophisticated phase agile
antenna simulator (J. Test poster)
Analog MUX
(Cross Point Switch)
since
1000 the pipelined stages divide their computation over N/D
4.2. SMA Wideband Astronomical ROACH2
Machine
clock cycles
the total number of multipliers only grows with
core interleaved e2v ADC EV8AQ160
The Quad ADC is constituted by four 8-bit ADC cores which can be considered independently (fourchannel mode) or grouped by two cores (two-channel mode with the ADCs interleaved two by two or
one-channel mode where all four ADCs are all interleaved).
D = 32 is
N 500
as log N . The main contributer to multiplier utilization
All four ADCs are clocked by the same external input clock signal and controlled via an SPI (Serial
Peripheral Interface). An analog multiplexer (cross-point switch) is used to select the analog input
depending on the mode the Quad ADC is used.
SWARM block
(above)
and
specifications
demux
factor.(below).
Tablediagram
2. instead
Table
ofthe
SWARM
specifications
Feature
Number of antennas
Bandwidth per receiver
Number of sidebands
Simultaneous receivers
Baselines
Spectral resolution
Fastest dump rate
Phased array bandwidth
The clock circuit is common to all four ADCs. This block receives an external 2.5 GHz clock (maximum
frequency) and preferably a low jitter symmetrical signal. In this block, the external clock signal is then
divided by two in order to generate the internal sampling clocks:
• In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H
• In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz
clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an interleaved
mode with an equivalent sampling frequency of 2.5 Gsps
0846I–BDC–12/10
e2v semiconductors SAS 2010
D = 64
D = 128
Specification
Remarks
Assuming
an 8-tap
FIR
filter,
the 2500
total number
of instanti0
500
1000
1500
2000
3000
3500
4000
8
2
receivers
each.
Number
of
PFB
channels
ated multipliers is governed by D log2 DN +6D. A plot of this
2 GHz
Dual polarization in each side band.
relationship
is shown in Fig. 3 for demux of 32, 64, and 128
2
90-270 Walsh splits SBs, Rx are DSB
along
the
upper
limit
forpolarization
implementing
multipliers
in
Fig.
3. with
Number
of
multipliers
number of
channels
2
Dual
frequency
or
dualversus
230PFB
&the
345
GHz for variou
2
values
of28demux.
line
the
DSP slices,
ondashed
the ROACH
2.upper limit if multipliers ar
56
per2016,
Rx,The
full
Stokes,
112 is
total
implemented
usingNyquist
DSP slices
on thechannels
ROACH 2.
140 kHz
2.3 GHz
/ 16384
0.65 s B. Adders
Single full Walsh cycle
4 GHz
2 GHz ⇥dual pol.
To find the total adders we go through a similar calculation
but noting that the butterflies have 32 as many adders as
=D
logonly
ND
+ TD
2Dtaps and thus(3
PFBthe
multipliersMand
FIR
needs
to sum all
|{z}
| {z2
} |{z}
performs D(T 1) adds.FFT
The total is
shown
below, again with
optimization
FIR
the contributions pointed out,
The most important thing to note from this equation is tha
since the pipelined3stages divide their computation over N/D
APFB = D log2 N D + D(T 1) + |{z}
D
(4)
clock cycles
the total
{z } only grows wit
|2 number
{z
}of |multipliers
reorder
F IR
N as log N . The mainFFT
contributer to
multiplier utilization i
instead the demux factor.
The added D results from extra adders in the block needing
an we
8-tap
FIR
filter, the
offitinstant
FPGA DSP Utilization: Before committingAssuming
to the ROACH2
needed
to understand
thattotal
the bitnumber
code would
the
to do the
final
reordering
of
the FFT
output.
A Asimilar
plot
Virtex 6 SX475T FPGA. Utilization is dominated
by
the
PFB,
(an
FFT
with
improved
channel
isolation).
hard
reality
ated multipliers is governed by D log2 DN +6D. A plot of thi
to
Fig.
3
can
be
shown
for
the
adders
however
it
would
look
is that the FPGA cannot run nearly as fast as the ADC. So D (demultiplex factor) of parallel streams are processed. D is
relationship
is shown
in Fig. 3 for demux of 32, 64, and 12
also the ratio of ADC to FPGA clock rate.essentially
Bandwidth (~D)
much more expensive than spectral resolution (~1/N).
the issame.
along with the upper limit for implementing the multipliers i
See https://www.cfa.harvard.edu/twpub/SMAwideband/MemoSeries/sma_wideband_utilization_1.pdf
3500
3000
SWARM ROACH2 assembly with two ADCs
installed, and dual SFP+ networking mezzanine cards.
Instantiated Multipliers
2500
Spurious Free Dynamic Range
(SFDR), Signal to Noise and
Distortion Ratio (SINAD) and Noise
Power Ratio (NPR), and the impact of
of quad core alignment (offset, gain and
phase, OGP, and Integral NonLinearity, INL) (Patel et al., JAI, 3, 1)
2000
1500
1000
D = 32
D = 64
D = 128
500
0
SWARM on Mauna Kea, and first light
fringe on maser source MWC349.
500
1000
1500
2000
2500
Number of PFB channels
3000
3500
4000
2