Advanced Imager Technology Development at MIT Lincoln Laboratory Vyshnavi Suntharalingam vyshi@LL.mit.edu Barry E. Burke, James Gregory, Robert K. Reich MIT Lincoln Laboratory Detectors for Astronomy, ESO Garching 12-16 October 2009 MIT Lincoln Laboratory ESO-DFA-1 VS 10/13/09 The MIT Lincoln Laboratory portion of this work was performed in part under a Collaboration Agreement between MIT Lincoln Laboratory and University of Hawaii (Pan-STARRs), sponsored in part by NASA, and the Air Force under the Department of the Air Force contract number FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government. Outline • Overview of MIT-LL X-ray, visible to NIR imaging technology – Tiled CCD Imagers for astronomy – Devices for adaptive optics – Back-illumination processes • Next-generation technologies – Stitched large-format, small-pixel CCDs – Four-side abuttable CCD and 3-D CMOS image sensors • ESO-DFA-2 VS 10/13/09 Summary MIT Lincoln Laboratory Imaging Devices at MIT Lincoln Laboratory Program Areas Space- and Ground-based Surveillance and Scientific Imagers Silicon Photon Counting Arrays High-Speed Imaging • Curved CCDs • Orthogonal Transfer Arrays • High-speed camera electronics • High-fill-factor APDs • Large-format, small-pixel • CMOS ROIC for photon counting • CMOS x-ray sensor imagers • Single-electron sensitive readout • Multi-sample CCD Technology Elements Detector Design ESO-DFA-3 VS 10/13/09 Silicon Detector Process Development Advanced Packaging Electronics MIT Lincoln Laboratory Microelectronics Facility Upgrade to 200-mm Silicon Wafer Size • Three-year capability upgrade in progress – First 200-mm device lots beginning Feb. 2011 • Nine CCID-20s on a 200-mm wafer – 15-m pixel, 2K x 4K, 32mm x 63mm CCID-20 CCID-20 illustration 100-mm wafer Two devices (2K x 4K) ESO-DFA-4 VS 10/13/09 150-mm wafer Six devices 200-mm wafer Nine devices MIT Lincoln Laboratory Tiled CCD Imagers for Astronomy 12-CCD UH/CFHT FPA 100Mpix 60 Orthogonal-Transfer CCDs Pan-STARRs (3° WFOV) 1.36 Gpixels Image from First Light (August 2007) 1.2 mm 200 m ESO-DFA-5 VS 10/13/09 MIT Lincoln Laboratory Lincoln Laboratory High-Speed CCDs for Adaptive Optics 1985 1990 1995 2000 2010 2005 First AO devices 6464, 4 ports 128128, 16 ports Electronic shutter ESO-DFA-6 VS 10/13/09 256256, 32/64 ports (in design) CCD for curvature wavefront sensing 160160, 20 ports; pJFET sense amplifier Polar-coordinate imager (in design) CCD and camera electronics MIT Lincoln Laboratory Amplifier read noise (rms electrons) Performance of pJFET-based Output Circuit Output Data Rate (MHz) Noise: pJFET vs. nMOSFET ESO-DFA-7 VS 10/13/09 MIT Lincoln Laboratory Output Circuit Comparison Sense-node capacitance is lower (higher responsivity) for JFET than MOSFET ESO-DFA-8 VS 10/13/09 Noise spectral voltage is lower for JFET than MOSFET MIT Lincoln Laboratory Back Illumination Processes MBE and Laser Anneal (IILA) External QE MBE Delivers Reflection-Limited QE 0.8 0.7 Reflectance Limit 0.6 0.5 MBE No ARC here 0.4 0.3 0.2 Room Temperature (20°C) Result 60-sec Integration Time Wafer-level Image of Buckman Tavern Front Illuminated 0.1 200 Dark Current (A/cm2) 1.E-08 300 400 500 600 700 800 Wavelength (nm) 900 1000 1100 MBE backside dark current 10x better than IILA Clock dithering can suppress front interface states (IS) 1.E-09 1.E-10 1.E-11 Vignetting from test setup 1.E-12 IILA-IS ESO-DFA-9 VS 10/13/09 IILABack MBE-IS MBE-Bulk Estimated MBE& Back Bulk Back Dark Current Sources MIT Lincoln Laboratory Outline • Overview of MIT-LL X-ray, visible to NIR imaging technology – Tiled CCD Imagers for astronomy – Devices for adaptive optics – Back-illumination processes • Next-generation technologies – Stitched large-format, small-pixel CCDs – Four-side abuttable, 3-D CMOS image sensors • ESO-DFA-10 VS 10/13/09 Summary MIT Lincoln Laboratory Deeply Scaled CCD Process Technology • Small pixels, low-voltage, CMOScompatible operation • Demonstrated small-array CCDs – Simplified single and two poly fabrication – Reduced pixel dimension (8-, 5-, 2-μm) – ~150,000 e- well capacity for 8-μm pixel at 3V 8-μm pixel Two Poly OTCCD 10μm 5-μm pixel Single Poly OTCCD • Current efforts: Apply to large area devices 10μm – Deep ultraviolet photolithography for submicron features (pixel sizes to 2 m) – Stitching for large format imagers 2-m pixel CCD 10μm ESO-DFA-11 VS 10/13/09 MIT Lincoln Laboratory Large-Format, Modular CCD Imagers • • Example: 3K x 3K OTCCD image sensor with 8m x 8m pixels Pixels with submicron dimensions require high-resolution (248-nm) patterning – • Lithography field size is smaller than device size Design is fractured into functional blocks onto a multi-field reticle and precisely stitched back together on wafer Design Concept ESO-DFA-12 VS 10/13/09 Layout Fractured Functional Blocks Multi-field Reticle Reassembled Design on Wafer MIT Lincoln Laboratory Completed 3K x 3K OTCCD Devices • • • • Large-area devices (26 mm x 50 mm) fabricated with low-voltage CCD technology Stitching methods achieve 35nm (3) precision with 8-m pixel active devices Device test results expected in Dec. 2009 Process technology will be migrated to 200-mm substrates 150 mm Stitched Boundary dual poly OT Image Array single poly Frame Store Reference Image (No Stitching Required) Poly-1 gate channel stop 300 nm 300 nm 8m 1m 1m Stitch boundary ESO-DFA-13 VS 10/13/09 MIT Lincoln Laboratory Four-Side Abuttable 3-D CMOS Image Sensor Development Addressing Conventional Monolithic CMOS Image Sensor 3-D Pixel Light PD pixel PD 3T pixel ROIC Processor Addressing A/D, CDS, … • • • • ESO-DFA-14 VS 10/13/09 Pixel electronics and detectors share area Fill factor loss Co-optimized fabrication Control and support electronics placed outside of imaging area • • • 100% fill factor detector Fabrication optimized by layer function Local image processing – Power and noise management • Scalable to large-area focal planes MIT Lincoln Laboratory Oxide-Bonded 3D-I Technology • • Smaller pixels than bump bonding 100% Fill Factor for Back Illumination Center of Pixel Array Tier-2 Readout SOI Transistor 3-D Via Oxide Bond Tier-1 Detector 50m thick 10m ESO-DFA-15 VS 10/13/09 Single 8-m pixel MIT Lincoln Laboratory Example 3D Imager Demonstrations (1) Two-Tier, CMOS Image Sensor 1024x1024 Array, 8-μm pixel Three-Tier, GmAPD Laser Radar 64x64 Array, 50-μm pixel 10μm Completed Pixel Cross-Sectional SEM 3D Via Transistors Back Illum. Chip Photomicrograph Tier-3: 1.5V SOI CMOS Layer 3D Via Transistors Tier-2: 3.5V SOI CMOS Layer 8μm Tier-1: 30V Back Illuminated APD Layer Target: Cone and Support Post Captured Range Image In Front of Flat Plate Shadow Tier-3 Wafer-probe-leveltest test Wafer-probe-level Off-chip A-to-D Off-chip A-to-D Mockup Tile with ADC Chip ESO-DFA-16 VS 10/13/09 -6 8 mm IEEE ISSCC 2005 IEEE ISSCC 2006 +3 3 feet MIT Lincoln Laboratory Example 3D Imager Demonstrations (2) Seven-Tier, Four-side Abuttable CMOS APS 1024x1024 Array, 8-μm pixel Two-Tier, InGaAs Detector 8-μm pixel Pixel Cross-Sectional SEM ~70μm SOI readout Tier-2: 3.5V SOI CMOS Layer 3D via 8μm Tier-1: InGaAs PIN diode (epi) 64-ch ADC 10 μm InP substrate Photo-response in PIN diode current Fe55 Captured Image at 10fps X-ray histogram 2 (companion two tier sensor) 200 Current (μA) Counts 300 12.6 electrons noise 180 eV 100 From temporary support IEEE ISSCC 2009 ESO-DFA-17 VS 10/13/09 0 20 40 60 80 Signal (mV) IEEE Trans. Elec. Dev.2009 100 1 0 Dark -1 -2 -2.0 Light -1.5 -1.0 -0.5 0 0.5 IEEE 3DIC 2009 MIT Lincoln Laboratory Bias (V) Summary • Lincoln Laboratory develops tiled CCD imagers with novel architectures for astronomy – First gigapixel focal plane successfully deployed • New device and process improvements continue to increase responsivity and reduce dark current • Next-generation imagers in development – – – – Small pixel, large format, four-side abuttable devices CCD and CMOS-based detectors Back-illuminated, 100% fill factor, 3-D integrated image sensors Advanced package development for higher data rate, tiled image sensors MIT Lincoln Laboratory ESO-DFA-18 VS 10/13/09 Acknowledgments Design Microelectronics Lab Microelectronics Lab Brian Aull Bob Berger Chang-Lee Chen Michael Cooper Brad Felton Kay Johnson Keith Percival Dennis Rathman Bruce Wheeler Doug Young Andy Loomis Chenson Chen Jeff Knecht Donna Yost Kevin Newcomb Keith Warner Dave Astolfi Vladimir Bolkhovsky Ken Belanger Desi Biasella Laurie Briere Marc Brunelle John Burke Joe Ciampi Jeff Decaprio Diane DeCastro Charlie Doherty Pascale Gouker Yvette Grinbush Paul Healey Bob Healey Denise Holohan Sal Ieni John Jarmalowicz Scott Ladd Renée Lambert Debbie Landers Jim Lawless Jamie Mongiello Chuck Monoxelos Alan O’Dea John Pentoliros Segundo Pichardo Joe Powers Sandra Roy Angel Reinold Dolly Shibles Chris Weinberg Peter O’Brien Wendy Ruth T.J. Wlodarczak C. Keast (Solid State Div.) D. Shaver (Solid State Div.) Testing Harry Clark David Craig William McGonagle Dan O’Mara Tony Soares ESO-DFA-19 VS 10/13/09 MIT Lincoln Laboratory Backup ESO-DFA-20 VS 10/13/09 MIT Lincoln Laboratory Tile Block Diagram • • • • • Vertically stacked Pixel readout on Tier-2 Timing control in Stack 64-ch 12-b pipelined ADC Digital output ESO-DFA-21 VS 10/13/09 Light MIT Lincoln Laboratory Finished Tile Stack Appearance Back Illuminated 3-D CMOS Imager 1024 x 1024 pixels 8.3 x 8.3 μm2 pixel 64 analog outputs Programmable Digital Imaging Tile ~70μm 5 layer stack 64 A/D converters Timing & Control 1024x1024 pixels >1 Million vias 144 gold stud bumps 2 x 96 side bus lines 88 POGO pins ESO-DFA-22 VS 10/13/09 MIT Lincoln Laboratory