Analysis of Three-Phase / Three-Level Rectifiers at Low Load and
Discontinuous Conduction Mode
P. Ide, N. Froehleke, H. Grotstollen
W. Korb, B. Margaritis
Institute for Power Electronics and Electrical Drives
University of Paderborn, FB-14 LEA
Pohlweg 47-49, 33098 Paderborn, Germany
Phone & Fax: +49 5251 60 3157
e-mail: ide@lea.uni-paderborn.de
ASCOM ENERGY SYSTEMS
Senator-Schwartz-Ring, 59494 Soest,
Germany
Phone +49 2921 987 592
isc
Abstract-A prominent boost-type three-level topology, which
proved to represent a cost effective and highly efficient solution
for switched mode rectifiers is inspected towards its operation at
discontinuous conduction mode (DCM). This mode of operation
occurs not only at high input voltage in conjunction with low
load currents but even at medium loading in the vicinity of mains
voltage zero crossings. And since the requirements on THD
conflict with the actual behavior of the circuit when operated at
DCM measures are needed for optimization. After reviewing
basic measures to avoid DCM the resemblance to threephase/single-switch boost rectifiers is utilized to control the
circuit. Novel measures to optimize the modulation scheme are
proposed, facilitating the design of even smaller inductors, thus
lowering costs. Selected simulation and measurement results
prove the enhanced modulation scheme.
vNc
isb
vNb
vSa
isa
vSb
vNa L
vSc
DFp
DNp
DMp
Ta
Tb
Tc
iM
Vd
DNm
DFm
DMm
Fig. 1. Three-level rectifier presented in [1] (3-level SMR).
I. INTRODUCTION
Three-phase high power factor switched mode rectifiers
(PFC-SMR) are undergoing rapid development in recent
years due to tough regulations, such as IEC 1000-3-2/4, hard
economic constraints and a large potential market.
Telecommunication devices, electrical drives, welding power
supplies and many types of industrial electronic equipment
need a high amount of electrical power supplied by PFCSMR. In [1] and [3] a three-phase / three-level boost-type
switched mode rectifier (3-level SMR, Fig. 1) is introduced,
characterized by a lower blocking voltage of semiconductor
devices and reduced size of boost inductors. Since only half
of the voltage as compared to the common boost topology is
effective, the switching frequency can be increased yielding a
better current-shaping with a lower THD at reasonable costs.
This is facilitated by the applicability of 500 V Power
MOSFETs or ultrafast low voltage IGBTs though the 3-level
SMR is supplied from 508 Vrms ,L − L maximum mains voltage.
This circuit was implemented as a utility interface in a
10 kW isolated power supply for telecommunication systems,
because this state-of the art topology turned out to combine
high power density due to high switching frequency with high
flexibility, due to facilitating operation in wide range and at
single-phase [8]. This paper explores problems of DCM for
the first time. A detailed analysis of relevant switching states
is described in III. including problems resulting from
interaction between error-amplifiers and modulation scheme.
In III. practical solutions are given verified by selected
measurement and simulation results.
II. DESCRIPTION OF PROBLEM
Contrary to single-phase systems control of the SMR given
above is more complex. Different control concepts have been
presented in [3], [1], [7]. Operating PFC-SMRs in universal
applications leads to the demand to cope with wide input
voltage [8] and load ranges (0 - 100%). Especially at high
input voltage levels and low load DCM cannot be avoided,
but even at medium load levels in the vicinity of mains
voltage zero-crossings DCM can be found. This nonlinear
behavior causes distortion in the current control loops, which
are - contrasting to single-phase systems - more complex to
investigate due to couplings between current and control
loops respectively.
The switching vectors according to the three-level rectifier
shown in Fig. 1 are depicted in Fig. 2, with 19 distinct voltage
vectors representing 27 switching states. Contrary to threelevel inverters at one single switching cycle only 8 spacevectors are applicable. The signs of the input currents
determine those space vectors, that are available during the
next switching cycle (see Fig. 2). Typically the phase-shift δ
between mains voltage v N and rectifier input voltage v s is
small ( δ < 2° ), due to a small inductance L. Fig. 3 shows a
representation of the input currents and voltages via complex
vectors. According to Fig. 3 the maximum phase shift ϕ
between mains voltage v N and input current i s is limited to
ϕ max
ms =57%
= 15°
depending on the modulation index
m s = 3VˆS / Vd . For ms → 1 no phase shift is possible, thus
the possibility to compensate reactive power is limited to
atypical operating conditions. This is not discussed any
further and ϕ = 0 is assumed. According to m s the ratio of
mains voltage to output voltage can be defined as
m = 3 ⋅ Vˆ / V .
N
N
d
β
,,
,,
,
b
gating signal of respective transistor. Because all switching
states except of <000> are selected passively, the phase
currents might become discontinuously. This leads to
additional switching stages, where one or all phase currents
are zero.
In Fig. 4 all switching states according to the gray shaded
hexagon in Fig. 2 are depicted, including the additional states
resulting for DCM. The supplementary state ‘x’ is introduced,
representing no current flow in the related phase. Thus all
respective semiconductors are non-conductive. The signs of
the currents are equal to those in the hatched area in Fig. 2
except of the dashed states. During these states either i sb or
-+-
-+0
-++
0+-
0+0 -0-
++-
+0-
++0 00-
0++
-00
+00
000
ϕN=30
isa>0
isb<0
isc<0
vS
0--
-0+
+--
α, a
i sc are positive. This does not lead to unwanted voltagevectors as long as the respective transistor is in the on-state,
while different signs of the currents lead to unwanted states
and voltage-vectors respectively. In Fig. 4 the states <0+->
and <0-+> for example are depicted. Note, the appearance of
most of the additional states depends on voltage ratio m N
and phase ϕ N .
+-0
--0
--+
0-0
00+
0-+
+0+
ϕN=-30
x-0
x00
+0x
00x
+-+
0+00-
+0-
x0-
c
+x-
+00
Fig. 2. Space vector representation of all possible switching states
without DCM
This limitation of phase shift ϕ is bound directly to the
basic difference between three-level rectifiers and three-level
inverters: not all space-vectors can be applied actively, as the
input currents need to be considered. At nominal operating
conditions and ϕ ≈ 0 the behavior is similar to three-level
inverters.
jωL is
vN
δ
vs
ϕ ϕ
N
γ
is
Fig. 3. Vector representation of input currents and input voltages
Hence, similar modulation algorithms can be applied. But
the dependency on input currents causes problems not only at
low input currents, but also in the vicinity of zero-crossings.
Hence, the zero-crossings of the currents have to be detected
carefully in order to select the right hexagon and switching
states, respectively. ‘+’, ‘0’ and ‘-‘ in Fig. 2 represent the
possible input terminal voltage of the rectifier depicted in Fig.
1, respectively, + Vd / 2 , 0 and − Vd / 2 , if the output voltage
centerpoint is the reference. Note, ‘0’ represents the positve
x0x
000
xxx
+-0-+
0-+-x
0-0
+-0
0x0
0-x
+x0
xx0
0xx
0x-
Fig. 4. Representation of switching states according to gray shaded hexagon
in Fig. 2 including additional switching states at DCM
A. Distortion due to phase-shift γ
The applicable rectifier input voltage v S depends on the
signs of the input currents (see Fig. 2). The exact zerocrossing is difficult to detect, because the sign of the
instantaneous current might be different from the local
average current level. Fig. 6 shows the inductor current of
phase b in the near of a zero-crossing. During the on-state of
the respective switch ( z b = 1 ) current flow in both directions
is possible. The sign of the current during off-state is of
importance, since it determines the applied voltage across
inductors. If e.g. at the zero-crossing of phase b at ϕ N = 30°
the current ib is lagging, then space vector <0−−> is applied
<0+->
D2
<0-->
Ta
D6
Ta
D5 D6
Fig. 5. Unintended voltages might be applied, because the sign of the
instantaneous current during off-state of the switch determines the voltage,
while the average current has a different sign.
The double-ramp comparison control concept presented in
[7] is sensitive to even small phase shifts γ ≠ 0 between
voltage v s and input current i s (see Fig. 3), while γ = 0
leads to a phase shift ϕ between input current i s and input
voltage v s . For small inductance values L and small phase
angles ϕ < 2° as in typical applications, this does not
represent a serious disadvantage.
zb
zc
zc
zb
za
3
2.0
isa
0
isc
-3
Inductor Curent iSb (A)
Inductor Current isb (A)
za
Contrary to single-phase boost-type rectifiers, where DCM
can be found in the vicinity of zero-crossings even at medium
load ranges, the behavior at DCM is much more complex. For
single-phase rectifiers three states have to be distinguished,
‘on’, ‘off’ and no-current flow at DCM. Due to the couplings
between the phases of three-phase systems (ref. to Fig. 4)
many additional states can be found. Thus disturbances in the
current control loop cannot be avoided, as long as it is
designed for CCM. In many applications minimum load
power is specified, hence the boundary between CCM and
DCM should be known.
Pulse pattern
<00->
B. DCM at medium load ranges in the vicinity of the zerocrossings of a single phase current.
Inductor Curents (A)
instead of <0+−>. Thus the sign of the applied voltage is
different, leading to a decrease of the current, while an
increase is intended (ref. to Fig. 5).
3
DCM
isb
0
-3
0.0
time (s)
Fig. 7. Inductors Currents at the boundary between CCM and DCM at
ϕ N ≈ 30° (Simulation result).
2.0
0.0198
0.0199
0.02
time (s)
0.0201
0.0202
Fig. 6. Simulation result of an inductor current at a zero-crossing and gating
signals. The signs of the instantaneous currents may be different from the
local average current level
But even a small phase shift γ causes false pulse pattern
and disturbance of the current control loops respectively. If,
e.g. current ib is leading with a phase shift γ = 1° , that is
equal to 3 switching cycles at f s = 40 kHz , then the
switching state <0+-> is applied instead of the intended state
<0—>. According to Fig. 2 these switching states are very
different, thus one cause of disturbance on the current control
loops becomes obvious. As shown in Fig. 6 the duty-cycle of
the critical state <0--> is very small in relation to the duty
cycle of the equivalent state <+00>. Thus the unintended
voltage and the disturbance of current is not dominant at
nominal operation.
In Fig. 7 the inductor currents at the boundary between
CCM and DCM are depicted. The absolute values of the
average currents i sa and i sc are approximately equal, since
the average value of the current i sb is zero. Discontinuous
behavior of the current i sb can be found during the off-states
of the respective switch ( z b = 0 ) for small duration. These
small duration is neglected when determining the boundary
between DCM and CCM, since the disturbance of the current
control loop is low. If a second current becomes
discontinuously the effects on the current waveforms are
more dominant. The minimum power level depends on the
inductor’s current ripple, which is a complex function of
inductance L , switching frequency f s , mains voltage V N
and output voltage Vd . For analysis at steady-state it is
assumed, that the modulation index equals the mains to
output-voltage ratio ( m s = m N ) and the representative
interval 0° < ϕ N < 30° is selected once again.
Fig. 8 shows the normalized minimum input power
Pnorm = Pin / P0 versus modulation index m s , where
P0 = Vd2 /( f s ⋅ L) . Additionally the ratio of the duty-cycles of
the equivalent states ρ = d + 00 /(d +00 + d 0− − ) has an influence
on the current ripple and minimum input power respectively.
If the duty-cycles of the two redundant switching states are
equal ( ρ = 1 / 2 ), then the ripple is least and the minimum
input power is least. On the other hand, to prevent
disturbances in the vicinity of the zero-crossings only one of
the redundant states should be selected ( ρ = 0 or ρ = 1 ).
Thus the upper curve represents a suitable approximation of
the minimum input power.
ρ=0
0.035
*
vsa
ρ=1
0.03
*
vaub
ρ = 0.25
0.025
ρ = 0.75
0.02
valb
ρ = 0.5
0.015
Fig. 10. Boundary of phase command voltages according to outer hexagon
0.01
0.005
0
0
0.2
0.4
0.6
Modulation index ms ( )
0.8
1
Fig. 8. Normalized minimum input power assuring CCM versus m
modulation index
iNa∗
iNa
kPi
TNi
vNa
C. Influence on current control and modulation section
vaub v
aw
valb
kPi
iNb∗
Modulator
TNi
vbub v
bw
vNb
iNb
vblb
vcub
v0
pulse
pattern
If the limitation of the outer hexagon is also considered,
the boundaries have to be selected according to Fig. 10, e.g.
the outer hexagon is the trajectory of v s . This outer
limitation of the linear operating region is reached at low load
and DCM respectively.
Inductor Current isa (A) Command Voltages (V)
Normalized Input Power Pnorm ( )
the other hand low power and DCM respectively the duty
cycles of the three switches have to be reduced. This is
equivalent to high command voltages v S , thus the boundaries
of the applicable voltages have to be taken into consideration,
e.g. v s is limited to the outer hexagon (Fig. 2). Fig. 9 shows
the current control section with two independent
proportional-integral error-amplifiers current controllers
generating the command phase voltages. This structure is
suitable for analogue implementation due to its simplicity.
The signs of the command voltages and of the respective
currents have to be the same, thus the command voltage is
limited to v sa > 0 for i sa > 0 and vice versa.
vsa*
0.0
vsc*
1.0
isa
0.0
-1.0
0.02
vcw
vclb
Fig. 9. Current control section with two independent proportional-integral
error-amplifiers and modulator-section based on two triangular carrier
signals
Typically the current control section is designed for
Continuous Conduction Mode (CCM) independent of the
modulation scheme. In this case according to Fig. 3 the
rectifiers input voltage is very close to the mains voltage
( m s ≈ m N ), independent of the current or power level. On
vsb*
0.03
time (s)
0.04
Fig. 11. Simulation result, if the command voltages are selected
according to the outer hexagon. Depending on the input voltage
there is still an input current.
That means always two transistors remain in the off-state,
while one is pulsating in the vicinity of the respective mains
voltage’s zero-crossing in a 60°-interval. This leads to a
current flow as long as the instantaneous difference between
two phase voltages is higher than half of the output voltage
( v Na − v Nb > Vd / 2 ). Due to the nonlinear behavior the input
power is still positive, while the THD is increased. Fig. 11
shows the input current i sa , if the command voltages are
selected according to the outer limit. The remaining input
power at the outer boundary depends on the input voltage
level, the inductance L and the switching frequency f s . This
means, if fixed frequency PWM and current mode control is
applied according to Fig. 9, a full load range cannot be
achieved.
Thus, a minimum load power has to be assured or
additional measures have to be implemented (III). Fig. 12
shows
the
normalized
minimum
input
power
2
( P0 = Vd /( f s ⋅ L) ) versus the input to output voltage ratio
Normalized Input Power Pnorm ( )
m N , if the maximum input voltages v s according to Fig. 10
are applied. For m N < 0.5 no input current is possible as
long as only one switch is pulsating. Loads less than the
minimum load level, lead to an increase of the output voltage.
To prevent the circuit from being damaged a carefully
designed overvoltage shutdown is imperative.
0.03
Plim(mN)
0.025
0.02
0.015
0.01
L0
cw0
ls0
cw
f
ls1
Lnom
i0 i1
iL
Fig. 13. Cross-section of stepped core to build up a nonlinear core.
Fortunately, modern core materials like molypermalloy
powder cores or iron powder cores show these characteristics,
hence they seem to be suitable for these applications on one
hand. On the other hand at high power levels and high current
levels respectively the inductors will become more bulky and
expensive than solutions applying standard ferrite cores.
Therefore ferrite cores with stepped air-gaps as depicted in
Fig. 13 represent more practical solutions, nevertheless they
are less cost-efficient than standard ferrite cores. In case of
low current levels the small air gap l s0 determines the
inductance, while at high current levels the small ferrite
bridge saturates. If c w0 << c w the saturated ferrite bridge has
nearly no impact on the inductance at high current levels.
L fs
0.005
4.0
0
0.6
0.7
0.8
Normalized Mains Voltage mN ( )
0.9
1
isc (A)
2.0
0.5
0.0
−2.0
−4.0
III. SOLUTIONS
4.0
2.0
iSb (A)
Fig. 12. Normalized minimum input power for fixed frequency PWM and
v s at the limit of the outer hexagon
0.0
−2.0
−4.0
A. Implementation of nonlinear Inductors
The minimum power levels depend on the product of
inductance and switching frequency. Hence, to prevent the
circuit from operation in DCM at light load or in the vicinity
of the phase-current’s zero-crossings the inductance could be
increased. This would lead to heavy and bulky input
inductors. A common practical solution is to select nonlinear
inductors, where the inductance L( i ) is high at small currents
and low at high currents.
local DCM of isb causes disturbance in iNa
2.0
iNa (A)
1.0
0.0
−1.0
−2.0
4.0
isa (A)
Different solutions have been investigated to achieve
stable and reliable operation even at low load. Typically the
power part is designed and optimized for a certain power
level, thus the measures should basically affect the control
section, especially since it is much more cost-efficient. The
following strategy was chosen: First of all DCM should be
avoided down to a lower power level as depicted in Fig. 8 and
Fig. 12. Below this power level, where DCM in all phases can
be found, a different modulation strategy should be applied.
0.0
−4.0
0.02
0.025
0.03
0.035
0.04
time (s)
Fig. 14. Inductor currents in case of an nonlinear inductor
( Lnom = 250 µH , Vd = 750 V , m N = 0.8 , Pnorm ≈ 1.3% )
A series arrangement of a saturable inductor and an
inductor designed for rated operation may also be a
reasonable solution. An increase of the inductance L
decreases the gain of the current control loop, thus the current
control loop should be designed for nominal inductance to
avoid stability problems at low load. Different characteristics
of nonlinear cores have been investigated by simulation. For
L0 ≈ 2 Lnom the minimum load according to Fig. 8 can be
halved, if i0 is approximately 30% of the current ripple at
nominal operation. A smooth transition between the
inductance levels avoids additional distortion in the current
control loop. Fig. 14 shows a simulation result at low load
with nonlinear inductors. The minimum power level in
halfed, while the current drawn form the mains shows low
distortion.
B. Adaptation of Switching Frequency
Alternatively the switching frequency f s can be used as a
further control variable. DCM can be suppressed to a certain
extend by increasing the switching frequency, e.g. doubled
switching frequency halves the minimum load according to
Fig. 8 and Fig. 12. Of course, this leads to higher switching
losses, but in case of light load efficiency deterioration is
mostly tolerated by industry. Thus an adaptation of the
switching frequency represents a good solution to reduce the
negative impact of DCM at low load. This measure is simple,
easy to implement and very cost-efficient for analogous or
digital implementation of the control-scheme. In case of
digital systems the switching frequency is increased, while the
sampling rate and the computing efforts are kept constant. In
case of analogous control the adaptation can be performed
easily by adding a signal-type transistor and a capacitor in
parallel to the capacitor that adjusts the switching frequency
(see Fig. 15). Contrary the digital systems the cross-over
frequency of the control loops is reduced at analogous
implementation, due to the variable dead time Tt = 1 /(2 ⋅ f s ) .
Along with an increase of switching frequency the dead time
of the current control loop is reduced. This has to be
considered when designing the current error amplifier.
According to experiences with this measure, an adaptation of
the error amplifier is not necessary without any loss of
performance, if the error amplifier design is based on the
(lower) standard switching frequency.
need to be implemented to suppress high frequency
oscillations of the adaptation. Otherwise unstable conditions
due to subharmonic oscillations might occur. According to
Fig. 12 a suitable power limit p N ( m N ) can be found
depending on the input voltage. In wide range applications it
might be useful to adapt this limitation to the input voltage,
otherwise the high currents at low input voltage will reduce
the efficiency at low load considerable.
C.
Resemblance with DCM in Three-Phase /
Single-Switch Converters
An increase of inductance and/or increase of switching
frequency are suitable to assure CCM down to a certain input
power level. At very light load DCM cannot be prevented,
thus an other measure should be activated. In [5] the well
known Three-phase/Single switch boost type SMR is
introduced, those principle of operation is based on DCM.
Basically two states have to be distinguished, during the first
state all three phases are shortened, thus the inductor’s
currents rises linearly, while during the second state the
currents decline to zero passively. The topology investigated
here can be operated in a similar way, if all three switches are
turned on and off simultaneously. That means state <000>
(all three switches are conductive) equals the on-state of the
single-switch topology, while during the off-state states
<+-->, <+x-> or <+-> and <xxx> are applied for
−30° < ϕ N < 30° (see Fig. 4 and Fig. 16). Contrary to CCM,
further switching state have to be considered, where,
depending on the present input voltage levels, one or all
phase current are zero. In [6] a detailed analysis of this threephase/single-switch topology is presented.
<+-->
<000>
<+x->
D1
D1
Ta
Tb
Tc
D6
D5 D6
<xxx>
<+00>
<0-->
D1
Ta
Tb
Plim(v^N)
C1
+
Modulator
C0
Tc
Fig. 16. Switching states equivalent to three-phase/single-switch topology
(<000>, <+-->, <+x->, <xxx>) and additional states to achieve balanced
output voltages (<+00>, <0-->) for v a > 0 > v b > v c
pN
D5 D6
sawtooth
Fig. 15. Adaptation of switching frequency depending on input power p N
However, a suitable condition need to be formulated for
the change of frequency. While it is difficult to generate a
signal, reflecting the actual current amplitudes, a signal
representing the input power is easily accessible. A hysteresis
Applying this principle of operation, basically three items
have to be considered:
Assuring balanced output voltages
The balance of the output voltages has to be assured
( v M = v d + − v d − = 0 ). Theoretically, if the on-times of the
switches are exactly equal, current i M is zero and no
unbalance will occur, but due to different delays of the drive
circuits and transistors the centerpoint might drift slowly.
vM
isa
XOR
Modulator
isb
Vd
XOR
∗
d000
Alternatively the signs of the input voltages can be selected
instead of the input currents, because just a small phase-shift
between input current and input voltage can be assumed. Fig.
18 shows simulation results of the proposed control scheme at
DCM, while Fig. 19 measurement results. An asymmetric
load is connected to the centerpoint drawing 0.1A , which is
compensated by different on-times of the three switches.
The input currents display the typical shape like threephase/single switch topologies. The THD is reduced for this
mode of operation, but due to the low current level the
harmonics are far below the limits of regulations.
Vd
isc
XOR
vNa (100 V / div.)
Fig. 17. Control scheme for DCM with consideration of
output voltage unbalance.
This can be compensated passively by adding resistors in
parallel to the bulk capacitors either or actively by applying
different on-times to the 3 switches. This means, according to
the gray shaded hexagon in Fig. 3 the states <+00> and <0-->
have to be considered for −30° < ϕ N < 30° . State <+00>
isa (1 A / div.)
leads to a negative current i M < 0 , while <0--> causes
i M > 0 . Applying this principle of operation no current
control is necessary, therefore the output voltage erroramplifier sets the duty cycle d 000 (Voltage Mode Control
VMC).
pulse pattern ()
za
input currents (A)
Selection of control mode
A suitable condition was found, to define whether the
standard control scheme with an inner currents control loop
has to be applied or VMC at DCM. Especially the boundary
between these concepts should be as smooth as possible. The
maximum power flow at DCM, which is a nonlinear function
of input to output voltage ratio m N and impedance
zb
zc
4.0
<0-->
isa
2.0
<+x->
0.0
<xxx>
isc
2.0
isb
<000>
<+-->
4.0
0.40556
0.40558
time (s)
Fig. 18. Inductor’s current waveforms at
Fig. 19. Input current and mains voltage in case of VMC according to III. C
Measurement Result at low load.
0.4056
m m = 91% and i M = 0.1A
in detail (simulation result) in case of DCM according to Fig. 17.
Fig. 17 depicts a simple control scheme to assure balanced
output voltages. The signs of the input currents and the sign
of the output-voltage unbalance are selected to apply either
state <+00> or state <0--> for a fixed duration ∆T (bangbang control). Contrary to Three-phase/Single-switch
topologies the input currents have to be sensed, but usually
this causes no additional effort, because the current sense
signal is also needed in case of nominal operation.
Z s = 2π ⋅ f s ⋅ L , need to be determined for the applied input
voltage range. Fig. 20 shows the maximum input power
versus mains voltage for a universal wide-range application.
The smaller the impedance Z s the higher the input power,
i.e. the maximum input power at DCM can be increased by
reducing the switching frequency or vise versa. This might be
helpful, if a „sleep mode“ below a certain power level is
defined, where the switching frequency is lowered. The
selection of the control mode can be implemented similar to
the adaptation of switching frequency by hysteresis.
According to Fig. 20 the maximum input power at the highest
possible input voltage defines a suitable condition to switch
between the control modes. At high input voltages
( m N > 90% ) the maximum power at VMC is lower than the
minimum power at CMC (hatched area). Reducing the
switching frequency to 1/3 of the nominal value increases the
input power at VMC and the input voltage range.
0.04
Normalized Input Power Pnorm ( )
0.035
maximum input power at VMC @ fs / 3
maximum input power at VMC
0.03
0.025
0.02
0.015
,,
,
minimum input power at CMC (outer limit of hexagon )
0.01
0.005
0.3
0.4
0.5
0.6
0.7
0.8
Normalized Mains Voltage mN ( )
0.9
1
Fig. 20. Comparison of normalized maximum input power at VMC
according to III. C (gray shaded area) and minimum input power at CMC
with fixed frequency PWM versus normalized mains voltage.
EMI
If the maximum normalized input power according to Fig.
20 is selected to Pnorm = 1.5% , then the maximum peak
current is approximately as high as the current ripple at CCM
(ref. Fig. 21). Thus, no further EMI-problems are expected as
long as the switching frequency is the same. If the switching
frequency is reduced at VMC, the peak current increases
proportionally. Hence EMI aspects should be checked even at
low load.
Normalized ripple current ( )
0.12
Peak Current at VMC
0.1
0.08
Ripple Current at CCM
0.06
0.04
0.02
0.3
0.4
0.5
0.6
0.7
0.8
Normalized mains voltage mN ( )
0.9
1
Fig. 21. Comparison of Normalized Peak Current at VMC and Ripple
Current at nominal operation (CCM) . I 0 = Vd /( f s ⋅ L )
IV. CONCLUSION
This paper describes the behavior of Three-Level rectifiers
at low load. Discontinuous Conduction Mode in one or all
phases can be found at low load and in the vicinity of zerocrossings. 72 additional switching states can occur at low
load, most of them depend on the input voltage level and
phase angle. Minimum power characteristics for the boundary
between CCM and DCM are presented. After that different
solutions like nonlinear inductors, adaptation of switching
frequency are presented to reduce the minimum power levels.
For very small power levels an alternative modulation scheme
is presented, based on the resemblance with ThreePhase/Single-Switch Converters.
ACKNOWLEDGMENT
The authors from the University would like to express their
acknowledgment to Ascom Energy Systems, Soest and Lust
Drives, Wetzlar for the support in the former project,
wherefrom findings derive in this follow-up project funded
by Ascom Energy Systems (former ABB Power Supplies).
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