使用STM32 设计HMI-硬件 介绍使用STM32提供的硬件资源和软件资源开发人机交互界面HMI的方法 Agenda 一、STM32 HMI设计硬件资源 LCD controller ChromeART accelerator SDRAM interface 二、 STM32 HMI设计软件资源 STemWin IS2T TouchGFX 2 Embedded graphics on STM32F4 OBJECTIVES 4 • Getting familiar with basics of graphics • General LCD connection • Color representation • Layers • Transparency / alpha channels • CLUT • Color keying • Understand how you can benefit from STM32F4’s HW acceleration • Usage of LTDC layer features • Offload CPU by using Chrom-ART • Hardware pixel format conversion 4 STM32F4x9 Block Diagram • Fully compatible with F4x AHB2 (max 180MHz) • 256KB SRAM • FMC with SDRAM + Support 32-bit data and • Audio PLL + Serial Audio I/F • LCD-TFT Controller • Chrom – ART Accelerator • Hash: supporting SHA-2 and GCM • More serial com and more fast timers running at Fcpu JTAG/SW Debug ETM Nested vect IT Ctrl 1 x Systic Timer DMA 80/112/140 I/Os AHB1 (max 180MHz) Bridge 2x6x 16-bit PWM New IPs/Features/more IPs instances 4 x SPI 2 x USART/LIN APB2 Up to 16 Ext. ITs USB 2.0 OTG FS 256KB SRAM External Memory Interface with SDRAM Power Supply LCD Controller Chrom-ART USB 2.0 OTG HS Reg 1.2V POR/PDR/PVD XTAL oscillators 32KHz + 8~25MHz Int. RC oscillators (max 45MHz) 32KHz + 16MHz PLL RTC / AWU 5x 16-bit Timer 4KB backup RAM 2x 32-bit Timer 2x Watchdog 3 x 16bit Timer • 1.71V-3.6V Supply Camera Interface 2x DAC + 2 Timers Synchronized AC Timer (max 90MHz) • 100 pins to 208 pins 2MB Flash Memory Dual Bank Ethernet MAC 10/100, IEEE1588 APB1 Bridge 16 Channels Clock Control Flash I/F CORTEX M4 CPU+ MPU + FPU 180 MHz • Dual Bank 2 x 1MB Flash ARM ® 32-bit multi-AHB bus matrix Arbiter (max 120MHz) • Up to 180MHz with over-drive mode Encryption (independent & window) 1x SDIO 2x CAN 2.0B 3x 12-bit ADC 2x SPI/I2S 24 channels / 2Msps 1xSAI 6x USART/LIN Temp Sensor 3x I2C 5 Dual Port DMA1 Master 2 Dual Port DMA2 Master 3 FIFO/8 Streams FIFO/8 Streams Ethernet 10/100 LCD-TFT DMA2D Master 4 High Speed USB2.0 Master 5 Master 6 Master 7 FIFO/DMA FIFO/DMA FIFO FIFO 6 Dual Port AHB1-APB2 AHB1 AHB2 Dual Port AHB1-APB1 SRAM1 112KB SRAM2 16KB SRAM3 64KB FMC I-Code Bank1 1Mbytes Multi-AHB Bus Matrix 2Mbytes Flash Bank2 1Mbytes D-Code ART Accelerator S-Bus I-Bus Master 1 System Architecture D-Bus CCM data RAM 64KB CORTEX-M4 180MHz FPU & MPU Graphics on STM32 Image quality needs • iPhone has completely changed the required level of graphical quality • Bigger display size • Better display resolution • Perfect icons • State of the art animations (coverflow…etc…) • User wants the same experience than on iPhone • Huge resource needs on microcontroller side • Hardware acceleration becomes mandatory • Content design/creation is a key aspect • But no need for a gaming machine • No need for real 3D : 2D graphics is wide enough 8 Overview • Past / Today • Keyboard and/or Knob • Optional 7-segment display • Optional dot-matrix display (text or graphical) • Limited interactivity 9 Typical embedded display needs • For home appliance • Display size and form factor will be very different from an equipment to another • In most of them we shall not be above 6~7 inches • iPad 2 display is 132PPI (pixels per inch) • 7” 4:3 display 800x600 represents @142PPI 10 From ones and zeros to image display Step 1 : Create the content in a frame buffer Text 1 • • Font 1 • Frame rate • Prev Refresh rate (60 Hz) The frame buffer is build by composing graphical primitive This operation is done by the CPU running a graphical library software It can be accelerated by a dedicated hardware used with the CPU through the graphical library More often the frame buffer can be updated, more fluent will be the animations (frames per second / fps) Step 2 : Display the frame buffer Next • • • The frame buffer is transferred to the display through a dedicated hardware interface Graphical oriented microcontroller are offering a TFT controller to drive directly the display The frame buffer must be sent at 60fps to have a perfect image color and stability (independently from the animation fps) 11 STM32F4x9 Architecture Cortex-M4 Chrom-ART Accelerator (DMA2D) TFT Controller Bus Matrix Internal Flash • • • • Internal SRAM External Memory Controller External memory TFT controller allows the interfacing Chrome-ART (DMA2D) provides a true HW graphical acceleration DMA2D offloads the CPU for operations like rectangle filling, rectangle copy (with or without pixel format conversion), and image blending DMA2D goes faster than the CPU for the equivalent operation 12 13 13 Implementation examples and resources requirements Using STM32F4x7/4X9 internal RAM (192K) for small resolutions BUFFER SIZES CGA (Kbytes) ↘ (320x200) bpp ↓ Image Building process QVGA (320x240) WQVGA (480x272) VGA (640x480) WVGA (800x480) SVGA XGA (800x600) (1024x768) 1 (2 colors) 7,8 9,4 15,8 37,5 46,9 58,6 96,0 2 (4 colors) 15,6 18,8 31,6 75,0 93,8 117,2 192,0 4(16 colors) 31,3 37,5 63,3 150,0 187,5 234,4 384,0 8 (256 colors) 62,5 75,0 126,6 300,0 375,0 468,8 768,0 16 (high color) 125,0 150,0 253,1 600,0 750,0 937,5 1536,0 24 (true color) 32 (deep color) 187,5 225,0 379,7 900,0 1125,0 1406,3 2304,0 250,0 300,0 506,3 1200,0 1500,0 1875,0 3072,0 Double buffer: New image and Frame buffers can be in internal RAM Single buffer : 2 options: • Image can be handled by regions: one region to be displayed while the other is been built and so only one buffer will be needed • new image buffer in internal RAM and frame buffer in external RAM or in display internal memory. External memory needed for both frame buffer and new image buffer 14 Single Chip MCU 16-bit QVGA, 8-bit WQVGA •Internal Flash up to 2MB •Internal SRAM up to 256KB • Frame buffer in internal SRAM • 16-bit QVGA (320 x 240 ~154 KB) • 8-bit WQVGA (400 x 240 ~97 KB) •Package LQFP 100pin Cortex-M4 Chrom-ART Accelerator TFT Controller Bus Matrix Cost saving + Graphic Acceleration Internal Flash Internal SRAM STM32F4x9 External Memory Controller 15 MCU with External Memory Up to SVGA ( 800x600 ) •Internal Flash up to 2MB •Internal SRAM up to 256KB •External Memory for frame buffer • 16-bit or 32-bit SDRAM / SRAM •Package: LQFP 144pin, up to 208. Cortex-M4 Chrom-ART Accelerator TFT Controller Bus Matrix Unique Graphical Capability and Flexible architecture Internal Flash Internal SRAM STM32F4x9 External Memory Controller SDRAM 16 Which package to use depending on the variant targeted? Variant TFT Controller External Memory - SDRAM STM32F4x9 package High-End Yes 32-bit LQFP208/BGA216 Mid-End Yes 16-bit LQFP144/ BGA176 / LQFP176 No No LQFP100/LQFP144 Yes No LQFP100/LQFP144 Low-End SDRAM devices example: • • MT48LC4M16A2P-7E : 64Mb MT48LC16M16A2P-7E : 256Mb 17 LCD-TFT Display Controller (LTDC) MCD Application Team Benefits • AHB bus Master • Can access any part of address space → ext. memory, internal SRAM, Flash. • Flexible programmable display parameters • Display control signals • Flexible color format • Multi-Layer Support • Windowing • Blending • Flexible programmable parameters for each Layer • On chip memory or External memory can be used as Frame buffer 19 LCD-TFT architecture FIFO PFC 64x32b LCD_CLK Blending LCD_HSYNC Layer2 LCD_VSYNC FIFO 64x32b PFC Dithering LCD_DE LCD_R[7:0] Configuration and status registers APB Interface LCD_G[7:0] Synchronous Timings Generation LCD_B[7:0] LCD Panel AHB Master Interface AHB Interface Layer1 20 LTDC Timings Start of Frame HSYNC Active Width HBP HFP VSYNC VBP D1,L1 VBP: Vertical Back porch VFP: Vertical Front porch HBP: Horizontal Back porch Active Heigh HFP: Horizontal Front porch Dm,, Ln VFP These timings come from the datasheet of the display. E.g. TFT on discovery kit. 8/12/2015 21 Frame Display 1 Frame VSYNC Vertical Back Porch (VBP) LCD Lines Vertical Front Porch (VFP) 1 Line HSYNC 1 LCD_CLK LCD RGBs LCD Data Enable Horizontal (VBP) 2 3 LCD Columns 4 5 Horizontal (HFP) x x x x x 480 22 Vertical/Horizontal transactions • Vertical transaction Start of Frame • Horizontal transaction Start of Scan Line 23 LCD basic timing signals • LCDs require the following basic timing signals: • VSYNC (Vertical Sync for TFT) • Used to reset the LCD row pointer to the top of the display • HSYNC (Horizontal sync for TFT) • Used to reset the LCD column pointer to the edge of the display • D0..Dxx (1 or more data lines) • Data line • LCDCLK (LCD pixel clock) • Used to control panel refresh rate • Some panels may require additional timing signals: • LCD_DE • LCD data Enable. Used to indicate valid data on the LCD data bus • Other signals – some optional • LCD power, backlight power, touchscreen 24 LCD Memory Requirements • Frame buffer size • The panel size and bits per pixel determine the amount of memory needed to hold the graphic buffer. • Memory Requirement (KB) = (bpp * Width * Height)/8 Panel Resolution Total Pixel bpp (bit per pixel) Required memory (KB) 320x240 (QVGA) 76.8K 16bpp 153.6 8bpp 76.8 480x272 (WQVGA) 130.5K 16bbp 261.12 640x480 (VGA) 307.2K 16bbp 614.4 • In many cases, more memory is needed. E.g. double buffering: one graphic buffer to store the current image while a second buffer used to prepare the next image. 25 LTDC Clocks and reset • Three clock domains: • AHB clock domain (HCLK) • To transfer data from the memories to the Layer FIFO and vise versa • APB2 clock domain (PCLK2) • To access the configuration and status registers • The Pixel Clock domain (LCD_CLK) • To generate LCD-TFT interface signals. • LCD_CLK output should be configured following the panel requirements. The LCD_CLK is configured through the PLLSAI • LTDC Reset • It is reset by setting the LTDCRST bit in the RCC_APB2RSTR register 26 LCD-TFT Signals • The LCD-TFT IO pins not used by the application can be used for other purposes. LCD-TFT Signals Description LCD_CLK Pixel Clock output LCD_HSYNC Horizontal Synchronization LCD_VSYNC Vertical Synchronization LCD_DE Data Enable LCD_R[7:0] 8-Bits Red data LCD_G[7:0] 8-Bits Green data LCD_B[7:0] 8-Bits Blue data 27 LTDC Main Features - (1/3) • 24-bit RGB Parallel Pixel Output; 8 bits-per-pixel ( RGB888) • AHB 32-Bit master with burst access of 16 words to any system memory • Dedicated FIFO per Layer (depth of 64 word) • Programmable timings to adapt to targeted display panel. • HSYNC width, VSYNC width, VBP, HBP, VFP, HFP • Programmable Polarity of: • HSYNC, VSYNC, Data Enable • Pixel clock • Supports only TFT (no STN) 28 LTDC Main Features - (2/3) • Programmable display Size • Supports up to 800 x 600 (SVGA) • Programmable Background color • 24-bit RGB, used for blending with bottom layer. • Multi-Layer Support with blending, 2 layers + solid color background • Dithering (2-bits per color channel (2,2,2 for RGB)) • Combination of adjacent pixels to simulate the desired shade • Dithering is applicable for 18bit color displays, to simulate 24bit colors. • Newly programmed values can be loaded immediately at run time or during Vertical blanking • 2 Interrupts generated on 4 event Flags 29 Alpha Channel Usage • The Alpha channel represent the transparency of a pixel • It’s mandatory as soon as you are manipulating bitmaps with non square edges or for anti-aliased font support Aliased • 0xFF = opaque Anti-aliased 0xFFFF0000 0xAAFF0000 0x30FF0000 Box filled with color in ARGB8888 format 30 Pixel Data Mapping vs Color Format 8 programmable Input color format per layer 31 bpp 31:24 23:16 15:8 ARBG8888 Ax[7:0] Rx[7:0] Gx[7:0] Bx[7:0] 32 RGB888 Bx+1[7:0] Rx[7:0] Gx[7:0] Bx[7:0] 24 RGB565 Rx+1[4:0] Gx+1[5:3] Gx+1[2:0] Bx+1[4:0] ARGB1555 Ax+1[ Rx+1[ Gx+1[ 0] 4:0] 4:3] Gx+1[2:0] Bx+1[4:0] ARGB4444 Ax+1[3:0] Rx+1[3:0] L8 Lx+3[7:0] Lx+2[7:0] Lx+1[7:0] Lx[7:0] 8 AL88 Ax+1[7:0] Lx+1[7:0] Ax[7:0] Lx[7:0] 16 AL44 Ax+3[3:0] Lx+3[3:0] Ax+2[3:0] Lx+2[3:0] Ax+1[3:0] Lx+1[3:0] Ax[3:0] Lx[3:0] 8 Gx+1[3:0] Bx+1[3:0] Rx[4:0] Ax[0] 7:0 Gx[5:3] Rx[4:0] Gx[4:3] Ax[3:0] Rx[3:0] Gx[2:0] Gx[2:0] Gx[3:0] Bn[4:0] 16 Bx[4:0] 16 Bx[3:0] 16 Pixel Format Conversion • The color format of a bitmap converted into another one : this operation is called Pixel Format Conversion (PFC) • Direct Mode to Direct Mode or Indirect Mode to Direct Mode is easy to do, but converting to an indirect color format would mean regenerating a CLUT which is a very complex operation... ARGB8888 ARGB1555 0 PFC 0 0 0 0 0 0 0 0 4 3 2 1 0 4 3 2 1 0 4 3 2 4 3 2 1 0 4 3 2 1 0 4 3 2 4 3 2 1 0 4 3 2 1 0 4 3 2 32 PFC - Direct color Mode 32-bit per pixel 24-bit per pixel 16-bit per pixel ARGB8888 RGB888 ARGB4444 ARGB1555 RGB565 Direct coding A R G B 33 PFC - Indirect color Mode 16-bit per pixel 8-bit per pixel 4-bit per pixel AL88 L8 AL44 A8 L4 A4 Index Color LookUp Table 0x00 A R G B 0x01 A R G B G B Indirect coding ... 0xFF A R A R G B 34 CLUT - Palletized color • Color Look-Up Table (CLUT) up to 256 entry per layer • The frame buffer will contain an index value for each pixel • The CLUT must be pre-loaded with RGB values for each index • Each RGB value is stored in a position in the CLUT. • The CLUT must be reloaded only when LTDC is disabled or during vertical blanking period • The CLUT can be enabled on the fly for every layer through the LTDC_LxCR register 35 CLUT- Palletized • The R, G and B values and their own respective address are programmed through the LTDC_LxCLUTWR register. • L8 and AL88 input pixel format, the CLUT has to be loaded by 256 colors • AL44 input pixel format, the CLUT has to be loaded by 16 colors. The address of each color must be filled by replicating the 4-bit L channel to 8-bit. • L0 (indexed color 0), at address 0x00, • L1, at address 0x11…. • L2, at address 0x22 Indexed 16 – L4 Source - wikipedia.org Indexed 256 - L8 RGB888 36 • Size of pictures displayed Demo – Color Formats • RGB 888 - 230kb – needed for pictures with uniform color transitions (like blue sky on the picture) • RGB565 - 154kb – good trade off between size and quality • L8 - 78kb – for small icons it is usually good enough, without significant quality decrease • Picture quality • Difference is mostly visible in the color transitions (like the blue sky) • Dithering is improving the quality, but it make worse details recognition • STM32F429I-Discovery kit display • 18bit interface, it is not possible to display 24bpp (RGB888) • Difference between direct RGB888 and RGB565 is not visible Dithering • HW dithering is improving the quality of RGB888 • Indexed L8 format can be improved by dithering implemented on PC side 12/08/2015 37 Layer Programmable Parameters: Window • Window position and size • The first and last visible Pixel are configured in the LTDC_LxWHPCR register. • The first and last visible line are configured in the LTDC_LxWVPCR START_POS_X START_POS_Y END_POS_Y END_X_POS 38 Layer Programmable Parameters: Color Frame Buffer • The frame buffer size, line length and the number of lines settings must be correctly configured : • If it is set to less bytes than required by the layer, FIFO underrun error will be set. • If it is set to more bytes than actually required by the layer, the useless data read is discarded. The useless data is not displayed. Start of layer frame buffer Frame Buffer Line Length Pitch . . Number of Lines 39 Layer Programmable Parameters: Color Frame Buffer - effects • Simply changing the start of the layer frame buffer you can scroll the picture over the layer • The picture stored in the memory must be bigger than actual layer size . . . . 40 Demo - Moving layer LTDC_Layer_InitStruct.LTDC_CFBStartAdress = (uint32_t)Image + 3 * (offsetH + (offsetV * Image_width)); • Bytes per pixel • Base address of image in memory • Horizontal scroll • Just by changing the layer buffer address you can move the visible layer over a bitmap which is bigger than the layer. • Vertical scroll 320 240 320 400 41 Layer Programmable Parameters: Multi-layer blending • Blending is always active using alpha value • Blending factors are configured through the LTDC_LxBFCR register • Fixed Constant alpha • Alpha pixel multiplied by the Constant Alpha • The blending order is fixed and it is bottom up. • Programmable Background Color for the bottom layer Layer 1 Solid color background Layer 2 42 Blending – Example 1 • Layer 1 blending with background • Background is black • Layer 2 is disabled. 100% 75% 50% 25% 0% 43 Blending – Example 2 • Layer 1 and Layer 2 blending • Background color is black • Layer 1 Constant Alpha set to 100 % • Layer 2 Constant Alpha is set to: 100% 75 % 50 % 25 % 0% 44 Demo – Two Layers • Example is using two layers • Layer 1 – static background picture • Layer 2 – moving ST logo with alpha channel • ST logo is moved using layer 2 parameters only, no load of CPU • Blending is done directly by Constant Alpha parameter, no load of CPU, done by LTDC controller directly 45 Layer Programmable Parameters: Color Keying • Transparent color (RGB) can be defined for each layer in the LTDC_LxCKCR register • When the Color Keying is enabled, the current pixels is compared to the color key. If they match for the programmed RGB value, all channels (ARGB) of that pixel are set to 0. • Color Keying can be enabled on the fly for each layer in the LTDC_LxCR regiser 46 Demo - Color Keying • Example is using two layers • Layer 1 – background picture “blue sky” • Layer 2 – ST logo with white background color • Keying color is set to WHITE • Disturbing artifacts can be removed by pre-processing using tools like Photoshop or Gimp, but quality of result is usually depending on the background anyway • Best suitable for rectangular graphical objects • Not optimal for photos – use alpha channel blending instead 47 Layer Programmable Parameters: Default Color • Default Color • The default color ( ARGB) is used outside the defined layer window or when a layer is disabled. • The default color is configured through the LTDC_LxDCCR register. • To bypass the default color, set the blending factor to transparent Alpha • Tricky use case: • Layer 1 is enabled • Layer 2 is disabled, with default color black. • If blending factor is set to ConstAlpha=0xFF, No image will be displayed. Only black window that will be displayed ( default color of Layer2 is black). 48 LTDC Shadow registers • The shadowed registers are all the Layer 1 and Layer 2 registers except the CLUT register (LTDC_LxCLUTWR). • The shadow registers should not be modified again before the reload has been done. • The new written value can only be read after the reload has taken place. • Shadow registers can be reloaded to active registers by: • Immediate Reload Set IMR bit in LTDC_SRCR register • Vertical blanking reload Set VBR bit in LTDC_SRCR register 49 LTDC interrupts • Two interrupts vectors: • LTDC global interrupt • Line interrupt • Register Reload • LTDC error interrupt • FIFO Underrun • Transfer Error Interrupt event Event flag Enable bit Line LIF LIE Register Reload RRIF RRIEN FIFO underrun FUERRIF FUERRIE Transfer Error TERRIF TERRIE 50 Chrom-ART Accelerator™ STM32F4 Graphic Accelerator (DMA2D) Overview Step 1 : Create the content in a frame buffer Text 1 • • Font 1 • Frame rate • Prev Refresh rate (60 Hz) The frame buffer is build by composing graphical primitive This operation is done by the CPU running a graphical library software It can be accelerated by a dedicated hardware used with the CPU through the graphical library More often the frame buffer can be updated, more fluent will be the animations (animation fps) Step 2 : Display the frame buffer Next • • • The frame buffer is transferred to the display through a dedicated hardware interface Graphical oriented microcontroller are offering a TFT controller to drive directly the display The frame buffer must be sent at 60fps to have a perfect image color and stability (independently from the animation fps) 52 53 Graphical content creation Creating something « cool » • How the frame buffer is generated for creating a “cool” graphical interface to be displayed through the TFT controller ? 14:21 Temperature 21°C Humidity 62% ARMED -5°C 54 Frame buffer construction • The frame buffer is generated drawing successively all the graphic objects 14:21 Temperature 21°C Humidity 62% ARMED -5°C 55 Frame buffer generation needs • The resulting frame buffer is an uncompressed bitmap of the size of the screen. • Each object to be drawn can be • A Bitmap with its own color coding (different from the final one), compressed or not • A Vector Description (a line, a circle with a texture...etc....) • (A Text) 56 Bitmap or Vector • • • • Bitmap High ROM usage No CPU usage if no compression, but can be needed for uncompressing Geometrical transformations limited and would need filtering Description standard bitmap files that are converted into C table • • • • Vector graphics Low ROM usage High CPU usage as image needs to be generated : a GPU is mandatory Geometrical transformations are natural Description through • Polygons : 3D graphics • Curves : 2D graphics 57 STM32F42x/F43x Architecture Cortex-M4 Chrom-ART Accelerator TFT Controller Bus Matrix Internal Flash • • • • Internal SRAM External Memory Controller TFT controller allows the interfacing DMA2D provides a true graphical acceleration DMA2D offloads the CPU for operations like rectangle filling, rectangle copy (with or without pixel format conversion), and image blending DMA2D goes faster than the CPU for the equivalent operation 58 59 Bitmaps Overview • Bitmap are an array representation of an image • It shall have the at least following properties • Width (in pixel) • Height (in pixel) • Color mode (direct, indirect, ARGB8888, RGB565...etc...) • Color Look Up Table (optional) Width How color are coded Height 60 Blending • Blending consist in drawing an image onto another respecting the transparency information • As a consequence blending implies to read 2 sources, then blend then write to the destination Blended Not Blended 61 Back to our « cool » interface Background 14:21 Almost Uniform L8 mode Temperature Button Round shape Gradient ARGB8888 mode 21°C Humidity 62% -5°C Icon Complex shape Many colors ARGB8888 mode ARMED Fonts Specific management with A8 or A4 mode 62 Demo – Content Creation • Moving successively graphical elements from internal FLASH into the frame buffer by Chrome-ART DMA2D source parameters: Location in memory, width, height, pixel format DMA2D destination parameters: Location in buffer, width, height, pixel format, line offset foreground output DMA2D ARMED background FLASH content ARMED 63 Font management • Bitmap fonts are managed only using alpha channel (transparency) PFC ROMed character bitmap (A8 or A4) Generated character bitmap with color information (ARGB8888, ARGB1555, ARGB4444) or (RGB888, RGB565) 64 Summary • To generate my 24bpp frame buffer I will have to • Copy background from the ROM to the frame buffer with PFC L8 to RGB888 • Copy buttons & icons from the ROM to the frame buffer with blending • Copy characters from the ROM to the frame buffer with PFC A4 to ARGB8888 and blending • Many copy operations with pixel conversion. Can be done by CPU, but it’s very time consuming → HW acceleration helps. 65 66 Chrom-ART Accelerator (DMA2D) Overview • The Chrom-ART combines both a DMA2D and graphical oriented functionality for image blending and pixel format conversion. • To offload the CPU of raw data copy, the Chrom-ART is able to copy a part of a graphic content into another part of a graphic content, or simply to fill an part of a graphic content with a specified color. • In addition to raw data copy, additional functionality can be added such as image format conversion or image blending (image mixing with some transparency). 67 Typical data flow Cortex-M4 Chrom-ART Accelerator TFT Controller Bus Matrix Internal Flash Internal SRAM External Memory Controller Creation of an object in a memory device by the Chrom-ART Update/Creation of the frame buffer in the external RAM by the Chrom-ART TFT controller data flow 68 Chrom-ART features • AHB bus master with burst access to any system memory • Programmable bitmap height, width and address in the memory • Programmable data format (from 4-bit indirect up to 32-bit direct) • Dedicated memory for color lookup table (CLUT) independent from LTDC • Programmable address destination and format • Optional image format conversion from direct or indirect color mode to direct color mode • Optional blending machine with programmable transparency factor and/or with native transparency channel between to independent image input to the destination image. 69 Chrom-ART pixel pipeline Foreground FG FIFO FG PFC Blender BG FIFO Background BG PFC Output PFC Output FIFO 70 Bitmap parameter Address Width Original_Address 14:21 Temperature 21°C Original_Height Height Humidity 62% -5°C ARME D Original_Width Address = Original_Address + (X + Original_Width * Y) * BPP LineOffset = Original_Width - Width 71 Supported color mode Color mode Input FG/BG CM[3:0] Output CM[2:0] ARGB8888 0000 000 RGB888 0001 001 RGB565 0010 010 ARGB1555 0011 011 ARGB4444 0100 100 L8 0101 Not supported AL44 0110 Not supported AL88 0111 Not supported L4 1000 Not supported A8 1001 Not supported A4 1010 Not supported 72 CLUT management • When an indirect color mode L8, AL44 or AL88 is used, the bitmap CLUT must be loaded into the Chrom-ART • Each FG and BG has its own dedicated memory for CLUT. • The CLUT can be loaded manually when no Chrom-ART operation are on going • The CLUT can be loaded automatically configuring the CLUT format (24-bit or 32-bit), the CLUT size and the CLUT address and setting the CLUT Start bit 73 Supported operations • 4 functional modes are supported • Register to memory : the destination bitmap is filled with the specified output color • Memory to memory : the data are fetch through the FG and are written to the destination bitmap without any color format modification (no PFC) • Memory to memory with PFC : the data are fetch through the FG and are written to the destination bitmap after being converted into the destination color format (PFC) • Memory to memory with PFC and blending : the data are fetched through the FG and the BG, are converted, are blended together and are written to the destination bitmap • Once configured, the Chrom-ART is launched setting the Start bit • The operation can be either suspended through the Suspend bit or aborted through the abort bit 74 Alpha modulation • When the PFC is activated the Alpha value of the pixel can be modified as follow • Kept as it is • Replaced by a fixed one • Replaced by the current one multiplied by the fixed one • This allows to perform easily fade in/out animations 75 Line Watermark • For synchronization purpose, an interrupt can be generated when a specified line has been written by the Chrom-ART into the memory • The line number is defined by the filed LW[15:0] of the DMA2D_LWR register DMA2D transfer Line watermark interrupt 76 Interrupts Interrupt Flag Enable Clear Description Transfer Error TERIF TERIE CTERIF An AHB error occured during a Chrom-ART operation Transfer Complete TCIF TCIE CTCIF The programmed operation is complete Transfer Watermark TWIF TWIE CTWIF The Watermarked line has been written An error has been generated accessing the CLUT (CPU tried to access the CLUT when the Chrom-ART is being active) CLUT Access Error CAEIF CAEIE CCAEIF CLUT Transfer Complete CTCIF CTCIE CCTCIF CEIF CEIE CCEIF Configuration Error The CLUT transfer is complete The Chrom-ART has been launched with an illegal configuration 77 Integration with Graphic Library Application Application STemWin STemWin Cortex-M4 • • • Chrom-ART Cortex-M4 Chrom-ART integration is transparent for the application The low-level drivers of the graphical stack are upgraded to directly use Chrom-ART for data transfer, pixel format conversion and blending CPU load is decreased and graphical operations are faster 78 STM32 Solution for Graphics • STM32 offers a unique graphical capability in the Cortex-M based MCU perimeter • Real TFT Controller for optimum display control • External memory interface to connect both Flash for static content and SRAM or SDRAM for dynamic content and frame buffer • On-chip hardware acceleration deeply coupled with graphical library • Standard graphical library taking advantage of on-chip graphical acceleration 79 Enhanced and upgrade of FSMC Flexible Memory Controller (FMC) CONTENTS • FMC features • SDRAM protocol • SDRAM FMC controller 81 OBJECTIVES 82 • Overview of FMC interface • Usage of high capacity RAM storage - SDRAM • For frame buffer • For picture storage and preparation • For animations 82 FMC Features (1/2) • 6 Banks to support External memories • FMC external access frequency is up 90MHz when HCLK is at 180MHz • Independent chip select control for each memory bank • Independent configuration for each memory bank • Programmable timings to support a wide range of devices • 8/16/32 bits data bus • External asynchronous wait control • Interfaces with Synchronous DRAM (SDRAM) memory-mapped 83 FMC Features (2/2) • Interfaces with static memory-mapped devices including: • static random access memory (SRAM) • read-only memory (ROM) • NOR/ OneNAND Flash memory • PSRAM • Interfaces parallel LCD modules: Intel 8080 and Motorola 6800 • Interfaces with NAND Flash and 16-bit PC Cards • With ECC hardware up to 8 Kbyte for NAND memory • 3 possible interrupt sources (Level, Rising edge and falling edge) • Supports burst mode access to synchronous devices (NOR Flash and PSRAM) 84 SDR SDRAM protocol overview SDRAM memory organization • Example of DRAM array with 12-bits row and 10-bits column • A row width is 2exp(10) = 1024 column Cw 4096 Rows • Column width is 8-bit, 16-bit or 32-bit (Cw) Row width : 1024 columns 86 SDRAM memory read operation • Read operation step 1(*): • On Row Access Strobe (RAS), selected row is copied to “Row Buffer” (a full row is transferred at once to the Row Buffer) • Read operation step 2: • On Column Access Strobe (CAS), column is selected from “Row Buffer” and presented on the memory interface (*): Row activation is only performed if the row is not active or at a row boundary 87 SDRAM memory read characteristics (1/2) • SDRAM read characteristics • Reads are destructive: contents are erased after reading • Row buffer • read a full row at once (a set of bits all at once), and then break down them based on different column addresses Vdd sense amp bitline voltage 1 0 Wordline Enabled Sense Amp Enabled After read cell contains something close to ½ Vdd Vdd storage cell voltage 88 SDRAM memory write characteristics • The SDRAM controller always checks the next write access destination, • Two cases: • If the next write access is in the same row or in another active row (in a different bank) • The write operation is carried out • If the next write access targets another row (not active), the SDRAM controller • Generates a precharge command • Activates the new row • Initiates a write command 90 STM32 FMC controller FMC SDRAM main features (1/4) • Up to 512MB continues memory range split into two banks, can be seen as a single device. 0xC000 0000 SDRAM Bank1 256MB (4x16MBx32-bit) FMC SDRAM Up to 512MB Independent chip select Independent configuration Easy to use SDRAM Bank2 256MB (4x16MBx32-bit) 0xDFFF FFFF SDRAM main features (2/4) • Fully programmable SDR (single data rate) SDRAM interface • Configurable SDRAM clock speed • Half AHB speed (HCLK /2), • One-third AHB speed (HCLK /3) • Programmable Timing parameters for different SDRAM devices requirements • Row to column delay ( TRCD ) • Self refresh time • CAS latency of 1,2,3 • Memory data bus width : 8-bit, 16-bit and 32-bit • Up to 4 internal banks with configurable Row and Column sizes : • up to 13-bits Address Row, • up to 11-bits Address Column. SDRAM main features (3/4) • Optimized initialization sequence by software • The initialization command sequence are executed simultaneously for the two banks. Initialization time can be divided by 2. • Automatic Refresh operation with programmable Refresh rate • Energy-saving capabilities : two low power modes are supported: • Self-refresh Mode • Power-down Mode SDRAM main features (4/4) • Multibank ping-pong access (FMC SDRAM controller keeps track of the active row in each bank) • Automatic row and bank boundary management • Optimized Read access : • Cacheable Read FIFO with depth of 6 lines x 32-bit • With 6x 14-bit Address Tag to identify each FIFO line content • Configurable Read Burst (to anticipate next read accesses during CAS latencies) • Buffered write access • Write Data FIFO with depth of 16 • With 16x Write Address FIFO to identify each FIFO line destination SDRAM controller benefits • AHB Slave interface up to 180MHz • Grant more RAM resources for user application • Accessible by all AHB masters • CPU can execute code from SDRAM • Reduce RAM memory cost (SDRAM vs. SRAM) 96 For more information welcome to visit our website: www.st.com/stm32 www.stmcu.com.cn www.stmcu.org 1 使用STM32 设计HMI-软件 介绍使用STM32提供的硬件资源和软件资源开发人机交互界面HMI的方法 Agenda STM32F42xx Technical Training 一、STM32 HMI设计硬件资源 LCD controller ChromeART accelerator SDRAM interface 二、 STM32 HMI设计软件资源 STemWin IS2T TouchGFX 12/08/2015 2 目录 STM32GUI方案介绍 STM32GUI硬件平台资源评估&选型 STM32GUI软件方案之STemWin 3 过去的嵌入式产品注重用户的实用性 过去的嵌入式产品注重用户的实用性 4 现在的 现在的嵌入式产品更加 嵌入式产品更加重 品更加重视用户体验 视用户体验 5 6 STM32丰富的外设资源和强大的 丰富的外设资源和强大的CPU 丰富的外设资源和强大的 处理能力 为嵌入式GUI系统提供强大的硬件支持 系统提供强大的硬件支持 为嵌入式 14 : 21 7 STM32硬件系统结构 STM32硬件系统结构 -5C STM32 MCU LCD接口 接口 LTDC (LCD-TFT Controller) (Chrom-ART Accelerator) FIFO FIFO DMA2D External RAM/FLASH SRAM 256KB BUS Matrix FMC/FSMC ART Accelerator FMC/FSMC LTDC ALARM Flash LTDC (LCD-TFT Controller) STM32硬件 STM32硬件-硬件--LTDC --LTDC性能演示 LTDC性能演示 (分辨率1024x768) 分辨率1024x768) STM32硬件 STM32硬件-硬件--DMA2D --DMA2D性能演示 DMA2D性能演示 DMA2D (Chrom-ART Accelerator) DMA2D CPU Load(约 约) 使用 5% 不使用 95% STM32不仅 不仅为客户提供丰 不仅为客户提供丰富 为客户提供丰富的硬件资源 而且为客户提供了STM32 GUI软件开发平台 软件开发平台 而且为客户提供了 STemWin IS2T TouchGFX 10 STM32GUI软件开发平台 软件开发平台--STemWin 软件开发平台 11 STM32GUI软件开发平台 软件开发平台--STemWin 软件开发平台 12 STM32GUI软件开发平台 软件开发平台--TouchGFX 软件开发平台 13 STM32GUI软件开发平台 软件开发平台--TouchGFX 软件开发平台 14 STM32GUI软件开发平台 软件开发平台—IS2T 软件开发平台 15 STM32GUI软件开发平台 软件开发平台—IS2T 软件开发平台 16 17 STM32GUI 硬件平台资 件平台资源评估&选型 源评估 选型 如何从STM32丰富的产品线中 如何从 丰富的产品线中 选择合适的STM32GUI硬件平台 硬件平台? 选择合适的 硬件平台? 18 STM32 MCU方 方案的选择需考虑 19 LCD接口类型 应用需要的存 储空间 (RAM&ROM) 需要MCU处理能 力 20 LCD接口类型 应用需要的存 储空间 (RAM&ROM) 需要MCU处理能 力 STM32提供的 提供的LCD接口外设 接口外设 提供的 21 • STM32提供的可用于LCD应用的外设 LCD接口 接口 STM32外 外设 F1 F2 F3 F4 SPI SPI √ √ √ √ MCU FMC/FSMC √ √ STM32F303xE Only √ RGB LTDC - - - STM32F4x9 - DMA2D( ChromART) - STM32F427 STM32F437 STM32F4x9 - - 8/12/2015 主流LCD接口 接口 22 • SPI • 写屏速度较慢 • 接口简单 • 不需要独立显存 FMC/FSMC (8080/6800) 写屏速度较快 接口较复杂 不需要独立显存 8/12/2015 主流LCD接口 接口( 主流 接口(续) • LTDC(RGB) LCD_CLK • 写屏速度较快 LCD_HSYNC • 写屏不需要CPU干预 LCD_VSYNC • 接口较复杂 • 需要MCU提供显存 • 只有STM32F429提供LTDC 外设 STM32F429 LCD_DE LCD Panel LCD_R[7:0] LCD_G[7:0] LCD_B[7:0] 8/12/2015 23 STM32 MCU方 方案的选择依赖于 24 LCD接口类型 应用需要的存 储空间 (RAM&ROM) 需要MCU处理能 力 ROM和 和RAM(以 以STemWin为例 为例) 为例 • 对存储空间(ROM/RAM)的 需求 • 应用程序的最小需求(STemWin) • 在不使用窗口管理时 • ROM 8.1KB • RAM 334Byte • 在使用窗口管理时 • ROM 60KB • RAM 6.6Byt • 随着用户界面的复杂程度增加,对应 的ROM和RAM的需求会随之增加。 • 可以使用外扩RAM作为STemWin的 内存 8/12/2015 25 内存分配(以STemWin为例) • 内存分配 • 可以灵活选择 MCU内部SRAM 或者外部RAM 作为STemWin 的内存块 SPI FSMC LTDC (DMA) ) CPU Bus Matrix Internal Flash Internal SRAM External Memory Controller 内部RAM作 作为内存空间 内部 内存空间 外部RAM作 作为内存空间 外部 内存空间 26 STM32 MCU方 方案的选择依赖于 27 LCD接口类型 应用需要的存 储空间 (RAM&ROM) MCU处理能力 28 • 市面上的主流LCD液晶屏接口及对比 LCD接口 接口 数据内存 显示内存 CPU任务 任务 DMA参与传送 参与传送 SPI MCU/扩展内存 LCD控制器内置 构图+传输 √ FMC/FSMC (8080/6800) MCU/扩展内存 LCD控制器内置 构图+传输 √ MCU/扩展内存 MCU片内SRAM 或 扩展SDRAM 构图 (STM32F4x9) DMA2D LTDC (RGB) 8/12/2015 STM32 MCU方 方案的选择依赖于 29 • 根据应用进行MCU选择 LCD接口类型 应用需要的存 储空间 (RAM&ROM) • 需要的CPU速度 • 72MHz ~ 180MHz • 接口 需要MCU处理能 力 • SPI,8080/6800,RGB • RAM/ROM用量 • 确定需要的MCU的Flash/SRAM size • 需要外扩RAM作为数据内存或者显存,外扩RAM的类型 • 确定是否需要FSMC(SRAM/PSRAM),FMC(SDRAM) 30 STM32GUI 软件方案之STemWin 软件方案之 预览 STemWin介绍 使用STemWin开发一个产品 STemWin开发资源 31 32 STemWin介绍 使用STemWin开发一个产品 STemWin开发资源 STemWin是什么 STemWin是什么 ST和Segger公司联合提供的嵌入式GUI方案 STM32 STemWin emWin STemWin高度可裁剪可移植性,完全支持STM32全系列MCU Presentation Title 12/08/2015 33 STemWin特性 STemWin特性 提供强大的2D 供强大的2D图像库和控件 2D图像库和控件 提供强大的图像显示功能(jpeg 供强大的图像显示功能(jpeg、 (jpeg、png、 png、gif) 提供多种字体( 供多种字体(默认字体、 认字体、扩展字体、 扩展字体、外语支持) 外语支持) 虚拟屏幕和多层显 虚拟屏幕和多层显示 多层显示 清晰的系统架构 支持嵌入式操作系统支持 清晰的驱动接口, 清晰的驱动接口,方便用户快速移植LCD 方便用户快速移植LCD驱动 LCD驱动、 驱动、存储设备 Presentation Title 12/08/2015 34 STemWin提供丰富美观的 STemWin提供丰富美观的GUI 提供丰富美观的GUI控件 GUI控件 12/08/2015 35 36 STemWin介绍 使用STemWin开发一个产品 STemWin开发资源 37 14 : 21 -5C ALARM STemWin开发平台基本结构 STemWin开发平台基本结构 38 应用程序 STemWin应用 应用 开发API 开发 VisualStudio 平台emWin开 开 平台 发库 UM03001 & AN43231 STM32平台开 平台开 发库 STemWin开发平台基本结构和开发方法 STemWin开发平台基本结构和开发方法 39 资源准备 VisualStudio平台 • 准备资源 • 图片/ 图片/字体/ 字体/控件/ 控件/动画等资源文件 • 代码转换 • 将资源文件转换为代码或者存储在外部存储器 • 基于VS平台开发包和 GUI API开发应用程序 开发应用程序 基于 平台开发包和STemWin 平台开发包和 • 在VS调试仿真工具调试效果 调试仿真工具调试效果 开发应用程序 • • • • STM32开发平台 • 移植 • 基于STM32 STemWin库进行移植 库进行移植 基于 STM32平台选择 平台选择 STM32 MCU BSP移植 移植 应用代码移植 调试运行 软件版本发布 40 2.1. 资源准备 2.1 资源准备— 资源准备—图片资源处理 使用BitmapConverter软件将bmp图片资源生成相应的.c文件 12/08/2015 41 2.1 资源准备— 资源准备—字体资源处理 使用FontConverter软件将字体文件资源生成相应的.c文件 42 2.1 资源准备— 资源准备—控件资源处理 使用GUIBuilder软件将用户自定义可视化窗口和控件资源生成相应的.c文件 43 44 2.2 使用VS开发应用程序 VS开发应用程序 2.2 使用VS开发应用程序 VS开发应用程序开发应用程序-认识STemWinVS 认识STemWinVS开发环境 STemWinVS开发环境 图标转换的C资源文件 主程序入口 绘制背景 绘制Layer0 绘制Layer1 主程序 12/08/2015 45 2.2 使用VS开发应用程序 VS开发应用程序开发应用程序-绘制背景层 static void background_deal(void) { GUI_DrawBitmap(&bmbg_big, 0,0); } 46 2.2 使用VS开发应用程序 VS开发应用程序开发应用程序-绘制layer0 绘制layer0层 layer0层 static void layer0_deal(void) { int i = 0; for(i=0;i<GUI_COUNTOF(_aBitmapItem_layer0);i++) { GUI_DrawBitmap(_aBitmapItem_layer0[i].pBitmap, _aBitmapItem_layer0[i].x,_aBitmapItem_layer0[i].y); } } 47 2.2 使用VS开发应用程序 VS开发应用程序开发应用程序-绘制layer1 绘制layer1层 layer1层 static void layer1_deal(void) { int i = 0; GUI_SelectLayer(1); GUI_SetColor(GUI_TRANSPARENT); for(i=0;i<GUI_COUNTOF(_aBitmapItem_layer1);i++) { GUI_DrawBitmap(_aBitmapItem_layer1[i].pBitmap, _aBitmapItem_layer1[i].x,_aBitmapItem_layer1[i].y); } } 48 2.2 使用VS 使用VS开发应用程序 VS开发应用程序开发应用程序-VS调试工具运行 VS调试工具运行 12/08/2015 49 50 2.3 应用程序移植到STM32 应用程序移植到 2.3 应用程序移植到STM32 应用程序移植到 应用代码移植 STM32 MCU BSP移植 12/08/2015 51 应用代码移植 52 将应用程序移植STM32 MCU开发平台 开发平台 将应用程序移植 12/08/2015 STM32 MCU BSP移植 53 • 信息收集 • 目标平台的LCD控制器 • 了解目标平台的LCD类型 • 目标平台的内存配置 • 要用到的ROM/RAM大小,决定是否移植,部分移植还是全部移植 • 能否使用外扩RAM • 目标平台的输入设备 • 了解目标平台的输入设备 • 触摸 • 鼠标 STemWin的驱动设置 - 从GUI_Init()开始 54 将预先定义好的内存块的地址传给STemWin 并由其管理这块内存。这个内存块通常是一个 数组或者是一片连续的内存空间 这个内存块可以位于STM32的片上SRAM, 也可以位于外扩的SDRAM STemWin集成了很多LCD控制器,要根据所使 用的LCD控制器进行驱动选择 设定应用需要的虚拟屏幕的分辨率,虚拟屏幕 的分辨率可以不同于LCD屏的物理分辨率 设定LCD屏的物理分辨率 设定MCU提供的显存入口地址,如果显存在 LCD上则不需要设定 触摸设备校准及方向设置,可以在STemWin中 填写,也可以在BSP中完成 应用程序只需要调用GUI_Init()初始化 显示驱动回调函数,一个任务是使显示开始工 作,其他要求执行硬件相关的操作如开显示启, 关闭显示,设定显示位置等。如果LCD不支持 这些操作,则不用处理这些操作。 调试运行 试运行 12/08/2015 55 56 STemWin介绍 使用STemWin开发一个产品 STemWin开发资源 开发资源获取 • PC端 端开发工具集 • VisualStudio2010 • SeggerEval_WIN32_MSVC_MinGW_GUI_V524 • STM32开发工具集 开发工具集 • IAR/KEIL • STemWin 例程库 目录下包含了一些小工具) 例程库(Tools目录下包含了一些小工具 目录下包含了一些小工具) http://www.st.com/web/catalog/tools/FM147/CL1794/SC961/SS1743/LN1734/PF259225 • 文档资源 • STemWin 例程库( 目录下) 例程库(Documents目 • 图像处理软件(举例 像处理软件 举例) 举例 • GIMP(图像处理软件 图像处理软件) 图像处理软件 • IconWorkshop(图标处理工具 图标处理工具) 图标处理工具 12/08/2015 57 58 更多资料敬请访问ST官方网站 www.st.com/stm32 www.stmcu.com.cn www.stmcu.org