A New Isolated Topology of DSTATCOM with
Unipolar Switching
Bhim Singh
Sabha Raj Arya
Department of Electrical Engineering
Indian Institute of Technology Delhi
Hauz Khas, New Delhi, 110016, India
bhimsingh1956@gmail.com
Department of Electrical Engineering
Indian Institute of Technology Delhi
Hauz Khas, New Delhi, 110016, India
sabharaj1@gmail.com
Abstract— This paper presents a design of distribution static
synchronous compensator (DSTATCOM) with a new isolated
topology for a three-phase four-wire distribution system. It is
based on six-leg voltage source converter (VSC) with the zigzag/three single-phase transformers configuration. It is used for
reactive power compensation, neutral current compensation;
harmonics elimination and voltage drop compensation under
linear/nonlinear loads with optimum DC link voltage. An
Icosineφ based control algorithm is used for extraction of load
fundamental active and reactive power components of currents
which are used for estimation of reference source currents. A
MATLAB based model of DSTATCOM is developed and its
performance is simulated for power factor correction (PFC) and
zero voltage regulation (ZVR) modes of operation. The
performance of DSTATCOM is observed quite satisfactory in
various operating conditions under linear and nonlinear loads.
Keywords-DSTATCOM;Six-leg VSC; Unipolar switching; Zigzag/three single phase transformer; PFC; ZVR
I.
INTRODUCTION
power with poor quality has ill effects on
ELECTRONIC
life of different domestic and industrial equipment [1].
Main power quality problems in medium and low voltage
distribution systems are harmonics currents, load unbalancing,
excessive neutral current, voltage drop due overloading, and
high reactive power demand etc [2, 3]. Active power
compensators are used as custom power devices (CPDs) for
mitigation of these power quality problems. It is proved that
the CPDs provide good performance compared to any
traditional power quality mitigation methods [4, 5]. Normally
national or international standard guidelines are used for the
design of distribution system at different voltage levels with
nonlinear loads [6]. Shunt connected CSD such as distribution
static compensator (DSTATCOM) is used for solving currents
related power quality problems at distribution level.
Performance and utilization of its components depend upon its
design, configuration, control algorithm used for reference
currents estimation and reliability of semiconductor devices
etc [7-9]. Some of the popular control algorithms are time
domain current detection, Icosφ control algorithm,
instantaneous p-q theory, synchronous detection based control
algorithm, perfect harmonic cancellation etc [10-14]. These
are used for estimation of reference currents for gating pulse
generation of VSC (Voltage Source Converter) of
DSTATCOM. Based on the application, a shunt compensator
can be classified as single-phase, three-phase, series -parallel
connected configurations etc. It is also classified based on the
reference currents estimation and levels of power rating [15].
A review on the various topologies of the shunt compensators
is reported in the literature [16-17]. These topologies include
three-phase three-wire VSC with transformer configuration,
three-phase four-wire, three-phase three-wire with multilevel
VSC etc. Generally in domestic and commercial applications,
an ac power is distributed through a three-phase, four-wire
systems. Unbalances of linear and nonlinear loads are the
major reasons for an excessive neutral current. This may
damage the neutral conductor and overheat the distribution
transformer. Some of transformer connections based neutral
current compensation techniques are zigzag transformer, stardelta transformer, Scott-transformer, T-connected transformer,
star-hexagon transformer, etc. Some of other techniques are
based on the use of synchronous machine, active power
compensator topologies using four-leg VSC, and three Hbridge VSC topology reported in the literature [18-19].
In this paper, a new isolated topology based on zigzag/three single-phase transformers is used in DSTATCOM to
select an optimum dc voltage for proper utilization of solid
state devices. An advantage of a zigzag transformer is to
mitigate the zero sequence currents and triplen harmonics in its
primary windings itself. Thus, it helps in the reduction of the
devices rating of VSC connected in the secondary windings. A
six-leg VSC of proposed DSTATCOM operated with six
gating signals has an advantage of doubling the frequency of
PWM voltages compared to switching frequency of the devices
using unipolar switching as compared to bipolar switching
which is used in three-leg VSC for a given switching
frequency. Moreover, its dc bus voltage of VSC is also reduced
as compared to three-leg VSC topology. Power losses are not
much increased compared to conventional solution due to
reduction of power rating of VSC and effect of unipolar
switching. Compared to non-isolated, it is more effective
because the dc bus voltage of VSC can be adjusted to an
optimal level and some protection issues are also solved due to
isolation.
II.
STRUCTURE Of DSTATCOM
Schematic diagram of a six-leg VSC with a zig-zag/three
single-phase transformer isolated topology based DSTATCOM
is shown in Fig. 1. It is compensating four wire linear/nonlinear
loads connected to grid supply with source impedance (ZS).
The power circuit of DSTATCOM includes a voltage source
converter (VSC), interfacing inductors (Lf), zig-zag/ three
single-phase transformers and series connected R-C circuit as a
ripple filter. It is used for filtering the high frequency switching
noise in PCC voltages. The required compensating currents
1
(iCa, iCb, iCc) are injected by six-leg VSC for power quality
improvement. For a considered load of 40 kVA (0.8 lagging),
DSTATCOM data are given in Appendix „A‟. The rating of
VSC for reactive power compensation and harmonics
elimination is found to be 30 kVA (Approximately 25% higher
than reactive current for rated value). The design of VSC, zigzag/ three single-phase transformer and other components of
DSTATCOM are given in Appendices „B‟ and „C‟.
N
a
b
c
isn
vsb
vsc
iCa iCb iCc
Lf
iLa
iLb Linear,
iLc Nonlinear
iLn loads
iTn
a
Cdc
N
vdc
b
vdc*
c
Zig-zag /Single
phase Transformer
Six leg VSC
Gating Pulses
isa
isb
Control Algorithm
isc
vsa vsb vsc
iLa iLb iLc
vdc
Fig. 1. Schematic diagram of DSTATCOM having a six-leg VSC with a zigzag /three single phase transformer
III.
CONTROL ALGORITHM
Fig.2. shows a block diagram of an Icosφ control
algorithm used for estimation of reference source currents.
The load currents (iLa, iLb, iLc), voltages at PCC (point of
common coupling) (vsa, vsb, vsc) and dc bus voltage (vdc) of
VSC are sensed as feedback control signals. Distorted load
currents can be expressed as [10, 11],

i La =
I
Lan
sin(n t - φan )
(1)
Lbn
sin(n t - φbn - 1200 )
(2)
n=1

i Lb =
I
n=1

i Lc =
I
Lcn
sin(n t - φcn - 2400 )
(3)
n=1
where φan, φbn, φcn are phase angles of nth harmonic current in
three phase load currents with their phase volatges. ILan, ILbn,
ILcn are amplitude of nth harmonic current in these phases.
The amplitude of active power component of current (ILpa)
of phase „a‟ is extracted from filtered value (through the band
pass filter) of distorted load current (iLfa) at the zero crossing
of quadrature phase unit template (cosφqa) of three phase PCC
voltages. A zero crossing detector and a “sample and hold”
signals are used to extract the ILpa (amplitude of filtered load
current at zero crossing of corresponding quadrature-phase
unit template). Similarly, other two phases amplitude of active
power component of current ILpb and ILpc are also extracted. In
+
vdc
PI Controller
LPF Extraction in phase and quadrature
component of phase „a‟ load current
Icp
sinφpb
ZCD1 cosφqa iLpa
sinφpc
sinφpa
+
+
SCH1 |Re |
+ 1/3 LPF +
iLa
iLfa
Reference S1
+
ILpA
BPF
ZCD2 sinφpa
Source
iLqa
Isp
Currents S4
SCH2 | Re |
S3
and
Gating S
Isq
6
Extraction in phase and iLpb
Pulse
S5
iLb
+
quadrature component of
Generation
+ 1/3 LPF +
S2
phase „b‟ load current iLqb
+
ILqA
cosφqb
sinφpb
Icq
vt*
iLpc
PI
iLc Extraction in phase and
+
quadrature component of i
Controller
Lqc
phase „c‟ load current
vt
vsa
vsb
vt and voltage cosφ,
cosφqc
sinφpc
vsc
sinφ Computation
cosφqc
c
Zs isa
isb
isc
cosφqb
N
AC
Mains
b
Ripple Filter
cosφqa
a
Cf
Rf
vsa
a case of balanced system, amplitude of active power
component of load currents is expressed as,
ILpA=(ILpa+ ILpb+ ILpc)/3
(4)
where ILpa, ILpb and ILpc are amplitude of load active power
component of three-phase currents.
For self supporting dc bus of VSC, an error in dc bus
voltage of VSC vde (n) of DSTATCOM at nth sampling instant
is as,
vde(n) = vdcr(n) – vdc(n)
(5)
where vdcr (n) is the reference dc voltage and vdc(n) is the
sensed dc bus voltage of the VSC.
The output of the proportional integral (PI) controller
which is used for regulating dc bus voltage of the VSC at the
nth sampling instant can be expressed as,
Icp(n) = Icp(n-1) + Kpd { vde(n) – vde(n-1)} + Kid vde(n)
(6)
where Icp(n) is considered as part of active power component
of reference source current. Kpd and Kid are the proportional
and integral gain constants of the dc bus PI voltage controller.
The amplitude of active power component (Isp) of
reference source currents are expressed as,
Isp= ILpA+Icp
(7)
sinφpa sinφpb sinφpc
Fig. 2. Estimation of reference source currents using Icosφ control algorithm
PCC phase voltages (vsa, vsb and vsc) are considered
sinusoidal and their amplitude is estimated as,
vt = √{(2/3) (vsa2 +vsb2 +vsc2)}
(8)
The unit vectors in phase with vsa, vsb and vsc are derived as
[12],
sinφpa = vsa/vt; sinφpb = vsb/vt; sinφpc= vsc/vt
(9)
In-phase components of reference source currents are
estimated as,
i*sap = Isp sinφpa; i*sbp = Isp sinφpb; i*scp = Isp sinφpc
(10)
The unit vectors (cosφqa, cosφqb and cosφqc) in quadrature
with three phase PCC voltages (vsa, vsb and vsc) are derived
using a quadrature transformation of the in-phase unit vectors
sinφpa, sinφpb and sinφpc as [12],
cosφqa= (- sinφpb / 3) + (sinφpc / 3)
(11)
2
cosφqb = (3 sinφpa / 2) + (sinφpb – sinφpc) / (23)
(12)
cosφqc = (-3 sinφpa / 2) + (sinφpb – sinφpc) / (23)
(13)
Amplitude of reactive power component of current (ILqa) of
phase „a‟ filtered load current (iLfa) is extracted at the zero
crossing of the unit template in-phase of the PCC voltage
(sinφpa). A zero crossing detector and a “sample and hold”
signal are used to extract ILqa (amplitude of filtered load
current at zero crossing of corresponding in-phase unit
template). Similarly, amplitude of reactive power component
of phase b (iLqb) and phase c (iLqc) are also estimated.
Amplitude of fundamental reactive power component of load
currents can be expressed as,
ILqA=(iLqa+ iLqb+ iLqc)/3
(14)
A voltage error in reference amplitude and estimated
amplitude of ac voltage vte at nth sampling instant is as,
vte(n) = vtr(n) – vt(n)
(15)
where vtr(n) is the amplitude of reference load terminal
voltage and vt(n) is the amplitude of the sensed three-phase ac
voltages at the PCC at nth instant.
The output of a PI controller Icq(n) which is used for
regulating the amplitude of PCC voltage at the nth sampling
instant is expressed as,
Icq(n) = Icq(n-1) + Kpq { vte(n) – vte(n-1)} + Kiq vte(n)
(16)
where Kpq and Kiq are the proportional and integral gain
constants of the PI ac voltage controller, vte (n) and vte (n-1) are
the voltage errors in nth and (n-1)th instant and Icq(n) is the part
of amplitude of reactive power component of the reference
source current at nth instant. Icq(n) is represented as Icq in
steady state.
The amplitude of reactive power component (Isq) of
reference source currents is as,
Isq = ILqA+Icq
(17)
The quadrature or reactive power component of reference
source currents are estimated as,
i*saq = Isq cosφqa; i*sbq = Isq cosφqb; i*scq = Isq cosφqc
(18)
Total reference source currents are sum of in-phase and
quadrature components of the reference source currents as,
i*sa = i*sap +i*saq
(19)
i*sb = i*sbp +i*sbq
(20)
i*sc = i*scp +i*scq
(21)
These reference source currents (i*sa, i*sb and i*sc) are
compared with the sensed source currents (isa, isb and isc) in PI
current controllers. Amplified values of these current errors for
all three phases are used to generate gating signals of IGBTs of
VSC using PWM current controller.
IV.
RESULTS AND DISCUSSION
Performance of DSTATCOM with new topology is
simulated in MATLAB environment using Simulink and Sim
Power System (SPS) toolboxes for PFC and ZVR modes of
operation at linear and nonlinear loads.
A. Performance of DSTATCOM in PFC Mode of Operation
The dynamic performance of a new topology of
DSTATCOM based on six-leg VSC is shown in Fig. 3 for
PFC mode of operation at linear loads. Performance indices as
phase voltages at PCC (vs), balanced source currents (is),
source neutral current (isn), load currents (iLa, iLb, iLc), load
neutral current (iLn), compensator currents (iCa, iCb, iCc), and dc
bus voltage (vdc) are shown under time varying linear loads
(at t=0.95s to 1.05s) conditions. These results show
satisfactory performance of DSTATCOM for reactive power
compensation, neutral current compensation and load
balancing.
Fig. 3. Dynamic performance of DSTATCOM under varying linear loads in
PFC mode
Similarly, a rectifier as a harmonics producing nonlinear
load is connected to the AC mains. The dynamic performance
of DSTATCOM (with PCC voltages, source currents, source
neutral current, load currents, load neutral current,
compensating currents and dc bus voltage) and waveforms of
phase „a‟ voltage at PCC (vsa), source current (isa) and load
current (iLa) with their harmonic spectra are shown in Fig. 4
and Figs. 5(a-c), respectively.
Total harmonic distortion (THD) of the phase „a‟ at PCC
voltage, source current, load current are 2.39%, 2.13% and
40.75% respectively. These observations have proved the
functions of DSTATCOM for harmonics currents elimination,
load balancing, neutral current and power factor correction.
B. Performance of DSTATCOM in ZVR Mode of Operation
In ZVR mode of operation of DSTATCOM, amplitude of
load terminal voltage is regulated to the rated value. This
mode required extra leading reactive power to regulate PCC
voltages. Fig. 6 shows the waveforms in the PCC phase
voltages (vs), balanced source currents (is), source neutral
current (isn), load currents (iLa, iLb, iLc), load neutral current (iLn),
compensator currents (iCa, iCb, iCc), amplitude of voltages at
PCC (vt) and dc bus voltage (vdc) under linear loads at t=0.95 s
to 1.05 s. Its performance is also recorded under nonlinear
loads. The dynamic performance of DSTATCOM in terms of
performance indices waveforms and harmonics spectra and
THD of phase „a‟ voltage at PCC (vsa), source current (isa) and
load current (iLa) are shown in Fig. 7 and Figs. 8 (a-c)
respectively. THDs of the phase „a‟ at PCC voltage, source
current, load current are 2.88%, 2.25% and 40.83%,
respectively. Three-phase PCC voltages are regulated and
3
maintained at desire level. Root mean square (RMS) value of
three phase PCC voltage is regulated from 237.3 V to 239.6 V
and 237.72 V to 239.63 V at linear and nonlinear loads
respectively. Table I demonstrates the performance of threephase DSTATCOM for harmonic elimination, reactive power
compensation and load balancing in PFC and ZVR modes of
operation.
(b)
(c)
Fig. 5. Waveforms and harmonic spectra of (a) PCC voltage of phase „a‟ (b)
source current of phase „a‟ (c) load current of phase „a‟ in PFC mode
Fig.4. Dynamic performance of DSTATCOM under varying nonlinear loads
in PFC mode
(a)
Fig. 6. Dynamic performance of DSTATCOM under varying linear loads in
ZVR mode
4
V.
CONCLUSIONS
A new isolated topology of the DSTATCOM (six-leg VSC
with isolated zig-zag /single phase transformer) has been
designed and implemented in MATLAB for compensation of
four-wire linear and nonlinear loads with maximum utilization
of dc bus voltage. An Icosineφ control algorithm has been used
for estimation reference source currents for control of
DSTATCOM. Performance of DSTATCOM has been found
quite satisfactory for power quality improvement in PFC and
ZVR modes of operation according to guidelines of IEEE-5191992 standard. Doubling the frequency of PWM voltages
compared to the switching frequency of IGBTs of VSC has
also been observed with application of unipolar switching in
six-leg VSC of DSTATCOM as compared to the bipolar
switching in three-leg VSC.
(b)
(c)
Fig. 8. Waveforms and harmonic spectra of (a) PCC voltage of phase „a‟ (b)
source current of phase „a‟ (c) load current of phase „a‟ in ZVR mode
Operating
Mode
Fig. 7. Dynamic performance of DSTATCOM under varying nonlinear loads
in ZVR mode
PFC Mode
TABLE I
PERFORMANCE OF DSTATCOM
Linear
Performance Indices
load
237.3V,
PCC voltage (V) , %THD
1.15%
41.64A,
Source current (A) , %THD
0.99%
Nonlinear
load
237.72V,
2.39%
23.75A,
2.13%
52.83A,
0.07%
239.6V,
1.44%
42.41A,
0.96, %
24.06A,
40.75%
239.63V,
2.88%
24.03A,
2.25%
Load current (A), % THD
53.34A,
0.10%
24.23A,
40.83%
dc bus voltage (V)
230V
230V
Load current (A) , %THD
PCC voltage (V), %THD
Source current (A), % THD
ZVR Mode
APPENDIX „A‟
AC supply source: 3Phase, 415 V (L-L), 50Hz; Source
Impedance: Rs=0.07 Ω, Ls=2 mH; Load: (1) Linear: 40 kVA,
0.8 p.f. lagging (2) Non-linear: Three phase full bridge
uncontrolled rectifier with R= 8 Ω and L= 100 mH; Ripple
filter: Rf = 5 Ω, Cf = 10μF; dc bus capacitance: 8500 μF;
Reference dc bus voltage: 230 V; interfacing inductor (Lf) =
(a)
5
2mH; Sampling time(ts) = 10µs, Switching frequency (fs) =
10kHz, Rating of zig-zag/three three single phase transformer
= 24 kVA, 50 Hz, 139/139/139V.
APPENDIX „B‟
Design of DSTATCOM
The design of DSTATCOM with transformer configuration
based new topology is given in this section.
A. Selection dc Voltage
DC bus voltage (vdc) = √2VLL/m
(22)
where, m (modulation index) considered as 1 and VLL (138.33
V) is the ac line output voltage of VSC used in DSTATCOM.
Calculated value of dc bus voltage is 195.63 V and its selected
value is 230V.
B. Selection of dc bus Capacitor
The value of dc bus of VSC of DSTATCOM is computed as
[7, 12],
Cdc 

2r v ph (kic )t
v
dc
2
 vdc12


=0.5[{3(ILn/3)VLL/√3)}+3{( ILn√3/3) Vz }] kVA
where ILn=√3IL (worst load condition) and Vz= VLL/3
VA of zig-zag/three single phase transformer is as,
=0.5[{3(96.37/3) (415/√3)}+3{(55.63)(415/3)}]
=23.09 kVA (Approx. 8 kVA per phase)
where, vdc is the nominal dc voltage and vdc1 is the minimum
voltage level of dc bus, „k‟ is the over loading factor, vph is the
supply phase voltage, factor „r‟ is varying between 0.04 to
0.15. ic is the phase current of the VSC and t is time for which
dc bus voltage is to be recovered. Calculated value of dc bus
capacitor is 7160.01µF and its selected value is 8500 µF.
[2]
[3]
[4]
[5]
[7]
[8]
[9]
[10]
C. Selection of ac Inductor
The value of interfacing inductor is estimated as[7, 12],
AC inductance (Lf) = Vdc / (8*k*fs*icrpp)
(24)
where vdc is the dc bus voltage, k=1.2, m=1, fs is the switching
frequency and icrpp is the acceptable % range of current ripple.
For a considered value of 2% of current ripple in
DSTATCOM current, calculated value of ac inductor is 1.77
mH and its selected value is 2 mH.
[11]
[12]
[13]
D. Voltage Rating of the IGBTs
The voltage rating (vsw) of IGBT under dynamic conditions as,
vsw=vdc+vd
(25)
where vd is the 15% overshoot in the dc bus voltage under
dynamic condition. The voltage rating of switch is calculated
as 264.45 V and it is selected of 600V.
E. Current Rating of the IGBT
The current rating (isw) of IGBT under dynamic conditions as,
isw=1.2(icr+ isp)
(26)
where isp (√2ic) and icr (5% of ic) are the peak value of
DSTATCOM current and value of allow ripple currents. The
minimum current rating of switch is observed 73.32 A and
these are selected of 75A.
[14]
[15]
[16]
[17]
[18]
APPENDIX „C‟
Rating of zig-zag/three single phase transformer [18] as,
VA of a zig zag /three single phase transformer
(28)
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6